Re: [Qemu-devel] [RFC] postcopy livemigration proposal
On Mon, Aug 08, 2011 at 03:38:54PM +0300, Avi Kivity wrote: > On 08/08/2011 06:24 AM, Isaku Yamahata wrote: >> This mail is on "Yabusame: Postcopy Live Migration for Qemu/KVM" >> on which we'll give a talk at KVM-forum. >> The purpose of this mail is to letting developers know it in advance >> so that we can get better feedback on its design/implementation approach >> early before our starting to implement it. > > Interesting; what is the impact of increased latency on memory reads? Many people has already discussed it much in another thread. :-) That's much more than I expected. >> There are several design points. >>- who takes care of pulling page contents. >> an independent daemon vs a thread in qemu >> The daemon approach is preferable because an independent daemon would >> easy for debug postcopy memory mechanism without qemu. >> If required, it wouldn't be difficult to convert a daemon into >> a thread in qemu > > Isn't this equivalent to touching each page in sequence? No. I don't get your point of this question. > Care must be taken that we don't post too many requests, or it could > affect the latency of synchronous accesses by the guest. Yes. >>- connection between the source and the destination >> The connection for live migration can be re-used after sending machine >> state. >> >>- transfer protocol >> The existing protocol that exists today can be extended. >> >>- hooking guest RAM access >> Introduce a character device to handle page fault. >> When page fault occurs, it queues page request up to user space daemon >> at the destination. And the daemon pulls page contents from the source >> and serves it into the character device. Then the page fault is >> resovlved. > > This doesn't play well with host swapping, transparent hugepages, or > ksm, does it? No. At least it wouldn't be so difficult to fix it, I haven't looked ksm, thp so closely though. Although the vma is backed by the device, the populated page is anonymous. (by MMAP_PRIVATE or the deriver returning anonymous page) So swapping, thp, ksm should work. > I see you note this later on. > >> * More on hooking guest RAM access >> There are several candidate for the implementation. Our preference is >> character device approach. >> >>- inserting hooks into everywhere in qemu/kvm >> This is impractical >> >>- backing store for guest ram >> a block device or a file can be used to back guest RAM. >> Thus hook the guest ram access. >> >> pros >> - new device driver isn't needed. >> cons >> - future improvement would be difficult >> - some KVM host feature(KSM, THP) wouldn't work >> >>- character device >> qemu mmap() the dedicated character device, and then hook page fault. >> >> pros >> - straght forward approach >> - future improvement would be easy >> cons >> - new driver is needed >> - some KVM host feature(KSM, THP) wouldn't work >>They checks if a given VMA is anonymous. This can be fixed. >> >>- swap device >> When creating guest, it is set up as if all the guest RAM is swapped out >> to a dedicated swap device, which may be nbd disk (or some kind of user >> space block device, BUSE?). >> When the VM tries to access memory, swap-in is triggered and IO to the >> swap device is issued. Then the IO to swap is routed to the daemon >> in user space with nbd protocol (or BUSE, AOE, iSCSI...). The daemon >> pulls >> pages from the migration source and services the IO request. >> >> pros >> - After the page transfer is complete, everything is same as normal >> case. >> - no new device driver isn't needed >> cons >> - future improvement would be difficult >> - administration: setting up nbd, swap device >> > > Using a swap device would be my preference. We'd still be using > anonymous memory so thp/ksm/ordinary swap still work. > > It would need to be a special kind of swap device since we only want to > swap in, and never out, to that device. We'd also need a special way of > telling the kernel that memory comes from that device. In that it's > similar your second option. > > Maybe we should use a backing file (using nbd) and have a madvise() call > that converts the vma to anonymous memory once the migration is finished. With whichever options, I'd like to convert the vma into anonymous area after the migration completes somehow. i.e. nulling vma->vm_ops. (The pages are already anonymous.) It seems troublesome involving complicated races/lockings. So I'm not sure it's worthwhile. -- yamahata
Re: [Qemu-devel] [RFC] postcopy livemigration proposal
On Mon, Aug 08, 2011 at 10:47:09PM +0300, Dor Laor wrote: > On 08/08/2011 06:59 PM, Anthony Liguori wrote: >> On 08/08/2011 10:36 AM, Avi Kivity wrote: >>> On 08/08/2011 06:29 PM, Anthony Liguori wrote: >>> - Efficient, reduce needed traffic no need to re-send pages. >> >> It's not quite that simple. Post-copy needs to introduce a protocol >> capable of requesting pages. > > Just another subsection.. (kidding), still it shouldn't be too > complicated, just an offset+pagesize and return page_content/error What I meant by this is that there is potentially a lot of round trip overhead. Pre-copy migration works well with reasonable high latency network connections because the downtime is capped only by the maximum latency sending from one point to another. But with something like this, the total downtime is 2*max_latency*nb_pagefaults. That's potentially pretty high. >>> >>> Let's be generous and assume that the latency is dominated by page copy >>> time. So the total downtime is equal to the first live migration pass, >>> ~20 sec for 2GB on 1GbE. It's distributed over potentially even more >>> time, though. If the guest does a lot of I/O, it may not be noticeable >>> (esp. if we don't copy over pages read from disk). If the guest is >>> cpu/memory bound, it'll probably suck badly. >>> So it may be desirable to try to reduce nb_pagefaults by prefaulting in pages, etc. Suffice to say, this ends up getting complicated and may end up burning network traffic too. > > It is complicated but can help (like pre faulting working set size > pages). Beyond that async page fault will help a bit. > Lastly, if a guest has several apps, those that are memory intensive > might suffer but light weight apps will function nicely. > It provides extra flexibility over the current protocol (that still has > value for some of the loads). We can also combine postcopy with precopy. For example, The migration is started in in precopy mode at the beginning and then at some point it is switched into postcopy mode. > >>> >>> Yeah, and prefaulting in the background adds latency to synchronous >>> requests. >>> >>> This really needs excellent networking resources to work well. >> >> Yup, it's very similar to other technologies using RDMA (single system >> image, lock step execution, etc.). >> >> Regards, >> >> Anthony Liguori >> >>> >> >> > -- yamahata
Re: [Qemu-devel] [RFC] postcopy livemigration proposal
On Mon, Aug 08, 2011 at 10:38:35AM +0100, Stefan Hajnoczi wrote: > On Mon, Aug 8, 2011 at 4:24 AM, Isaku Yamahata wrote: > > This mail is on "Yabusame: Postcopy Live Migration for Qemu/KVM" > > on which we'll give a talk at KVM-forum. > > I'm curious if this approach is compatible with asynchronous page > faults? The idea there was to tell the guest about a page fault so it > can continue to do useful work in the meantime (if the fault was in > guest userspace). Yes. It's quite possible to inject async page fault into the guest when the faulted page isn't available on the destination. At the same time the page will be requested to the source of the migration. I think it's not so difficult. -- yamahata
[Qemu-devel] [RFC] postcopy livemigration proposal
This mail is on "Yabusame: Postcopy Live Migration for Qemu/KVM" on which we'll give a talk at KVM-forum. The purpose of this mail is to letting developers know it in advance so that we can get better feedback on its design/implementation approach early before our starting to implement it. Background == * What's is postcopy livemigration It is is yet another live migration mechanism for Qemu/KVM, which implements the migration technique known as "postcopy" or "lazy" migration. Just after the "migrate" command is invoked, the execution host of a VM is instantaneously switched to a destination host. The benefit is, total migration time is shorter because it transfer a page only once. On the other hand precopy may repeat sending same pages again and again because they can be dirtied. The switching time from the source to the destination is several hunderds mili seconds so that it enables quick load balancing. For details, please refer to the papers. We believe this is useful for others so that we'd like to merge this feature into the upstream qemu/kvm. The existing implementation that we have right now is very ad-hoc because it's for academic research. For the upstream merge, we're starting to re-design/implement it and we'd like to get feedback early. Although many improvements/optimizations are possible, we should implement/merge the simple/clean, but extensible as well, one at first and then improve/optimize it later. postcopy livemigration will be introduced as optional feature. The existing precopy livemigration remains as default behavior. * related links: project page http://sites.google.com/site/grivonhome/quick-kvm-migration Enabling Instantaneous Relocation of Virtual Machines with a Lightweight VMM Extension, (proof-of-concept, ad-hoc prototype. not a new design) http://grivon.googlecode.com/svn/pub/docs/ccgrid2010-hirofuchi-paper.pdf http://grivon.googlecode.com/svn/pub/docs/ccgrid2010-hirofuchi-talk.pdf Reactive consolidation of virtual machines enabled by postcopy live migration (advantage for VM consolidation) http://portal.acm.org/citation.cfm?id=1996125 http://www.emn.fr/x-info/ascola/lib/exe/fetch.php?media=internet:vtdc-postcopy.pdf Qemu wiki http://wiki.qemu.org/Features/PostCopyLiveMigration Design/Implementation = The basic idea of postcopy livemigration is to use a sort of distributed shared memory between the migration source and destination. The migration procedure looks like - start migration stop the guest VM on the source and send the machine states except guest RAM to the destination - resume the guest VM on the destination without guest RAM contents - Hook guest access to pages, and pull page contents from the source This continues until all the pages are pulled to the destination The big picture is depicted at http://wiki.qemu.org/File:Postcopy-livemigration.png There are several design points. - who takes care of pulling page contents. an independent daemon vs a thread in qemu The daemon approach is preferable because an independent daemon would easy for debug postcopy memory mechanism without qemu. If required, it wouldn't be difficult to convert a daemon into a thread in qemu - connection between the source and the destination The connection for live migration can be re-used after sending machine state. - transfer protocol The existing protocol that exists today can be extended. - hooking guest RAM access Introduce a character device to handle page fault. When page fault occurs, it queues page request up to user space daemon at the destination. And the daemon pulls page contents from the source and serves it into the character device. Then the page fault is resovlved. * More on hooking guest RAM access There are several candidate for the implementation. Our preference is character device approach. - inserting hooks into everywhere in qemu/kvm This is impractical - backing store for guest ram a block device or a file can be used to back guest RAM. Thus hook the guest ram access. pros - new device driver isn't needed. cons - future improvement would be difficult - some KVM host feature(KSM, THP) wouldn't work - character device qemu mmap() the dedicated character device, and then hook page fault. pros - straght forward approach - future improvement would be easy cons - new driver is needed - some KVM host feature(KSM, THP) wouldn't work They checks if a given VMA is anonymous. This can be fixed. - swap device When creating guest, it is set up as if all the guest RAM is swapped out to a dedicated swap device, which may be nbd disk (or some kind of user space block device, BUSE?). When the VM tries to access memory, swap-in is triggered and IO to the swap device is issued. Then the IO to swap is routed to the daemon in user space with nbd protocol (or
[Qemu-devel] [PATCH] pcie/aer: fix inject aer error command
various fixes to make aer inject error command work.
- wrong assert
- command line parser
- err.status needs initialization
Signed-off-by: Isaku Yamahata
---
hw/pcie_aer.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index be019c7..4346345 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -415,7 +415,7 @@ static void pcie_aer_update_log(PCIDevice *dev, const
PCIEAERErr *err)
int i;
assert(err->status);
-assert(err->status & (err->status - 1));
+assert(!(err->status & (err->status - 1)));
errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
errcap |= PCI_ERR_CAP_FEP(first_bit);
@@ -495,7 +495,7 @@ static int pcie_aer_record_error(PCIDevice *dev,
int fep = PCI_ERR_CAP_FEP(errcap);
assert(err->status);
-assert(err->status & (err->status - 1));
+assert(!(err->status & (err->status - 1)));
if (errcap & PCI_ERR_CAP_MHRE &&
(pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) {
@@ -979,20 +979,21 @@ int do_pcie_aer_inejct_error(Monitor *mon,
if (pcie_aer_parse_error_string(error_name, &error_status, &correctable)) {
char *e = NULL;
error_status = strtoul(error_name, &e, 0);
-correctable = !!qdict_get_int(qdict, "correctable");
+correctable = qdict_get_try_bool(qdict, "correctable", 0);
if (!e || *e != '\0') {
monitor_printf(mon, "invalid error status value. \"%s\"",
error_name);
return -EINVAL;
}
}
+err.status = error_status;
err.source_id = (pci_bus_num(dev->bus) << 8) | dev->devfn;
err.flags = 0;
if (correctable) {
err.flags |= PCIE_AER_ERR_IS_CORRECTABLE;
}
-if (qdict_get_int(qdict, "advisory_non_fatal")) {
+if (qdict_get_try_bool(qdict, "advisory_non_fatal", 0)) {
err.flags |= PCIE_AER_ERR_MAYBE_ADVISORY;
}
if (qdict_haskey(qdict, "header0")) {
--
1.7.1.1
[Qemu-devel] [PATCH] pcie/slot: fix hotplug event
When slot status register is cleared, PCIDevice::exp.hpev_notify
needs to be cleared.
Otherwise, PCIDevice::exp.hpev_notify is never set to false resulting
in no more hot plug event once it's raised.
Signed-off-by: Isaku Yamahata
---
hw/pcie.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/hw/pcie.c b/hw/pcie.c
index 39607bf..5c9eb2f 100644
--- a/hw/pcie.c
+++ b/hw/pcie.c
@@ -175,6 +175,14 @@ static void hotplug_event_notify(PCIDevice *dev)
}
}
+static void hotplug_event_clear(PCIDevice *dev)
+{
+hotplug_event_update_event_status(dev);
+if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
+qemu_set_irq(dev->irq[dev->exp.hpev_intx], 0);
+}
+}
+
/*
* A PCI Express Hot-Plug Event has occurred, so update slot status register
* and notify OS of the event if necessary.
@@ -320,6 +328,10 @@ void pcie_cap_slot_write_config(PCIDevice *dev,
uint8_t *exp_cap = dev->config + pos;
uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
+if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
+hotplug_event_clear(dev);
+}
+
if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
return;
}
--
1.7.1.1
[Qemu-devel] [PATCH] qdev: Eliminate duplicate reset
qbus_reset_all_fn was registered twice, so a lot of device reset
functions were also called twice when QEMU started.
Which was introduced by 80376c3fc2c38fdd45354e4b0eb45031f35587ed
This patch fixes it by making the main_system_bus creation not register
reset handler.
Cc: Stefan Weil
Signed-off-by: Isaku Yamahata
Tested-by: Stefan Weil
---
hw/qdev.c | 14 --
1 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/qdev.c b/hw/qdev.c
index b4ea8e1..6819537 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -36,6 +36,7 @@ static bool qdev_hot_removed = false;
/* This is a nasty hack to allow passing a NULL bus to qdev_create. */
static BusState *main_system_bus;
+static void main_system_bus_create(void);
DeviceInfo *device_info_list;
@@ -328,8 +329,7 @@ static int qdev_reset_one(DeviceState *dev, void *opaque)
BusState *sysbus_get_default(void)
{
if (!main_system_bus) {
-main_system_bus = qbus_create(&system_bus_info, NULL,
- "main-system-bus");
+main_system_bus_create();
}
return main_system_bus;
}
@@ -784,6 +784,16 @@ BusState *qbus_create(BusInfo *info, DeviceState *parent,
const char *name)
return bus;
}
+static void main_system_bus_create(void)
+{
+/* assign main_system_bus before qbus_create_inplace()
+ * in order to make "if (bus != main_system_bus)" work */
+main_system_bus = qemu_mallocz(system_bus_info.size);
+main_system_bus->qdev_allocated = 1;
+qbus_create_inplace(main_system_bus, &system_bus_info, NULL,
+"main-system-bus");
+}
+
void qbus_free(BusState *bus)
{
DeviceState *dev;
--
1.7.1.1
Re: [Qemu-devel] [PATCH] Fix duplicate device reset
Hi, here is the patch. Can you please give it a try?
>From 41039df3174fa46477c4faf93d13eab360dccc22 Mon Sep 17 00:00:00 2001
Message-Id:
<41039df3174fa46477c4faf93d13eab360dccc22.1312196365.git.yamah...@valinux.co.jp>
From: Isaku Yamahata
Date: Mon, 1 Aug 2011 19:56:42 +0900
Subject: [PATCH] qdev: Fix duplicate reset
qbus_reset_all_fn was registered twice, so a lot of device reset
functions were also called twice when QEMU started.
Which was introduced by 80376c3fc2c38fdd45354e4b0eb45031f35587ed
This patch fixes it by making the main_sytem_bus creation not register
reset handler.
Cc: Stefan Weil
Signed-off-by: Isaku Yamahata
---
hw/qdev.c | 14 --
1 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/qdev.c b/hw/qdev.c
index b4ea8e1..6819537 100644
--- a/hw/qdev.c
+++ b/hw/qdev.c
@@ -36,6 +36,7 @@ static bool qdev_hot_removed = false;
/* This is a nasty hack to allow passing a NULL bus to qdev_create. */
static BusState *main_system_bus;
+static void main_system_bus_create(void);
DeviceInfo *device_info_list;
@@ -328,8 +329,7 @@ static int qdev_reset_one(DeviceState *dev, void *opaque)
BusState *sysbus_get_default(void)
{
if (!main_system_bus) {
-main_system_bus = qbus_create(&system_bus_info, NULL,
- "main-system-bus");
+main_system_bus_create();
}
return main_system_bus;
}
@@ -784,6 +784,16 @@ BusState *qbus_create(BusInfo *info, DeviceState *parent,
const char *name)
return bus;
}
+static void main_system_bus_create(void)
+{
+/* assign main_system_bus before qbus_create_inplace()
+ * in order to make "if (bus != main_system_bus)" work */
+main_system_bus = qemu_mallocz(system_bus_info.size);
+main_system_bus->qdev_allocated = 1;
+qbus_create_inplace(main_system_bus, &system_bus_info, NULL,
+"main-system-bus");
+}
+
void qbus_free(BusState *bus)
{
DeviceState *dev;
--
1.7.1.1
--
yamahata
Re: [Qemu-devel] [PATCH] Correctly assign PCI domain numbers
[Added mst to Cc.] In order to use multi PCI domain, several areas need to be addressed in addition to this patch. For example, bios, acpi dsdt. Do you have any plan for addressing those area? What's your motivation for multi pci domain? NOTE: I'm not opposing to this patch. Just curious for your motivation/plan. On Mon, Aug 01, 2011 at 04:51:02PM +1000, David Gibson wrote: > qemu already almost supports PCI domains; that is, several entirely > independent PCI host bridges on the same machine. However, a bug in > pci_bus_new_inplace() means that every host bridge gets assigned domain > number zero and so can't be properly distinguished. This patch fixes the > bug, giving each new host bridge a new domain number. > > Signed-off-by: David Gibson > --- > hw/pci.c |5 - > 1 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/hw/pci.c b/hw/pci.c > index 36db58b..2b4aecb 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -262,6 +262,8 @@ int pci_find_domain(const PCIBus *bus) > return -1; > } > > +static int pci_next_domain; /* = 0 */ > + > void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, > const char *name, > MemoryRegion *address_space, > @@ -274,7 +276,8 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, > > /* host bridge */ > QLIST_INIT(&bus->child); > -pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported > */ > + > +pci_host_bus_register(pci_next_domain++, bus); > > vmstate_register(NULL, -1, &vmstate_pcibus, bus); > } > -- > 1.7.5.4 > > -- yamahata
Re: [Qemu-devel] [PATCH] v6 revamp acpitable parsing and allow to specify complete (headerful) table
On Fri, Jul 15, 2011 at 07:51:43PM +0300, Blue Swirl wrote:
> On Fri, Jul 15, 2011 at 6:18 PM, John Baboval
> wrote:
> > Is there something I can do to help take this patch the rest of the way?
> >
> > I'd hate to see it die because of a style issue and a compiler warning.
>
> There's also suspicious missing 'break' statement. How about fixing
> the issues and submitting the patch?
I fixed the compile error.
I think the missing break is intentional, so added an comment there. Michael?
Blue, can you please take a look of it?
>From 9a5e4158074ea251ab064a946927bcaf861f5c1e Mon Sep 17 00:00:00 2001
Message-Id:
<9a5e4158074ea251ab064a946927bcaf861f5c1e.1311903724.git.yamah...@valinux.co.jp>
From: Michael Tokarev
Date: Thu, 12 May 2011 18:44:17 +0400
Subject: [PATCH] revamp acpitable parsing and allow to specify complete
(headerful) table
>From Michael Tokarev
This patch almost rewrites acpi_table_add() function
(but still leaves it using old get_param_value() interface).
The result is that it's now possible to specify whole table
(together with a header) in an external file, instead of just
data portion, with a new file= parameter, but at the same time
it's still possible to specify header fields as before.
Now with the checkpatch.pl formatting fixes, thanks to
Stefan Hajnoczi for suggestions, with changes from
Isaku Yamahata, and with my further refinements.
Signed-off-by: Michael Tokarev
Cc:: Isaku Yamahata
Cc: John Baboval
Cc: Blue Swirl
---
v5: rediffed against current qemu/master.
v6: fix one "} else {" coding style defect (noted by Blue Swirl)
v7: style fix and added an comment for suspicious break
I think that the missing break of case 0 is intentional.
I added the fallthrough comment there.
---
hw/acpi.c | 298 ---
qemu-options.hx |7 +-
2 files changed, 178 insertions(+), 127 deletions(-)
diff --git a/hw/acpi.c b/hw/acpi.c
index ad40fb4..79ec66c 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -20,19 +20,30 @@
#include "pc.h"
#include "acpi.h"
-struct acpi_table_header
-{
-char signature [4];/* ACPI signature (4 ASCII characters) */
+struct acpi_table_header {
+uint16_t _length; /* our length, not actual part of the hdr */
+ /* XXX why we have 2 length fields here? */
+char sig[4]; /* ACPI signature (4 ASCII characters) */
uint32_t length; /* Length of table, in bytes, including header */
uint8_t revision; /* ACPI Specification minor version # */
uint8_t checksum; /* To make sum of entire table == 0 */
-char oem_id [6]; /* OEM identification */
-char oem_table_id [8]; /* OEM table identification */
+char oem_id[6]; /* OEM identification */
+char oem_table_id[8]; /* OEM table identification */
uint32_t oem_revision;/* OEM revision number */
-char asl_compiler_id [4]; /* ASL compiler vendor ID */
+char asl_compiler_id[4]; /* ASL compiler vendor ID */
uint32_t asl_compiler_revision; /* ASL compiler revision number */
} __attribute__((packed));
+#define ACPI_TABLE_HDR_SIZE sizeof(struct acpi_table_header)
+#define ACPI_TABLE_PFX_SIZE sizeof(uint16_t) /* size of the extra prefix */
+
+static const char dfl_hdr[ACPI_TABLE_HDR_SIZE] =
+"\0\0" /* fake _length (2) */
+"QEMU\0\0\0\0\1\0" /* sig (4), len(4), revno (1), csum (1) */
+"QEMUQEQEMUQEMU\1\0\0\0" /* OEM id (6), table (8), revno (4) */
+"QEMU\1\0\0\0" /* ASL compiler ID (4), version (4) */
+;
+
char *acpi_tables;
size_t acpi_tables_len;
@@ -40,163 +51,198 @@ static int acpi_checksum(const uint8_t *data, int len)
{
int sum, i;
sum = 0;
-for(i = 0; i < len; i++)
+for (i = 0; i < len; i++) {
sum += data[i];
+}
return (-sum) & 0xff;
}
+/* like strncpy() but zero-fills the tail of destination */
+static void strzcpy(char *dst, const char *src, size_t size)
+{
+size_t len = strlen(src);
+if (len >= size) {
+len = size;
+} else {
+ memset(dst + len, 0, size - len);
+}
+memcpy(dst, src, len);
+}
+
+/* XXX fixme: this function uses obsolete argument parsing interface */
int acpi_table_add(const char *t)
{
-static const char *dfl_id = "QEMUQEMU";
char buf[1024], *p, *f;
-struct acpi_table_header acpi_hdr;
unsigned long val;
-uint32_t length;
-struct acpi_table_header *acpi_hdr_p;
-size_t off;
+size_t len, start, allen;
+bool has_header;
+int changed;
+int r;
+struct acpi_table_header hdr;
+
+r = 0;
+r |= get_param_value(buf, sizeof(buf), "data", t) ? 1 : 0;
+r |= get_param_value(buf, sizeof(buf), "file", t) ? 2 : 0;
+switch
Re: [Qemu-devel] [PATCH v2] pci: Common overflow prevention
On Thu, Jul 28, 2011 at 11:40:21AM +0300, Michael S. Tsirkin wrote:
> I don't see a problem with this, but could you please clarify when does
> this happen? I think this is only possible for a pci device
> behind an express root. If so, this belongs in pcie_host.c
>
> I'd also like this info to be recorded in the commit log.
>From 1dd598fd35d4e988dc51487829ed66208ca89021 Mon Sep 17 00:00:00 2001
Message-Id:
<1dd598fd35d4e988dc51487829ed66208ca89021.1311901239.git.yamah...@valinux.co.jp>
From: Isaku Yamahata
Date: Fri, 29 Jul 2011 09:52:45 +0900
Subject: [PATCH] pcie_host: limit check of pcie_mmcfg_data_write/read
This patch adds the check where the offset in the configuration space
is in its configuration size.
MMCFG area allows access of pcie configuration space to be in
offset [0, 4K).
At the same time, conventional pci devices whose configuration space size
is 256 bytes can be behind pcie-to-pci bridge.
The access whose offset is [256, 4K) should have no effect
on the conventional pci device
Add the limit check and ignore such accesses.
Signed-off-by: Isaku Yamahata
---
hw/pcie_host.c | 28 ++--
1 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index f0b3d13..f9fea3d 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -56,23 +56,39 @@ static void pcie_mmcfg_data_write(PCIBus *s,
uint32_t mmcfg_addr, uint32_t val, int len)
{
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
+uint32_t addr;
+uint32_t limit;
if (!pci_dev) {
return;
}
-pci_host_config_write_common(pci_dev, PCIE_MMCFG_CONFOFFSET(mmcfg_addr),
- pci_config_size(pci_dev), val, len);
+addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
+limit = pci_config_size(pci_dev);
+if (limit <= addr) {
+/* conventional pci device can be behind pcie-to-pci bridge.
+ 256 <= addr < 4K has no effects. */
+return;
+}
+pci_host_config_write_common(pci_dev, addr, limit, val, len);
}
-static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t addr, int len)
+static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
{
-PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, addr);
+PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
+uint32_t addr;
+uint32_t limit;
if (!pci_dev) {
return ~0x0;
}
-return pci_host_config_read_common(pci_dev, PCIE_MMCFG_CONFOFFSET(addr),
- pci_config_size(pci_dev), len);
+addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
+limit = pci_config_size(pci_dev);
+if (limit <= addr) {
+/* conventional pci device can be behind pcie-to-pci bridge.
+ 256 <= addr < 4K has no effects. */
+return ~0x0;
+}
+return pci_host_config_read_common(pci_dev, addr, limit, len);
}
static void pcie_mmcfg_data_writeb(void *opaque,
--
1.7.1.1
--
yamahata
Re: [Qemu-devel] [PATCH v2] pci: Common overflow prevention
On Thu, Jul 28, 2011 at 11:40:21AM +0300, Michael S. Tsirkin wrote:
> On Thu, Jul 28, 2011 at 04:23:24PM +0900, Isaku Yamahata wrote:
> > This might be a bit late comment...
> >
> > On Fri, Jul 22, 2011 at 11:05:01AM +0200, Jan Kiszka wrote:
> > > diff --git a/hw/pci_host.c b/hw/pci_host.c
> > > index 728e2d4..bfdc321 100644
> > > --- a/hw/pci_host.c
> > > +++ b/hw/pci_host.c
> > > @@ -47,17 +47,33 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus
> > > *bus, uint32_t addr)
> > > return pci_find_device(bus, bus_num, devfn);
> > > }
> > >
> > > +void pci_config_write_common(PCIDevice *pci_dev, uint32_t addr,
> > > + uint32_t limit, uint32_t val, uint32_t len)
> > > +{
> > > +assert(len <= 4);
> > > +pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
> > > +}
> > > +
> > > +uint32_t pci_config_read_common(PCIDevice *pci_dev, uint32_t addr,
> > > +uint32_t limit, uint32_t len)
> > > +{
> > > +assert(len <= 4);
> > > +return pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
> > > +}
> > > +
> >
> > Since limit and addr is unsigned, MIN(len, limit - addr) = len if limit <
> > addr.
> > So we need explicit "if (limit < addr) return;".
> > Here's the patch for pci branch.
> >
> > >From 75c1a2b47c93ad987cd7a37fb62bda9a59f27948 Mon Sep 17 00:00:00 2001
> > Message-Id:
> > <75c1a2b47c93ad987cd7a37fb62bda9a59f27948.1311837763.git.yamah...@valinux.co.jp>
> > From: Isaku Yamahata
> > Date: Thu, 28 Jul 2011 16:20:28 +0900
> > Subject: [PATCH] pci/host: limit check of pci_host_config_read/write_common
> >
> > This patch adds boundary check in pci_host_config_read/write_common()
> > Since limit and addr is unsigned, MIN(len, limit - addr) = len if limit <
> > addr.
> > So we need explicit "if (limit <= addr) return;"
> >
> > Signed-off-by: Isaku Yamahata
>
> I don't see a problem with this, but could you please clarify when does
> this happen? I think this is only possible for a pci device
> behind an express root. If so, this belongs in pcie_host.c
Right. I'll move the check into pcie_host.c
--
yamahata
Re: [Qemu-devel] [PATCH v2] pci: Common overflow prevention
This might be a bit late comment...
On Fri, Jul 22, 2011 at 11:05:01AM +0200, Jan Kiszka wrote:
> diff --git a/hw/pci_host.c b/hw/pci_host.c
> index 728e2d4..bfdc321 100644
> --- a/hw/pci_host.c
> +++ b/hw/pci_host.c
> @@ -47,17 +47,33 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus
> *bus, uint32_t addr)
> return pci_find_device(bus, bus_num, devfn);
> }
>
> +void pci_config_write_common(PCIDevice *pci_dev, uint32_t addr,
> + uint32_t limit, uint32_t val, uint32_t len)
> +{
> +assert(len <= 4);
> +pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
> +}
> +
> +uint32_t pci_config_read_common(PCIDevice *pci_dev, uint32_t addr,
> +uint32_t limit, uint32_t len)
> +{
> +assert(len <= 4);
> +return pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
> +}
> +
Since limit and addr is unsigned, MIN(len, limit - addr) = len if limit < addr.
So we need explicit "if (limit < addr) return;".
Here's the patch for pci branch.
>From 75c1a2b47c93ad987cd7a37fb62bda9a59f27948 Mon Sep 17 00:00:00 2001
Message-Id:
<75c1a2b47c93ad987cd7a37fb62bda9a59f27948.1311837763.git.yamah...@valinux.co.jp>
From: Isaku Yamahata
Date: Thu, 28 Jul 2011 16:20:28 +0900
Subject: [PATCH] pci/host: limit check of pci_host_config_read/write_common
This patch adds boundary check in pci_host_config_read/write_common()
Since limit and addr is unsigned, MIN(len, limit - addr) = len if limit < addr.
So we need explicit "if (limit <= addr) return;"
Signed-off-by: Isaku Yamahata
---
hw/pci_host.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/pci_host.c b/hw/pci_host.c
index 2e8a29f..71fd3a1 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -51,6 +51,9 @@ void pci_host_config_write_common(PCIDevice *pci_dev,
uint32_t addr,
uint32_t limit, uint32_t val, uint32_t len)
{
assert(len <= 4);
+if (limit <= addr) {
+return;
+}
pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
}
@@ -58,6 +61,9 @@ uint32_t pci_host_config_read_common(PCIDevice *pci_dev,
uint32_t addr,
uint32_t limit, uint32_t len)
{
assert(len <= 4);
+if (limit <= addr) {
+return 0;
+}
return pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
}
--
1.7.1.1
--
yamahata
Re: [Qemu-devel] [PATCH] pci: Length-align config space accesses
On Wed, Jul 20, 2011 at 06:18:43PM +0200, Jan Kiszka wrote:
> On 2011-07-20 18:17, Isaku Yamahata wrote:
> > On Wed, Jul 20, 2011 at 04:27:08PM +0200, Jan Kiszka wrote:
> >> On 2011-07-20 14:15, Jan Kiszka wrote:
> >>> On 2011-07-20 14:00, Isaku Yamahata wrote:
> >>>> Hi. This clean up looks good basically.
> >>>
> >>> Oops, forgot to cc you. Sorry.
> >>>
> >>>> But when conventional pci device is accessed via MMCONFIG area,
> >>>> addr &= addr_mask doesn't work as expected.
> >>>> The config area of [256, 4K) of conventional pci should have no effect.
> >>>
> >>> Mmh, I see. Looks like we need to split accesses at this boundary and
> >>> executed them separately.
> >>
> >> Nope, no such issue: we already automatically split up accesses that
> >> span the legacy/extended boundary. Just like so far, legacy config space
> >> handlers have to filter out requests that address regions >= 256.
> >
> > For example, when accessing to offset 257 of conventional pci device,
> > the access is routed to offset 1 due to the masking.
> > Such overwrapping isn't correct.
>
> No, it isn't routed like that. The mask used via mmio is 0xfff.
Ah sorry, you're right.
So pci_default_{read, write}_config() need to check it.
--
yamahata
Re: [Qemu-devel] [PATCH] pci: Length-align config space accesses
On Wed, Jul 20, 2011 at 04:27:08PM +0200, Jan Kiszka wrote: > On 2011-07-20 14:15, Jan Kiszka wrote: > > On 2011-07-20 14:00, Isaku Yamahata wrote: > >> Hi. This clean up looks good basically. > > > > Oops, forgot to cc you. Sorry. > > > >> But when conventional pci device is accessed via MMCONFIG area, > >> addr &= addr_mask doesn't work as expected. > >> The config area of [256, 4K) of conventional pci should have no effect. > > > > Mmh, I see. Looks like we need to split accesses at this boundary and > > executed them separately. > > Nope, no such issue: we already automatically split up accesses that > span the legacy/extended boundary. Just like so far, legacy config space > handlers have to filter out requests that address regions >= 256. For example, when accessing to offset 257 of conventional pci device, the access is routed to offset 1 due to the masking. Such overwrapping isn't correct. -- yamahata
Re: [Qemu-devel] [PATCH] pci: Length-align config space accesses
Hi. This clean up looks good basically.
But when conventional pci device is accessed via MMCONFIG area,
addr &= addr_mask doesn't work as expected.
The config area of [256, 4K) of conventional pci should have no effect.
thanks,
On Tue, Jul 19, 2011 at 11:39:02PM +0200, Jan Kiszka wrote:
> From: Jan Kiszka
>
> Introduce pci_config_read/write helpers to split up config space
> accesses that are not length-aligned. This particularly avoids that each
> and every device needs to check for config space overruns. Also move the
> access length assertion to the new helpers.
>
> Signed-off-by: Jan Kiszka
> ---
>
> This will also simplify my cap refactorings for the device-assignment
> code in qemu-kvm.
>
> hw/pci.c | 43 +++
> hw/pci.h |5 +
> hw/pci_host.c | 14 ++
> hw/pcie_host.c | 12 ++--
> 4 files changed, 56 insertions(+), 18 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index b904a4e..6957ece 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1104,12 +1104,48 @@ static void pci_update_irq_disabled(PCIDevice *d, int
> was_irq_disabled)
> }
> }
>
> +void pci_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t addr_mask,
> + uint32_t val, uint32_t len)
> +{
> +assert(len == 1 || len == 2 || len == 4);
> +
> +addr &= addr_mask;
> +
> +if (addr & (len - 1)) {
> +len >>= 1;
> +pci_config_write(pci_dev, addr, addr_mask, val, len);
> +pci_config_write(pci_dev, addr + len, addr_mask,
> + val >> (len * 8), len);
> +} else {
> +pci_dev->config_write(pci_dev, addr, val, len);
> +}
> +}
> +
> +uint32_t pci_config_read(PCIDevice *pci_dev, uint32_t addr, uint32_t
> addr_mask,
> + uint32_t len)
> +{
> +uint32_t val;
> +
> +assert(len == 1 || len == 2 || len == 4);
> +
> +addr &= addr_mask;
> +
> +if (addr & (len - 1)) {
> +len >>= 1;
> +val = pci_config_read(pci_dev, addr, addr_mask, len);
> +val |= pci_config_read(pci_dev, addr + len,
> + addr_mask, len) << (len * 8);
> +} else {
> +val = pci_dev->config_read(pci_dev, addr, len);
> +}
> +return val;
> +}
> +
> uint32_t pci_default_read_config(PCIDevice *d,
> uint32_t address, int len)
> {
> uint32_t val = 0;
> -assert(len == 1 || len == 2 || len == 4);
> -len = MIN(len, pci_config_size(d) - address);
> +
> memcpy(&val, d->config + address, len);
> return le32_to_cpu(val);
> }
> @@ -1117,9 +1153,8 @@ uint32_t pci_default_read_config(PCIDevice *d,
> void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int
> l)
> {
> int i, was_irq_disabled = pci_irq_disabled(d);
> -uint32_t config_size = pci_config_size(d);
>
> -for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
> +for (i = 0; i < l; val >>= 8, ++i) {
> uint8_t wmask = d->wmask[addr + i];
> uint8_t w1cmask = d->w1cmask[addr + i];
> assert(!(wmask & w1cmask));
> diff --git a/hw/pci.h b/hw/pci.h
> index c220745..3d5b39c 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -482,4 +482,9 @@ static inline uint32_t pci_config_size(const PCIDevice *d)
> return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE :
> PCI_CONFIG_SPACE_SIZE;
> }
>
> +void pci_config_write(PCIDevice *pci_dev, uint32_t addr, uint32_t addr_mask,
> + uint32_t val, uint32_t len);
> +uint32_t pci_config_read(PCIDevice *pci_dev, uint32_t addr, uint32_t
> addr_mask,
> + uint32_t len);
> +
> #endif
> diff --git a/hw/pci_host.c b/hw/pci_host.c
> index 728e2d4..db888fb 100644
> --- a/hw/pci_host.c
> +++ b/hw/pci_host.c
> @@ -50,30 +50,28 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus
> *bus, uint32_t addr)
> void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
> {
> PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
> -uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
>
> -if (!pci_dev)
> +if (!pci_dev) {
> return;
> +}
>
> PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n",
> -__func__, pci_dev->name, config_addr, val, len);
> -pci_dev->config_write(pci_dev, config_addr, val, len);
> +__func__, pci_dev->name, addr, val, len);
> +pci_config_write(pci_dev, addr, PCI_CONFIG_SPACE_SIZE - 1, val, len);
> }
>
> uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
> {
> PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
> -uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
> uint32_t val;
>
> -assert(len == 1 || len == 2 || len == 4);
> if (!pci_dev) {
> return ~0x0;
> }
>
> -val = pci_dev->config_read(pci_dev, config_addr, len);
> +val = pci_config_read(pci_dev, addr, PCI_C
Re: [Qemu-devel] [PATCH] Fix duplicate device reset
On Tue, Jul 19, 2011 at 07:56:41AM +0200, Stefan Weil wrote: > Am 19.07.2011 04:39, schrieb Isaku Yamahata: >> Thank you for addressing this. Similar patches were proposed and >> weren't merged unfortunately. >> >> The reason why the qdev_register_reset() in vl.c is to keep the reset order. >> The reset for main_system_bus shouldn't registered by qbus_create_inplace(). >> But the check, bus != main_system_bus, doesn't work as intended because >> main_system_bus is NULL in early qdev creation. >> So there are possible ways for the fix. >> >> - Don't care the reset order >>your patch + >>remove "if (bus != main_system_bus)" in qbus_create_inplace() >> >> - keep the reset order >>- instantiate main_system_bus early. >> So the check, bus != main_system_bus in qbus_create_inplace(), will >> work. >>or >>- fix the check, bus != main_system_bus in qbus_create_inplace(), somehow >> >> thanks, > > Hi, > > my patch does not remove sysbus_get_default(), > so the reset order is kept because main_system_bus > is instantiated by this call. Yes, your patch doesn't change the order from the existing code. I think it's not intended one. During machine creation, someone may call sysbus_get_default(). So the reset for main_system_bus may not be the lastly registered. The changeset of 80376c3f tries to keep the reset order, but failed. That's the issue. -- yamahata
Re: [Qemu-devel] [PATCH] Fix duplicate device reset
Thank you for addressing this. Similar patches were proposed and weren't merged unfortunately. The reason why the qdev_register_reset() in vl.c is to keep the reset order. The reset for main_system_bus shouldn't registered by qbus_create_inplace(). But the check, bus != main_system_bus, doesn't work as intended because main_system_bus is NULL in early qdev creation. So there are possible ways for the fix. - Don't care the reset order your patch + remove "if (bus != main_system_bus)" in qbus_create_inplace() - keep the reset order - instantiate main_system_bus early. So the check, bus != main_system_bus in qbus_create_inplace(), will work. or - fix the check, bus != main_system_bus in qbus_create_inplace(), somehow thanks, On Mon, Jul 18, 2011 at 10:22:26PM +0200, Stefan Weil wrote: > qbus_reset_all_fn was registered twice, so a lot of device reset > functions were also called twice when QEMU started. > > It is sufficient to call sysbus_get_default() which will > register qbus_reset_all_fn. > > Signed-off-by: Stefan Weil > --- > vl.c |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/vl.c b/vl.c > index fcd7395..fb2f6db 100644 > --- a/vl.c > +++ b/vl.c > @@ -3301,7 +3301,7 @@ int main(int argc, char **argv, char **envp) > > /* TODO: once all bus devices are qdevified, this should be done > * when bus is created by qdev.c */ > -qemu_register_reset(qbus_reset_all_fn, sysbus_get_default()); > +sysbus_get_default(); > qemu_run_machine_init_done_notifiers(); > > qemu_system_reset(VMRESET_SILENT); > -- > 1.7.2.5 > -- yamahata
Re: [Qemu-devel] [PATCH] pci: add standard bridge device
On Mon, Jul 04, 2011 at 12:43:59PM +0300, Michael S. Tsirkin wrote:
> +/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
> + * revision 1.2 */
> +/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
> +static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
> +{
> +return (irq_num + PCI_SLOT(dev->devfn) + irq_num) % PCI_NUM_PINS;
^^^ ^^^
Typo. There are 2 irq_num.
--
yamahata
Re: [Qemu-devel] [PATCH 01/10] ppce500: move device/vendor/class id to qdev
On Tue, Jun 14, 2011 at 08:35:20PM +0300, Michael S. Tsirkin wrote:
> Signed-off-by: Michael S. Tsirkin
> ---
> hw/ppce500_pci.c | 13 +++--
> 1 files changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
> index 069af96..fc11af4 100644
> --- a/hw/ppce500_pci.c
> +++ b/hw/ppce500_pci.c
> @@ -304,20 +304,13 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
> return 0;
> }
>
> -static int e500_host_bridge_initfn(PCIDevice *dev)
> -{
> -pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_FREESCALE);
> -pci_config_set_device_id(dev->config, PCI_DEVICE_ID_MPC8533E);
> -pci_config_set_class(dev->config, PCI_CLASS_PROCESSOR_POWERPC);
> -
> -return 0;
> -}
> -
> static PCIDeviceInfo e500_host_bridge_info = {
> .qdev.name= "e500-host-bridge",
> .qdev.desc= "Host bridge",
> .qdev.size= sizeof(PCIDevice),
> -.init = e500_host_bridge_initfn,
> +.vendor_id= PCI_VENDOR_ID_FREESCALE,
> +.device_id= PCI_DEVICE_ID_MPC8533E,
> +.class_id = PCI_CLASS_PROCESSOR_POWERPC,
> };
>
> static SysBusDeviceInfo e500_pcihost_info = {
> --
> 1.7.5.53.gc233e
>
Now PCIDeviceInfo::init is NULL. So we want the following patch.
>From 45ea80e32966bf8105e56b7d08926d1e6675ae48 Mon Sep 17 00:00:00 2001
Message-Id:
<45ea80e32966bf8105e56b7d08926d1e6675ae48.1308091239.git.yamah...@valinux.co.jp>
In-Reply-To:
References:
From: Isaku Yamahata
Date: Wed, 15 Jun 2011 07:37:47 +0900
Subject: [PATCH] pci: don't call qdev pci init method
As pci id initialization is moved to common layer,
some initialization function can be empty.
So don't call init method if NULL.
Signed-off-by: Isaku Yamahata
---
hw/pci.c | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index ba0598b..b904a4e 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1681,10 +1681,12 @@ static int pci_qdev_init(DeviceState *qdev, DeviceInfo
*base)
do_pci_unregister_device(pci_dev);
return -1;
}
-rc = info->init(pci_dev);
-if (rc != 0) {
-do_pci_unregister_device(pci_dev);
-return rc;
+if (info->init) {
+rc = info->init(pci_dev);
+if (rc != 0) {
+do_pci_unregister_device(pci_dev);
+return rc;
+}
}
/* rom loading */
--
1.7.1.1
--
yamahata
Re: [Qemu-devel] [PATCH 05/10] wdt: remove unused variables
It seems that I overlooked the variable when pci id conversion.
Acked-off-by: Isaku Yamahata
On Tue, Jun 14, 2011 at 08:35:52PM +0300, Michael S. Tsirkin wrote:
> Signed-off-by: Michael S. Tsirkin
> ---
> hw/wdt_i6300esb.c |3 ---
> 1 files changed, 0 insertions(+), 3 deletions(-)
>
> diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
> index bd57fd3..53786ce 100644
> --- a/hw/wdt_i6300esb.c
> +++ b/hw/wdt_i6300esb.c
> @@ -381,7 +381,6 @@ static const VMStateDescription vmstate_i6300esb = {
> static int i6300esb_init(PCIDevice *dev)
> {
> I6300State *d = DO_UPCAST(I6300State, dev, dev);
> -uint8_t *pci_conf;
> int io_mem;
> static CPUReadMemoryFunc * const mem_read[3] = {
> i6300esb_mem_readb,
> @@ -399,8 +398,6 @@ static int i6300esb_init(PCIDevice *dev)
> d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
> d->previous_reboot_flag = 0;
>
> -pci_conf = d->dev.config;
> -
> io_mem = cpu_register_io_memory(mem_read, mem_write, d,
> DEVICE_NATIVE_ENDIAN);
> pci_register_bar_simple(&d->dev, 0, 0x10, 0, io_mem);
> --
> 1.7.5.53.gc233e
>
--
yamahata
Re: [Qemu-devel] [PATCH] v6 revamp acpitable parsing and allow to specify complete (headerful) table
No more comments on the patch?
All comments were addressed and there is no comments so far.
And this patch only adds one more option to -acpi, thus it's quite safe
to merge this patch. So please pick this patch up.
Anyway who is the maintainer of acpi.c(or acpi related files)?
According to MAINTAINER file, there is no specific assigned maintainer.
By using git log, I found some people involved and added them to Cc.
If the lack of maintainer is the issue, I'm willing to stand up
(unless Michael Tokarev wants to be.)
thanks
On Sat, Jun 11, 2011 at 02:29:38AM +0400, Michael Tokarev wrote:
> I've given up on this one. Personally I don't need
> this stuff for my win7 guests since I can hack either
> bios or the O/S loader to include all the necessary
> verifications for the win7 activation to work. I
> tried to make this process to be legal (no hacks
> or "cracks" needed) and easy for others, but since
> noone is interested in this after 6 versions and 5
> resends, I wont continue - what I am trying to achieve
> by pushing this so hard, after all?
>
> Thanks to everyone who gave (mostly code style) comments -
> at least I know the changes has been read by someone.
>
> Frustrated,
> /mjt
>
> 12.05.2011 18:44, Michael Tokarev wrote:
> > This patch almost rewrites acpi_table_add() function
> > (but still leaves it using old get_param_value() interface).
> > The result is that it's now possible to specify whole table
> > (together with a header) in an external file, instead of just
> > data portion, with a new file= parameter, but at the same time
> > it's still possible to specify header fields as before.
> >
> > Now with the checkpatch.pl formatting fixes, thanks to
> > Stefan Hajnoczi for suggestions, with changes from
> > Isaku Yamahata, and with my further refinements.
> >
> > v5: rediffed against current qemu/master.
> > v6: fix one "} else {" coding style defect (noted by Blue Swirl)
> >
> > Signed-off-by: Michael Tokarev
> > ---
> > hw/acpi.c | 292
> > ---
> > qemu-options.hx |7 +-
> > 2 files changed, 175 insertions(+), 124 deletions(-)
> >
> > diff --git a/hw/acpi.c b/hw/acpi.c
> > index ad40fb4..4316189 100644
> > --- a/hw/acpi.c
> > +++ b/hw/acpi.c
> > @@ -22,17 +22,29 @@
> >
> > struct acpi_table_header
> > {
> > -char signature [4];/* ACPI signature (4 ASCII characters) */
> > +uint16_t _length; /* our length, not actual part of the hdr */
> > + /* XXX why we have 2 length fields here? */
> > +char sig[4]; /* ACPI signature (4 ASCII characters) */
> > uint32_t length; /* Length of table, in bytes, including
> > header */
> > uint8_t revision; /* ACPI Specification minor version # */
> > uint8_t checksum; /* To make sum of entire table == 0 */
> > -char oem_id [6]; /* OEM identification */
> > -char oem_table_id [8]; /* OEM table identification */
> > +char oem_id[6]; /* OEM identification */
> > +char oem_table_id[8]; /* OEM table identification */
> > uint32_t oem_revision;/* OEM revision number */
> > -char asl_compiler_id [4]; /* ASL compiler vendor ID */
> > +char asl_compiler_id[4]; /* ASL compiler vendor ID */
> > uint32_t asl_compiler_revision; /* ASL compiler revision number */
> > } __attribute__((packed));
> >
> > +#define ACPI_TABLE_HDR_SIZE sizeof(struct acpi_table_header)
> > +#define ACPI_TABLE_PFX_SIZE sizeof(uint16_t) /* size of the extra prefix
> > */
> > +
> > +static const char dfl_hdr[ACPI_TABLE_HDR_SIZE] =
> > +"\0\0" /* fake _length (2) */
> > +"QEMU\0\0\0\0\1\0" /* sig (4), len(4), revno (1), csum (1) */
> > +"QEMUQEQEMUQEMU\1\0\0\0" /* OEM id (6), table (8), revno (4) */
> > +"QEMU\1\0\0\0" /* ASL compiler ID (4), version (4) */
> > +;
> > +
> > char *acpi_tables;
> > size_t acpi_tables_len;
> >
> > @@ -45,158 +57,192 @@ static int acpi_checksum(const uint8_t *data, int len)
> > return (-sum) & 0xff;
> > }
> >
> > +/* like strncpy() but zero-fills the tail of destination */
> > +static void strzcpy(char *dst, const char *src, size_t size)
> > +{
> > +size_t len = strlen(src);
> > +if (len >= size) {
> > +len = size;
> > +} else {
> > + memset(dst
Re: [Qemu-devel] [PATCH] pci: Update pci_regs header
pcie_aer.c change looks good. Thanks. On Thu, Jun 09, 2011 at 09:18:30AM +0200, Jan Kiszka wrote: > From: Jan Kiszka > > Pulls in latest version from kernel 3.0-rc2. > > Some changes around AER now require local defines as QEMU accesses the > error source identification register via sub-words. > > CC: Isaku Yamahata > Signed-off-by: Jan Kiszka > --- > > I don't think the #define requirements of pcie_aer are upstream > compatible, therefore private constants. > > This will allow to drop libpci build dependency from qemu-kvm. > > hw/pci_regs.h | 60 > hw/pcie_aer.c |9 ++- > 2 files changed, 62 insertions(+), 7 deletions(-) > > diff --git a/hw/pci_regs.h b/hw/pci_regs.h > index 5a5ab89..e884096 100644 > --- a/hw/pci_regs.h > +++ b/hw/pci_regs.h > @@ -300,12 +300,22 @@ > #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit > devices */ > #define PCI_MSI_MASK_64 16 /* Mask bits register for > 64-bit devices */ > > -/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */ > +/* MSI-X registers */ > #define PCI_MSIX_FLAGS 2 > #define PCI_MSIX_FLAGS_QSIZE0x7FF > #define PCI_MSIX_FLAGS_ENABLE (1 << 15) > #define PCI_MSIX_FLAGS_MASKALL (1 << 14) > -#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) > +#define PCI_MSIX_TABLE 4 > +#define PCI_MSIX_PBA 8 > +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) > + > +/* MSI-X entry's format */ > +#define PCI_MSIX_ENTRY_SIZE 16 > +#define PCI_MSIX_ENTRY_LOWER_ADDR 0 > +#define PCI_MSIX_ENTRY_UPPER_ADDR 4 > +#define PCI_MSIX_ENTRY_DATA 8 > +#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 > +#define PCI_MSIX_ENTRY_CTRL_MASKBIT1 > > /* CompactPCI Hotswap Register */ > > @@ -365,6 +375,11 @@ > #define PCI_X_STATUS_266MHZ 0x4000 /* 266 MHz capable */ > #define PCI_X_STATUS_533MHZ 0x8000 /* 533 MHz capable */ > > +/* PCI Bridge Subsystem ID registers */ > + > +#define PCI_SSVID_VENDOR_ID 4/* PCI-Bridge subsystem vendor id > register */ > +#define PCI_SSVID_DEVICE_ID 6/* PCI-Bridge subsystem device id > register */ > + > /* PCI Express capability registers */ > > #define PCI_EXP_FLAGS2 /* Capabilities register */ > @@ -420,7 +435,7 @@ > #define PCI_EXP_LNKCAP_L0SEL0x7000 /* L0s Exit Latency */ > #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ > #define PCI_EXP_LNKCAP_CLKPM0x0004 /* L1 Clock Power Management > */ > -#define PCI_EXP_LNKCAP_SDERC0x0008 /* Suprise Down Error > Reporting Capable */ > +#define PCI_EXP_LNKCAP_SDERC0x0008 /* Surprise Down Error > Reporting Capable */ > #define PCI_EXP_LNKCAP_DLLLARC 0x0010 /* Data Link Layer Link > Active Reporting Capable */ > #define PCI_EXP_LNKCAP_LBNC 0x0020 /* Link Bandwidth Notification > Capability */ > #define PCI_EXP_LNKCAP_PN 0xff00 /* Port Number */ > @@ -437,7 +452,10 @@ > #define PCI_EXP_LNKCTL_LABIE0x0800 /* Lnk Autonomous Bandwidth > Interrupt Enable */ > #define PCI_EXP_LNKSTA 18 /* Link Status */ > #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ > +#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ > +#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ > #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ > +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ > #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ > #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ > #define PCI_EXP_LNKSTA_DLLLA0x2000 /* Data Link Layer Link Active > */ > @@ -486,10 +504,22 @@ > #define PCI_EXP_RTCTL_CRSSVE0x10/* CRS Software Visibility > Enable */ > #define PCI_EXP_RTCAP30 /* Root Capabilities */ > #define PCI_EXP_RTSTA32 /* Root Status */ > +#define PCI_EXP_RTSTA_PME0x1 /* PME status */ > +#define PCI_EXP_RTSTA_PENDING0x2 /* PME pending */ > #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ > #define PCI_EXP_DEVCAP2_ARI 0x20/* Alternative Routing-ID */ > +#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */ > +#define PCI_EXP_OBFF_MASK 0xc /* OBFF support mechanism */ > +#define PCI_EXP_OBFF_MSG0x4 /* New message signaling */ > +#define PCI_EXP_OBFF_WAKE 0x8 /* Re-use WAKE# for OBFF */ > #define
Re: [Qemu-devel] [PATCH v3 00/39] pci: initialize ids in pci common code
Ping? On Wed, May 25, 2011 at 10:57:57AM +0900, Isaku Yamahata wrote: > Okay, here is the v3 as there seems no more comments on the series. > > patch descriptions: > vender id/device id... in pci configuration space are read-only registers > which are commonly defined for all pci devices. > So initialize them in common code and it simplifies the initialization a bit. > Potentially in the future, qemu would be able to list supported devices > with device id and so on possibly with more updated description by linking > libpci. > > v2 -> v3: > - eliminated redandant comments > - converted virtio-pci > > changes v1 -> v2: > - dropped header_type and prog_interface > - converted more > > Isaku Yamahata (39): > pci: move ids of config space into PCIDeviceInfo > usb-uhci: convert to PCIDEviceInfo to initialize ids > eepro100: convert to PCIDeviceInfo to initialize ids > dec_pci: convert to PCIDeviceInfo to initialize ids > apb_pci: convert to PCIDeviceInfo to initialize ids > ide/piix: convert to PCIDeviceInfo to initialize ids > vmware_vga.c: convert to PCIDeviceInfo to initialize ids > hw/ac97.c: convert to PCIDeviceInfo to initialize ids > hw/acpi_piix4.c: convert to PCIDeviceInfo to initialize ids > hw/bonito.c: convert to PCIDeviceInfo to initialize ids > hw/cirrus_vga.c: convert to PCIDeviceInfo to initialize ids > hw/e1000.c: convert to PCIDeviceInfo to initialize ids > hw/es1370.c: convert to PCIDeviceInfo to initialize ids > hw/grackle_pci.c: convert to PCIDeviceInfo to initialize ids > hw/gt64xxx.c: convert to PCIDeviceInfo to initialize ids > hw/ide/cmd646.c: convert to PCIDeviceInfo to initialize ids > hw/ide/ich.c: convert to PCIDeviceInfo to initialize ids > hw/ide/via.c: convert to PCIDeviceInfo to initialize ids > hw/intel-hda.c: convert to PCIDeviceInfo to initialize ids > hw/ioh3420.c: convert to PCIDeviceInfo to initialize ids > hw/ivshmem.c: convert to PCIDeviceInfo to initialize ids > hw/lsi53c895a.c: convert to PCIDeviceInfo to initialize ids > hw/ne2000.c: convert to PCIDeviceInfo to initialize ids > hw/pcnet-pci.c: convert to PCIDeviceInfo to initialize ids > hw/piix4.c: convert to PCIDeviceInfo to initialize ids > hw/piix_pci.c: convert to PCIDeviceInfo to initialize ids > hw/qxl.c: convert to PCIDeviceInfo to initialize ids > hw/rtl8139.c: convert to PCIDeviceInfo to initialize ids > hw/sh_pci.c: convert to PCIDeviceInfo to initialize ids > hw/sun4u.c: convert to PCIDeviceInfo to initialize ids > hw/unin_pci.c: convert to PCIDeviceInfo to initialize ids > hw/usb-ohci.c: convert to PCIDeviceInfo to initialize ids > hw/versatile_pci.c: convert to PCIDeviceInfo to initialize ids > hw/vga-pci.c: convert to PCIDeviceInfo to initialize ids > hw/vt82c686.c: convert to PCIDeviceInfo to initialize ids > hw/wdt_i6300esb.c: convert to PCIDeviceInfo to initialize ids > hw/xio3130_downstream.c: convert to PCIDeviceInfo to initialize ids > hw/xio3130_upstream.c: convert to PCIDeviceInfo to initialize ids > virtio-pci.c: convert to PCIDEviceInfo to initialize ids > > hw/ac97.c |9 ++--- > hw/acpi_piix4.c |8 ++-- > hw/apb_pci.c| 13 > hw/bonito.c |9 +++-- > hw/cirrus_vga.c | 10 +++--- > hw/dec_pci.c| 26 > hw/e1000.c |8 ++-- > hw/eepro100.c | 74 > +-- > hw/es1370.c | 24 +++ > hw/grackle_pci.c|8 ++-- > hw/gt64xxx.c|8 ++-- > hw/ide/cmd646.c | 10 ++ > hw/ide/ich.c|9 ++--- > hw/ide/piix.c | 32 ++-- > hw/ide/via.c|8 ++-- > hw/intel-hda.c |8 ++-- > hw/ioh3420.c|7 ++-- > hw/ivshmem.c|8 ++--- > hw/lsi53c895a.c | 13 ++-- > hw/ne2000.c |6 ++-- > hw/pci.c| 46 - > hw/pci.h|7 > hw/pcnet-pci.c |8 ++-- > hw/piix4.c | 10 ++ > hw/piix_pci.c | 19 --- > hw/qxl.c|7 ++-- > hw/rtl8139.c|8 ++-- > hw/sh_pci.c |4 +- > hw/sun4u.c |8 ++-- > hw/unin_pci.c | 33 ++--- > hw/usb-ohci.c |7 ++-- > hw/usb-uhci.c | 46 +++-- > hw/versatile_pci.c |8 ++-- > hw/vga-pci.c| 11 +++ > hw/virtio-pci.c | 69 +++ > hw/vmware_vga.c | 13 > hw/vt82c686.c | 35 ++ > hw/wdt_i6300esb.c |6 ++-- > hw/xio3130_downstream.c |6 ++-- > hw/xio3130_upstream.c |6 ++-- > 40 files changed, 300 insertions(+), 355 deletions(-) > > -- yamahata
Re: [Qemu-devel] [PATCH 6/7] msix: Align MSI-X constants to libpci definitions and extend them
On Wed, Jun 08, 2011 at 12:26:44PM +0200, Jan Kiszka wrote: > Add PCI_MSIX_TABLE and PCI_MSIX_PBA, align other MSIX related constant > names to libpci style. Will be used for device assignment code in > qemu-kvm. So since libpci would be used by qemu, you are claiming that it should be switched to libpci style from Linux pci_regs.h? -- yamahata
Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support
On Wed, May 25, 2011 at 09:15:55AM +0200, Jan Kiszka wrote:
> FWIW, patch below fixes UHCI here. I suspect more bugs in this area as
> accessing the chip_config registers appears to rely on the host being
> little endian (direct memcpy).
>
> In contrast, the PCI mapping issue turned out to be a read herring. The
> unmapped regions were actually ROM BARs which are usually unmapped. And
> the network issues were related to an outdated DSDT. Somehow rebuilding
> Seabios did not always properly regenerate them, so my polarity fixes
> were not inluded. Haven't looked into details, but deleting out/ and
> src/*.hex resolved that.
Good catch. I queued it in my repo.
>
> I'll have to put this topic aside for now as it looks like we don't
> depend on it for PCIe pass-through. Still, it's a cool thing, and I
> would be happy to find it upstream soon!
>
> Jan
>
> --8<---
>
> From: Jan Kiszka
> Subject: [PATCH] q35: Fix irr initialization for slots 25..31
>
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
>
> Signed-off-by: Jan Kiszka
> ---
> hw/q35.c | 10 +++---
> 1 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/hw/q35.c b/hw/q35.c
> index a06ea7d..0ab8532 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -424,14 +424,18 @@ static void ich9_cc_update_ir(uint8_t
> irr[PCI_NUM_PINS], uint32_t ir)
> static void ich9_cc_update(ICH9_LPCState *lpc)
> {
> int slot;
> -int reg_offset;
> +int reg;
> int intx;
>
> /* D{25 - 31}IR, but D30IR is read only to 0. */
> -for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> +for (slot = 31, reg = ICH9_CC_D31IR; slot >= 25; slot--, reg += 2) {
> if (slot != 30) {
> ich9_cc_update_ir(lpc->irr[slot],
> - lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> + lpc->chip_config[reg] |
> + (uint32_t)lpc->chip_config[reg + 1] << 8);
> +}
> +if (slot <= 27) {
> +reg += 2;
> }
> }
>
> --
> 1.7.1
>
--
yamahata
[Qemu-devel] [PATCH v3 11/39] hw/cirrus_vga.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/cirrus_vga.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 722cac7..79874b1 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -3097,8 +3097,8 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
{
PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
CirrusVGAState *s = &d->cirrus_vga;
- uint8_t *pci_conf = d->dev.config;
- int device_id = CIRRUS_ID_CLGD5446;
+ PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->qdev.info);
+ int16_t device_id = info->device_id;
/* setup VGA */
vga_common_init(&s->vga, VGA_RAM_SIZE);
@@ -3108,9 +3108,6 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
&s->vga);
/* setup PCI */
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
- pci_config_set_device_id(pci_conf, device_id);
- pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
/* setup memory space */
/* memory #0 LFB */
@@ -3139,6 +3136,9 @@ static PCIDeviceInfo cirrus_vga_info = {
.init = pci_cirrus_vga_initfn,
.romfile = VGABIOS_CIRRUS_FILENAME,
.config_write = pci_cirrus_write_config,
+.vendor_id= PCI_VENDOR_ID_CIRRUS,
+.device_id= CIRRUS_ID_CLGD5446,
+.class_id = PCI_CLASS_DISPLAY_VGA,
};
static void cirrus_vga_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 17/39] hw/ide/ich.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ide/ich.c |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index e44339b..cb1c405 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -77,11 +77,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
struct AHCIPCIState *d;
d = DO_UPCAST(struct AHCIPCIState, card, dev);
-pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR);
-
-pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA);
-pci_config_set_revision(d->card.config, 0x02);
pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
@@ -131,6 +126,10 @@ static PCIDeviceInfo ich_ahci_info[] = {
.init = pci_ich9_ahci_init,
.exit = pci_ich9_uninit,
.config_write = pci_ich9_write_config,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82801IR,
+.revision = 0x02,
+.class_id = PCI_CLASS_STORAGE_SATA,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v3 37/39] hw/xio3130_downstream.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/xio3130_downstream.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index 5aa6a6b..d3c387d 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -69,9 +69,6 @@ static int xio3130_downstream_initfn(PCIDevice *d)
}
pcie_port_init_reg(d);
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_TI);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_TI_XIO3130D);
-d->config[PCI_REVISION_ID] = XIO3130_REVISION;
rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
@@ -182,6 +179,9 @@ static PCIDeviceInfo xio3130_downstream_info = {
.config_write = xio3130_downstream_write_config,
.init = xio3130_downstream_initfn,
.exit = xio3130_downstream_exitfn,
+.vendor_id = PCI_VENDOR_ID_TI,
+.device_id = PCI_DEVICE_ID_TI_XIO3130D,
+.revision = XIO3130_REVISION,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
--
1.7.1.1
[Qemu-devel] [PATCH v3 34/39] hw/vga-pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/vga-pci.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index ce9ec45..481f448 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -74,7 +74,6 @@ static int pci_vga_initfn(PCIDevice *dev)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
VGACommonState *s = &d->vga;
- uint8_t *pci_conf = d->dev.config;
// vga + console init
vga_common_init(s, VGA_RAM_SIZE);
@@ -83,11 +82,6 @@ static int pci_vga_initfn(PCIDevice *dev)
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
- // dummy VGA (same as Bochs ID)
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
- pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
-
/* XXX: VGA_RAM_SIZE must be a power of two */
pci_register_bar(&d->dev, 0, VGA_RAM_SIZE,
PCI_BASE_ADDRESS_MEM_PREFETCH, vga_map);
@@ -114,6 +108,11 @@ static PCIDeviceInfo vga_info = {
.init = pci_vga_initfn,
.config_write = pci_vga_write_config,
.romfile = "vgabios-stdvga.bin",
+
+/* dummy VGA (same as Bochs ID) */
+.vendor_id= PCI_VENDOR_ID_QEMU,
+.device_id= PCI_DEVICE_ID_QEMU_VGA,
+.class_id = PCI_CLASS_DISPLAY_VGA,
};
static void vga_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 39/39] virtio-pci.c: convert to PCIDEviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/virtio-pci.c | 69 --
1 files changed, 31 insertions(+), 38 deletions(-)
diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index c19629d..270e2c7 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -669,9 +669,7 @@ static const VirtIOBindings virtio_pci_bindings = {
.vmstate_change = virtio_pci_vmstate_change,
};
-static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev,
-uint16_t vendor, uint16_t device,
-uint16_t class_code, uint8_t pif)
+static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)
{
uint8_t *config;
uint32_t size;
@@ -679,19 +677,12 @@ static void virtio_init_pci(VirtIOPCIProxy *proxy,
VirtIODevice *vdev,
proxy->vdev = vdev;
config = proxy->pci_dev.config;
-pci_config_set_vendor_id(config, vendor);
-pci_config_set_device_id(config, device);
-
-config[0x08] = VIRTIO_PCI_ABI_VERSION;
-
-config[0x09] = pif;
-pci_config_set_class(config, class_code);
-
-config[0x2c] = vendor & 0xFF;
-config[0x2d] = (vendor >> 8) & 0xFF;
-config[0x2e] = vdev->device_id & 0xFF;
-config[0x2f] = (vdev->device_id >> 8) & 0xFF;
+if (proxy->class_code) {
+pci_config_set_class(config, proxy->class_code);
+}
+pci_set_word(config + 0x2c, pci_get_word(config + PCI_VENDOR_ID));
+pci_set_word(config + 0x2e, vdev->device_id);
config[0x3d] = 1;
if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) {
@@ -735,10 +726,7 @@ static int virtio_blk_init_pci(PCIDevice *pci_dev)
return -1;
}
vdev->nvectors = proxy->nvectors;
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_BLOCK,
-proxy->class_code, 0x00);
+virtio_init_pci(proxy, vdev);
/* make the actual value visible */
proxy->nvectors = vdev->nvectors;
return 0;
@@ -776,10 +764,7 @@ static int virtio_serial_init_pci(PCIDevice *pci_dev)
vdev->nvectors = proxy->nvectors == DEV_NVECTORS_UNSPECIFIED
? proxy->serial.max_virtserial_ports +
1
: proxy->nvectors;
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_CONSOLE,
-proxy->class_code, 0x00);
+virtio_init_pci(proxy, vdev);
proxy->nvectors = vdev->nvectors;
return 0;
}
@@ -801,11 +786,7 @@ static int virtio_net_init_pci(PCIDevice *pci_dev)
vdev = virtio_net_init(&pci_dev->qdev, &proxy->nic, &proxy->net);
vdev->nvectors = proxy->nvectors;
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_NET,
-PCI_CLASS_NETWORK_ETHERNET,
-0x00);
+virtio_init_pci(proxy, vdev);
/* make the actual value visible */
proxy->nvectors = vdev->nvectors;
@@ -827,11 +808,7 @@ static int virtio_balloon_init_pci(PCIDevice *pci_dev)
VirtIODevice *vdev;
vdev = virtio_balloon_init(&pci_dev->qdev);
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_BALLOON,
-PCI_CLASS_MEMORY_RAM,
-0x00);
+virtio_init_pci(proxy, vdev);
return 0;
}
@@ -843,11 +820,7 @@ static int virtio_9p_init_pci(PCIDevice *pci_dev)
vdev = virtio_9p_init(&pci_dev->qdev, &proxy->fsconf);
vdev->nvectors = proxy->nvectors;
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-0x1009,
-0x2,
-0x00);
+virtio_init_pci(proxy, vdev);
/* make the actual value visible */
proxy->nvectors = vdev->nvectors;
return 0;
@@ -861,6 +834,10 @@ static PCIDeviceInfo virtio_info[] = {
.qdev.size = sizeof(VirtIOPCIProxy),
.init = virtio_blk_init_pci,
.exit = virtio_blk_exit_pci,
+.vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET,
+.device_id = PCI_DEVICE_ID_VIRTIO_BLOCK,
+.revision = VIRTIO_PCI_ABI_VERSION,
+.class_id = PCI_CLASS_STORAGE_SCSI,
.qdev.props = (Property[]) {
DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0),
DEFINE_BLOCK_PROPERTIES(VirtIOPCIProxy, block),
@@ -878,6 +855,10 @@ static PCIDeviceInfo virtio_info[] = {
.init = virtio_net_init_pci,
.exit = virtio_net_exit_pci,
.romfile= "pxe-virtio.rom",
+
[Qemu-devel] [PATCH v3 02/39] usb-uhci: convert to PCIDEviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/usb-uhci.c | 46 +-
1 files changed, 17 insertions(+), 29 deletions(-)
diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index 346db3e..536c24c 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -1115,14 +1115,13 @@ static USBPortOps uhci_port_ops = {
.wakeup = uhci_wakeup,
};
-static int usb_uhci_common_initfn(UHCIState *s)
+static int usb_uhci_common_initfn(PCIDevice *dev)
{
+UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
uint8_t *pci_conf = s->dev.config;
int i;
-pci_conf[PCI_REVISION_ID] = 0x01; // revision number
pci_conf[PCI_CLASS_PROG] = 0x00;
-pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
/* TODO: reset value should be 0. */
pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3
pci_conf[0x60] = 0x10; // release number
@@ -1148,34 +1147,11 @@ static int usb_uhci_common_initfn(UHCIState *s)
return 0;
}
-static int usb_uhci_piix3_initfn(PCIDevice *dev)
-{
-UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
-uint8_t *pci_conf = s->dev.config;
-
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2);
-return usb_uhci_common_initfn(s);
-}
-
-static int usb_uhci_piix4_initfn(PCIDevice *dev)
-{
-UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
-uint8_t *pci_conf = s->dev.config;
-
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2);
-return usb_uhci_common_initfn(s);
-}
-
static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
{
UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
uint8_t *pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_UHCI);
-
/* USB misc control 1/2 */
pci_set_long(pci_conf + 0x40,0x1000);
/* PM capability */
@@ -1183,7 +1159,7 @@ static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
/* USB legacy support */
pci_set_long(pci_conf + 0xc0,0x2000);
-return usb_uhci_common_initfn(s);
+return usb_uhci_common_initfn(dev);
}
static PCIDeviceInfo uhci_info[] = {
@@ -1191,17 +1167,29 @@ static PCIDeviceInfo uhci_info[] = {
.qdev.name= "piix3-usb-uhci",
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
-.init = usb_uhci_piix3_initfn,
+.init = usb_uhci_common_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371SB_2,
+.revision = 0x01,
+.class_id = PCI_CLASS_SERIAL_USB,
},{
.qdev.name= "piix4-usb-uhci",
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
-.init = usb_uhci_piix4_initfn,
+.init = usb_uhci_common_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371AB_2,
+.revision = 0x01,
+.class_id = PCI_CLASS_SERIAL_USB,
},{
.qdev.name= "vt82c686b-usb-uhci",
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
.init = usb_uhci_vt82c686b_initfn,
+.vendor_id= PCI_VENDOR_ID_VIA,
+.device_id= PCI_DEVICE_ID_VIA_UHCI,
+.revision = 0x01,
+.class_id = PCI_CLASS_SERIAL_USB,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v3 09/39] hw/acpi_piix4.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/acpi_piix4.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 96f5222..232008d 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -317,13 +317,9 @@ static int piix4_pm_initfn(PCIDevice *dev)
uint8_t *pci_conf;
pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
pci_conf[0x06] = 0x80;
pci_conf[0x07] = 0x02;
-pci_conf[0x08] = 0x03; // revision number
pci_conf[0x09] = 0x00;
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
pci_conf[0x3d] = 0x01; // interrupt pin 1
pci_conf[0x40] = 0x01; /* PM io base read only bit */
@@ -394,6 +390,10 @@ static PCIDeviceInfo piix4_pm_info = {
.no_hotplug = 1,
.init = piix4_pm_initfn,
.config_write = pm_write_config,
+.vendor_id = PCI_VENDOR_ID_INTEL,
+.device_id = PCI_DEVICE_ID_INTEL_82371AB_3,
+.revision = 0x03,
+.class_id = PCI_CLASS_BRIDGE_OTHER,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v3 38/39] hw/xio3130_upstream.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/xio3130_upstream.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index a7640f5..8283695 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -65,9 +65,6 @@ static int xio3130_upstream_initfn(PCIDevice *d)
}
pcie_port_init_reg(d);
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_TI);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_TI_XIO3130U);
-d->config[PCI_REVISION_ID] = XIO3130_REVISION;
rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
@@ -159,6 +156,9 @@ static PCIDeviceInfo xio3130_upstream_info = {
.config_write = xio3130_upstream_write_config,
.init = xio3130_upstream_initfn,
.exit = xio3130_upstream_exitfn,
+.vendor_id = PCI_VENDOR_ID_TI,
+.device_id = PCI_DEVICE_ID_TI_XIO3130U,
+.revision = XIO3130_REVISION,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
--
1.7.1.1
[Qemu-devel] [PATCH v3 32/39] hw/usb-ohci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/usb-ohci.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index d21c820..7ff2322 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1716,11 +1716,7 @@ static int usb_ohci_initfn_pci(struct PCIDevice *dev)
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
int num_ports = 3;
-pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(ohci->pci_dev.config,
- PCI_DEVICE_ID_APPLE_IPID_USB);
ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
-pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
/* TODO: RST# value should be 0. */
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
@@ -1760,6 +1756,9 @@ static PCIDeviceInfo ohci_pci_info = {
.qdev.desc= "Apple USB Controller",
.qdev.size= sizeof(OHCIPCIState),
.init = usb_ohci_initfn_pci,
+.vendor_id= PCI_VENDOR_ID_APPLE,
+.device_id= PCI_DEVICE_ID_APPLE_IPID_USB,
+.class_id = PCI_CLASS_SERIAL_USB,
};
static SysBusDeviceInfo ohci_sysbus_info = {
--
1.7.1.1
[Qemu-devel] [PATCH v3 35/39] hw/vt82c686.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/vt82c686.c | 35 ---
1 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/hw/vt82c686.c b/hw/vt82c686.c
index ca8f826..5c973ed 100644
--- a/hw/vt82c686.c
+++ b/hw/vt82c686.c
@@ -326,11 +326,6 @@ static int vt82c686b_ac97_initfn(PCIDevice *dev)
VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97);
-pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO);
-pci_config_set_revision(pci_conf, 0x50);
-
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
@@ -353,6 +348,10 @@ static PCIDeviceInfo via_ac97_info = {
.qdev.desc = "AC97",
.qdev.size = sizeof(VT686AC97State),
.init = vt82c686b_ac97_initfn,
+.vendor_id = PCI_VENDOR_ID_VIA,
+.device_id = PCI_DEVICE_ID_VIA_AC97,
+.revision = 0x50,
+.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
};
static void vt82c686b_ac97_register(void)
@@ -367,11 +366,6 @@ static int vt82c686b_mc97_initfn(PCIDevice *dev)
VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97);
-pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER);
-pci_config_set_revision(pci_conf, 0x30);
-
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
PCI_COMMAND_VGA_PALETTE);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
@@ -393,6 +387,10 @@ static PCIDeviceInfo via_mc97_info = {
.qdev.desc = "MC97",
.qdev.size = sizeof(VT686MC97State),
.init = vt82c686b_mc97_initfn,
+.vendor_id = PCI_VENDOR_ID_VIA,
+.device_id = PCI_DEVICE_ID_VIA_MC97,
+.class_id = PCI_CLASS_COMMUNICATION_OTHER,
+.revision = 0x30,
};
static void vt82c686b_mc97_register(void)
@@ -409,11 +407,6 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
uint8_t *pci_conf;
pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI);
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
-pci_config_set_revision(pci_conf, 0x40);
-
pci_set_word(pci_conf + PCI_COMMAND, 0);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
PCI_STATUS_DEVSEL_MEDIUM);
@@ -462,6 +455,10 @@ static PCIDeviceInfo via_pm_info = {
.qdev.vmsd = &vmstate_acpi,
.init = vt82c686b_pm_initfn,
.config_write = pm_write_config,
+.vendor_id = PCI_VENDOR_ID_VIA,
+.device_id = PCI_DEVICE_ID_VIA_ACPI,
+.class_id = PCI_CLASS_BRIDGE_OTHER,
+.revision = 0x40,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
DEFINE_PROP_END_OF_LIST(),
@@ -496,11 +493,7 @@ static int vt82c686b_initfn(PCIDevice *d)
isa_bus_new(&d->qdev);
pci_conf = d->config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE);
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
pci_config_set_prog_interface(pci_conf, 0x0);
-pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */
wmask = d->wmask;
for (i = 0x00; i < 0xff; i++) {
@@ -531,6 +524,10 @@ static PCIDeviceInfo via_info = {
.qdev.no_user = 1,
.init = vt82c686b_initfn,
.config_write = vt82c686b_write_config,
+.vendor_id= PCI_VENDOR_ID_VIA,
+.device_id= PCI_DEVICE_ID_VIA_ISA_BRIDGE,
+.class_id = PCI_CLASS_BRIDGE_ISA,
+.revision = 0x40,
};
static void vt82c686b_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 36/39] hw/wdt_i6300esb.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/wdt_i6300esb.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index 0791721..bd57fd3 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -400,9 +400,6 @@ static int i6300esb_init(PCIDevice *dev)
d->previous_reboot_flag = 0;
pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9);
-pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);
io_mem = cpu_register_io_memory(mem_read, mem_write, d,
DEVICE_NATIVE_ENDIAN);
@@ -425,6 +422,9 @@ static PCIDeviceInfo i6300esb_info = {
.config_read = i6300esb_config_read,
.config_write = i6300esb_config_write,
.init = i6300esb_init,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_ESB_9,
+.class_id = PCI_CLASS_SYSTEM_OTHER,
};
static void i6300esb_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 10/39] hw/bonito.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/bonito.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/bonito.c b/hw/bonito.c
index 65a4a63..e8c57a3 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -691,11 +691,7 @@ static int bonito_initfn(PCIDevice *dev)
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"
*/
-pci_config_set_vendor_id(dev->config, 0xdf53);
-pci_config_set_device_id(dev->config, 0x00d5);
-pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
pci_config_set_prog_interface(dev->config, 0x00);
-pci_config_set_revision(dev->config, 0x01);
/* set the north bridge register mapping */
s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
@@ -796,6 +792,11 @@ static PCIDeviceInfo bonito_info = {
.qdev.vmsd= &vmstate_bonito,
.qdev.no_user = 1,
.init = bonito_initfn,
+/*Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"*/
+.vendor_id= 0xdf53,
+.device_id= 0x00d5,
+.revision = 0x01,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static SysBusDeviceInfo bonito_pcihost_info = {
--
1.7.1.1
[Qemu-devel] [PATCH v3 21/39] hw/ivshmem.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ivshmem.c |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index 7b19a81..3055dd2 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -706,12 +706,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
}
pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT_QUMRANET);
-pci_conf[0x02] = 0x10;
-pci_conf[0x03] = 0x11;
pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_RAM);
-pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
pci_config_set_interrupt_pin(pci_conf, 1);
@@ -809,6 +804,9 @@ static PCIDeviceInfo ivshmem_info = {
.qdev.reset = ivshmem_reset,
.init = pci_ivshmem_init,
.exit = pci_ivshmem_uninit,
+.vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET,
+.device_id = 0x1110,
+.class_id = PCI_CLASS_MEMORY_RAM,
.qdev.props = (Property[]) {
DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
DEFINE_PROP_STRING("size", IVShmemState, sizearg),
--
1.7.1.1
[Qemu-devel] [PATCH v3 15/39] hw/gt64xxx.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/gt64xxx.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index c66188f..8e1f6a0 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1118,14 +1118,10 @@ static int gt64120_init(SysBusDevice *dev)
static int gt64120_pci_init(PCIDevice *d)
{
/* FIXME: Malta specific hw assumptions ahead */
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MARVELL);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_MARVELL_GT6412X);
pci_set_word(d->config + PCI_COMMAND, 0);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
-pci_set_byte(d->config + PCI_CLASS_REVISION, 0x10);
pci_config_set_prog_interface(d->config, 0);
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x0008);
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x0108);
pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c00);
@@ -1141,6 +1137,10 @@ static PCIDeviceInfo gt64120_pci_info = {
.qdev.name = "gt64120_pci",
.qdev.size = sizeof(PCIDevice),
.init = gt64120_pci_init,
+.vendor_id = PCI_VENDOR_ID_MARVELL,
+.device_id = PCI_DEVICE_ID_MARVELL_GT6412X,
+.revision = 0x10,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static void gt64120_pci_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 08/39] hw/ac97.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ac97.c |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/ac97.c b/hw/ac97.c
index d71072d..c26a86d 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -1281,9 +1281,6 @@ static int ac97_initfn (PCIDevice *dev)
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
uint8_t *c = s->dev.config;
-pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
-pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
-
/* TODO: no need to override */
c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
c[PCI_COMMAND + 1] = 0x00;
@@ -1292,9 +1289,7 @@ static int ac97_initfn (PCIDevice *dev)
c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
-c[PCI_REVISION_ID] = 0x01; /* rid revision ro */
c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
-pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
/* TODO set when bar is registered. no need to override. */
/* nabmar native audio mixer base address rw */
@@ -1341,6 +1336,10 @@ static PCIDeviceInfo ac97_info = {
.qdev.size= sizeof (AC97LinkState),
.qdev.vmsd= &vmstate_ac97,
.init = ac97_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82801AA_5,
+.revision = 0x01,
+.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
};
static void ac97_register (void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 26/39] hw/piix_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/piix_pci.c | 19 +++
1 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 5f0d92f..b927f01 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -228,11 +228,6 @@ static int i440fx_initfn(PCIDevice *dev)
{
PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
-pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
-d->dev.config[0x08] = 0x02; // revision
-pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
-
d->dev.config[I440FX_SMRAM] = 0x02;
cpu_smm_register(&i440fx_set_smm, d);
@@ -406,15 +401,8 @@ static const VMStateDescription vmstate_piix3 = {
static int piix3_initfn(PCIDevice *dev)
{
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
-uint8_t *pci_conf;
isa_bus_new(&d->dev.qdev);
-
-pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); //
82371SB PIIX3 PCI-to-ISA bridge (Step A1)
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
-
qemu_register_reset(piix3_reset, d);
return 0;
}
@@ -429,6 +417,10 @@ static PCIDeviceInfo i440fx_info[] = {
.no_hotplug = 1,
.init = i440fx_initfn,
.config_write = i440fx_write_config,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82441,
+.revision = 0x02,
+.class_id = PCI_CLASS_BRIDGE_HOST,
},{
.qdev.name= "PIIX3",
.qdev.desc= "ISA bridge",
@@ -438,6 +430,9 @@ static PCIDeviceInfo i440fx_info[] = {
.no_hotplug = 1,
.init = piix3_initfn,
.config_write = piix3_write_config,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3
PCI-to-ISA bridge (Step A1)
+.class_id = PCI_CLASS_BRIDGE_ISA,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v3 23/39] hw/ne2000.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ne2000.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ne2000.c b/hw/ne2000.c
index b668ad1..f8acaae 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -721,9 +721,6 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
uint8_t *pci_conf;
pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
/* TODO: RST# value should be 0. PCI spec 6.2.4 */
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
@@ -767,6 +764,9 @@ static PCIDeviceInfo ne2000_info = {
.qdev.vmsd = &vmstate_pci_ne2000,
.init = pci_ne2000_init,
.exit = pci_ne2000_exit,
+.vendor_id = PCI_VENDOR_ID_REALTEK,
+.device_id = PCI_DEVICE_ID_REALTEK_8029,
+.class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v3 00/39] pci: initialize ids in pci common code
Okay, here is the v3 as there seems no more comments on the series. patch descriptions: vender id/device id... in pci configuration space are read-only registers which are commonly defined for all pci devices. So initialize them in common code and it simplifies the initialization a bit. Potentially in the future, qemu would be able to list supported devices with device id and so on possibly with more updated description by linking libpci. v2 -> v3: - eliminated redandant comments - converted virtio-pci changes v1 -> v2: - dropped header_type and prog_interface - converted more Isaku Yamahata (39): pci: move ids of config space into PCIDeviceInfo usb-uhci: convert to PCIDEviceInfo to initialize ids eepro100: convert to PCIDeviceInfo to initialize ids dec_pci: convert to PCIDeviceInfo to initialize ids apb_pci: convert to PCIDeviceInfo to initialize ids ide/piix: convert to PCIDeviceInfo to initialize ids vmware_vga.c: convert to PCIDeviceInfo to initialize ids hw/ac97.c: convert to PCIDeviceInfo to initialize ids hw/acpi_piix4.c: convert to PCIDeviceInfo to initialize ids hw/bonito.c: convert to PCIDeviceInfo to initialize ids hw/cirrus_vga.c: convert to PCIDeviceInfo to initialize ids hw/e1000.c: convert to PCIDeviceInfo to initialize ids hw/es1370.c: convert to PCIDeviceInfo to initialize ids hw/grackle_pci.c: convert to PCIDeviceInfo to initialize ids hw/gt64xxx.c: convert to PCIDeviceInfo to initialize ids hw/ide/cmd646.c: convert to PCIDeviceInfo to initialize ids hw/ide/ich.c: convert to PCIDeviceInfo to initialize ids hw/ide/via.c: convert to PCIDeviceInfo to initialize ids hw/intel-hda.c: convert to PCIDeviceInfo to initialize ids hw/ioh3420.c: convert to PCIDeviceInfo to initialize ids hw/ivshmem.c: convert to PCIDeviceInfo to initialize ids hw/lsi53c895a.c: convert to PCIDeviceInfo to initialize ids hw/ne2000.c: convert to PCIDeviceInfo to initialize ids hw/pcnet-pci.c: convert to PCIDeviceInfo to initialize ids hw/piix4.c: convert to PCIDeviceInfo to initialize ids hw/piix_pci.c: convert to PCIDeviceInfo to initialize ids hw/qxl.c: convert to PCIDeviceInfo to initialize ids hw/rtl8139.c: convert to PCIDeviceInfo to initialize ids hw/sh_pci.c: convert to PCIDeviceInfo to initialize ids hw/sun4u.c: convert to PCIDeviceInfo to initialize ids hw/unin_pci.c: convert to PCIDeviceInfo to initialize ids hw/usb-ohci.c: convert to PCIDeviceInfo to initialize ids hw/versatile_pci.c: convert to PCIDeviceInfo to initialize ids hw/vga-pci.c: convert to PCIDeviceInfo to initialize ids hw/vt82c686.c: convert to PCIDeviceInfo to initialize ids hw/wdt_i6300esb.c: convert to PCIDeviceInfo to initialize ids hw/xio3130_downstream.c: convert to PCIDeviceInfo to initialize ids hw/xio3130_upstream.c: convert to PCIDeviceInfo to initialize ids virtio-pci.c: convert to PCIDEviceInfo to initialize ids hw/ac97.c |9 ++--- hw/acpi_piix4.c |8 ++-- hw/apb_pci.c| 13 hw/bonito.c |9 +++-- hw/cirrus_vga.c | 10 +++--- hw/dec_pci.c| 26 hw/e1000.c |8 ++-- hw/eepro100.c | 74 +-- hw/es1370.c | 24 +++ hw/grackle_pci.c|8 ++-- hw/gt64xxx.c|8 ++-- hw/ide/cmd646.c | 10 ++ hw/ide/ich.c|9 ++--- hw/ide/piix.c | 32 ++-- hw/ide/via.c|8 ++-- hw/intel-hda.c |8 ++-- hw/ioh3420.c|7 ++-- hw/ivshmem.c|8 ++--- hw/lsi53c895a.c | 13 ++-- hw/ne2000.c |6 ++-- hw/pci.c| 46 - hw/pci.h|7 hw/pcnet-pci.c |8 ++-- hw/piix4.c | 10 ++ hw/piix_pci.c | 19 --- hw/qxl.c|7 ++-- hw/rtl8139.c|8 ++-- hw/sh_pci.c |4 +- hw/sun4u.c |8 ++-- hw/unin_pci.c | 33 ++--- hw/usb-ohci.c |7 ++-- hw/usb-uhci.c | 46 +++-- hw/versatile_pci.c |8 ++-- hw/vga-pci.c| 11 +++ hw/virtio-pci.c | 69 +++ hw/vmware_vga.c | 13 hw/vt82c686.c | 35 ++ hw/wdt_i6300esb.c |6 ++-- hw/xio3130_downstream.c |6 ++-- hw/xio3130_upstream.c |6 ++-- 40 files changed, 300 insertions(+), 355 deletions(-)
[Qemu-devel] [PATCH v3 05/39] apb_pci: convert to PCIDeviceInfo to initialize ids
Use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/apb_pci.c | 13 ++---
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 84e9af7..974c87a 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -304,9 +304,6 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
return rc;
}
-pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_SUN);
-pci_config_set_device_id(dev->config, PCI_DEVICE_ID_SUN_SIMBA);
-
/*
* command register:
* According to PCI bridge spec, after reset
@@ -321,7 +318,6 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
pci_set_word(dev->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
PCI_STATUS_DEVSEL_MEDIUM);
-pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
return 0;
}
@@ -436,14 +432,11 @@ static int pci_pbm_init_device(SysBusDevice *dev)
static int pbm_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
pci_set_word(d->config + PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
PCI_STATUS_DEVSEL_MEDIUM);
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
return 0;
}
@@ -451,6 +444,9 @@ static PCIDeviceInfo pbm_pci_host_info = {
.qdev.name = "pbm",
.qdev.size = sizeof(PCIDevice),
.init = pbm_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_SUN,
+.device_id = PCI_DEVICE_ID_SUN_SABRE,
+.class_id = PCI_CLASS_BRIDGE_HOST,
.is_bridge = 1,
};
@@ -468,6 +464,9 @@ static PCIDeviceInfo pbm_pci_bridge_info = {
.qdev.reset = pci_bridge_reset,
.init = apb_pci_bridge_initfn,
.exit = pci_bridge_exitfn,
+.vendor_id = PCI_VENDOR_ID_SUN,
+.device_id = PCI_DEVICE_ID_SUN_SIMBA,
+.revision = 0x11,
.config_write = pci_bridge_write_config,
.is_bridge = 1,
};
--
1.7.1.1
[Qemu-devel] [PATCH v3 31/39] hw/unin_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/unin_pci.c | 33 -
1 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index c57c0a1..d364daa 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -279,10 +279,6 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic)
static int unin_main_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
-d->config[0x08] = 0x00; // revision
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
@@ -291,10 +287,6 @@ static int unin_main_pci_host_init(PCIDevice *d)
static int unin_agp_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
-d->config[0x08] = 0x00; // revision
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
//d->config[0x34] = 0x80; // capabilities_pointer
@@ -303,11 +295,6 @@ static int unin_agp_pci_host_init(PCIDevice *d)
static int u3_agp_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
-/* revision */
-d->config[0x08] = 0x00;
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
/* cache line size */
d->config[0x0C] = 0x08;
/* latency timer */
@@ -317,10 +304,6 @@ static int u3_agp_pci_host_init(PCIDevice *d)
static int unin_internal_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
-d->config[0x08] = 0x00; // revision
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
@@ -331,24 +314,40 @@ static PCIDeviceInfo unin_main_pci_host_info = {
.qdev.name = "uni-north",
.qdev.size = sizeof(PCIDevice),
.init = unin_main_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
+.revision = 0x00,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static PCIDeviceInfo u3_agp_pci_host_info = {
.qdev.name = "u3-agp",
.qdev.size = sizeof(PCIDevice),
.init = u3_agp_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
+.revision = 0x00,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static PCIDeviceInfo unin_agp_pci_host_info = {
.qdev.name = "uni-north-agp",
.qdev.size = sizeof(PCIDevice),
.init = unin_agp_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
+.revision = 0x00,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static PCIDeviceInfo unin_internal_pci_host_info = {
.qdev.name = "uni-north-pci",
.qdev.size = sizeof(PCIDevice),
.init = unin_internal_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
+.revision = 0x00,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static void unin_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 27/39] hw/qxl.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/qxl.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/qxl.c b/hw/qxl.c
index fe4212b..63cffc3 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -1233,7 +1233,6 @@ static int qxl_init_common(PCIQXLDevice *qxl)
break;
}
-pci_config_set_vendor_id(config, REDHAT_PCI_VENDOR_ID);
pci_config_set_device_id(config, pci_device_id);
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
@@ -1310,7 +1309,6 @@ static int qxl_init_primary(PCIDevice *dev)
qxl0 = qxl;
register_displaychangelistener(vga->ds, &display_listener);
-pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_VGA);
return qxl_init_common(qxl);
}
@@ -1330,7 +1328,6 @@ static int qxl_init_secondary(PCIDevice *dev)
qxl->vga.vram_size);
qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
-pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_OTHER);
return qxl_init_common(qxl);
}
@@ -1493,6 +1490,8 @@ static PCIDeviceInfo qxl_info_primary = {
.init = qxl_init_primary,
.config_write = qxl_write_config,
.romfile = "vgabios-qxl.bin",
+.vendor_id= REDHAT_PCI_VENDOR_ID,
+.class_id = PCI_CLASS_DISPLAY_VGA,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024
* 1024),
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 *
1024),
@@ -1511,6 +1510,8 @@ static PCIDeviceInfo qxl_info_secondary = {
.qdev.reset = qxl_reset_handler,
.qdev.vmsd= &qxl_vmstate,
.init = qxl_init_secondary,
+.vendor_id= REDHAT_PCI_VENDOR_ID,
+.class_id = PCI_CLASS_DISPLAY_OTHER,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024
* 1024),
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 *
1024),
--
1.7.1.1
[Qemu-devel] [PATCH v3 33/39] hw/versatile_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/versatile_pci.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 2fed8a0..8e75ffc 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -133,12 +133,8 @@ static int pci_realview_init(SysBusDevice *dev)
static int versatile_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX);
-/* Both boards have the same device ID. Oh well. */
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_XILINX_XC2VP30);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
-pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO);
pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
return 0;
}
@@ -147,6 +143,10 @@ static PCIDeviceInfo versatile_pci_host_info = {
.qdev.name = "versatile_pci_host",
.qdev.size = sizeof(PCIDevice),
.init = versatile_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_XILINX,
+/* Both boards have the same device ID. Oh well. */
+.device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
+.class_id = PCI_CLASS_PROCESSOR_CO,
};
static void versatile_pci_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 28/39] hw/rtl8139.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/rtl8139.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index c7c7a3c..34e3a9e 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -3453,10 +3453,6 @@ static int pci_rtl8139_init(PCIDevice *dev)
uint8_t *pci_conf;
pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
-pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
pci_conf[PCI_INTERRUPT_PIN] = 1;/* interrupt pin 0 */
/* TODO: start of capability list, but no capability
* list bit in status register, and offset 0xdc seems unused. */
@@ -3510,6 +3506,10 @@ static PCIDeviceInfo rtl8139_info = {
.init = pci_rtl8139_init,
.exit = pci_rtl8139_uninit,
.romfile= "pxe-rtl8139.rom",
+.vendor_id = PCI_VENDOR_ID_REALTEK,
+.device_id = PCI_DEVICE_ID_REALTEK_8139,
+.revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */
+.class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(RTL8139State, conf),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v3 29/39] hw/sh_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/sh_pci.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index e99d8db..a076cf2 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -137,8 +137,6 @@ static int sh_pci_init_device(SysBusDevice *dev)
static int sh_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_HITACHI);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_HITACHI_SH7751R);
pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
@@ -149,6 +147,8 @@ static PCIDeviceInfo sh_pci_host_info = {
.qdev.name = "sh_pci_host",
.qdev.size = sizeof(PCIDevice),
.init = sh_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_HITACHI,
+.device_id = PCI_DEVICE_ID_HITACHI_SH7751R,
};
static void sh_pci_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 03/39] eepro100: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/eepro100.c | 74 +---
1 files changed, 33 insertions(+), 41 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 05450e8..84b98c0 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -129,8 +129,6 @@
typedef struct {
PCIDeviceInfo pci;
uint32_t device;
-uint16_t device_id;
-uint8_t revision;
uint8_t stats_size;
bool has_extended_tcb_support;
bool power_management;
@@ -526,16 +524,9 @@ static void e100_pci_reset(EEPRO100State * s,
E100PCIDeviceInfo *e100_device)
TRACE(OTHER, logout("%p\n", s));
-/* PCI Vendor ID */
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-/* PCI Device ID */
-pci_config_set_device_id(pci_conf, e100_device->device_id);
/* PCI Status */
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
PCI_STATUS_FAST_BACK);
-/* PCI Revision ID */
-pci_config_set_revision(pci_conf, e100_device->revision);
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
/* PCI Latency Timer */
pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32
clocks */
/* Capability Pointer is set by PCI framework. */
@@ -563,12 +554,7 @@ static void e100_pci_reset(EEPRO100State * s,
E100PCIDeviceInfo *e100_device)
case i82559ER:
case i82562:
case i82801:
-break;
case i82559C:
-#if EEPROM_SIZE > 0
-pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
-pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
-#endif
break;
default:
logout("Device %X is undefined!\n", device);
@@ -2040,9 +2026,9 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.desc = "Intel i82550 Ethernet",
.device = i82550,
/* TODO: check device id. */
-.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
/* Revision ID: 0x0c, 0x0d, 0x0e. */
-.revision = 0x0e,
+.pci.revision = 0x0e,
/* TODO: check size of statistical counters. */
.stats_size = 80,
/* TODO: check extended tcb support. */
@@ -2052,9 +2038,9 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82551",
.pci.qdev.desc = "Intel i82551 Ethernet",
.device = i82551,
-.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
/* Revision ID: 0x0f, 0x10. */
-.revision = 0x0f,
+.pci.revision = 0x0f,
/* TODO: check size of statistical counters. */
.stats_size = 80,
.has_extended_tcb_support = true,
@@ -2063,29 +2049,29 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82557a",
.pci.qdev.desc = "Intel i82557A Ethernet",
.device = i82557A,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x01,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x01,
.power_management = false,
},{
.pci.qdev.name = "i82557b",
.pci.qdev.desc = "Intel i82557B Ethernet",
.device = i82557B,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x02,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x02,
.power_management = false,
},{
.pci.qdev.name = "i82557c",
.pci.qdev.desc = "Intel i82557C Ethernet",
.device = i82557C,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x03,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x03,
.power_management = false,
},{
.pci.qdev.name = "i82558a",
.pci.qdev.desc = "Intel i82558A Ethernet",
.device = i82558A,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x04,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x04,
.stats_size = 76,
.has_extended_tcb_support = true,
.power_management = true,
@@ -2093,8 +2079,8 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82558b",
.pci.qdev.desc = "Intel i82558B Ethernet",
.device = i82558B,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x05,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x05,
.stats_size = 76,
.has_extended_tcb_support = true,
.power_management = true,
@@ -2102,8 +2088,8 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82559a",
.pci.qdev.desc = "Intel
[Qemu-devel] [PATCH v3 14/39] hw/grackle_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/grackle_pci.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index d35701f..cee07e0 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -104,11 +104,7 @@ static int pci_grackle_init_device(SysBusDevice *dev)
static int grackle_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
-d->config[0x08] = 0x00; // revision
d->config[0x09] = 0x01;
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
return 0;
}
@@ -116,6 +112,10 @@ static PCIDeviceInfo grackle_pci_host_info = {
.qdev.name = "grackle",
.qdev.size = sizeof(PCIDevice),
.init = grackle_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_MOTOROLA,
+.device_id = PCI_DEVICE_ID_MOTOROLA_MPC106,
+.revision = 0x00,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static void grackle_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 06/39] ide/piix: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ide/piix.c | 32 ++--
1 files changed, 10 insertions(+), 22 deletions(-)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index c349644..84f72b0 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -131,12 +131,12 @@ static void pci_piix_init_ports(PCIIDEState *d) {
}
}
-static int pci_piix_ide_initfn(PCIIDEState *d)
+static int pci_piix_ide_initfn(PCIDevice *dev)
{
+PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
-pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
qemu_register_reset(piix3_reset, d);
@@ -149,24 +149,6 @@ static int pci_piix_ide_initfn(PCIIDEState *d)
return 0;
}
-static int pci_piix3_ide_initfn(PCIDevice *dev)
-{
-PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
-
-pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
-return pci_piix_ide_initfn(d);
-}
-
-static int pci_piix4_ide_initfn(PCIDevice *dev)
-{
-PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
-
-pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
-return pci_piix_ide_initfn(d);
-}
-
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
@@ -195,13 +177,19 @@ static PCIDeviceInfo piix_ide_info[] = {
.qdev.size= sizeof(PCIIDEState),
.qdev.no_user = 1,
.no_hotplug = 1,
-.init = pci_piix3_ide_initfn,
+.init = pci_piix_ide_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371SB_1,
+.class_id = PCI_CLASS_STORAGE_IDE,
},{
.qdev.name= "piix4-ide",
.qdev.size= sizeof(PCIIDEState),
.qdev.no_user = 1,
.no_hotplug = 1,
-.init = pci_piix4_ide_initfn,
+.init = pci_piix_ide_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371AB,
+.class_id = PCI_CLASS_STORAGE_IDE,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v3 24/39] hw/pcnet-pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/pcnet-pci.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
index 9415a1e..216cf81 100644
--- a/hw/pcnet-pci.c
+++ b/hw/pcnet-pci.c
@@ -265,12 +265,8 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
pci_conf = pci_dev->config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
pci_set_word(pci_conf + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
-pci_conf[PCI_REVISION_ID] = 0x10;
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
@@ -318,6 +314,10 @@ static PCIDeviceInfo pcnet_info = {
.qdev.vmsd = &vmstate_pci_pcnet,
.init = pci_pcnet_init,
.exit = pci_pcnet_uninit,
+.vendor_id = PCI_VENDOR_ID_AMD,
+.device_id = PCI_DEVICE_ID_AMD_LANCE,
+.revision = 0x10,
+.class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v3 25/39] hw/piix4.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/piix4.c | 10 +++---
1 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/piix4.c b/hw/piix4.c
index 71f1f84..9590e7b 100644
--- a/hw/piix4.c
+++ b/hw/piix4.c
@@ -86,15 +86,8 @@ static const VMStateDescription vmstate_piix4 = {
static int piix4_initfn(PCIDevice *dev)
{
PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
-uint8_t *pci_conf;
isa_bus_new(&d->dev.qdev);
-
-pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); //
82371AB/EB/MB PIIX4 PCI-to-ISA bridge
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
-
piix4_dev = &d->dev;
qemu_register_reset(piix4_reset, d);
return 0;
@@ -117,6 +110,9 @@ static PCIDeviceInfo piix4_info[] = {
.qdev.no_user = 1,
.no_hotplug = 1,
.init = piix4_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371AB_0, // 82371AB/EB/MB PIIX4
PCI-to-ISA bridge
+.class_id = PCI_CLASS_BRIDGE_ISA,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v3 30/39] hw/sun4u.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/sun4u.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 5eb38cf..d7dcaf0 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -553,15 +553,11 @@ pci_ebus_init1(PCIDevice *s)
{
isa_bus_new(&s->qdev);
-pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
-pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
s->config[0x04] = 0x06; // command = bus master, pci mem
s->config[0x05] = 0x00;
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
s->config[0x07] = 0x03; // status = medium devsel
-s->config[0x08] = 0x01; // revision
s->config[0x09] = 0x00; // programming i/f
-pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
s->config[0x0D] = 0x0a; // latency_timer
pci_register_bar(s, 0, 0x100, PCI_BASE_ADDRESS_SPACE_MEMORY,
@@ -575,6 +571,10 @@ static PCIDeviceInfo ebus_info = {
.qdev.name = "ebus",
.qdev.size = sizeof(PCIDevice),
.init = pci_ebus_init1,
+.vendor_id = PCI_VENDOR_ID_SUN,
+.device_id = PCI_DEVICE_ID_SUN_EBUS,
+.revision = 0x01,
+.class_id = PCI_CLASS_BRIDGE_OTHER,
};
static void pci_ebus_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 16/39] hw/ide/cmd646.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ide/cmd646.c | 10 --
1 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 5d5464a..56302b5 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -226,14 +226,8 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
qemu_irq *irq;
int i;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
-
-pci_conf[PCI_REVISION_ID] = 0x07; // IDE controller revision
pci_conf[PCI_CLASS_PROG] = 0x8f;
-pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
-
pci_conf[0x51] = 0x04; // enable IDE0
if (d->secondary) {
/* XXX: if not enabled, really disable the seconday IDE controller */
@@ -282,6 +276,10 @@ static PCIDeviceInfo cmd646_ide_info[] = {
.qdev.name= "cmd646-ide",
.qdev.size= sizeof(PCIIDEState),
.init = pci_cmd646_ide_initfn,
+.vendor_id= PCI_VENDOR_ID_CMD,
+.device_id= PCI_DEVICE_ID_CMD_646,
+.revision = 0x07, // IDE controller revision
+.class_id = PCI_CLASS_STORAGE_IDE,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v3 19/39] hw/intel-hda.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/intel-hda.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 5485745..0ce 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -1138,10 +1138,6 @@ static int intel_hda_init(PCIDevice *pci)
d->name = d->pci.qdev.info->name;
-pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(conf, 0x2668);
-pci_config_set_revision(conf, 1);
-pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO);
pci_config_set_interrupt_pin(conf, 1);
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
@@ -1265,6 +1261,10 @@ static PCIDeviceInfo intel_hda_info = {
.init = intel_hda_init,
.exit = intel_hda_exit,
.config_write = intel_hda_write_config,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= 0x2668,
+.revision = 1,
+.class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
--
1.7.1.1
[Qemu-devel] [PATCH v3 04/39] dec_pci: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/dec_pci.c | 26 +++---
1 files changed, 7 insertions(+), 19 deletions(-)
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index bf88f2a..a35f382 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -50,28 +50,16 @@ static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
return irq_num;
}
-static int dec_21154_initfn(PCIDevice *dev)
-{
-int rc;
-
-rc = pci_bridge_initfn(dev);
-if (rc < 0) {
-return rc;
-}
-
-pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_DEC);
-pci_config_set_device_id(dev->config, PCI_DEVICE_ID_DEC_21154);
-return 0;
-}
-
static PCIDeviceInfo dec_21154_pci_bridge_info = {
.qdev.name = "dec-21154-p2p-bridge",
.qdev.desc = "DEC 21154 PCI-PCI bridge",
.qdev.size = sizeof(PCIBridge),
.qdev.vmsd = &vmstate_pci_device,
.qdev.reset = pci_bridge_reset,
-.init = dec_21154_initfn,
+.init = pci_bridge_initfn,
.exit = pci_bridge_exitfn,
+.vendor_id = PCI_VENDOR_ID_DEC,
+.device_id = PCI_DEVICE_ID_DEC_21154,
.config_write = pci_bridge_write_config,
.is_bridge = 1,
};
@@ -108,10 +96,6 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
static int dec_21154_pci_host_init(PCIDevice *d)
{
/* PCI2PCI bridge same values as PearPC - check this */
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
-pci_set_byte(d->config + PCI_REVISION_ID, 0x02);
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
return 0;
}
@@ -119,6 +103,10 @@ static PCIDeviceInfo dec_21154_pci_host_info = {
.qdev.name = "dec-21154",
.qdev.size = sizeof(PCIDevice),
.init = dec_21154_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_DEC,
+.device_id = PCI_DEVICE_ID_DEC_21154,
+.revision = 0x02,
+.class_id = PCI_CLASS_BRIDGE_PCI,
.is_bridge = 1,
};
--
1.7.1.1
[Qemu-devel] [PATCH v3 22/39] hw/lsi53c895a.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/lsi53c895a.c | 13 -
1 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index be4df58..6b9c904 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -2212,15 +2212,6 @@ static int lsi_scsi_init(PCIDevice *dev)
pci_conf = s->dev.config;
-/* PCI Vendor ID (word) */
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_LSI_LOGIC);
-/* PCI device ID (word) */
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A);
-/* PCI base class code */
-pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI);
-/* PCI subsystem ID */
-pci_conf[PCI_SUBSYSTEM_ID] = 0x00;
-pci_conf[PCI_SUBSYSTEM_ID + 1] = 0x10;
/* PCI latency timer = 255 */
pci_conf[PCI_LATENCY_TIMER] = 0xff;
/* TODO: RST# value should be 0 */
@@ -2256,6 +2247,10 @@ static PCIDeviceInfo lsi_info = {
.qdev.vmsd = &vmstate_lsi_scsi,
.init = lsi_scsi_init,
.exit = lsi_scsi_uninit,
+.vendor_id = PCI_VENDOR_ID_LSI_LOGIC,
+.device_id = PCI_DEVICE_ID_LSI_53C895A,
+.class_id = PCI_CLASS_STORAGE_SCSI,
+.subsystem_id = 0x1000,
};
static void lsi53c895a_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 18/39] hw/ide/via.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ide/via.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index 04f3290..3474c37 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -160,11 +160,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
uint8_t *pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE);
-pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
-pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x00c0);
qemu_register_reset(via_reset, d);
@@ -191,6 +187,10 @@ static PCIDeviceInfo via_ide_info = {
.qdev.size= sizeof(PCIIDEState),
.qdev.no_user = 1,
.init = vt82c686b_ide_initfn,
+.vendor_id= PCI_VENDOR_ID_VIA,
+.device_id= PCI_DEVICE_ID_VIA_IDE,
+.revision = 0x06,
+.class_id = PCI_CLASS_STORAGE_IDE,
};
static void via_ide_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 07/39] vmware_vga.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/vmware_vga.c | 13 ++---
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 4656767..354c221 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1280,15 +1280,8 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
struct pci_vmsvga_state_s *s =
DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
-pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
-pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
-pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
s->card.config[PCI_CACHE_LINE_SIZE]= 0x08; /* Cache line
size */
s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
-s->card.config[PCI_SUBSYSTEM_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
-s->card.config[PCI_SUBSYSTEM_VENDOR_ID + 1]= PCI_VENDOR_ID_VMWARE
>> 8;
-s->card.config[PCI_SUBSYSTEM_ID] = SVGA_PCI_DEVICE_ID & 0xff;
-s->card.config[PCI_SUBSYSTEM_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
pci_register_bar(&s->card, 0, 0x10,
@@ -1316,6 +1309,12 @@ static PCIDeviceInfo vmsvga_info = {
.no_hotplug = 1,
.init = pci_vmsvga_initfn,
.romfile = "vgabios-vmware.bin",
+
+.vendor_id= PCI_VENDOR_ID_VMWARE,
+.device_id= SVGA_PCI_DEVICE_ID,
+.class_id = PCI_CLASS_DISPLAY_VGA,
+.subsystem_vendor_id = PCI_VENDOR_ID_VMWARE,
+.subsystem_id = SVGA_PCI_DEVICE_ID,
};
static void vmsvga_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v3 12/39] hw/e1000.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/e1000.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/e1000.c b/hw/e1000.c
index f160bfc..96d84f9 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1164,12 +1164,8 @@ static int pci_e1000_init(PCIDevice *pci_dev)
pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, E1000_DEVID);
/* TODO: we have no capabilities, so why is this bit set? */
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
-pci_conf[PCI_REVISION_ID] = 0x03;
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
/* TODO: RST# value should be 0, PCI spec 6.2.4 */
pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
@@ -1221,6 +1217,10 @@ static PCIDeviceInfo e1000_info = {
.init = pci_e1000_init,
.exit = pci_e1000_uninit,
.romfile= "pxe-e1000.rom",
+.vendor_id = PCI_VENDOR_ID_INTEL,
+.device_id = E1000_DEVID,
+.revision = 0x03,
+.class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(E1000State, conf),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v3 01/39] pci: move ids of config space into PCIDeviceInfo
vender id/device id... in configuration space are read-only registers
which are commonly defined for all pci devices.
So move those initialization into common place.
Signed-off-by: Isaku Yamahata
---
changes v1 -> v2:
- dropped prog_interface, header_type
- added assert() for header type = 1
---
hw/pci.c | 46 --
hw/pci.h |7 +++
2 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 0875654..0e97a02 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -726,10 +726,11 @@ static void pci_config_free(PCIDevice *pci_dev)
/* -1 for devfn means auto assign */
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
const char *name, int devfn,
- PCIConfigReadFunc *config_read,
- PCIConfigWriteFunc *config_write,
- bool is_bridge)
+ const PCIDeviceInfo *info)
{
+PCIConfigReadFunc *config_read = info->config_read;
+PCIConfigWriteFunc *config_write = info->config_write;
+
if (devfn < 0) {
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
devfn += PCI_FUNC_MAX) {
@@ -750,13 +751,29 @@ static PCIDevice *do_pci_register_device(PCIDevice
*pci_dev, PCIBus *bus,
pci_dev->irq_state = 0;
pci_config_alloc(pci_dev);
-if (!is_bridge) {
-pci_set_default_subsystem_id(pci_dev);
+pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
+pci_config_set_device_id(pci_dev->config, info->device_id);
+pci_config_set_revision(pci_dev->config, info->revision);
+pci_config_set_class(pci_dev->config, info->class_id);
+
+if (!info->is_bridge) {
+if (info->subsystem_vendor_id || info->subsystem_id) {
+pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
+ info->subsystem_vendor_id);
+pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
+ info->subsystem_id);
+} else {
+pci_set_default_subsystem_id(pci_dev);
+}
+} else {
+/* subsystem_vendor_id/subsystem_id are only for header type 0 */
+assert(!info->subsystem_vendor_id);
+assert(!info->subsystem_id);
}
pci_init_cmask(pci_dev);
pci_init_wmask(pci_dev);
pci_init_w1cmask(pci_dev);
-if (is_bridge) {
+if (info->is_bridge) {
pci_init_wmask_bridge(pci_dev);
}
if (pci_init_multifunction(bus, pci_dev)) {
@@ -783,17 +800,20 @@ static void do_pci_unregister_device(PCIDevice *pci_dev)
pci_config_free(pci_dev);
}
+/* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
int instance_size, int devfn,
PCIConfigReadFunc *config_read,
PCIConfigWriteFunc *config_write)
{
PCIDevice *pci_dev;
+PCIDeviceInfo info = {
+.config_read = config_read,
+.config_write = config_write,
+};
pci_dev = qemu_mallocz(instance_size);
-pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
- config_read, config_write,
- PCI_HEADER_TYPE_NORMAL);
+pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
if (pci_dev == NULL) {
hw_error("PCI: can't register device\n");
}
@@ -1643,7 +1663,7 @@ static int pci_qdev_init(DeviceState *qdev, DeviceInfo
*base)
PCIDevice *pci_dev = (PCIDevice *)qdev;
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
PCIBus *bus;
-int devfn, rc;
+int rc;
bool is_default_rom;
/* initialize cap_present for pci_is_express() and pci_config_size() */
@@ -1652,10 +1672,8 @@ static int pci_qdev_init(DeviceState *qdev, DeviceInfo
*base)
}
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
-devfn = pci_dev->devfn;
-pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
- info->config_read, info->config_write,
- info->is_bridge);
+pci_dev = do_pci_register_device(pci_dev, bus, base->name,
+ pci_dev->devfn, info);
if (pci_dev == NULL)
return -1;
if (qdev->hotplugged && info->no_hotplug) {
diff --git a/hw/pci.h b/hw/pci.h
index c6a6eb6..ce214f4 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -433,6 +433,13 @@ typedef struct {
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
+uint16_t vendor_id;
+uint16_t device_id;
+uint8_t revision;
+uint16_
[Qemu-devel] [PATCH v3 20/39] hw/ioh3420.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ioh3420.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 95adf09..a6bfbb9 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -104,12 +104,8 @@ static int ioh3420_initfn(PCIDevice *d)
return rc;
}
-d->config[PCI_REVISION_ID] = PCI_DEVICE_ID_IOH_REV;
pcie_port_init_reg(d);
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_IOH_EPORT);
-
rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
if (rc < 0) {
@@ -217,6 +213,9 @@ static PCIDeviceInfo ioh3420_info = {
.config_write = ioh3420_write_config,
.init = ioh3420_initfn,
.exit = ioh3420_exitfn,
+.vendor_id = PCI_VENDOR_ID_INTEL,
+.device_id = PCI_DEVICE_ID_IOH_EPORT,
+.revision = PCI_DEVICE_ID_IOH_REV,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
--
1.7.1.1
[Qemu-devel] [PATCH v3 13/39] hw/es1370.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/es1370.c | 24 +++-
1 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/hw/es1370.c b/hw/es1370.c
index 40cb48c..1ed62b7 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -998,21 +998,9 @@ static int es1370_initfn (PCIDevice *dev)
ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
uint8_t *c = s->dev.config;
-pci_config_set_vendor_id (c, PCI_VENDOR_ID_ENSONIQ);
-pci_config_set_device_id (c, PCI_DEVICE_ID_ENSONIQ_ES1370);
c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_SLOW >> 8;
-pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO);
-#if 1
-c[PCI_SUBSYSTEM_VENDOR_ID] = 0x42;
-c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x49;
-c[PCI_SUBSYSTEM_ID] = 0x4c;
-c[PCI_SUBSYSTEM_ID + 1] = 0x4c;
-#else
-c[PCI_SUBSYSTEM_VENDOR_ID] = 0x74;
-c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x12;
-c[PCI_SUBSYSTEM_ID] = 0x71;
-c[PCI_SUBSYSTEM_ID + 1] = 0x13;
+#if 0
c[PCI_CAPABILITY_LIST] = 0xdc;
c[PCI_INTERRUPT_LINE] = 10;
c[0xdc] = 0x00;
@@ -1043,6 +1031,16 @@ static PCIDeviceInfo es1370_info = {
.qdev.size= sizeof (ES1370State),
.qdev.vmsd= &vmstate_es1370,
.init = es1370_initfn,
+.vendor_id= PCI_VENDOR_ID_ENSONIQ,
+.device_id= PCI_DEVICE_ID_ENSONIQ_ES1370,
+.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
+#if 1
+.subsystem_vendor_id = 0x4942,
+.subsystem_id = 0x4c4c,
+#else
+.subsystem_vendor_id = 0x1274,
+.subsystem_id = 0x1371,
+#endif
};
static void es1370_register (void)
--
1.7.1.1
Re: [Qemu-devel] [PATCH] piix_pci: fix piix3_set_irq_pic()
Thank you.
Acked-by: Isaku Yamahata
On Mon, May 16, 2011 at 07:50:55PM +0800, TeLeMan wrote:
> If pic_irq is greater than 7, the irq level is always 0 on 32bits.
>
> Signed-off-by: TeLeMan
> ---
> hw/piix_pci.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 7f1c4cc..85a320e 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -312,7 +312,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3,
> int pic_irq)
> {
> qemu_set_irq(piix3->pic[pic_irq],
> !!(piix3->pic_levels &
> -(((1UL << PIIX_NUM_PIRQS) - 1) <<
> +(((1ULL << PIIX_NUM_PIRQS) - 1) <<
> (pic_irq * PIIX_NUM_PIRQS;
> }
>
> --
> 1.7.3.1.msysgit.0
> --
> SUN OF A BEACH
>
--
yamahata
Re: [Qemu-devel] [PATCH v2 09/38] hw/acpi_piix4.c: convert to PCIDeviceInfo to initialize ids
On Thu, May 19, 2011 at 02:36:04PM +0200, Markus Armbruster wrote: > > no reason to respin the whole patchset, just this patch. > > Same comment in 14/38 and possibly more. Suggest a quick grep. I revised the series and fixed the followings. 03, 08, 11, 14, 18, 22, 26, 30, 31, 33, 35, 39, 40, 41 Should I send only the updated one or resend the whole series? -- yamahata
Re: [Qemu-devel] [PATCH v2 09/38] hw/acpi_piix4.c: convert to PCIDeviceInfo to initialize ids
On Thu, May 19, 2011 at 02:59:42PM +0300, Michael S. Tsirkin wrote:
> no reason to respin the whole patchset, just this patch.
Here is the update patch.
>From c3629ffd472018505a6818422b310ce96aedbc42 Mon Sep 17 00:00:00 2001
Message-Id:
In-Reply-To:
References:
From: Isaku Yamahata
Date: Wed, 18 May 2011 01:26:45 +0900
Subject: [PATCH 09/42] hw/acpi_piix4.c: convert to PCIDeviceInfo to initialize
ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/acpi_piix4.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 96f5222..232008d 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -317,13 +317,9 @@ static int piix4_pm_initfn(PCIDevice *dev)
uint8_t *pci_conf;
pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
pci_conf[0x06] = 0x80;
pci_conf[0x07] = 0x02;
-pci_conf[0x08] = 0x03; // revision number
pci_conf[0x09] = 0x00;
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
pci_conf[0x3d] = 0x01; // interrupt pin 1
pci_conf[0x40] = 0x01; /* PM io base read only bit */
@@ -394,6 +390,10 @@ static PCIDeviceInfo piix4_pm_info = {
.no_hotplug = 1,
.init = piix4_pm_initfn,
.config_write = pm_write_config,
+.vendor_id = PCI_VENDOR_ID_INTEL,
+.device_id = PCI_DEVICE_ID_INTEL_82371AB_3,
+.revision = 0x03,
+.class_id = PCI_CLASS_BRIDGE_OTHER,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
--
yamahata
Re: [Qemu-devel] [PATCH v2 09/38] hw/acpi_piix4.c: convert to PCIDeviceInfo to initialize ids
On Thu, May 19, 2011 at 10:10:09AM +0200, Markus Armbruster wrote:
> Isaku Yamahata writes:
>
> > use PCIDeviceInfo to initialize ids.
> >
> > Signed-off-by: Isaku Yamahata
> > ---
> > hw/acpi_piix4.c |8
> > 1 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
> > index 96f5222..03d833a 100644
> > --- a/hw/acpi_piix4.c
> > +++ b/hw/acpi_piix4.c
> > @@ -317,13 +317,9 @@ static int piix4_pm_initfn(PCIDevice *dev)
> > uint8_t *pci_conf;
> >
> > pci_conf = s->dev.config;
> > -pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
> > -pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
> > pci_conf[0x06] = 0x80;
> > pci_conf[0x07] = 0x02;
> > -pci_conf[0x08] = 0x03; // revision number
> > pci_conf[0x09] = 0x00;
> > -pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
> > pci_conf[0x3d] = 0x01; // interrupt pin 1
> >
> > pci_conf[0x40] = 0x01; /* PM io base read only bit */
> > @@ -394,6 +390,10 @@ static PCIDeviceInfo piix4_pm_info = {
> > .no_hotplug = 1,
> > .init = piix4_pm_initfn,
> > .config_write = pm_write_config,
> > +.vendor_id = PCI_VENDOR_ID_INTEL,
> > +.device_id = PCI_DEVICE_ID_INTEL_82371AB_3,
> > +.revision = 0x03, // revision number
>
> The comment is now redundant. Drop it?
Okay, will do.
>
> > +.class_id = PCI_CLASS_BRIDGE_OTHER,
> > .qdev.props = (Property[]) {
> > DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
> > DEFINE_PROP_END_OF_LIST(),
>
--
yamahata
Re: [Qemu-devel] [PATCH] Ignore pci unplug requests for unpluggable devices (CVE-2011-1751)
On Thu, May 19, 2011 at 01:23:18PM +0200, Markus Armbruster wrote:
> Gerd Hoffmann writes:
>
> > Hi,
> >
> > Markus Armbruster writes:
> >
> >> Gerd Hoffmann writes:
> >>
> >>> This patch makes qemu ignore unplug requests from the guest for pci
> >>> devices which are tagged as non-hotpluggable. Trouble spot is the
> >>> piix4 chipset with the ISA bridge. Requests to unplug that one will
> >>> make it go away together with all ISA bus devices, which are not
> >>> prepared to be unplugged and thus don't cleanup, leaving active
> >>> qemu timers behind in free'ed memory.
> >>>
> >>> Signed-off-by: Gerd Hoffmann
> >>> ---
> >>> hw/acpi_piix4.c |4 +++-
> >>> 1 files changed, 3 insertions(+), 1 deletions(-)
> >>>
> >>> diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
> >>> diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
> >>> index 96f5222..6c908ff 100644
> >>> --- a/hw/acpi_piix4.c
> >>> +++ b/hw/acpi_piix4.c
> >>> @@ -471,11 +471,13 @@ static void pciej_write(void *opaque, uint32_t
> >>> addr, uint32_t val)
> >>> BusState *bus = opaque;
> >>> DeviceState *qdev, *next;
> >>> PCIDevice *dev;
> >>> +PCIDeviceInfo *info;
> >>> int slot = ffs(val) - 1;
> >>>
> >>> QLIST_FOREACH_SAFE(qdev,&bus->children, sibling, next) {
> >>> dev = DO_UPCAST(PCIDevice, qdev, qdev);
> >>> -if (PCI_SLOT(dev->devfn) == slot) {
> >>> +info = container_of(qdev->info, PCIDeviceInfo, qdev);
> >>> +if (PCI_SLOT(dev->devfn) == slot&& !info->no_hotplug) {
> >>> qdev_free(qdev);
> >>> }
> >>> }
> >>
> >> Looks good, but what about pcie_cap_slot_hotplug()?
> >
> > Dunno, didn't look at q35 yet. I'd expect the root bus isn't
> > hot-pluggable, so the guest wouldn't be able to rip out any essential
> > chipset devices. But having someone more familier with pcie + q35
> > double-check would be good ...
>
> I guess that would be Isaku Yamahata (cc'ed).
The root pci bus of q35 isn't hot pluggable. The pcie bus with
the hotplug capability means that the slot in the bus is always
hot pluggable. So pcie_cap_slot_hotplug() doesn't need to check
no_hotplug.
If some sort of check is wanted, the check should be done at
the device initialization, I think.
Populating a non-hotpluggable devince in hot pluggable slot doesn't make
sense.
thanks,
--
yamahata
Re: [Qemu-devel] [PATCH] xen: fix interrupt routing
On Wed, May 18, 2011 at 06:53:40PM +0100, stefano.stabell...@eu.citrix.com
wrote:
> From: Stefano Stabellini
>
> Match the routing informations built by seabios:
>
> - remove i440fx_write_config_xen
> we don't need to intercept pci config writes to i440FX;
>
> - introduce piix3_write_config_xen
> we do need to intercept pci config write to the PCI-ISA bridge to update
> the PCI link routing;
So "i440FX-xen" isn't needed anymore, and something like PIIX3-xen
is necessary instead of overwriting piix3->dev.config_write.
thanks,
>
> - remove xen_pci_slot_get_pirq
> we are now using the same link routing as seabios and qemu so we don't
> need a diffirent get_pirq function;
>
> - fix xen_piix3_set_irq
> we always inject one of the 4 pci intx, so we can use
> xc_hvm_set_isa_irq_level to inject the interrupt. Use pci_irqs as
> initialized by seabios to map a pirq into an ISA irq. This has the
> benefit of removing all the calls to xc_hvm_set_pci_intx_level that
> doesn't work correctly anymore because from the same device number and
> intx Xen calculates a different PCI link compared to Qemu and Seabios.
>
> Signed-off-by: Stefano Stabellini
> ---
> hw/piix_pci.c | 21 -
> xen-all.c | 16
> 2 files changed, 20 insertions(+), 17 deletions(-)
>
> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 7f1c4cc..aae6a48 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -78,6 +78,8 @@ struct PCII440FXState {
> #define I440FX_SMRAM0x72
>
> static void piix3_set_irq(void *opaque, int pirq, int level);
> +static void piix3_write_config_xen(PCIDevice *dev,
> + uint32_t address, uint32_t val, int len);
>
> /* return the global irq number corresponding to a given device irq
> pin. We could also use the bus number to have a more precise
> @@ -173,13 +175,6 @@ static void i440fx_write_config(PCIDevice *dev,
> }
> }
>
> -static void i440fx_write_config_xen(PCIDevice *dev,
> -uint32_t address, uint32_t val, int len)
> -{
> -xen_piix_pci_write_config_client(address, val, len);
> -i440fx_write_config(dev, address, val, len);
> -}
> -
> static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
> {
> PCII440FXState *d = opaque;
> @@ -301,7 +296,8 @@ PCIBus *i440fx_xen_init(PCII440FXState **pi440fx_state,
> int *piix3_devfn,
> PCIBus *b;
>
> b = i440fx_common_init("i440FX-xen", pi440fx_state, piix3_devfn, pic,
> ram_size);
> -pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> +(*pi440fx_state)->piix3->dev.config_write = piix3_write_config_xen;
> +pci_bus_irqs(b, xen_piix3_set_irq, pci_slot_get_pirq,
> (*pi440fx_state)->piix3, PIIX_NUM_PIRQS);
>
> return b;
> @@ -365,6 +361,13 @@ static void piix3_write_config(PCIDevice *dev,
> }
> }
>
> +static void piix3_write_config_xen(PCIDevice *dev,
> + uint32_t address, uint32_t val, int len)
> +{
> +xen_piix_pci_write_config_client(address, val, len);
> +piix3_write_config(dev, address, val, len);
> +}
> +
> static void piix3_reset(void *opaque)
> {
> PIIX3State *d = opaque;
> @@ -471,7 +474,7 @@ static PCIDeviceInfo i440fx_info[] = {
> .qdev.vmsd= &vmstate_i440fx,
> .qdev.no_user = 1,
> .init = i440fx_initfn,
> -.config_write = i440fx_write_config_xen,
> +.config_write = i440fx_write_config,
> },{
> .qdev.name= "PIIX3",
> .qdev.desc= "ISA bridge",
> diff --git a/xen-all.c b/xen-all.c
> index 0eac202..7d7863f 100644
> --- a/xen-all.c
> +++ b/xen-all.c
> @@ -70,17 +70,16 @@ typedef struct XenIOState {
> Notifier exit;
> } XenIOState;
>
> -/* Xen specific function for piix pci */
> +/* pci_irqs as initialized by seabios */
> +uint8_t pci_irqs[4] = {
> +10, 10, 11, 11
> +};
>
> -int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
> -{
> -return irq_num + ((pci_dev->devfn >> 3) << 2);
> -}
> +/* Xen specific function for piix pci */
>
> -void xen_piix3_set_irq(void *opaque, int irq_num, int level)
> +void xen_piix3_set_irq(void *opaque, int pirq, int level)
> {
> -xc_hvm_set_pci_intx_level(xen_xc, xen_domid, 0, 0, irq_num >> 2,
> - irq_num & 3, level);
> +xc_hvm_set_isa_irq_level(xen_xc, xen_domid, pci_irqs[pirq], level);
> }
>
> void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int
> len)
> @@ -95,6 +94,7 @@ void xen_piix_pci_write_config_client(uint32_t address,
> uint32_t val, int len)
> }
> v &= 0xf;
> if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
> +pci_irqs[address + i - 0x60] = v;
> xc_hvm_set_pci_link_route(xen_xc, xen_domid, address + i - 0x60,
> v);
> }
> }
> --
> 1.7.2.3
>
>
--
yamahata
Re: [Qemu-devel] [PATCH v2 00/38] pci: initialize ids in pci common code
On Wed, May 18, 2011 at 12:17:46PM +0300, Michael S. Tsirkin wrote:
> On Wed, May 18, 2011 at 01:55:17AM +0900, Isaku Yamahata wrote:
> > vender id/device id... in pci configuration space are read-only registers
> > which are commonly defined for all pci devices.
> > So initialize them in common code and it simplifies the initialization a
> > bit.
> > I didn't converted virtio-pci and qxl because it determines ids dynaically.
> > So I'll leave those conversion (or not to convert) to the authors.
>
> Hmm, virtio doesn't:
> static PCIDeviceInfo virtio_info[] = {
> ...
> }
>
> has the array of devices.
Okay. I missed it somehow. I get the following, And I'll leave
qxl convection to Gerd.
The remaining issue is, should I adopt/drop prog_interface conversion?
>From c9834234c73eb03d764a3c999cbd34f4814a5553 Mon Sep 17 00:00:00 2001
Message-Id:
In-Reply-To:
References:
From: Isaku Yamahata
Date: Wed, 18 May 2011 19:46:04 +0900
Subject: [PATCH] virtio-pci.c: convert to PCIDEviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/virtio-pci.c | 69 --
1 files changed, 31 insertions(+), 38 deletions(-)
diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index c19629d..270e2c7 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -669,9 +669,7 @@ static const VirtIOBindings virtio_pci_bindings = {
.vmstate_change = virtio_pci_vmstate_change,
};
-static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev,
-uint16_t vendor, uint16_t device,
-uint16_t class_code, uint8_t pif)
+static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)
{
uint8_t *config;
uint32_t size;
@@ -679,19 +677,12 @@ static void virtio_init_pci(VirtIOPCIProxy *proxy,
VirtIODevice *vdev,
proxy->vdev = vdev;
config = proxy->pci_dev.config;
-pci_config_set_vendor_id(config, vendor);
-pci_config_set_device_id(config, device);
-
-config[0x08] = VIRTIO_PCI_ABI_VERSION;
-
-config[0x09] = pif;
-pci_config_set_class(config, class_code);
-
-config[0x2c] = vendor & 0xFF;
-config[0x2d] = (vendor >> 8) & 0xFF;
-config[0x2e] = vdev->device_id & 0xFF;
-config[0x2f] = (vdev->device_id >> 8) & 0xFF;
+if (proxy->class_code) {
+pci_config_set_class(config, proxy->class_code);
+}
+pci_set_word(config + 0x2c, pci_get_word(config + PCI_VENDOR_ID));
+pci_set_word(config + 0x2e, vdev->device_id);
config[0x3d] = 1;
if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) {
@@ -735,10 +726,7 @@ static int virtio_blk_init_pci(PCIDevice *pci_dev)
return -1;
}
vdev->nvectors = proxy->nvectors;
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_BLOCK,
-proxy->class_code, 0x00);
+virtio_init_pci(proxy, vdev);
/* make the actual value visible */
proxy->nvectors = vdev->nvectors;
return 0;
@@ -776,10 +764,7 @@ static int virtio_serial_init_pci(PCIDevice *pci_dev)
vdev->nvectors = proxy->nvectors == DEV_NVECTORS_UNSPECIFIED
? proxy->serial.max_virtserial_ports +
1
: proxy->nvectors;
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_CONSOLE,
-proxy->class_code, 0x00);
+virtio_init_pci(proxy, vdev);
proxy->nvectors = vdev->nvectors;
return 0;
}
@@ -801,11 +786,7 @@ static int virtio_net_init_pci(PCIDevice *pci_dev)
vdev = virtio_net_init(&pci_dev->qdev, &proxy->nic, &proxy->net);
vdev->nvectors = proxy->nvectors;
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_NET,
-PCI_CLASS_NETWORK_ETHERNET,
-0x00);
+virtio_init_pci(proxy, vdev);
/* make the actual value visible */
proxy->nvectors = vdev->nvectors;
@@ -827,11 +808,7 @@ static int virtio_balloon_init_pci(PCIDevice *pci_dev)
VirtIODevice *vdev;
vdev = virtio_balloon_init(&pci_dev->qdev);
-virtio_init_pci(proxy, vdev,
-PCI_VENDOR_ID_REDHAT_QUMRANET,
-PCI_DEVICE_ID_VIRTIO_BALLOON,
-PCI_CLASS_MEMORY_RAM,
-0x00);
+virtio_init_pci(proxy, vdev);
return 0;
}
@@ -843,11 +820,7 @@ static int virtio_9p_init_pci(PCIDevice *pci_dev)
vdev = virtio_9p_init(&pci_dev->qdev, &proxy->fsconf);
vdev->nv
Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support
On Tue, May 17, 2011 at 04:21:11PM +0200, Jan Kiszka wrote: > I also succeeded with passing through a PCIe host device. Nicely, the > full set capabilities showed up on the guest side this way. But GPU > pass-through did not improve this way (it rather regressed, yet unclear > why). Interesting. > > I had a quick look at your patches. > > With seabios patch of 94710189f5323034e00b510fe5a0865a7b576a9f, > > you ignored MCFG area. > > > > (start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR, size = 256MB) is used > > for MCFG (!= pci region), so it can't be used for PCI region. > > That's why 256M is added to s. > > And Q35_HOST_BRIDGE_PCIEXBAR_ADDR in dev-q35.h also needs to be adjusted. > > Confused. Where was the PCI region located without my hack? I mean the following patch on top of your tree. At the moment, I only compiled it. diff --git a/src/dev-q35.c b/src/dev-q35.c index c0aa057..eee50c4 100644 --- a/src/dev-q35.c +++ b/src/dev-q35.c @@ -36,13 +36,15 @@ void mch_mem_addr_init(u16 bdf, void *arg) /* * BUILD_MAX_HIGHMEM == 0xc000 - * [0xc000 , 0xf000 ) for MCFG - * 4GB - 1GB, 4GB - 256MB + * [0xc000 , 0xd000 ) for MCFG + * 3GB ,3GB + 256MB + * [0xd000 , 0xf000 ) for pci memory region + * 3GB + 256MB, 4GB - 256MB * [0xf000 , 0xfec0 ) for DMI interface(subtractive decode) * 4GB - 256MB, 4GB - 20MB */ -s = BUILD_MAX_HIGHMEM; -e = s + 128 * 1024 * 1024 - 1 + 512 * 1024 * 1024; +s = Q35_HOST_BRIDGE_PCIEXBAR_ADDR + Q35_HOST_BRIDGE_PCIEXBAR_SIZE; +e = s + 512 * 1024 * 1024 - 1; pci_region_init(addr->pci_bios_mem_region, s, e); /* pci_bios_mem_addr + */ diff --git a/src/dev-q35.h b/src/dev-q35.h index f5cae62..0d83dba 100644 --- a/src/dev-q35.h +++ b/src/dev-q35.h @@ -8,7 +8,7 @@ #define Q35_HOST_BRIDGE_SMRAM 0x9d #define Q35_HOST_BRIDGE_PCIEXBAR0x60 #define Q35_HOST_BRIDGE_PCIEXBAR_SIZE (256 * 1024 * 1024) -#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR 0xe000 +#define Q35_HOST_BRIDGE_PCIEXBAR_ADDR BUILD_MAX_HIGHMEM #define Q35_HOST_BRIDGE_PCIEXBAREN ((u64)1) #define Q35_HOST_PCIE_PCI_SEGMENT 0 #define Q35_HOST_PCIE_START_BUS_NUMBER 0 > BTW, the PCI bar mapping failures of VGA or e1000 are independent of > that seabios commit. You should see them with your tree as well. Hmm, I'll look into it. > > After pushing out pci id clean up and once they are accepted, > > I'll publish rebased/cleaned up one. > > Note that I dropped "simply i440fx initialization". It was a premature > cleanup that caused regressions. The good news: I'm working on PAM/SMRAM > fixes that will include such a cleanup after removing the need for the > init function. The bad news: Those patches will force you to rebase > again (to break out the new PAM/SMRAM code). Please keep CCed on me. -- yamahata
Re: [Qemu-devel] [PATCH v2 00/38] pci: initialize ids in pci common code
Here is the prog_interface part.
You were unsure about prog_interface, so I split it out.
Thus you can determine if prog_interface conversion is wanted or not.
>From abaf67175190c2f4d0c222c2ae8010e9de38bf59 Mon Sep 17 00:00:00 2001
Message-Id:
From: Isaku Yamahata
Date: Wed, 18 May 2011 09:58:21 +0900
Subject: [PATCH] pci: initialize prog_interface by common code
Add prog_interface to PCIDeviceInfo and initialize
prog_interface register in the common initialization code.
It's read-only register.
Signed-off-by: Isaku Yamahata
---
hw/ac97.c|2 --
hw/acpi_piix4.c |1 -
hw/bonito.c |3 ---
hw/grackle_pci.c |2 +-
hw/gt64xxx.c |1 -
hw/ide/cmd646.c |3 +--
hw/ide/ich.c |3 +--
hw/ide/piix.c|5 ++---
hw/ide/via.c |2 +-
hw/pci.c |1 +
hw/pci.h |1 +
hw/sun4u.c |1 -
hw/usb-ohci.c|2 +-
hw/usb-uhci.c|1 -
hw/vt82c686.c|4
15 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/hw/ac97.c b/hw/ac97.c
index bf1d1d4..ec2b928 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -1289,8 +1289,6 @@ static int ac97_initfn (PCIDevice *dev)
c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
-c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
-
/* TODO set when bar is registered. no need to override. */
/* nabmar native audio mixer base address rw */
c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 03d833a..4e5674f 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -319,7 +319,6 @@ static int piix4_pm_initfn(PCIDevice *dev)
pci_conf = s->dev.config;
pci_conf[0x06] = 0x80;
pci_conf[0x07] = 0x02;
-pci_conf[0x09] = 0x00;
pci_conf[0x3d] = 0x01; // interrupt pin 1
pci_conf[0x40] = 0x01; /* PM io base read only bit */
diff --git a/hw/bonito.c b/hw/bonito.c
index e8c57a3..d1e6d1f 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -690,9 +690,6 @@ static int bonito_initfn(PCIDevice *dev)
{
PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
-/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"
*/
-pci_config_set_prog_interface(dev->config, 0x00);
-
/* set the north bridge register mapping */
s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
DEVICE_NATIVE_ENDIAN);
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 7a5221c..46ead7b 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -104,7 +104,6 @@ static int pci_grackle_init_device(SysBusDevice *dev)
static int grackle_pci_host_init(PCIDevice *d)
{
-d->config[0x09] = 0x01;
return 0;
}
@@ -115,6 +114,7 @@ static PCIDeviceInfo grackle_pci_host_info = {
.vendor_id = PCI_VENDOR_ID_MOTOROLA,
.device_id = PCI_DEVICE_ID_MOTOROLA_MPC106,
.revision = 0x00, // revision
+.prog_interface = 0x01,
.class_id = PCI_CLASS_BRIDGE_HOST,
};
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 8e1f6a0..54ace8e 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1121,7 +1121,6 @@ static int gt64120_pci_init(PCIDevice *d)
pci_set_word(d->config + PCI_COMMAND, 0);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
-pci_config_set_prog_interface(d->config, 0);
pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x0008);
pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x0108);
pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c00);
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 56302b5..0ca9767 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -226,8 +226,6 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
qemu_irq *irq;
int i;
-pci_conf[PCI_CLASS_PROG] = 0x8f;
-
pci_conf[0x51] = 0x04; // enable IDE0
if (d->secondary) {
/* XXX: if not enabled, really disable the seconday IDE controller */
@@ -279,6 +277,7 @@ static PCIDeviceInfo cmd646_ide_info[] = {
.vendor_id= PCI_VENDOR_ID_CMD,
.device_id= PCI_DEVICE_ID_CMD_646,
.revision = 0x07, // IDE controller revision
+.prog_intarface = 0x8f,
.class_id = PCI_CLASS_STORAGE_IDE,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index cb1c405..784bd96 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -77,8 +77,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
struct AHCIPCIState *d;
d = DO_UPCAST(struct AHCIPCIState, card, dev);
-pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
-
d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line s
[Qemu-devel] [PATCH v2 25/38] hw/piix4.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/piix4.c | 10 +++---
1 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/hw/piix4.c b/hw/piix4.c
index 71f1f84..9590e7b 100644
--- a/hw/piix4.c
+++ b/hw/piix4.c
@@ -86,15 +86,8 @@ static const VMStateDescription vmstate_piix4 = {
static int piix4_initfn(PCIDevice *dev)
{
PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
-uint8_t *pci_conf;
isa_bus_new(&d->dev.qdev);
-
-pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); //
82371AB/EB/MB PIIX4 PCI-to-ISA bridge
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
-
piix4_dev = &d->dev;
qemu_register_reset(piix4_reset, d);
return 0;
@@ -117,6 +110,9 @@ static PCIDeviceInfo piix4_info[] = {
.qdev.no_user = 1,
.no_hotplug = 1,
.init = piix4_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371AB_0, // 82371AB/EB/MB PIIX4
PCI-to-ISA bridge
+.class_id = PCI_CLASS_BRIDGE_ISA,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v2 03/38] eepro100: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/eepro100.c | 72 +---
1 files changed, 32 insertions(+), 40 deletions(-)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 05450e8..f010f78 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -129,8 +129,6 @@
typedef struct {
PCIDeviceInfo pci;
uint32_t device;
-uint16_t device_id;
-uint8_t revision;
uint8_t stats_size;
bool has_extended_tcb_support;
bool power_management;
@@ -526,15 +524,9 @@ static void e100_pci_reset(EEPRO100State * s,
E100PCIDeviceInfo *e100_device)
TRACE(OTHER, logout("%p\n", s));
-/* PCI Vendor ID */
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-/* PCI Device ID */
-pci_config_set_device_id(pci_conf, e100_device->device_id);
/* PCI Status */
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
PCI_STATUS_FAST_BACK);
-/* PCI Revision ID */
-pci_config_set_revision(pci_conf, e100_device->revision);
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
/* PCI Latency Timer */
pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32
clocks */
@@ -563,12 +555,7 @@ static void e100_pci_reset(EEPRO100State * s,
E100PCIDeviceInfo *e100_device)
case i82559ER:
case i82562:
case i82801:
-break;
case i82559C:
-#if EEPROM_SIZE > 0
-pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
-pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
-#endif
break;
default:
logout("Device %X is undefined!\n", device);
@@ -2040,9 +2027,9 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.desc = "Intel i82550 Ethernet",
.device = i82550,
/* TODO: check device id. */
-.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
/* Revision ID: 0x0c, 0x0d, 0x0e. */
-.revision = 0x0e,
+.pci.revision = 0x0e,
/* TODO: check size of statistical counters. */
.stats_size = 80,
/* TODO: check extended tcb support. */
@@ -2052,9 +2039,9 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82551",
.pci.qdev.desc = "Intel i82551 Ethernet",
.device = i82551,
-.device_id = PCI_DEVICE_ID_INTEL_82551IT,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82551IT,
/* Revision ID: 0x0f, 0x10. */
-.revision = 0x0f,
+.pci.revision = 0x0f,
/* TODO: check size of statistical counters. */
.stats_size = 80,
.has_extended_tcb_support = true,
@@ -2063,29 +2050,29 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82557a",
.pci.qdev.desc = "Intel i82557A Ethernet",
.device = i82557A,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x01,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x01,
.power_management = false,
},{
.pci.qdev.name = "i82557b",
.pci.qdev.desc = "Intel i82557B Ethernet",
.device = i82557B,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x02,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x02,
.power_management = false,
},{
.pci.qdev.name = "i82557c",
.pci.qdev.desc = "Intel i82557C Ethernet",
.device = i82557C,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x03,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x03,
.power_management = false,
},{
.pci.qdev.name = "i82558a",
.pci.qdev.desc = "Intel i82558A Ethernet",
.device = i82558A,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x04,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x04,
.stats_size = 76,
.has_extended_tcb_support = true,
.power_management = true,
@@ -2093,8 +2080,8 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82558b",
.pci.qdev.desc = "Intel i82558B Ethernet",
.device = i82558B,
-.device_id = PCI_DEVICE_ID_INTEL_82557,
-.revision = 0x05,
+.pci.device_id = PCI_DEVICE_ID_INTEL_82557,
+.pci.revision = 0x05,
.stats_size = 76,
.has_extended_tcb_support = true,
.power_management = true,
@@ -2102,8 +2089,8 @@ static E100PCIDeviceInfo e100_devices[] = {
.pci.qdev.name = "i82559a",
.pci.qdev.desc = "Intel i82559A Ethernet",
.device = i82559A,
-
[Qemu-devel] [PATCH v2 13/38] hw/es1370.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/es1370.c | 24 +++-
1 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/hw/es1370.c b/hw/es1370.c
index 40cb48c..1ed62b7 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -998,21 +998,9 @@ static int es1370_initfn (PCIDevice *dev)
ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
uint8_t *c = s->dev.config;
-pci_config_set_vendor_id (c, PCI_VENDOR_ID_ENSONIQ);
-pci_config_set_device_id (c, PCI_DEVICE_ID_ENSONIQ_ES1370);
c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_SLOW >> 8;
-pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO);
-#if 1
-c[PCI_SUBSYSTEM_VENDOR_ID] = 0x42;
-c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x49;
-c[PCI_SUBSYSTEM_ID] = 0x4c;
-c[PCI_SUBSYSTEM_ID + 1] = 0x4c;
-#else
-c[PCI_SUBSYSTEM_VENDOR_ID] = 0x74;
-c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x12;
-c[PCI_SUBSYSTEM_ID] = 0x71;
-c[PCI_SUBSYSTEM_ID + 1] = 0x13;
+#if 0
c[PCI_CAPABILITY_LIST] = 0xdc;
c[PCI_INTERRUPT_LINE] = 10;
c[0xdc] = 0x00;
@@ -1043,6 +1031,16 @@ static PCIDeviceInfo es1370_info = {
.qdev.size= sizeof (ES1370State),
.qdev.vmsd= &vmstate_es1370,
.init = es1370_initfn,
+.vendor_id= PCI_VENDOR_ID_ENSONIQ,
+.device_id= PCI_DEVICE_ID_ENSONIQ_ES1370,
+.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
+#if 1
+.subsystem_vendor_id = 0x4942,
+.subsystem_id = 0x4c4c,
+#else
+.subsystem_vendor_id = 0x1274,
+.subsystem_id = 0x1371,
+#endif
};
static void es1370_register (void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 06/38] ide/piix: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ide/piix.c | 32 ++--
1 files changed, 10 insertions(+), 22 deletions(-)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index c349644..84f72b0 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -131,12 +131,12 @@ static void pci_piix_init_ports(PCIIDEState *d) {
}
}
-static int pci_piix_ide_initfn(PCIIDEState *d)
+static int pci_piix_ide_initfn(PCIDevice *dev)
{
+PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
uint8_t *pci_conf = d->dev.config;
pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
-pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
qemu_register_reset(piix3_reset, d);
@@ -149,24 +149,6 @@ static int pci_piix_ide_initfn(PCIIDEState *d)
return 0;
}
-static int pci_piix3_ide_initfn(PCIDevice *dev)
-{
-PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
-
-pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
-return pci_piix_ide_initfn(d);
-}
-
-static int pci_piix4_ide_initfn(PCIDevice *dev)
-{
-PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
-
-pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
-return pci_piix_ide_initfn(d);
-}
-
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
@@ -195,13 +177,19 @@ static PCIDeviceInfo piix_ide_info[] = {
.qdev.size= sizeof(PCIIDEState),
.qdev.no_user = 1,
.no_hotplug = 1,
-.init = pci_piix3_ide_initfn,
+.init = pci_piix_ide_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371SB_1,
+.class_id = PCI_CLASS_STORAGE_IDE,
},{
.qdev.name= "piix4-ide",
.qdev.size= sizeof(PCIIDEState),
.qdev.no_user = 1,
.no_hotplug = 1,
-.init = pci_piix4_ide_initfn,
+.init = pci_piix_ide_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371AB,
+.class_id = PCI_CLASS_STORAGE_IDE,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v2 24/38] hw/pcnet-pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/pcnet-pci.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
index 9415a1e..216cf81 100644
--- a/hw/pcnet-pci.c
+++ b/hw/pcnet-pci.c
@@ -265,12 +265,8 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
pci_conf = pci_dev->config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
pci_set_word(pci_conf + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
-pci_conf[PCI_REVISION_ID] = 0x10;
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
@@ -318,6 +314,10 @@ static PCIDeviceInfo pcnet_info = {
.qdev.vmsd = &vmstate_pci_pcnet,
.init = pci_pcnet_init,
.exit = pci_pcnet_uninit,
+.vendor_id = PCI_VENDOR_ID_AMD,
+.device_id = PCI_DEVICE_ID_AMD_LANCE,
+.revision = 0x10,
+.class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v2 35/38] hw/vt82c686.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/vt82c686.c | 35 ---
1 files changed, 16 insertions(+), 19 deletions(-)
diff --git a/hw/vt82c686.c b/hw/vt82c686.c
index ca8f826..f23bea9 100644
--- a/hw/vt82c686.c
+++ b/hw/vt82c686.c
@@ -326,11 +326,6 @@ static int vt82c686b_ac97_initfn(PCIDevice *dev)
VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97);
-pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO);
-pci_config_set_revision(pci_conf, 0x50);
-
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
@@ -353,6 +348,10 @@ static PCIDeviceInfo via_ac97_info = {
.qdev.desc = "AC97",
.qdev.size = sizeof(VT686AC97State),
.init = vt82c686b_ac97_initfn,
+.vendor_id = PCI_VENDOR_ID_VIA,
+.device_id = PCI_DEVICE_ID_VIA_AC97,
+.revision = 0x50,
+.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
};
static void vt82c686b_ac97_register(void)
@@ -367,11 +366,6 @@ static int vt82c686b_mc97_initfn(PCIDevice *dev)
VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
uint8_t *pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97);
-pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER);
-pci_config_set_revision(pci_conf, 0x30);
-
pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
PCI_COMMAND_VGA_PALETTE);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
@@ -393,6 +387,10 @@ static PCIDeviceInfo via_mc97_info = {
.qdev.desc = "MC97",
.qdev.size = sizeof(VT686MC97State),
.init = vt82c686b_mc97_initfn,
+.vendor_id = PCI_VENDOR_ID_VIA,
+.device_id = PCI_DEVICE_ID_VIA_MC97,
+.class_id = PCI_CLASS_COMMUNICATION_OTHER,
+.revision = 0x30,
};
static void vt82c686b_mc97_register(void)
@@ -409,11 +407,6 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
uint8_t *pci_conf;
pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI);
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
-pci_config_set_revision(pci_conf, 0x40);
-
pci_set_word(pci_conf + PCI_COMMAND, 0);
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
PCI_STATUS_DEVSEL_MEDIUM);
@@ -462,6 +455,10 @@ static PCIDeviceInfo via_pm_info = {
.qdev.vmsd = &vmstate_acpi,
.init = vt82c686b_pm_initfn,
.config_write = pm_write_config,
+.vendor_id = PCI_VENDOR_ID_VIA,
+.device_id = PCI_DEVICE_ID_VIA_ACPI,
+.class_id = PCI_CLASS_BRIDGE_OTHER,
+.revision = 0x40,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
DEFINE_PROP_END_OF_LIST(),
@@ -496,11 +493,7 @@ static int vt82c686b_initfn(PCIDevice *d)
isa_bus_new(&d->qdev);
pci_conf = d->config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE);
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
pci_config_set_prog_interface(pci_conf, 0x0);
-pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */
wmask = d->wmask;
for (i = 0x00; i < 0xff; i++) {
@@ -531,6 +524,10 @@ static PCIDeviceInfo via_info = {
.qdev.no_user = 1,
.init = vt82c686b_initfn,
.config_write = vt82c686b_write_config,
+.vendor_id= PCI_VENDOR_ID_VIA,
+.device_id= PCI_DEVICE_ID_VIA_ISA_BRIDGE,
+.class_id = PCI_CLASS_BRIDGE_ISA,
+.revision = 0x40, /* Revision 4.0 */
};
static void vt82c686b_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 32/38] hw/usb-ohci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/usb-ohci.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index d21c820..7ff2322 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1716,11 +1716,7 @@ static int usb_ohci_initfn_pci(struct PCIDevice *dev)
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
int num_ports = 3;
-pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(ohci->pci_dev.config,
- PCI_DEVICE_ID_APPLE_IPID_USB);
ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
-pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
/* TODO: RST# value should be 0. */
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
@@ -1760,6 +1756,9 @@ static PCIDeviceInfo ohci_pci_info = {
.qdev.desc= "Apple USB Controller",
.qdev.size= sizeof(OHCIPCIState),
.init = usb_ohci_initfn_pci,
+.vendor_id= PCI_VENDOR_ID_APPLE,
+.device_id= PCI_DEVICE_ID_APPLE_IPID_USB,
+.class_id = PCI_CLASS_SERIAL_USB,
};
static SysBusDeviceInfo ohci_sysbus_info = {
--
1.7.1.1
[Qemu-devel] [PATCH v2 34/38] hw/vga-pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/vga-pci.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index ce9ec45..481f448 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -74,7 +74,6 @@ static int pci_vga_initfn(PCIDevice *dev)
{
PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
VGACommonState *s = &d->vga;
- uint8_t *pci_conf = d->dev.config;
// vga + console init
vga_common_init(s, VGA_RAM_SIZE);
@@ -83,11 +82,6 @@ static int pci_vga_initfn(PCIDevice *dev)
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
- // dummy VGA (same as Bochs ID)
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
- pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
-
/* XXX: VGA_RAM_SIZE must be a power of two */
pci_register_bar(&d->dev, 0, VGA_RAM_SIZE,
PCI_BASE_ADDRESS_MEM_PREFETCH, vga_map);
@@ -114,6 +108,11 @@ static PCIDeviceInfo vga_info = {
.init = pci_vga_initfn,
.config_write = pci_vga_write_config,
.romfile = "vgabios-stdvga.bin",
+
+/* dummy VGA (same as Bochs ID) */
+.vendor_id= PCI_VENDOR_ID_QEMU,
+.device_id= PCI_DEVICE_ID_QEMU_VGA,
+.class_id = PCI_CLASS_DISPLAY_VGA,
};
static void vga_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 18/38] hw/ide/via.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ide/via.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index 04f3290..e9e67de 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -160,11 +160,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
uint8_t *pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE);
-pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
-pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x00c0);
qemu_register_reset(via_reset, d);
@@ -191,6 +187,10 @@ static PCIDeviceInfo via_ide_info = {
.qdev.size= sizeof(PCIIDEState),
.qdev.no_user = 1,
.init = vt82c686b_ide_initfn,
+.vendor_id= PCI_VENDOR_ID_VIA,
+.device_id= PCI_DEVICE_ID_VIA_IDE,
+.revision = 0x06, /* Revision 0.6 */
+.class_id = PCI_CLASS_STORAGE_IDE,
};
static void via_ide_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 17/38] hw/ide/ich.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ide/ich.c |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index e44339b..cb1c405 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -77,11 +77,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
struct AHCIPCIState *d;
d = DO_UPCAST(struct AHCIPCIState, card, dev);
-pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR);
-
-pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA);
-pci_config_set_revision(d->card.config, 0x02);
pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
@@ -131,6 +126,10 @@ static PCIDeviceInfo ich_ahci_info[] = {
.init = pci_ich9_ahci_init,
.exit = pci_ich9_uninit,
.config_write = pci_ich9_write_config,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82801IR,
+.revision = 0x02,
+.class_id = PCI_CLASS_STORAGE_SATA,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v2 23/38] hw/ne2000.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ne2000.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ne2000.c b/hw/ne2000.c
index b668ad1..f8acaae 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -721,9 +721,6 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
uint8_t *pci_conf;
pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
/* TODO: RST# value should be 0. PCI spec 6.2.4 */
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
@@ -767,6 +764,9 @@ static PCIDeviceInfo ne2000_info = {
.qdev.vmsd = &vmstate_pci_ne2000,
.init = pci_ne2000_init,
.exit = pci_ne2000_exit,
+.vendor_id = PCI_VENDOR_ID_REALTEK,
+.device_id = PCI_DEVICE_ID_REALTEK_8029,
+.class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v2 33/38] hw/versatile_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/versatile_pci.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 2fed8a0..58a8f7e 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -133,9 +133,6 @@ static int pci_realview_init(SysBusDevice *dev)
static int versatile_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX);
-/* Both boards have the same device ID. Oh well. */
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_XILINX_XC2VP30);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO);
@@ -147,6 +144,9 @@ static PCIDeviceInfo versatile_pci_host_info = {
.qdev.name = "versatile_pci_host",
.qdev.size = sizeof(PCIDevice),
.init = versatile_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_XILINX,
+/* Both boards have the same device ID. Oh well. */
+.device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
};
static void versatile_pci_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 31/38] hw/unin_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/unin_pci.c | 34 +-
1 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index c57c0a1..4e1c6a4 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -279,10 +279,6 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic)
static int unin_main_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
-d->config[0x08] = 0x00; // revision
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
@@ -291,10 +287,6 @@ static int unin_main_pci_host_init(PCIDevice *d)
static int unin_agp_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
-d->config[0x08] = 0x00; // revision
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
//d->config[0x34] = 0x80; // capabilities_pointer
@@ -303,11 +295,6 @@ static int unin_agp_pci_host_init(PCIDevice *d)
static int u3_agp_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
-/* revision */
-d->config[0x08] = 0x00;
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
/* cache line size */
d->config[0x0C] = 0x08;
/* latency timer */
@@ -317,10 +304,6 @@ static int u3_agp_pci_host_init(PCIDevice *d)
static int unin_internal_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
-d->config[0x08] = 0x00; // revision
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
@@ -331,24 +314,41 @@ static PCIDeviceInfo unin_main_pci_host_info = {
.qdev.name = "uni-north",
.qdev.size = sizeof(PCIDevice),
.init = unin_main_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
+.revision = 0x00, // revision
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static PCIDeviceInfo u3_agp_pci_host_info = {
.qdev.name = "u3-agp",
.qdev.size = sizeof(PCIDevice),
.init = u3_agp_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
+/* revision */
+.revision = 0x00,
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static PCIDeviceInfo unin_agp_pci_host_info = {
.qdev.name = "uni-north-agp",
.qdev.size = sizeof(PCIDevice),
.init = unin_agp_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
+.revision = 0x00, // revision
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static PCIDeviceInfo unin_internal_pci_host_info = {
.qdev.name = "uni-north-pci",
.qdev.size = sizeof(PCIDevice),
.init = unin_internal_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_APPLE,
+.device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
+.revision = 0x00, // revision
+.class_id = PCI_CLASS_BRIDGE_HOST,
};
static void unin_register_devices(void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 30/38] hw/sun4u.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/sun4u.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 5eb38cf..b95daea 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -553,15 +553,11 @@ pci_ebus_init1(PCIDevice *s)
{
isa_bus_new(&s->qdev);
-pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
-pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
s->config[0x04] = 0x06; // command = bus master, pci mem
s->config[0x05] = 0x00;
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
s->config[0x07] = 0x03; // status = medium devsel
-s->config[0x08] = 0x01; // revision
s->config[0x09] = 0x00; // programming i/f
-pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
s->config[0x0D] = 0x0a; // latency_timer
pci_register_bar(s, 0, 0x100, PCI_BASE_ADDRESS_SPACE_MEMORY,
@@ -575,6 +571,10 @@ static PCIDeviceInfo ebus_info = {
.qdev.name = "ebus",
.qdev.size = sizeof(PCIDevice),
.init = pci_ebus_init1,
+.vendor_id = PCI_VENDOR_ID_SUN,
+.device_id = PCI_DEVICE_ID_SUN_EBUS,
+.revision = 0x01, // revision
+.class_id = PCI_CLASS_BRIDGE_OTHER,
};
static void pci_ebus_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 05/38] apb_pci: convert to PCIDeviceInfo to initialize ids
Use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/apb_pci.c | 13 ++---
1 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 84e9af7..974c87a 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -304,9 +304,6 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
return rc;
}
-pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_SUN);
-pci_config_set_device_id(dev->config, PCI_DEVICE_ID_SUN_SIMBA);
-
/*
* command register:
* According to PCI bridge spec, after reset
@@ -321,7 +318,6 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
pci_set_word(dev->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
PCI_STATUS_DEVSEL_MEDIUM);
-pci_set_byte(dev->config + PCI_REVISION_ID, 0x11);
return 0;
}
@@ -436,14 +432,11 @@ static int pci_pbm_init_device(SysBusDevice *dev)
static int pbm_pci_host_init(PCIDevice *d)
{
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE);
pci_set_word(d->config + PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_set_word(d->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
PCI_STATUS_DEVSEL_MEDIUM);
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
return 0;
}
@@ -451,6 +444,9 @@ static PCIDeviceInfo pbm_pci_host_info = {
.qdev.name = "pbm",
.qdev.size = sizeof(PCIDevice),
.init = pbm_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_SUN,
+.device_id = PCI_DEVICE_ID_SUN_SABRE,
+.class_id = PCI_CLASS_BRIDGE_HOST,
.is_bridge = 1,
};
@@ -468,6 +464,9 @@ static PCIDeviceInfo pbm_pci_bridge_info = {
.qdev.reset = pci_bridge_reset,
.init = apb_pci_bridge_initfn,
.exit = pci_bridge_exitfn,
+.vendor_id = PCI_VENDOR_ID_SUN,
+.device_id = PCI_DEVICE_ID_SUN_SIMBA,
+.revision = 0x11,
.config_write = pci_bridge_write_config,
.is_bridge = 1,
};
--
1.7.1.1
[Qemu-devel] [PATCH v2 26/38] hw/piix_pci.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/piix_pci.c | 19 +++
1 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 5f0d92f..41ba15c 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -228,11 +228,6 @@ static int i440fx_initfn(PCIDevice *dev)
{
PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
-pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
-d->dev.config[0x08] = 0x02; // revision
-pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
-
d->dev.config[I440FX_SMRAM] = 0x02;
cpu_smm_register(&i440fx_set_smm, d);
@@ -406,15 +401,8 @@ static const VMStateDescription vmstate_piix3 = {
static int piix3_initfn(PCIDevice *dev)
{
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
-uint8_t *pci_conf;
isa_bus_new(&d->dev.qdev);
-
-pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); //
82371SB PIIX3 PCI-to-ISA bridge (Step A1)
-pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
-
qemu_register_reset(piix3_reset, d);
return 0;
}
@@ -429,6 +417,10 @@ static PCIDeviceInfo i440fx_info[] = {
.no_hotplug = 1,
.init = i440fx_initfn,
.config_write = i440fx_write_config,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82441,
+.revision = 0x02, // revision
+.class_id = PCI_CLASS_BRIDGE_HOST,
},{
.qdev.name= "PIIX3",
.qdev.desc= "ISA bridge",
@@ -438,6 +430,9 @@ static PCIDeviceInfo i440fx_info[] = {
.no_hotplug = 1,
.init = piix3_initfn,
.config_write = piix3_write_config,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3
PCI-to-ISA bridge (Step A1)
+.class_id = PCI_CLASS_BRIDGE_ISA,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v2 02/38] usb-uhci: convert to PCIDEviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/usb-uhci.c | 46 +-
1 files changed, 17 insertions(+), 29 deletions(-)
diff --git a/hw/usb-uhci.c b/hw/usb-uhci.c
index 346db3e..536c24c 100644
--- a/hw/usb-uhci.c
+++ b/hw/usb-uhci.c
@@ -1115,14 +1115,13 @@ static USBPortOps uhci_port_ops = {
.wakeup = uhci_wakeup,
};
-static int usb_uhci_common_initfn(UHCIState *s)
+static int usb_uhci_common_initfn(PCIDevice *dev)
{
+UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
uint8_t *pci_conf = s->dev.config;
int i;
-pci_conf[PCI_REVISION_ID] = 0x01; // revision number
pci_conf[PCI_CLASS_PROG] = 0x00;
-pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
/* TODO: reset value should be 0. */
pci_conf[PCI_INTERRUPT_PIN] = 4; // interrupt pin 3
pci_conf[0x60] = 0x10; // release number
@@ -1148,34 +1147,11 @@ static int usb_uhci_common_initfn(UHCIState *s)
return 0;
}
-static int usb_uhci_piix3_initfn(PCIDevice *dev)
-{
-UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
-uint8_t *pci_conf = s->dev.config;
-
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2);
-return usb_uhci_common_initfn(s);
-}
-
-static int usb_uhci_piix4_initfn(PCIDevice *dev)
-{
-UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
-uint8_t *pci_conf = s->dev.config;
-
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2);
-return usb_uhci_common_initfn(s);
-}
-
static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
{
UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
uint8_t *pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
-pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_UHCI);
-
/* USB misc control 1/2 */
pci_set_long(pci_conf + 0x40,0x1000);
/* PM capability */
@@ -1183,7 +1159,7 @@ static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
/* USB legacy support */
pci_set_long(pci_conf + 0xc0,0x2000);
-return usb_uhci_common_initfn(s);
+return usb_uhci_common_initfn(dev);
}
static PCIDeviceInfo uhci_info[] = {
@@ -1191,17 +1167,29 @@ static PCIDeviceInfo uhci_info[] = {
.qdev.name= "piix3-usb-uhci",
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
-.init = usb_uhci_piix3_initfn,
+.init = usb_uhci_common_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371SB_2,
+.revision = 0x01,
+.class_id = PCI_CLASS_SERIAL_USB,
},{
.qdev.name= "piix4-usb-uhci",
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
-.init = usb_uhci_piix4_initfn,
+.init = usb_uhci_common_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82371AB_2,
+.revision = 0x01,
+.class_id = PCI_CLASS_SERIAL_USB,
},{
.qdev.name= "vt82c686b-usb-uhci",
.qdev.size= sizeof(UHCIState),
.qdev.vmsd= &vmstate_uhci,
.init = usb_uhci_vt82c686b_initfn,
+.vendor_id= PCI_VENDOR_ID_VIA,
+.device_id= PCI_DEVICE_ID_VIA_UHCI,
+.revision = 0x01,
+.class_id = PCI_CLASS_SERIAL_USB,
},{
/* end of list */
}
--
1.7.1.1
[Qemu-devel] [PATCH v2 20/38] hw/ioh3420.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ioh3420.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 95adf09..a6bfbb9 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -104,12 +104,8 @@ static int ioh3420_initfn(PCIDevice *d)
return rc;
}
-d->config[PCI_REVISION_ID] = PCI_DEVICE_ID_IOH_REV;
pcie_port_init_reg(d);
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_IOH_EPORT);
-
rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
if (rc < 0) {
@@ -217,6 +213,9 @@ static PCIDeviceInfo ioh3420_info = {
.config_write = ioh3420_write_config,
.init = ioh3420_initfn,
.exit = ioh3420_exitfn,
+.vendor_id = PCI_VENDOR_ID_INTEL,
+.device_id = PCI_DEVICE_ID_IOH_EPORT,
+.revision = PCI_DEVICE_ID_IOH_REV,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
--
1.7.1.1
[Qemu-devel] [PATCH v2 01/38] pci: move ids of config space into PCIDeviceInfo
vender id/device id... in configuration space are read-only registers
which are commonly defined for all pci devices.
So move those initialization into common place.
Signed-off-by: Isaku Yamahata
---
changes v1 -> v2:
- dropped prog_interface, header_type
- added assert() for header type = 1
---
hw/pci.c | 46 --
hw/pci.h |7 +++
2 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 0875654..0e97a02 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -726,10 +726,11 @@ static void pci_config_free(PCIDevice *pci_dev)
/* -1 for devfn means auto assign */
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
const char *name, int devfn,
- PCIConfigReadFunc *config_read,
- PCIConfigWriteFunc *config_write,
- bool is_bridge)
+ const PCIDeviceInfo *info)
{
+PCIConfigReadFunc *config_read = info->config_read;
+PCIConfigWriteFunc *config_write = info->config_write;
+
if (devfn < 0) {
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
devfn += PCI_FUNC_MAX) {
@@ -750,13 +751,29 @@ static PCIDevice *do_pci_register_device(PCIDevice
*pci_dev, PCIBus *bus,
pci_dev->irq_state = 0;
pci_config_alloc(pci_dev);
-if (!is_bridge) {
-pci_set_default_subsystem_id(pci_dev);
+pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
+pci_config_set_device_id(pci_dev->config, info->device_id);
+pci_config_set_revision(pci_dev->config, info->revision);
+pci_config_set_class(pci_dev->config, info->class_id);
+
+if (!info->is_bridge) {
+if (info->subsystem_vendor_id || info->subsystem_id) {
+pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
+ info->subsystem_vendor_id);
+pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
+ info->subsystem_id);
+} else {
+pci_set_default_subsystem_id(pci_dev);
+}
+} else {
+/* subsystem_vendor_id/subsystem_id are only for header type 0 */
+assert(!info->subsystem_vendor_id);
+assert(!info->subsystem_id);
}
pci_init_cmask(pci_dev);
pci_init_wmask(pci_dev);
pci_init_w1cmask(pci_dev);
-if (is_bridge) {
+if (info->is_bridge) {
pci_init_wmask_bridge(pci_dev);
}
if (pci_init_multifunction(bus, pci_dev)) {
@@ -783,17 +800,20 @@ static void do_pci_unregister_device(PCIDevice *pci_dev)
pci_config_free(pci_dev);
}
+/* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
int instance_size, int devfn,
PCIConfigReadFunc *config_read,
PCIConfigWriteFunc *config_write)
{
PCIDevice *pci_dev;
+PCIDeviceInfo info = {
+.config_read = config_read,
+.config_write = config_write,
+};
pci_dev = qemu_mallocz(instance_size);
-pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
- config_read, config_write,
- PCI_HEADER_TYPE_NORMAL);
+pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
if (pci_dev == NULL) {
hw_error("PCI: can't register device\n");
}
@@ -1643,7 +1663,7 @@ static int pci_qdev_init(DeviceState *qdev, DeviceInfo
*base)
PCIDevice *pci_dev = (PCIDevice *)qdev;
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
PCIBus *bus;
-int devfn, rc;
+int rc;
bool is_default_rom;
/* initialize cap_present for pci_is_express() and pci_config_size() */
@@ -1652,10 +1672,8 @@ static int pci_qdev_init(DeviceState *qdev, DeviceInfo
*base)
}
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
-devfn = pci_dev->devfn;
-pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
- info->config_read, info->config_write,
- info->is_bridge);
+pci_dev = do_pci_register_device(pci_dev, bus, base->name,
+ pci_dev->devfn, info);
if (pci_dev == NULL)
return -1;
if (qdev->hotplugged && info->no_hotplug) {
diff --git a/hw/pci.h b/hw/pci.h
index c6a6eb6..ce214f4 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -433,6 +433,13 @@ typedef struct {
PCIConfigReadFunc *config_read;
PCIConfigWriteFunc *config_write;
+uint16_t vendor_id;
+uint16_t device_id;
+uint8_t revision;
+uint16_
[Qemu-devel] [PATCH v2 21/38] hw/ivshmem.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ivshmem.c |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index 7b19a81..3055dd2 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -706,12 +706,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
}
pci_conf = s->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT_QUMRANET);
-pci_conf[0x02] = 0x10;
-pci_conf[0x03] = 0x11;
pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_RAM);
-pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
pci_config_set_interrupt_pin(pci_conf, 1);
@@ -809,6 +804,9 @@ static PCIDeviceInfo ivshmem_info = {
.qdev.reset = ivshmem_reset,
.init = pci_ivshmem_init,
.exit = pci_ivshmem_uninit,
+.vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET,
+.device_id = 0x1110,
+.class_id = PCI_CLASS_MEMORY_RAM,
.qdev.props = (Property[]) {
DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
DEFINE_PROP_STRING("size", IVShmemState, sizearg),
--
1.7.1.1
[Qemu-devel] [PATCH v2 12/38] hw/e1000.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/e1000.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/e1000.c b/hw/e1000.c
index f160bfc..96d84f9 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1164,12 +1164,8 @@ static int pci_e1000_init(PCIDevice *pci_dev)
pci_conf = d->dev.config;
-pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
-pci_config_set_device_id(pci_conf, E1000_DEVID);
/* TODO: we have no capabilities, so why is this bit set? */
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST);
-pci_conf[PCI_REVISION_ID] = 0x03;
-pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
/* TODO: RST# value should be 0, PCI spec 6.2.4 */
pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
@@ -1221,6 +1217,10 @@ static PCIDeviceInfo e1000_info = {
.init = pci_e1000_init,
.exit = pci_e1000_uninit,
.romfile= "pxe-e1000.rom",
+.vendor_id = PCI_VENDOR_ID_INTEL,
+.device_id = E1000_DEVID,
+.revision = 0x03,
+.class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(E1000State, conf),
DEFINE_PROP_END_OF_LIST(),
--
1.7.1.1
[Qemu-devel] [PATCH v2 11/38] hw/cirrus_vga.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/cirrus_vga.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 722cac7..e239e21 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -3097,7 +3097,6 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
{
PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
CirrusVGAState *s = &d->cirrus_vga;
- uint8_t *pci_conf = d->dev.config;
int device_id = CIRRUS_ID_CLGD5446;
/* setup VGA */
@@ -3108,9 +3107,6 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)
&s->vga);
/* setup PCI */
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
- pci_config_set_device_id(pci_conf, device_id);
- pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
/* setup memory space */
/* memory #0 LFB */
@@ -3139,6 +3135,9 @@ static PCIDeviceInfo cirrus_vga_info = {
.init = pci_cirrus_vga_initfn,
.romfile = VGABIOS_CIRRUS_FILENAME,
.config_write = pci_cirrus_write_config,
+.vendor_id= PCI_VENDOR_ID_CIRRUS,
+.device_id= CIRRUS_ID_CLGD5446,
+.class_id = PCI_CLASS_DISPLAY_VGA,
};
static void cirrus_vga_register(void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 27/38] hw/qxl.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/qxl.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/qxl.c b/hw/qxl.c
index fe4212b..63cffc3 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -1233,7 +1233,6 @@ static int qxl_init_common(PCIQXLDevice *qxl)
break;
}
-pci_config_set_vendor_id(config, REDHAT_PCI_VENDOR_ID);
pci_config_set_device_id(config, pci_device_id);
pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
@@ -1310,7 +1309,6 @@ static int qxl_init_primary(PCIDevice *dev)
qxl0 = qxl;
register_displaychangelistener(vga->ds, &display_listener);
-pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_VGA);
return qxl_init_common(qxl);
}
@@ -1330,7 +1328,6 @@ static int qxl_init_secondary(PCIDevice *dev)
qxl->vga.vram_size);
qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
-pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_OTHER);
return qxl_init_common(qxl);
}
@@ -1493,6 +1490,8 @@ static PCIDeviceInfo qxl_info_primary = {
.init = qxl_init_primary,
.config_write = qxl_write_config,
.romfile = "vgabios-qxl.bin",
+.vendor_id= REDHAT_PCI_VENDOR_ID,
+.class_id = PCI_CLASS_DISPLAY_VGA,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024
* 1024),
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 *
1024),
@@ -1511,6 +1510,8 @@ static PCIDeviceInfo qxl_info_secondary = {
.qdev.reset = qxl_reset_handler,
.qdev.vmsd= &qxl_vmstate,
.init = qxl_init_secondary,
+.vendor_id= REDHAT_PCI_VENDOR_ID,
+.class_id = PCI_CLASS_DISPLAY_OTHER,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024
* 1024),
DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 *
1024),
--
1.7.1.1
[Qemu-devel] [PATCH v2 08/38] hw/ac97.c: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/ac97.c |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/ac97.c b/hw/ac97.c
index d71072d..bf1d1d4 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -1281,9 +1281,6 @@ static int ac97_initfn (PCIDevice *dev)
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
uint8_t *c = s->dev.config;
-pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
-pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
-
/* TODO: no need to override */
c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
c[PCI_COMMAND + 1] = 0x00;
@@ -1292,9 +1289,7 @@ static int ac97_initfn (PCIDevice *dev)
c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
-c[PCI_REVISION_ID] = 0x01; /* rid revision ro */
c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
-pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
/* TODO set when bar is registered. no need to override. */
/* nabmar native audio mixer base address rw */
@@ -1341,6 +1336,10 @@ static PCIDeviceInfo ac97_info = {
.qdev.size= sizeof (AC97LinkState),
.qdev.vmsd= &vmstate_ac97,
.init = ac97_initfn,
+.vendor_id= PCI_VENDOR_ID_INTEL,
+.device_id= PCI_DEVICE_ID_INTEL_82801AA_5,
+.revision = 0x01, /* rid revision ro */
+.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
};
static void ac97_register (void)
--
1.7.1.1
[Qemu-devel] [PATCH v2 04/38] dec_pci: convert to PCIDeviceInfo to initialize ids
use PCIDeviceInfo to initialize ids.
Signed-off-by: Isaku Yamahata
---
hw/dec_pci.c | 26 +++---
1 files changed, 7 insertions(+), 19 deletions(-)
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index bf88f2a..a35f382 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -50,28 +50,16 @@ static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
return irq_num;
}
-static int dec_21154_initfn(PCIDevice *dev)
-{
-int rc;
-
-rc = pci_bridge_initfn(dev);
-if (rc < 0) {
-return rc;
-}
-
-pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_DEC);
-pci_config_set_device_id(dev->config, PCI_DEVICE_ID_DEC_21154);
-return 0;
-}
-
static PCIDeviceInfo dec_21154_pci_bridge_info = {
.qdev.name = "dec-21154-p2p-bridge",
.qdev.desc = "DEC 21154 PCI-PCI bridge",
.qdev.size = sizeof(PCIBridge),
.qdev.vmsd = &vmstate_pci_device,
.qdev.reset = pci_bridge_reset,
-.init = dec_21154_initfn,
+.init = pci_bridge_initfn,
.exit = pci_bridge_exitfn,
+.vendor_id = PCI_VENDOR_ID_DEC,
+.device_id = PCI_DEVICE_ID_DEC_21154,
.config_write = pci_bridge_write_config,
.is_bridge = 1,
};
@@ -108,10 +96,6 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
static int dec_21154_pci_host_init(PCIDevice *d)
{
/* PCI2PCI bridge same values as PearPC - check this */
-pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
-pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
-pci_set_byte(d->config + PCI_REVISION_ID, 0x02);
-pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
return 0;
}
@@ -119,6 +103,10 @@ static PCIDeviceInfo dec_21154_pci_host_info = {
.qdev.name = "dec-21154",
.qdev.size = sizeof(PCIDevice),
.init = dec_21154_pci_host_init,
+.vendor_id = PCI_VENDOR_ID_DEC,
+.device_id = PCI_DEVICE_ID_DEC_21154,
+.revision = 0x02,
+.class_id = PCI_CLASS_BRIDGE_PCI,
.is_bridge = 1,
};
--
1.7.1.1
