Re: [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)

[Philippe Mathieu-Daudé]

On 4/20/21 7:54 PM, Philippe Mathieu-Daudé wrote:
> The CACHEE opcode "requires CP0 privilege".
> 
> The pseudocode checks in the ISA manual is:
> 
> if is_eva and not C0.Config5.EVA:
>   raise exception('RI')
> 
> if not IsCoprocessor0Enabled():
>   raise coprocessor_exception(0)
> 
> Add the missing checks.
> 
> Inspired-by: Richard Henderson 
> Signed-off-by: Philippe Mathieu-Daudé 
> ---
>  target/mips/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Thanks, applied to mips-next.

Re: [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)

[Richard Henderson]

On 4/20/21 10:54 AM, Philippe Mathieu-Daudé wrote:

The CACHEE opcode "requires CP0 privilege".

The pseudocode checks in the ISA manual is:

 if is_eva and not C0.Config5.EVA:
   raise exception('RI')

 if not IsCoprocessor0Enabled():
   raise coprocessor_exception(0)

Add the missing checks.

Inspired-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
  target/mips/translate.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)


Reviewed-by: Richard Henderson 

r~

[PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)

[Philippe Mathieu-Daudé]

The CACHEE opcode "requires CP0 privilege".

The pseudocode checks in the ISA manual is:

if is_eva and not C0.Config5.EVA:
  raise exception('RI')

if not IsCoprocessor0Enabled():
  raise coprocessor_exception(0)

Add the missing checks.

Inspired-by: Richard Henderson 
Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 71fa5ec1973..5dad75cdf37 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20957,6 +20957,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, 
DisasContext *ctx)
 gen_ld(ctx, OPC_LHUE, rt, rs, s);
 break;
 case NM_CACHEE:
+check_eva(ctx);
+check_cp0_enabled(ctx);
 check_nms_dl_il_sl_tl_l2c(ctx);
 gen_cache_operation(ctx, rt, rs, s);
 break;
@@ -24530,11 +24532,11 @@ static void decode_opc_special3(CPUMIPSState *env, 
DisasContext *ctx)
 gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
 return;
 case OPC_CACHEE:
+check_eva(ctx);
 check_cp0_enabled(ctx);
 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
 gen_cache_operation(ctx, rt, rs, imm);
 }
-/* Treat as NOP. */
 return;
 case OPC_PREFE:
 check_cp0_enabled(ctx);
-- 
2.26.3