Re: [PATCH 1/2] riscv: zicond: make non-experimental
On Wed, Aug 9, 2023 at 4:18 AM Vineet Gupta wrote:
>
> zicond is now codegen supported in both llvm and gcc.
>
> This change allows seamless enabling/testing of zicond in downstream
> projects. e.g. currently riscv-gnu-toolchain parses elf attributes
> to create a cmdline for qemu but fails short of enabling it because of
> the "x-" prefix.
>
> Signed-off-by: Vineet Gupta
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6b93b04453c8..022bd9d01223 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1816,6 +1816,7 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
> DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
> DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
> +DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
>
> /* Vendor-specific custom extensions */
> DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
> @@ -1832,7 +1833,6 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
> false),
>
> /* These are experimental so mark with 'x-' */
> -DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
>
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.34.1
>
>
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On 8/10/23 10:14, Alistair Francis wrote:
On Tue, Aug 8, 2023 at 2:18 PM Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.
Signed-off-by: Vineet Gupta
Reviewed-by: Alistair Francis
Alistair
Gentle ping to remind that this lands in some -next tree and not forgotten !
Thx,
-Vineet
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453c8..022bd9d01223 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1816,6 +1816,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
@@ -1832,7 +1833,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
/* These are experimental so mark with 'x-' */
-DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.34.1
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On Tue, Aug 8, 2023 at 2:18 PM Vineet Gupta wrote:
>
> zicond is now codegen supported in both llvm and gcc.
>
> This change allows seamless enabling/testing of zicond in downstream
> projects. e.g. currently riscv-gnu-toolchain parses elf attributes
> to create a cmdline for qemu but fails short of enabling it because of
> the "x-" prefix.
>
> Signed-off-by: Vineet Gupta
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6b93b04453c8..022bd9d01223 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1816,6 +1816,7 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
> DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
> DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
> +DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
>
> /* Vendor-specific custom extensions */
> DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
> @@ -1832,7 +1833,6 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
> false),
>
> /* These are experimental so mark with 'x-' */
> -DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
>
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.34.1
>
>
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On Tue, Aug 8, 2023 at 5:16 PM Palmer Dabbelt wrote:
>
> On Tue, 08 Aug 2023 14:10:54 PDT (-0700), dbarb...@ventanamicro.com wrote:
> >
> >
> > On 8/8/23 17:52, Palmer Dabbelt wrote:
> >> On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
> >>>
> >>>
> >>> On 8/8/23 11:29, Richard Henderson wrote:
> On 8/8/23 11:17, Vineet Gupta wrote:
> > zicond is now codegen supported in both llvm and gcc.
>
> It is still not in
>
> https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
> >>>
> >>> Right, its been frozen since April though and with support trickling in
> >>> rest of tooling it becomes harder to test.
> >>> I don't know what exactly QEMU's policy is on this ?
> >>
> >> IIUC we'd historically marked stuff as non-experimental when it's frozen,
> >> largely because ratification is such a nebulous process. There's obviously
> >> risk there, but there's risk to anything. Last I can find is 260b594d8a
> >> ("RISC-V: Add Zawrs ISA extension support"), which specifically calls out
> >> Zawrs as frozen and IIUC adds support without the "x-" prefix.
> >
> > If that's the case then I think it's sensible to remove the 'experimental'
> > status
> > of zicond as well.
> >
> >>
> >> I can't find anything written down about it, though...
> >
> > As soon as we agree on an official policy I'll do a doc update. Thanks,
>
> Thanks. We should probably give Alistair some time to chime in, it's
> still pretty early there.
Frozen should be enough to remove the `x-`. We do have it written down
at:
https://wiki.qemu.org/Documentation/Platforms/RISCV#RISC-V_Foundation_Extensions
Alistair
>
> >
> >
> > Daniel
> >
> >>
>
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On Tue, 08 Aug 2023 14:10:54 PDT (-0700), dbarb...@ventanamicro.com wrote:
On 8/8/23 17:52, Palmer Dabbelt wrote:
On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
On 8/8/23 11:29, Richard Henderson wrote:
On 8/8/23 11:17, Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
It is still not in
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Right, its been frozen since April though and with support trickling in
rest of tooling it becomes harder to test.
I don't know what exactly QEMU's policy is on this ?
IIUC we'd historically marked stuff as non-experimental when it's frozen, largely because
ratification is such a nebulous process. There's obviously risk there, but there's risk to
anything. Last I can find is 260b594d8a ("RISC-V: Add Zawrs ISA extension support"),
which specifically calls out Zawrs as frozen and IIUC adds support without the "x-"
prefix.
If that's the case then I think it's sensible to remove the 'experimental'
status
of zicond as well.
I can't find anything written down about it, though...
As soon as we agree on an official policy I'll do a doc update. Thanks,
Thanks. We should probably give Alistair some time to chime in, it's
still pretty early there.
Daniel
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On 8/8/23 17:52, Palmer Dabbelt wrote:
On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
On 8/8/23 11:29, Richard Henderson wrote:
On 8/8/23 11:17, Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
It is still not in
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Right, its been frozen since April though and with support trickling in
rest of tooling it becomes harder to test.
I don't know what exactly QEMU's policy is on this ?
IIUC we'd historically marked stuff as non-experimental when it's frozen, largely because
ratification is such a nebulous process. There's obviously risk there, but there's risk to
anything. Last I can find is 260b594d8a ("RISC-V: Add Zawrs ISA extension support"),
which specifically calls out Zawrs as frozen and IIUC adds support without the "x-"
prefix.
If that's the case then I think it's sensible to remove the 'experimental'
status
of zicond as well.
I can't find anything written down about it, though...
As soon as we agree on an official policy I'll do a doc update. Thanks,
Daniel
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
On 8/8/23 11:29, Richard Henderson wrote:
On 8/8/23 11:17, Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
It is still not in
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Right, its been frozen since April though and with support trickling in
rest of tooling it becomes harder to test.
I don't know what exactly QEMU's policy is on this ?
IIUC we'd historically marked stuff as non-experimental when it's
frozen, largely because ratification is such a nebulous process.
There's obviously risk there, but there's risk to anything. Last I can
find is 260b594d8a ("RISC-V: Add Zawrs ISA extension support"), which
specifically calls out Zawrs as frozen and IIUC adds support without the
"x-" prefix.
I can't find anything written down about it, though...
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On 8/8/23 11:29, Richard Henderson wrote: On 8/8/23 11:17, Vineet Gupta wrote: zicond is now codegen supported in both llvm and gcc. It is still not in https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions Right, its been frozen since April though and with support trickling in rest of tooling it becomes harder to test. I don't know what exactly QEMU's policy is on this ? -Vineet
Re: [PATCH 1/2] riscv: zicond: make non-experimental
On 8/8/23 11:17, Vineet Gupta wrote: zicond is now codegen supported in both llvm and gcc. It is still not in https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions r~
[PATCH 1/2] riscv: zicond: make non-experimental
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.
Signed-off-by: Vineet Gupta
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453c8..022bd9d01223 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1816,6 +1816,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
@@ -1832,7 +1833,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
/* These are experimental so mark with 'x-' */
-DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.34.1
