Re: [PATCH v1 2/2] target/riscv: Drop support for ISA spec version 1.09.1

2020-05-07 Thread Alistair Francis 
On Wed, May 6, 2020 at 5:11 AM Philippe Mathieu-Daudé  wrote:
>
> Hi Alistair,
>
> On 5/6/20 3:12 AM, Alistair Francis wrote:
> > The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
> > 4.1. It's not commonly used so let's remove support for it.
> >
> > Signed-off-by: Alistair Francis 
> > ---
> >   target/riscv/cpu.c| 30 ---
> >   target/riscv/cpu.h|  8 --
> >   target/riscv/csr.c| 82 ---
> >   .../riscv/insn_trans/trans_privileged.inc.c   |  6 --
> >   tests/qtest/machine-none-test.c   |  4 +-
> >   5 files changed, 19 insertions(+), 111 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 059d71f2c7..eeb91f8513 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
> >   set_misa(env, 0);
> >   }
> >
> > -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > -CPURISCVState *env = _CPU(obj)->env;
> > -set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > -set_priv_version(env, PRIV_VERSION_1_09_1);
> > -set_resetvec(env, DEFAULT_RSTVEC);
> > -set_feature(env, RISCV_FEATURE_MMU);
> > -set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> >   static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> >   {
> >   CPURISCVState *env = _CPU(obj)->env;
> > @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
> >   set_misa(env, 0);
> >   }
> >
> > -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > -CPURISCVState *env = _CPU(obj)->env;
> > -set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > -set_priv_version(env, PRIV_VERSION_1_09_1);
> > -set_resetvec(env, DEFAULT_RSTVEC);
> > -set_feature(env, RISCV_FEATURE_MMU);
> > -set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> >   static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> >   {
> >   CPURISCVState *env = _CPU(obj)->env;
> > @@ -388,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> > **errp)
> >   priv_version = PRIV_VERSION_1_11_0;
> >   } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
> >   priv_version = PRIV_VERSION_1_10_0;
> > -} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
> > -priv_version = PRIV_VERSION_1_09_1;
> >   } else {
> >   error_setg(errp,
> >  "Unsupported privilege spec version '%s'",
> > @@ -621,18 +599,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> >   DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,   rv32imacu_nommu_cpu_init),
> >   DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,   
> > rv32imafcu_nommu_cpu_init),
> >   DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,   
> > rv32gcsu_priv1_10_0_cpu_init),
> > -/* Depreacted */
> > -DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
> > -DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, 
> > rv32gcsu_priv1_09_1_cpu_init),
> > -DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, 
> > rv32gcsu_priv1_10_0_cpu_init)
>
> Shouldn't you let TYPE_RISCV_CPU_RV32GCSU_V1_10_0 until you remove v1.10.0?
>
> Or remove TYPE_RISCV_CPU_RV32GCSU_V1_10_0 &
> TYPE_RISCV_CPU_RV64GCSU_V1_10_0 in another patch after this one
> (restricted to 1.09.1).

Fixed in v2, I have split this patch into 2.

Alistair

>
> >   #elif defined(TARGET_RISCV64)
> >   DEFINE_CPU(TYPE_RISCV_CPU_BASE64,   riscv_base64_cpu_init),
> >   DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,   rv64imacu_nommu_cpu_init),
> >   DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,   
> > rv64gcsu_priv1_10_0_cpu_init),
> > -/* Deprecated */
> > -DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
> > -DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, 
> > rv64gcsu_priv1_09_1_cpu_init),
> > -DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, 
> > rv64gcsu_priv1_10_0_cpu_init)
>
> Ditto.
>
> >   #endif
> >   };
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index d0e7f5b9c5..c022539012 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -40,13 +40,6 @@
> >   #define TYPE_RISCV_CPU_SIFIVE_E51   RISCV_CPU_TYPE_NAME("sifive-e51")
> >   #define TYPE_RISCV_CPU_SIFIVE_U34   RISCV_CPU_TYPE_NAME("sifive-u34")
> >   #define TYPE_RISCV_CPU_SIFIVE_U54   RISCV_CPU_TYPE_NAME("sifive-u54")
> > -/* Deprecated */
> > -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  
> > RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 
> > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 
> > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
>
> Ditto.
>
> > -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  
> > RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 
> >

Re: [PATCH v1 2/2] target/riscv: Drop support for ISA spec version 1.09.1

2020-05-06 Thread Philippe Mathieu-Daudé 

Hi Alistair,

On 5/6/20 3:12 AM, Alistair Francis wrote:

The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.

Signed-off-by: Alistair Francis 
---
  target/riscv/cpu.c| 30 ---
  target/riscv/cpu.h|  8 --
  target/riscv/csr.c| 82 ---
  .../riscv/insn_trans/trans_privileged.inc.c   |  6 --
  tests/qtest/machine-none-test.c   |  4 +-
  5 files changed, 19 insertions(+), 111 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..eeb91f8513 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
  set_misa(env, 0);
  }
  
-static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)

-{
-CPURISCVState *env = _CPU(obj)->env;
-set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-set_priv_version(env, PRIV_VERSION_1_09_1);
-set_resetvec(env, DEFAULT_RSTVEC);
-set_feature(env, RISCV_FEATURE_MMU);
-set_feature(env, RISCV_FEATURE_PMP);
-}
-
  static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
  {
  CPURISCVState *env = _CPU(obj)->env;
@@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
  set_misa(env, 0);
  }
  
-static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)

-{
-CPURISCVState *env = _CPU(obj)->env;
-set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-set_priv_version(env, PRIV_VERSION_1_09_1);
-set_resetvec(env, DEFAULT_RSTVEC);
-set_feature(env, RISCV_FEATURE_MMU);
-set_feature(env, RISCV_FEATURE_PMP);
-}
-
  static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
  {
  CPURISCVState *env = _CPU(obj)->env;
@@ -388,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
  priv_version = PRIV_VERSION_1_11_0;
  } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
  priv_version = PRIV_VERSION_1_10_0;
-} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
-priv_version = PRIV_VERSION_1_09_1;
  } else {
  error_setg(errp,
 "Unsupported privilege spec version '%s'",
@@ -621,18 +599,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,   rv32imacu_nommu_cpu_init),
  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,   rv32imafcu_nommu_cpu_init),
  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,   rv32gcsu_priv1_10_0_cpu_init),
-/* Depreacted */
-DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)


Shouldn't you let TYPE_RISCV_CPU_RV32GCSU_V1_10_0 until you remove v1.10.0?

Or remove TYPE_RISCV_CPU_RV32GCSU_V1_10_0 & 
TYPE_RISCV_CPU_RV64GCSU_V1_10_0 in another patch after this one 
(restricted to 1.09.1).



  #elif defined(TARGET_RISCV64)
  DEFINE_CPU(TYPE_RISCV_CPU_BASE64,   riscv_base64_cpu_init),
  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,   rv64imacu_nommu_cpu_init),
  DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,   rv64gcsu_priv1_10_0_cpu_init),
-/* Deprecated */
-DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)


Ditto.


  #endif
  };
  
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

index d0e7f5b9c5..c022539012 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -40,13 +40,6 @@
  #define TYPE_RISCV_CPU_SIFIVE_E51   RISCV_CPU_TYPE_NAME("sifive-e51")
  #define TYPE_RISCV_CPU_SIFIVE_U34   RISCV_CPU_TYPE_NAME("sifive-u34")
  #define TYPE_RISCV_CPU_SIFIVE_U54   RISCV_CPU_TYPE_NAME("sifive-u54")
-/* Deprecated */
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")


Ditto.


-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")


Ditto.

  
  #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))

  #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
@@ -80,7 +73,6 @@ enum {
  RISCV_FEATURE_MISA
  };
  
-#define PRIV_VERSION_1_09_1 0x00010901

  #define PRIV_VERSION_1_10_0 0x00011000
  #define PRIV_VERSION_1_11_0 0x00011100
  
diff --git a/target/riscv/csr.c b/target/riscv/csr.c

index 11d184cd16..df3498b24f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@

[PATCH v1 2/2] target/riscv: Drop support for ISA spec version 1.09.1

2020-05-05 Thread Alistair Francis 
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.

Signed-off-by: Alistair Francis 
---
 target/riscv/cpu.c| 30 ---
 target/riscv/cpu.h|  8 --
 target/riscv/csr.c| 82 ---
 .../riscv/insn_trans/trans_privileged.inc.c   |  6 --
 tests/qtest/machine-none-test.c   |  4 +-
 5 files changed, 19 insertions(+), 111 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..eeb91f8513 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
 set_misa(env, 0);
 }
 
-static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
-{
-CPURISCVState *env = _CPU(obj)->env;
-set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-set_priv_version(env, PRIV_VERSION_1_09_1);
-set_resetvec(env, DEFAULT_RSTVEC);
-set_feature(env, RISCV_FEATURE_MMU);
-set_feature(env, RISCV_FEATURE_PMP);
-}
-
 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
 {
 CPURISCVState *env = _CPU(obj)->env;
@@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
 set_misa(env, 0);
 }
 
-static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
-{
-CPURISCVState *env = _CPU(obj)->env;
-set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
-set_priv_version(env, PRIV_VERSION_1_09_1);
-set_resetvec(env, DEFAULT_RSTVEC);
-set_feature(env, RISCV_FEATURE_MMU);
-set_feature(env, RISCV_FEATURE_PMP);
-}
-
 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
 {
 CPURISCVState *env = _CPU(obj)->env;
@@ -388,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
**errp)
 priv_version = PRIV_VERSION_1_11_0;
 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 priv_version = PRIV_VERSION_1_10_0;
-} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
-priv_version = PRIV_VERSION_1_09_1;
 } else {
 error_setg(errp,
"Unsupported privilege spec version '%s'",
@@ -621,18 +599,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,   rv32imacu_nommu_cpu_init),
 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,   rv32imafcu_nommu_cpu_init),
 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,   rv32gcsu_priv1_10_0_cpu_init),
-/* Depreacted */
-DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
 #elif defined(TARGET_RISCV64)
 DEFINE_CPU(TYPE_RISCV_CPU_BASE64,   riscv_base64_cpu_init),
 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,   rv64imacu_nommu_cpu_init),
 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,   rv64gcsu_priv1_10_0_cpu_init),
-/* Deprecated */
-DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
-DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
 #endif
 };
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0e7f5b9c5..c022539012 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -40,13 +40,6 @@
 #define TYPE_RISCV_CPU_SIFIVE_E51   RISCV_CPU_TYPE_NAME("sifive-e51")
 #define TYPE_RISCV_CPU_SIFIVE_U34   RISCV_CPU_TYPE_NAME("sifive-u34")
 #define TYPE_RISCV_CPU_SIFIVE_U54   RISCV_CPU_TYPE_NAME("sifive-u54")
-/* Deprecated */
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
 
 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
@@ -80,7 +73,6 @@ enum {
 RISCV_FEATURE_MISA
 };
 
-#define PRIV_VERSION_1_09_1 0x00010901
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..df3498b24f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -58,31 +58,11 @@ static int ctr(CPURISCVState *env, int csrno)
 #if !defined(CONFIG_USER_ONLY)
 CPUState *cs = env_cpu(env);
 RISCVCPU *cpu = RISCV_CPU(cs);
-uint32_t ctr_en = ~0u;
 
 if (!cpu->cfg.ext_counters) {
 /* The Counters extensions is not enabled */
 return -1;
 }
-
-/*
- * The counters are always