Re: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState

[LIU Zhiwei]

On 2020/2/11 23:53, Richard Henderson wrote:

On 2/10/20 8:12 AM, LIU Zhiwei wrote:

The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
base address.

Signed-off-by: LIU Zhiwei 
---
  target/riscv/cpu.h | 13 +
  1 file changed, 13 insertions(+)

Reviewed-by: Richard Henderson 

I still don't think you need to put stuff into a sub-structure.  These register
names are unique in the manual, and not subdivided there.

OK. I will scatter these registers next patch.


r~

Re: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState

[Richard Henderson]

On 2/10/20 8:12 AM, LIU Zhiwei wrote:
> The 32 vector registers will be viewed as a continuous memory block.
> It avoids the convension between element index and (regno,offset).
> Thus elements can be directly accessed by offset from the first vector
> base address.
> 
> Signed-off-by: LIU Zhiwei 
> ---
>  target/riscv/cpu.h | 13 +
>  1 file changed, 13 insertions(+)

Reviewed-by: Richard Henderson 

I still don't think you need to put stuff into a sub-structure.  These register
names are unique in the manual, and not subdivided there.


r~

[PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState

[LIU Zhiwei]

The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno,offset).
Thus elements can be directly accessed by offset from the first vector
base address.

Signed-off-by: LIU Zhiwei 
---
 target/riscv/cpu.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de0a8d893a..07e63016a7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -93,9 +93,22 @@ typedef struct CPURISCVState CPURISCVState;
 
 #include "pmp.h"
 
+#define RV_VLEN_MAX 512
+
 struct CPURISCVState {
 target_ulong gpr[32];
 uint64_t fpr[32]; /* assume both F and D extensions */
+
+/* vector coprocessor state. */
+struct {
+ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
+ target_ulong vxrm;
+ target_ulong vxsat;
+ target_ulong vl;
+ target_ulong vstart;
+ target_ulong vtype;
+} vext;
+
 target_ulong pc;
 target_ulong load_res;
 target_ulong load_val;
-- 
2.23.0