RE: [PATCH v5 09/14] target/hexagon: import lexer for idef-parser

2021-06-23 Thread Taylor Simpson 



> -Original Message-
> From: Alessandro Di Federico 
> Sent: Saturday, June 19, 2021 3:37 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; bab...@rev.ng; ni...@rev.ng; phi...@redhat.com;
> richard.hender...@linaro.org; Alessandro Di Federico 
> Subject: [PATCH v5 09/14] target/hexagon: import lexer for idef-parser
> 
> From: Paolo Montesel 
> 
> Signed-off-by: Alessandro Di Federico 
> Signed-off-by: Paolo Montesel 
> ---
>  target/hexagon/idef-parser/idef-parser.h  | 262 
>  target/hexagon/idef-parser/idef-parser.lex| 597 ++
>  target/hexagon/meson.build|   4 +
>  tests/docker/dockerfiles/alpine.docker|   1 +
>  tests/docker/dockerfiles/centos8.docker   |   1 +
>  tests/docker/dockerfiles/debian-amd64.docker  |   1 +
>  tests/docker/dockerfiles/debian10.docker  |   1 +
>  .../dockerfiles/fedora-i386-cross.docker  |   1 +
>  .../dockerfiles/fedora-win32-cross.docker |   1 +
>  .../dockerfiles/fedora-win64-cross.docker |   1 +
>  tests/docker/dockerfiles/fedora.docker|   1 +
>  tests/docker/dockerfiles/opensuse-leap.docker |   1 +
>  tests/docker/dockerfiles/ubuntu.docker|   1 +
>  tests/docker/dockerfiles/ubuntu1804.docker|   1 +
>  tests/docker/dockerfiles/ubuntu2004.docker|   3 +-
>  15 files changed, 876 insertions(+), 1 deletion(-)  create mode 100644
> target/hexagon/idef-parser/idef-parser.h
>  create mode 100644 target/hexagon/idef-parser/idef-parser.lex
> 
> diff --git a/target/hexagon/idef-parser/idef-parser.h b/target/hexagon/idef-
> parser/idef-parser.h
> new file mode 100644

> +/**
> + * Types of control registers, assigned to the HexReg.id field  */
> +typedef enum {SP, FP, LR, GP, LC0, LC1, SA0, SA1} CregType;

Where is this used?  SP, FP, LR are not control registers - they are general 
purpose registers.


> diff --git a/target/hexagon/idef-parser/idef-parser.lex
> b/target/hexagon/idef-parser/idef-parser.lex
> new file mode 100644


> +"fREAD_SP()" |
> +"SP" { yylval->rvalue.type = REGISTER;
> +   yylval->rvalue.reg.type = CONTROL;
> +   yylval->rvalue.reg.id = SP;
> +   yylval->rvalue.reg.bit_width = 32;
> +   yylval->rvalue.bit_width = 32;
> +   return REG; }
> +"fREAD_FP()" |
> +"FP" { yylval->rvalue.type = REGISTER;
> +   yylval->rvalue.reg.type = CONTROL;
> +   yylval->rvalue.reg.id = FP;
> +   yylval->rvalue.reg.bit_width = 32;
> +   yylval->rvalue.bit_width = 32;
> +   return REG; }
> +"fREAD_LR()" |
> +"LR" { yylval->rvalue.type = REGISTER;
> +   yylval->rvalue.reg.type = CONTROL;
> +   yylval->rvalue.reg.id = LR;
> +   yylval->rvalue.reg.bit_width = 32;
> +   yylval->rvalue.bit_width = 32;
> +   return REG; }

This looks like the use where you are treating these as control registers.  
Just lex them as general purpose registers with numbers 29, 30, 31.

[PATCH v5 09/14] target/hexagon: import lexer for idef-parser

2021-06-19 Thread Alessandro Di Federico via 
From: Paolo Montesel 

Signed-off-by: Alessandro Di Federico 
Signed-off-by: Paolo Montesel 
---
 target/hexagon/idef-parser/idef-parser.h  | 262 
 target/hexagon/idef-parser/idef-parser.lex| 597 ++
 target/hexagon/meson.build|   4 +
 tests/docker/dockerfiles/alpine.docker|   1 +
 tests/docker/dockerfiles/centos8.docker   |   1 +
 tests/docker/dockerfiles/debian-amd64.docker  |   1 +
 tests/docker/dockerfiles/debian10.docker  |   1 +
 .../dockerfiles/fedora-i386-cross.docker  |   1 +
 .../dockerfiles/fedora-win32-cross.docker |   1 +
 .../dockerfiles/fedora-win64-cross.docker |   1 +
 tests/docker/dockerfiles/fedora.docker|   1 +
 tests/docker/dockerfiles/opensuse-leap.docker |   1 +
 tests/docker/dockerfiles/ubuntu.docker|   1 +
 tests/docker/dockerfiles/ubuntu1804.docker|   1 +
 tests/docker/dockerfiles/ubuntu2004.docker|   3 +-
 15 files changed, 876 insertions(+), 1 deletion(-)
 create mode 100644 target/hexagon/idef-parser/idef-parser.h
 create mode 100644 target/hexagon/idef-parser/idef-parser.lex

diff --git a/target/hexagon/idef-parser/idef-parser.h 
b/target/hexagon/idef-parser/idef-parser.h
new file mode 100644
index 00..d5feac8710
--- /dev/null
+++ b/target/hexagon/idef-parser/idef-parser.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#ifndef IDEF_PARSER_H
+#define IDEF_PARSER_H
+
+#include 
+#include 
+#include 
+#include 
+
+#define TCGV_NAME_SIZE 7
+#define MAX_WRITTEN_REGS 32
+#define OFFSET_STR_LEN 32
+#define ALLOC_LIST_LEN 32
+#define ALLOC_NAME_SIZE 32
+#define INIT_LIST_LEN 32
+#define OUT_BUF_LEN (1024 * 1024)
+#define SIGNATURE_BUF_LEN (128 * 1024)
+#define HEADER_BUF_LEN (128 * 1024)
+
+/* Variadic macros to wrap the buffer printing functions */
+#define EMIT(c, ...) \
+do { \
+g_string_append_printf((c)->out_str, __VA_ARGS__);   \
+} while (0)
+
+#define EMIT_SIG(c, ...)   
\
+do {   
\
+g_string_append_printf((c)->signature_str, __VA_ARGS__);   
\
+} while (0)
+
+#define EMIT_HEAD(c, ...)  
\
+do {   
\
+g_string_append_printf((c)->header_str, __VA_ARGS__);  
\
+} while (0)
+
+/**
+ * Type of register, assigned to the HexReg.type field
+ */
+typedef enum {GENERAL_PURPOSE, CONTROL, MODIFIER, DOTNEW} RegType;
+
+/**
+ * Types of control registers, assigned to the HexReg.id field
+ */
+typedef enum {SP, FP, LR, GP, LC0, LC1, SA0, SA1} CregType;
+
+/**
+ * Identifier string of the control registers, indexed by the CregType enum
+ */
+extern const char *creg_str[];
+
+/**
+ * Semantic record of the REG tokens, identifying registers
+ */
+typedef struct HexReg {
+CregType id;/**< Identifier of the register  */
+RegType type;   /**< Type of the register*/
+unsigned bit_width; /**< Bit width of the reg, 32 or 64 bits */
+} HexReg;
+
+/**
+ * Data structure, identifying a TCGv temporary value
+ */
+typedef struct HexTmp {
+int index;  /**< Index of the TCGv temporary value*/
+} HexTmp;
+
+/**
+ * Enum of the possible immediated, an immediate is a value which is known
+ * at tinycode generation time, e.g. an integer value, not a TCGv
+ */
+enum ImmUnionTag {
+I,
+VARIABLE,
+VALUE,
+QEMU_TMP,
+IMM_PC,
+IMM_NPC,
+IMM_CONSTEXT,
+};
+
+/**
+ * Semantic record of the IMM token, identifying an immediate constant
+ */
+typedef struct HexImm {
+union {
+char id;/**< Identifier of the immediate */
+uint64_t value; /**< Immediate value (for VALUE type immediates) */
+uint64_t index; /**< Index of the immediate (for int temp vars)  */
+};
+enum ImmUnionTag type;  /**< Type of the immediate  */
+} HexImm;
+
+/**
+ * Semantic record of the PRE