Re: [PULL v2 00/69] MIPS patches for 2021-01-14
On Thu, 14 Jan 2021 at 16:56, Philippe Mathieu-Daudé wrote: > > Resending the MIPS pull request from MIPS patches from last week > (2021-01-07) now than the "decodetree: Open files with encoding='utf-8'" > patch got merged (commit 4cacecaaa2b). > > > MIPS patches queue > > - Simplify CPU/ISA definitions > - Various maintenance code movements in translate.c > - Convert part of the MSA ASE instructions to decodetree > - Convert some instructions removed from Release 6 to decodetree > - Remove deprecated 'fulong2e' machine alias > > > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
[PULL v2 00/69] MIPS patches for 2021-01-14
Resending the MIPS pull request from MIPS patches from last week
(2021-01-07) now than the "decodetree: Open files with encoding='utf-8'"
patch got merged (commit 4cacecaaa2b).
Pre-existing checkpatch warnings in patch 23
(target/mips: Move common helpers from helper.c to cpu.c):
ERROR: space prohibited after that '&' (ctx:WxW)
#52: FILE: target/mips/cpu.c:53:
+cu = (v >> CP0St_CU0) & 0xf;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#53: FILE: target/mips/cpu.c:54:
+mx = (v >> CP0St_MX) & 0x1;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#54: FILE: target/mips/cpu.c:55:
+ksu = (v >> CP0St_KSU) & 0x3;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#81: FILE: target/mips/cpu.c:82:
+uint32_t ksux = (1 << CP0St_KX) & val;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#89: FILE: target/mips/cpu.c:90:
+mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#116: FILE: target/mips/cpu.c:117:
+mask &= ~((1 << CP0Ca_WP) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#121: FILE: target/mips/cpu.c:122:
+if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
^
ERROR: space prohibited after that '&' (ctx:WxW)
#131: FILE: target/mips/cpu.c:132:
+if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
^
total: 8 errors, 0 warnings, 433 lines checked
The following changes since commit 7c79721606be11b5bc556449e5bcbc331ef6867d:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210113' into
staging (2021-01-14 09:54:29 +)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/mips-20210114
for you to fetch changes up to cd669e20516fad3d8154629f67d4b6caede9b381:
docs/system: Remove deprecated 'fulong2e' machine alias (2021-01-14 17:13:54
+0100)
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
Jiaxun Yang (1):
target/mips/addr: Add translation helpers for KSEG1
Philippe Mathieu-Daudé (68):
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
target/mips: Replace CP0_Config0 magic values by proper definitions
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
target/mips/mips-defs: Reorder CPU_MIPS5 definition
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
target/mips: Inline cpu_state_reset() in mips_cpu_reset()
target/mips: Extract FPU helpers to 'fpu_helper.h'
target/mips: Add !CONFIG_USER_ONLY comment after #endif
target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
target/mips: Move common helpers from helper.c to cpu.c
target/mips: Rename helper.c as tlb_helper.c
target/mips: Fix code style for checkpatch.pl
target/mips: Move mmu_init() functions to tlb_helper.c
target/mips: Rename translate_init.c as cpu-defs.c
target/mips/translate: Extract DisasContext structure
target/mips/translate: Add declarations for generic code
target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
target/mips: Replace gen_exception_end(EXCP_RI) by
gen_rsvd_instruction
target/mips: Declare generic FPU / Coprocessor functions in
translate.h
target/mips: Extract FPU specific definitions to translate.h
target/mips: Only build TCG code when CONFIG_TCG is set
target/mips/translate: Extract decode_opc_legacy() from decode_opc()
target/mips/translate: Expose check_mips_64() to 32-bit mode
target/mips: Introduce
