Re: [Qemu-devel] [PATCH] ppc: Add support for 'mffsce' instruction

[David Gibson]

On Sat, Sep 14, 2019 at 01:00:21PM -0400, Richard Henderson wrote:
> On 9/12/19 8:54 AM, Paul A. Clarke wrote:
> > From: "Paul A. Clarke" 
> > 
> > ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> > instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
> > This patch adds support for 'mffsce' instruction.
> > 
> > 'mffsce' is identical to 'mffs', except that it also clears the exception
> > enable bits in the FPSCR.
> > 
> > On CPUs without support for 'mffsce' (below ISA 3.0), the
> > instruction will execute identically to 'mffs'.
> > 
> > Signed-off-by: Paul A. Clarke 
> > ---
> >  target/ppc/translate/fp-impl.inc.c | 30 ++
> >  target/ppc/translate/fp-ops.inc.c  |  2 ++
> >  2 files changed, 32 insertions(+)
> > 
> > diff --git a/target/ppc/translate/fp-impl.inc.c 
> > b/target/ppc/translate/fp-impl.inc.c
> > index 59a4faf..34edc45 100644
> > --- a/target/ppc/translate/fp-impl.inc.c
> > +++ b/target/ppc/translate/fp-impl.inc.c
> > @@ -639,6 +639,36 @@ static void gen_mffsl(DisasContext *ctx)
> >  tcg_temp_free_i64(t0);
> >  }
> >  
> > +/* mffsce */
> > +static void gen_mffsce(DisasContext *ctx)
> > +{
> > +TCGv_i64 t0;
> > +TCGv_i32 mask;
> > +
> > +if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
> > +return gen_mffs(ctx);
> > +}
> > +
> > +if (unlikely(!ctx->fpu_enabled)) {
> > +gen_exception(ctx, POWERPC_EXCP_FPU);
> > +return;
> > +}
> > +
> > +t0 = tcg_temp_new_i64();
> > +
> > +gen_reset_fpstatus();
> 
> Note for future cleanup: we should not need to sprinkle these all over.  This
> should be the steady-state condition after softfp exceptions have been
> processed into powerpc exceptions, after every single fp instruction.
> 
> That said, you're mirroring gen_mffs here, and the cleanup should
> happen globally.

This doesn't apply, presuambly because it's on top of the other
patch.  So I'll wait for the respin that includes the small update
that rtc requested on that one.

> 
> Reviewed-by: Richard Henderson 
> 
> 
> r~
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH] ppc: Add support for 'mffsce' instruction

[Richard Henderson]

On 9/12/19 8:54 AM, Paul A. Clarke wrote:
> From: "Paul A. Clarke" 
> 
> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
> This patch adds support for 'mffsce' instruction.
> 
> 'mffsce' is identical to 'mffs', except that it also clears the exception
> enable bits in the FPSCR.
> 
> On CPUs without support for 'mffsce' (below ISA 3.0), the
> instruction will execute identically to 'mffs'.
> 
> Signed-off-by: Paul A. Clarke 
> ---
>  target/ppc/translate/fp-impl.inc.c | 30 ++
>  target/ppc/translate/fp-ops.inc.c  |  2 ++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/target/ppc/translate/fp-impl.inc.c 
> b/target/ppc/translate/fp-impl.inc.c
> index 59a4faf..34edc45 100644
> --- a/target/ppc/translate/fp-impl.inc.c
> +++ b/target/ppc/translate/fp-impl.inc.c
> @@ -639,6 +639,36 @@ static void gen_mffsl(DisasContext *ctx)
>  tcg_temp_free_i64(t0);
>  }
>  
> +/* mffsce */
> +static void gen_mffsce(DisasContext *ctx)
> +{
> +TCGv_i64 t0;
> +TCGv_i32 mask;
> +
> +if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
> +return gen_mffs(ctx);
> +}
> +
> +if (unlikely(!ctx->fpu_enabled)) {
> +gen_exception(ctx, POWERPC_EXCP_FPU);
> +return;
> +}
> +
> +t0 = tcg_temp_new_i64();
> +
> +gen_reset_fpstatus();

Note for future cleanup: we should not need to sprinkle these all over.  This
should be the steady-state condition after softfp exceptions have been
processed into powerpc exceptions, after every single fp instruction.

That said, you're mirroring gen_mffs here, and the cleanup should happen 
globally.

Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [PATCH] ppc: Add support for 'mffsce' instruction

[Paul A. Clarke]

From: "Paul A. Clarke" 

ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.

'mffsce' is identical to 'mffs', except that it also clears the exception
enable bits in the FPSCR.

On CPUs without support for 'mffsce' (below ISA 3.0), the
instruction will execute identically to 'mffs'.

Signed-off-by: Paul A. Clarke 
---
 target/ppc/translate/fp-impl.inc.c | 30 ++
 target/ppc/translate/fp-ops.inc.c  |  2 ++
 2 files changed, 32 insertions(+)

diff --git a/target/ppc/translate/fp-impl.inc.c 
b/target/ppc/translate/fp-impl.inc.c
index 59a4faf..34edc45 100644
--- a/target/ppc/translate/fp-impl.inc.c
+++ b/target/ppc/translate/fp-impl.inc.c
@@ -639,6 +639,36 @@ static void gen_mffsl(DisasContext *ctx)
 tcg_temp_free_i64(t0);
 }
 
+/* mffsce */
+static void gen_mffsce(DisasContext *ctx)
+{
+TCGv_i64 t0;
+TCGv_i32 mask;
+
+if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
+return gen_mffs(ctx);
+}
+
+if (unlikely(!ctx->fpu_enabled)) {
+gen_exception(ctx, POWERPC_EXCP_FPU);
+return;
+}
+
+t0 = tcg_temp_new_i64();
+
+gen_reset_fpstatus();
+tcg_gen_extu_tl_i64(t0, cpu_fpscr);
+set_fpr(rD(ctx->opcode), t0);
+
+/* Clear exception enable bits in the FPSCR.  */
+tcg_gen_andi_i64(t0, t0, ~FP_ENABLES);
+mask = tcg_const_i32(0x0003);
+gen_helper_store_fpscr(cpu_env, t0, mask);
+
+tcg_temp_free_i32(mask);
+tcg_temp_free_i64(t0);
+}
+
 static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
 {
 TCGv_i64 t0 = tcg_temp_new_i64();
diff --git a/target/ppc/translate/fp-ops.inc.c 
b/target/ppc/translate/fp-ops.inc.c
index f2bcf0e..88fab65 100644
--- a/target/ppc/translate/fp-ops.inc.c
+++ b/target/ppc/translate/fp-ops.inc.c
@@ -105,6 +105,8 @@ GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x0001, 
PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x0001, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
 GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x, PPC_FLOAT, PPC_NONE),
+GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x, PPC_FLOAT,
+PPC2_ISA300),
 GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x, PPC_FLOAT,
 PPC2_ISA300),
 GEN_HANDLER_E_2(mffscrn, 0x3F, 0x07, 0x12, 0x16, 0x, PPC_FLOAT,
-- 
1.8.3.1