Re: [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180809042206.15726-1-richard.hender...@linaro.org Subject: [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline $BASE.. | wc -l) failed=0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram commits="$(git log --format=%H --reverse $BASE..)" for c in $commits; do echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..." if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then failed=1 echo fi n=$((n+1)) done exit $failed === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 35e9c8f21d target/arm: Pass TCGMemOpIdx to sve memory helpers 6b726db20c target/arm: Rewrite vector gather first-fault loads 42f47a681a target/arm: Rewrite vector gather stores ebdf36bdd6 target/arm: Rewrite vector gather loads bea4bda9bd target/arm: Split contiguous stores for endianness f74a87d369 target/arm: Split contiguous loads for endianness 522240fd71 target/arm: Rewrite helper_sve_st[1234]*_r 291c9a4079 target/arm: Rewrite helper_sve_ld[234]*_r 761fe6b96c target/arm: Rewrite helper_sve_ld1*_r using pages 439f82f39c target/arm: Clear unused predicate bits for LD1RQ 9f664be291 target/arm: Adjust aarch64_cpu_dump_state for system mode SVE 72b8c608a0 target/arm: Handle SVE vector length changes in system mode 4d25343973 target/arm: Pass in current_el to fp and sve_exception_el f63e45c476 target/arm: Fix is_a64 for user-only 77c7e3327f target/arm: Fix arm_current_el for user-only 065eea0432 target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only 4fb82ef6d0 target/arm: Adjust sve_exception_el bc8fa3f868 target/arm: Define ID_AA64ZFR0_EL1 3233806b21 target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max 2989413056 target/arm: Set ISAR bits for -cpu max === OUTPUT BEGIN === Checking PATCH 1/20: target/arm: Set ISAR bits for -cpu max... Checking PATCH 2/20: target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max... Checking PATCH 3/20: target/arm: Define ID_AA64ZFR0_EL1... Checking PATCH 4/20: target/arm: Adjust sve_exception_el... ERROR: return is not a function, parentheses are not required #57: FILE: target/arm/helper.c:4367: +return (arm_feature(env, ARM_FEATURE_EL2) total: 1 errors, 0 warnings, 113 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 5/20: target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only... Checking PATCH 6/20: target/arm: Fix arm_current_el for user-only... Checking PATCH 7/20: target/arm: Fix is_a64 for user-only... Checking PATCH 8/20: target/arm: Pass in current_el to fp and sve_exception_el... Checking PATCH 9/20: target/arm: Handle SVE vector length changes in system mode... Checking PATCH 10/20: target/arm: Adjust aarch64_cpu_dump_state for system mode SVE... Checking PATCH 11/20: target/arm: Clear unused predicate bits for LD1RQ... Checking PATCH 12/20: target/arm: Rewrite helper_sve_ld1*_r using pages... Checking PATCH 13/20: target/arm: Rewrite helper_sve_ld[234]*_r... Checking PATCH 14/20: target/arm: Rewrite helper_sve_st[1234]*_r... ERROR: spaces required around that '*' (ctx:WxV) #215: FILE: target/arm/sve_helper.c:4825: + sve_st1_tlb_fn *tlb_fn) ^ total: 1 errors, 0 warnings, 392 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 15/20: target/arm: Split contiguous loads for endianness... Checking PATCH 16/20: target/arm: Split contiguous stores for endianness... Checking PATCH 17/20: target/arm: Rewrite vector gather loads... Checking PATCH 18/20: target/arm: Rewrite vector gather stores... Checking PATCH 19/20: target/arm: Rewrite vector gather first-fault loads... ERROR: spaces required around that '*' (ctx:WxV) #292: FILE: target/arm/sve_helper.c:5216: +zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn, ^ ERROR: spaces required around that '*' (ctx:WxV) #292: FILE: target/arm/sve_helper.c:5216: +zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn, ^ ERROR: spaces required around that '*' (ctx:WxV) #293: FILE: target/arm/sve_helper.c:5217: +sve_ld1_nf_fn *nonfault_fn) ^ total: 3 errors, 0 warnings, 573 lines checked Your patch has style problems, please review. If any of these errors are fa
Re: [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches
Hi, This series failed docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180809042206.15726-1-richard.hender...@linaro.org Subject: [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches === TEST SCRIPT BEGIN === #!/bin/bash time make docker-test-quick@centos7 SHOW_ENV=1 J=8 === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 35e9c8f21d target/arm: Pass TCGMemOpIdx to sve memory helpers 6b726db20c target/arm: Rewrite vector gather first-fault loads 42f47a681a target/arm: Rewrite vector gather stores ebdf36bdd6 target/arm: Rewrite vector gather loads bea4bda9bd target/arm: Split contiguous stores for endianness f74a87d369 target/arm: Split contiguous loads for endianness 522240fd71 target/arm: Rewrite helper_sve_st[1234]*_r 291c9a4079 target/arm: Rewrite helper_sve_ld[234]*_r 761fe6b96c target/arm: Rewrite helper_sve_ld1*_r using pages 439f82f39c target/arm: Clear unused predicate bits for LD1RQ 9f664be291 target/arm: Adjust aarch64_cpu_dump_state for system mode SVE 72b8c608a0 target/arm: Handle SVE vector length changes in system mode 4d25343973 target/arm: Pass in current_el to fp and sve_exception_el f63e45c476 target/arm: Fix is_a64 for user-only 77c7e3327f target/arm: Fix arm_current_el for user-only 065eea0432 target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only 4fb82ef6d0 target/arm: Adjust sve_exception_el bc8fa3f868 target/arm: Define ID_AA64ZFR0_EL1 3233806b21 target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max 2989413056 target/arm: Set ISAR bits for -cpu max === OUTPUT BEGIN === BUILD centos7 make[1]: Entering directory '/var/tmp/patchew-tester-tmp-6uc3dv26/src' GEN /var/tmp/patchew-tester-tmp-6uc3dv26/src/docker-src.2018-08-18-05.57.51.13090/qemu.tar Cloning into '/var/tmp/patchew-tester-tmp-6uc3dv26/src/docker-src.2018-08-18-05.57.51.13090/qemu.tar.vroot'... done. Your branch is up-to-date with 'origin/test'. Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into '/var/tmp/patchew-tester-tmp-6uc3dv26/src/docker-src.2018-08-18-05.57.51.13090/qemu.tar.vroot/dtc'... Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42' Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb' Cloning into '/var/tmp/patchew-tester-tmp-6uc3dv26/src/docker-src.2018-08-18-05.57.51.13090/qemu.tar.vroot/ui/keycodemapdb'... Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce' COPYRUNNER RUN test-quick in qemu:centos7 Packages installed: SDL-devel-1.2.15-14.el7.x86_64 bison-3.0.4-1.el7.x86_64 bzip2-devel-1.0.6-13.el7.x86_64 ccache-3.3.4-1.el7.x86_64 csnappy-devel-0-6.20150729gitd7bc683.el7.x86_64 flex-2.5.37-3.el7.x86_64 gcc-4.8.5-16.el7_4.2.x86_64 gettext-0.19.8.1-2.el7.x86_64 git-1.8.3.1-12.el7_4.x86_64 glib2-devel-2.50.3-3.el7.x86_64 libepoxy-devel-1.3.1-1.el7.x86_64 libfdt-devel-1.4.6-1.el7.x86_64 lzo-devel-2.06-8.el7.x86_64 make-3.82-23.el7.x86_64 mesa-libEGL-devel-17.0.1-6.20170307.el7.x86_64 mesa-libgbm-devel-17.0.1-6.20170307.el7.x86_64 package g++ is not installed package librdmacm-devel is not installed pixman-devel-0.34.0-1.el7.x86_64 spice-glib-devel-0.33-6.el7_4.1.x86_64 spice-server-devel-0.12.8-2.el7.1.x86_64 tar-1.26-32.el7.x86_64 vte-devel-0.28.2-10.el7.x86_64 xen-devel-4.6.6-10.el7.x86_64 zlib-devel-1.2.7-17.el7.x86_64 Environment variables: PACKAGES=bison bzip2-devel ccache csnappy-devel flex g++ gcc gettext git glib2-devel libepoxy-devel libfdt-devel librdmacm-devel lzo-devel make mesa-libEGL-devel mesa-libgbm-devel pixman-devel SDL-devel spice-glib-devel spice-server-devel tar vte-devel xen-devel zlib-devel HOSTNAME=78baf9183a69 MAKEFLAGS= -j8 J=8 CCACHE_DIR=/var/tmp/ccache EXTRA_CONFIGURE_OPTS= V= SHOW_ENV=1 PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin PWD=/ TARGET_LIST= SHLVL=1 HOME=/home/patchew TEST_DIR=/tmp/qemu-test FEATURES= dtc DEBUG= _=/usr/bin/env Configure options: --enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/tmp/qemu-test/install No C++ compiler available; disabling C++ specific optional code Install prefix/tmp/qemu-test/install BIOS directory/tmp/qemu-test/install/share/qemu firmware path /tmp/qemu-test/install/share/qemu-firmware binary directory /tmp/qemu-test/install/bin library directory /tmp/qemu-test/install/lib module directory /tmp/qemu-test/install/lib/qemu libexec directory /tmp/qemu-test/install/libexec include directory /tmp/qemu-test/install/include config directory /tmp/qemu-test/install/etc local state directory /tmp/qemu-test/install/var Manual directory /tmp/qemu-test/install/share/man ELF
Re: [Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches
Hello, On Thu, Aug 9, 2018 at 6:21 AM, Richard Henderson wrote: > This is my current set of patches for running SVE in system mode. > > The first half deal with the system registers that affect SVE. > I recall that Peter has said he'd like the first patch to be > done a different way, but we haven't had a chance to talk about > what form it should take. I've left it as-is since it does what > I need for now. > > The second half re-implement the SVE memory operations. > The FF and NF loads had been stubbed out. Getting those to work > requires some infrastructure that can be reused to speed up normal > loads -- one guest-to-host tlb lookup can be reused for the rest > of the page. I did not review every patch individually but tested the whole and found no issue. Tested-by: Laurent Desnogues Thanks, Laurent > > r~ > > > Based-on: <20180809034033.10579-1-richard.hender...@linaro.org> > Richard Henderson (20): > target/arm: Set ISAR bits for -cpu max > target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max > target/arm: Define ID_AA64ZFR0_EL1 > target/arm: Adjust sve_exception_el > target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only > target/arm: Fix arm_current_el for user-only > target/arm: Fix is_a64 for user-only > target/arm: Pass in current_el to fp and sve_exception_el > target/arm: Handle SVE vector length changes in system mode > target/arm: Adjust aarch64_cpu_dump_state for system mode SVE > target/arm: Clear unused predicate bits for LD1RQ > target/arm: Rewrite helper_sve_ld1*_r using pages > target/arm: Rewrite helper_sve_ld[234]*_r > target/arm: Rewrite helper_sve_st[1234]*_r > target/arm: Split contiguous loads for endianness > target/arm: Split contiguous stores for endianness > target/arm: Rewrite vector gather loads > target/arm: Rewrite vector gather stores > target/arm: Rewrite vector gather first-fault loads > target/arm: Pass TCGMemOpIdx to sve memory helpers > > target/arm/cpu.h | 47 +- > target/arm/helper-sve.h| 385 +-- > target/arm/internals.h |5 + > target/arm/cpu.c | 24 +- > target/arm/cpu64.c | 93 +- > target/arm/helper.c| 237 +++-- > target/arm/op_helper.c |1 + > target/arm/sve_helper.c| 2062 +--- > target/arm/translate-a64.c |8 +- > target/arm/translate-sve.c | 670 > 10 files changed, 2453 insertions(+), 1079 deletions(-) > > -- > 2.17.1 >
[Qemu-devel] [PATCH 00/20] target/arm: sve system mode patches
This is my current set of patches for running SVE in system mode. The first half deal with the system registers that affect SVE. I recall that Peter has said he'd like the first patch to be done a different way, but we haven't had a chance to talk about what form it should take. I've left it as-is since it does what I need for now. The second half re-implement the SVE memory operations. The FF and NF loads had been stubbed out. Getting those to work requires some infrastructure that can be reused to speed up normal loads -- one guest-to-host tlb lookup can be reused for the rest of the page. r~ Based-on: <20180809034033.10579-1-richard.hender...@linaro.org> Richard Henderson (20): target/arm: Set ISAR bits for -cpu max target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max target/arm: Define ID_AA64ZFR0_EL1 target/arm: Adjust sve_exception_el target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only target/arm: Fix arm_current_el for user-only target/arm: Fix is_a64 for user-only target/arm: Pass in current_el to fp and sve_exception_el target/arm: Handle SVE vector length changes in system mode target/arm: Adjust aarch64_cpu_dump_state for system mode SVE target/arm: Clear unused predicate bits for LD1RQ target/arm: Rewrite helper_sve_ld1*_r using pages target/arm: Rewrite helper_sve_ld[234]*_r target/arm: Rewrite helper_sve_st[1234]*_r target/arm: Split contiguous loads for endianness target/arm: Split contiguous stores for endianness target/arm: Rewrite vector gather loads target/arm: Rewrite vector gather stores target/arm: Rewrite vector gather first-fault loads target/arm: Pass TCGMemOpIdx to sve memory helpers target/arm/cpu.h | 47 +- target/arm/helper-sve.h| 385 +-- target/arm/internals.h |5 + target/arm/cpu.c | 24 +- target/arm/cpu64.c | 93 +- target/arm/helper.c| 237 +++-- target/arm/op_helper.c |1 + target/arm/sve_helper.c| 2062 +--- target/arm/translate-a64.c |8 +- target/arm/translate-sve.c | 670 10 files changed, 2453 insertions(+), 1079 deletions(-) -- 2.17.1
