Re: [Qemu-devel] [PATCH RFC v19 00/13] QEMU AVR 8 bit cores
No, I can't. I did not build any peripherals. I expect other people to join for this task. On Wed, Jul 5, 2017, 6:59 PM Richard Henderson wrote: > On 07/04/2017 08:34 PM, Michael Rolnik wrote: > > Hi Richard. > > > > Thank you for finding a bug. > > As for the testing > > 1. I have a small program that calculates fibonacci numbers. I use it to > test > > mainly stack operations for different CPU flavors (1, 2 or 3 bytes PC). > > 2. I manually verified that I can debug with gdb, that includes > > a. stepping > > b. running > > c. stopping > > d. breakpoints > > e. backtrace shows correct stack > > 3. I manually verified that I can save and load vm states > > 4. `make check` passes > > > > If you please point me to a doc that explains how automatic unit tests > can be > > added to a QEMU target, I will happily add them. > > Can you boot an AVR kernel? > > How about the environment that newlib builds with libgloss? With that > you'd be > able to run the gcc testsuite, which would be extremely helpful. > > > r~ >
Re: [Qemu-devel] [PATCH RFC v19 00/13] QEMU AVR 8 bit cores
On 07/04/2017 08:34 PM, Michael Rolnik wrote: Hi Richard. Thank you for finding a bug. As for the testing 1. I have a small program that calculates fibonacci numbers. I use it to test mainly stack operations for different CPU flavors (1, 2 or 3 bytes PC). 2. I manually verified that I can debug with gdb, that includes a. stepping b. running c. stopping d. breakpoints e. backtrace shows correct stack 3. I manually verified that I can save and load vm states 4. `make check` passes If you please point me to a doc that explains how automatic unit tests can be added to a QEMU target, I will happily add them. Can you boot an AVR kernel? How about the environment that newlib builds with libgloss? With that you'd be able to run the gcc testsuite, which would be extremely helpful. r~
Re: [Qemu-devel] [PATCH RFC v19 00/13] QEMU AVR 8 bit cores
Hi Richard.
Thank you for finding a bug.
As for the testing
1. I have a small program that calculates fibonacci numbers. I use it to
test mainly stack operations for different CPU flavors (1, 2 or 3 bytes PC).
2. I manually verified that I can debug with gdb, that includes
a. stepping
b. running
c. stopping
d. breakpoints
e. backtrace shows correct stack
3. I manually verified that I can save and load vm states
4. `make check` passes
If you please point me to a doc that explains how automatic unit tests can
be added to a QEMU target, I will happily add them.
Regards,
Michael
On Wed, Jul 5, 2017 at 1:38 AM, Richard Henderson wrote:
> On 06/21/2017 09:15 PM, Michael Rolnik wrote:
>
>> Hi all,
>>
>> are there any action items for me?
>>
>
> What kind of testing are you doing for this?
>
> I just briefly browsed through the code again and happened to see that ROR
> has a critical typo. Considering that ROR must be used for multi-byte
> shifts, I'm wondering how you wouldn't have found this via even cursory
> testing.
>
> +int avr_translate_ROR(CPUAVRState *env, DisasContext *ctx, uint32_t
>> opcode)
>> +{
>> +TCGv Rd = cpu_r[ROR_Rd(opcode)];
>> +TCGv t0 = tcg_temp_new_i32();
>> +
>> +tcg_gen_shli_tl(t0, cpu_Cf, 7);
>> +tcg_gen_andi_tl(cpu_Cf, Rd, 0);
>>
>
>
> r~
>
--
Best Regards,
Michael Rolnik
Re: [Qemu-devel] [PATCH RFC v19 00/13] QEMU AVR 8 bit cores
On 06/21/2017 09:15 PM, Michael Rolnik wrote:
Hi all,
are there any action items for me?
What kind of testing are you doing for this?
I just briefly browsed through the code again and happened to see that ROR has
a critical typo. Considering that ROR must be used for multi-byte shifts, I'm
wondering how you wouldn't have found this via even cursory testing.
+int avr_translate_ROR(CPUAVRState *env, DisasContext *ctx, uint32_t opcode)
+{
+TCGv Rd = cpu_r[ROR_Rd(opcode)];
+TCGv t0 = tcg_temp_new_i32();
+
+tcg_gen_shli_tl(t0, cpu_Cf, 7);
+tcg_gen_andi_tl(cpu_Cf, Rd, 0);
r~
Re: [Qemu-devel] [PATCH RFC v19 00/13] QEMU AVR 8 bit cores
Anyone can explain what is the blocking problem for this target to be pulled upstream? I apologize for bothering but I don't have the workflow clear in my mind. thanks, Anichang > Original Message > Subject: Re: [PATCH RFC v19 00/13] QEMU AVR 8 bit cores > Local Time: June 22, 2017 9:15 AM > UTC Time: June 22, 2017 7:15 AM > From: mrol...@gmail.com > To: QEMU Developers > Anichang , Michael Rolnik > > Hi all, > are there any action items for me? > Regards, > Michael > > On Thu, Jun 8, 2017 at 9:49 PM, Michael Rolnik wrote: > >> This series of patches adds 8bit AVR cores to QEMU. >> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully >> tested yet. >> However I was able to execute simple code with functions. e.g fibonacci >> calculation. >> This series of patches include a non real, sample board. >> No fuses support yet. PC is set to 0 at reset. >> the patches include the following >> 1. just a basic 8bit AVR CPU, without instruction decoding or translation >> 2. CPU features which allow define the following 8bit AVR cores >> avr1 >> avr2 avr25 >> avr3 avr31 avr35 >> avr4 >> avr5 avr51 >> avr6 >> xmega2 xmega4 xmega5 xmega6 xmega7 >> 3. a definition of sample machine with SRAM, FLASH and CPU which allows to >> execute simple code >> 4. encoding for all AVR instructions >> 5. interrupt handling >> 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions >> 7. a decoder which given an opcode decides what istruction it is >> 8. translation of AVR instruction into TCG >> 9. all features together >> changes since v3 >> 1. rampD/X/Y/Z registers are encoded as 0x00ff (instead of 0x00ff) >> for faster address manipulaton >> 2. ffs changed to ctz32 >> 3. duplicate code removed at avr_cpu_do_interrupt >> 4. using andc instead of not + and >> 5. fixing V flag calculation in varios instructions >> 6. freeing local variables in PUSH >> 7. tcg_const_local_i32 -> tcg_const_i32 >> 8. using sextract32 instead of my implementation >> 9. fixing BLD instruction >> 10.xor(r) instead of 0xff - r at COM >> 11.fixing MULS/MULSU not to modify inputs' content >> 12.using SUB for NEG >> 13.fixing tcg_gen_qemu_ld/st call in XCH >> changes since v4 >> 1. target is now defined as big endian in order to optimize push_ret/pop_ret >> 2. all style warnings are fixed >> 3. adding cpu_set/get_sreg functions >> 4. simplifying gen_goto_tb as there is no real paging >> 5. env->pc -> env->pc_w >> 6. making flag dump more compact >> 7. more spacing >> 8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX >> 9. removing avr_set_feature >> 10. SPL/SPH set bug fix >> 11. switching stb_phys to cpu_stb_data >> 12. cleaning up avr_decode >> 13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm) >> 14. saving CPU features (savevm) >> changes since v5 >> 1. BLD bug fix >> 2. decoder generator is added >> chages since v6 >> 1. using cpu_get_sreg/cpu_set_sreg in >> avr_cpu_gdb_read_register/avr_cpu_gdb_write_register >> 2. configure the target as little endian because otherwise GDB does not work >> 3. fixing and testing gen_push_ret/gen_pop_ret >> changes since v7 >> 1. folding back v6 >> 2. logging at helper_outb and helper_inb are done for non supported yet >> registers only >> 3. MAINTAINERS updated >> changes since v8 >> 1. removing hw/avr from hw/Makefile.obj as it should not be built for all >> 2. making linux compilable >> 3. testing on >> a. Mac, Apple LLVM version 7.0.0 >> b. Ubuntu 12.04, gcc 4.9.2 >> c. Fedora 23, gcc 5.3.1 >> 4. folding back some patches >> 5. translation bug fixes for ORI, CPI, XOR instructions >> 6. propper handling of cpu register writes though memory >> changes since v9 >> 1. removing forward declarations of static functions >> 2. disabling debug prints >> 3. switching to case range instead of if else if ... >> 4. LD/ST IN/OUT accessing CPU maintainder registers are not routed to any >> device >> 5. commenst about sample board and sample IO device added >> 6. sample board description is more descriptive now >> 7. memory_region_allocate_system_memory is used to create RAM >> 8. now there are helper_fullrd & helper_fullwr when LD/ST try to access >> registers >> changes since v10 >> 1. movig back fullwr & fullrd into the commit where outb and inb were >> introduced >> 2. changing tlb_fill function signature >> 3. adding empty line between functions >> 4. adding newline on the last line of the file >> 5. using tb->flags to generae full access ST/LD instructions >> 6. fixing SBRC bug >> 7. folding back 10th commit >> 8. whenever a new file is introduced it's added to Makefile.objs >> changes since v11 >> 1. updating to v2.7.0-rc >> 2. removing assignment to env->fullacc from gen_intermediate_code >> changes since v12 >> 1. fixing spacing >> 2. fixing get/put_segment functions >> 3. removing target-avr/machine.h file >> 4. VMSTATE_SINGLE_TEST -> VMSTATE_SINGLE >> 5. comment spelling >> 6. removing hw/avr/sample_io.c >> 7. char const* -> const char* >> 8. proper ram allo
Re: [Qemu-devel] [PATCH RFC v19 00/13] QEMU AVR 8 bit cores
Hi all, are there any action items for me? Regards, Michael On Thu, Jun 8, 2017 at 9:49 PM, Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. > However I was able to execute simple code with functions. e.g fibonacci > calculation. > This series of patches include a non real, sample board. > No fuses support yet. PC is set to 0 at reset. > > the patches include the following > 1. just a basic 8bit AVR CPU, without instruction decoding or translation > 2. CPU features which allow define the following 8bit AVR cores > avr1 > avr2 avr25 > avr3 avr31 avr35 > avr4 > avr5 avr51 > avr6 > xmega2 xmega4 xmega5 xmega6 xmega7 > 3. a definition of sample machine with SRAM, FLASH and CPU which allows to > execute simple code > 4. encoding for all AVR instructions > 5. interrupt handling > 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions > 7. a decoder which given an opcode decides what istruction it is > 8. translation of AVR instruction into TCG > 9. all features together > > changes since v3 > 1. rampD/X/Y/Z registers are encoded as 0x00ff (instead of 0x00ff) > for faster address manipulaton > 2. ffs changed to ctz32 > 3. duplicate code removed at avr_cpu_do_interrupt > 4. using andc instead of not + and > 5. fixing V flag calculation in varios instructions > 6. freeing local variables in PUSH > 7. tcg_const_local_i32 -> tcg_const_i32 > 8. using sextract32 instead of my implementation > 9. fixing BLD instruction > 10.xor(r) instead of 0xff - r at COM > 11.fixing MULS/MULSU not to modify inputs' content > 12.using SUB for NEG > 13.fixing tcg_gen_qemu_ld/st call in XCH > > changes since v4 > 1. target is now defined as big endian in order to optimize > push_ret/pop_ret > 2. all style warnings are fixed > 3. adding cpu_set/get_sreg functions > 4. simplifying gen_goto_tb as there is no real paging > 5. env->pc -> env->pc_w > 6. making flag dump more compact > 7. more spacing > 8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX > 9. removing avr_set_feature > 10. SPL/SPH set bug fix > 11. switching stb_phys to cpu_stb_data > 12. cleaning up avr_decode > 13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm) > 14. saving CPU features (savevm) > > changes since v5 > 1. BLD bug fix > 2. decoder generator is added > > chages since v6 > 1. using cpu_get_sreg/cpu_set_sreg in avr_cpu_gdb_read_register/avr_ > cpu_gdb_write_register > 2. configure the target as little endian because otherwise GDB does not > work > 3. fixing and testing gen_push_ret/gen_pop_ret > > changes since v7 > 1. folding back v6 > 2. logging at helper_outb and helper_inb are done for non supported yet > registers only > 3. MAINTAINERS updated > > changes since v8 > 1. removing hw/avr from hw/Makefile.obj as it should not be built for all > 2. making linux compilable > 3. testing on > a. Mac, Apple LLVM version 7.0.0 > b. Ubuntu 12.04, gcc 4.9.2 > c. Fedora 23, gcc 5.3.1 > 4. folding back some patches > 5. translation bug fixes for ORI, CPI, XOR instructions > 6. propper handling of cpu register writes though memory > > changes since v9 > 1. removing forward declarations of static functions > 2. disabling debug prints > 3. switching to case range instead of if else if ... > 4. LD/ST IN/OUT accessing CPU maintainder registers are not routed to any > device > 5. commenst about sample board and sample IO device added > 6. sample board description is more descriptive now > 7. memory_region_allocate_system_memory is used to create RAM > 8. now there are helper_fullrd & helper_fullwr when LD/ST try to access > registers > > changes since v10 > 1. movig back fullwr & fullrd into the commit where outb and inb were > introduced > 2. changing tlb_fill function signature > 3. adding empty line between functions > 4. adding newline on the last line of the file > 5. using tb->flags to generae full access ST/LD instructions > 6. fixing SBRC bug > 7. folding back 10th commit > 8. whenever a new file is introduced it's added to Makefile.objs > > changes since v11 > 1. updating to v2.7.0-rc > 2. removing assignment to env->fullacc from gen_intermediate_code > > changes since v12 > 1. fixing spacing > 2. fixing get/put_segment functions > 3. removing target-avr/machine.h file > 4. VMSTATE_SINGLE_TEST -> VMSTATE_SINGLE > 5. comment spelling > 6. removing hw/avr/sample_io.c > 7. char const* -> const char* > 8. proper ram allocation > 9. fixing breakpoint functionality. > 10.env1 -> env > 11.fixing avr_cpu_gdb_write_register & avr_cpu_gdb_read_register functions > 12.any cpu is removed > 12.feature bits are not saved into vm state > > changes since v13 > 1. rebasing to v2.7.0-rc1 > > changes since v14 > 1. I made self review with git gui tool. (I did not know such a thing > exists) > 2. removing all double/tripple spaces > 3. removing comment reference to SampleIO > 4. folding back some changes, so
[Qemu-devel] [PATCH RFC v19 00/13] QEMU AVR 8 bit cores
This series of patches adds 8bit AVR cores to QEMU. All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested yet. However I was able to execute simple code with functions. e.g fibonacci calculation. This series of patches include a non real, sample board. No fuses support yet. PC is set to 0 at reset. the patches include the following 1. just a basic 8bit AVR CPU, without instruction decoding or translation 2. CPU features which allow define the following 8bit AVR cores avr1 avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 xmega2 xmega4 xmega5 xmega6 xmega7 3. a definition of sample machine with SRAM, FLASH and CPU which allows to execute simple code 4. encoding for all AVR instructions 5. interrupt handling 6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions 7. a decoder which given an opcode decides what istruction it is 8. translation of AVR instruction into TCG 9. all features together changes since v3 1. rampD/X/Y/Z registers are encoded as 0x00ff (instead of 0x00ff) for faster address manipulaton 2. ffs changed to ctz32 3. duplicate code removed at avr_cpu_do_interrupt 4. using andc instead of not + and 5. fixing V flag calculation in varios instructions 6. freeing local variables in PUSH 7. tcg_const_local_i32 -> tcg_const_i32 8. using sextract32 instead of my implementation 9. fixing BLD instruction 10.xor(r) instead of 0xff - r at COM 11.fixing MULS/MULSU not to modify inputs' content 12.using SUB for NEG 13.fixing tcg_gen_qemu_ld/st call in XCH changes since v4 1. target is now defined as big endian in order to optimize push_ret/pop_ret 2. all style warnings are fixed 3. adding cpu_set/get_sreg functions 4. simplifying gen_goto_tb as there is no real paging 5. env->pc -> env->pc_w 6. making flag dump more compact 7. more spacing 8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX 9. removing avr_set_feature 10. SPL/SPH set bug fix 11. switching stb_phys to cpu_stb_data 12. cleaning up avr_decode 13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm) 14. saving CPU features (savevm) changes since v5 1. BLD bug fix 2. decoder generator is added chages since v6 1. using cpu_get_sreg/cpu_set_sreg in avr_cpu_gdb_read_register/avr_cpu_gdb_write_register 2. configure the target as little endian because otherwise GDB does not work 3. fixing and testing gen_push_ret/gen_pop_ret changes since v7 1. folding back v6 2. logging at helper_outb and helper_inb are done for non supported yet registers only 3. MAINTAINERS updated changes since v8 1. removing hw/avr from hw/Makefile.obj as it should not be built for all 2. making linux compilable 3. testing on a. Mac, Apple LLVM version 7.0.0 b. Ubuntu 12.04, gcc 4.9.2 c. Fedora 23, gcc 5.3.1 4. folding back some patches 5. translation bug fixes for ORI, CPI, XOR instructions 6. propper handling of cpu register writes though memory changes since v9 1. removing forward declarations of static functions 2. disabling debug prints 3. switching to case range instead of if else if ... 4. LD/ST IN/OUT accessing CPU maintainder registers are not routed to any device 5. commenst about sample board and sample IO device added 6. sample board description is more descriptive now 7. memory_region_allocate_system_memory is used to create RAM 8. now there are helper_fullrd & helper_fullwr when LD/ST try to access registers changes since v10 1. movig back fullwr & fullrd into the commit where outb and inb were introduced 2. changing tlb_fill function signature 3. adding empty line between functions 4. adding newline on the last line of the file 5. using tb->flags to generae full access ST/LD instructions 6. fixing SBRC bug 7. folding back 10th commit 8. whenever a new file is introduced it's added to Makefile.objs changes since v11 1. updating to v2.7.0-rc 2. removing assignment to env->fullacc from gen_intermediate_code changes since v12 1. fixing spacing 2. fixing get/put_segment functions 3. removing target-avr/machine.h file 4. VMSTATE_SINGLE_TEST -> VMSTATE_SINGLE 5. comment spelling 6. removing hw/avr/sample_io.c 7. char const* -> const char* 8. proper ram allocation 9. fixing breakpoint functionality. 10.env1 -> env 11.fixing avr_cpu_gdb_write_register & avr_cpu_gdb_read_register functions 12.any cpu is removed 12.feature bits are not saved into vm state changes since v13 1. rebasing to v2.7.0-rc1 changes since v14 1. I made self review with git gui tool. (I did not know such a thing exists) 2. removing all double/tripple spaces 3. removing comment reference to SampleIO 4. folding back some changes, so there is not deleted lines in my code 5. moving avr configuration, within configure file, before chris changes since v15 1. removing IO registers cache from CPU 2. implementing CBI/SBI as read(helper_inb), modify, write(helper_outb) 3. implementing CBIC/SBIC as read(helper_inb), check, branch 4. adding missing tcg_temp_free_i32 for tcg_const_i32 changes since v16 1. remov
