[Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Signed-off-by: Michael Clark --- Makefile.objs | 1 + arch_init.c| 2 ++ configure | 11 +++ cpus.c | 6 ++ default-configs/riscv32-linux-user.mak | 1 + default-configs/riscv32-softmmu.mak| 4 default-configs/riscv64-linux-user.mak | 1 + default-configs/riscv64-softmmu.mak| 4 hw/riscv/Makefile.objs | 12 include/sysemu/arch_init.h | 1 + qapi-schema.json | 14 +- scripts/qemu-binfmt-conf.sh| 13 - target/riscv/Makefile.objs | 2 ++ target/riscv/trace-events | 1 + 14 files changed, 71 insertions(+), 2 deletions(-) create mode 100644 default-configs/riscv32-linux-user.mak create mode 100644 default-configs/riscv32-softmmu.mak create mode 100644 default-configs/riscv64-linux-user.mak create mode 100644 default-configs/riscv64-softmmu.mak create mode 100644 hw/riscv/Makefile.objs create mode 100644 target/riscv/Makefile.objs create mode 100644 target/riscv/trace-events diff --git a/Makefile.objs b/Makefile.objs index 285c6f3..ae8658e 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -164,6 +164,7 @@ trace-events-subdirs += target/mips trace-events-subdirs += target/sparc trace-events-subdirs += target/s390x trace-events-subdirs += target/ppc +trace-events-subdirs += target/riscv trace-events-subdirs += qom trace-events-subdirs += linux-user trace-events-subdirs += qapi diff --git a/arch_init.c b/arch_init.c index a0b8ed6..dcf356b 100644 --- a/arch_init.c +++ b/arch_init.c @@ -69,6 +69,8 @@ int graphic_depth = 32; #define QEMU_ARCH QEMU_ARCH_OPENRISC #elif defined(TARGET_PPC) #define QEMU_ARCH QEMU_ARCH_PPC +#elif defined(TARGET_RISCV) +#define QEMU_ARCH QEMU_ARCH_RISCV #elif defined(TARGET_S390X) #define QEMU_ARCH QEMU_ARCH_S390X #elif defined(TARGET_SH4) diff --git a/configure b/configure index 100309c..832e025 100755 --- a/configure +++ b/configure @@ -6530,6 +6530,14 @@ case "$target_name" in echo "TARGET_ABI32=y" >> $config_target_mak gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml" ;; + riscv32) +TARGET_BASE_ARCH=riscv +TARGET_ABI_DIR=riscv + ;; + riscv64) +TARGET_BASE_ARCH=riscv +TARGET_ABI_DIR=riscv + ;; sh4|sh4eb) TARGET_ARCH=sh4 bflt="yes" @@ -6692,6 +6700,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do ppc*) disas_config "PPC" ;; + riscv) +disas_config "RISCV" + ;; s390*) disas_config "S390" ;; diff --git a/cpus.c b/cpus.c index 83700c1..702da8b 100644 --- a/cpus.c +++ b/cpus.c @@ -1909,6 +1909,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_SPARC) SPARCCPU *sparc_cpu = SPARC_CPU(cpu); CPUSPARCState *env = &sparc_cpu->env; +#elif defined(TARGET_RISCV) +RISCVCPU *riscv_cpu = RISCV_CPU(cpu); +CPURISCVState *env = &riscv_cpu->env; #elif defined(TARGET_MIPS) MIPSCPU *mips_cpu = MIPS_CPU(cpu); CPUMIPSState *env = &mips_cpu->env; @@ -1942,6 +1945,9 @@ CpuInfoList *qmp_query_cpus(Error **errp) #elif defined(TARGET_TRICORE) info->value->arch = CPU_INFO_ARCH_TRICORE; info->value->u.tricore.PC = env->PC; +#elif defined(TARGET_RISCV) +info->value->arch = CPU_INFO_ARCH_RISCV; +info->value->u.riscv.pc = env->pc; #else info->value->arch = CPU_INFO_ARCH_OTHER; #endif diff --git a/default-configs/riscv32-linux-user.mak b/default-configs/riscv32-linux-user.mak new file mode 100644 index 000..865b362 --- /dev/null +++ b/default-configs/riscv32-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for riscv-linux-user diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak new file mode 100644 index 000..f9e7421 --- /dev/null +++ b/default-configs/riscv32-softmmu.mak @@ -0,0 +1,4 @@ +# Default configuration for riscv-softmmu + +CONFIG_SERIAL=y +CONFIG_VIRTIO=y diff --git a/default-configs/riscv64-linux-user.mak b/default-configs/riscv64-linux-user.mak new file mode 100644 index 000..865b362 --- /dev/null +++ b/default-configs/riscv64-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for riscv-linux-user diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak new file mode 100644 index 000..f9e7421 --- /dev/null +++ b/default-configs/riscv64-softmmu.mak @@
Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
On Fri, Jan 5, 2018 at 7:22 PM, Michael Clark wrote: > > On Fri, 5 Jan 2018 at 5:55 AM, Antony Pavlov > wrote: > >> On Wed, 3 Jan 2018 13:44:25 +1300 >> Michael Clark wrote: >> >> > This adds RISC-V into the build system enabling the following targets: >> > >> > - riscv32-softmmu >> > - riscv64-softmmu >> > - riscv32-linux-user >> > - riscv64-linux-user >> > >> >> ... >> >> > diff --git a/default-configs/riscv32-softmmu.mak >> b/default-configs/riscv32-softmmu.mak >> > new file mode 100644 >> > index 000..f9e7421 >> > --- /dev/null >> > +++ b/default-configs/riscv32-softmmu.mak >> > @@ -0,0 +1,4 @@ >> > +# Default configuration for riscv-softmmu >> > + >> > +CONFIG_SERIAL=y >> > +CONFIG_VIRTIO=y >> > diff --git a/default-configs/riscv64-linux-user.mak >> b/default-configs/riscv64-linux-user.mak >> > new file mode 100644 >> > index 000..865b362 >> > --- /dev/null >> > +++ b/default-configs/riscv64-linux-user.mak >> > @@ -0,0 +1 @@ >> > +# Default configuration for riscv-linux-user >> > diff --git a/default-configs/riscv64-softmmu.mak >> b/default-configs/riscv64-softmmu.mak >> > new file mode 100644 >> > index 000..f9e7421 >> > --- /dev/null >> > +++ b/default-configs/riscv64-softmmu.mak >> > @@ -0,0 +1,4 @@ >> > +# Default configuration for riscv-softmmu >> > + >> > +CONFIG_SERIAL=y >> > +CONFIG_VIRTIO=y >> > diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs >> > new file mode 100644 >> > index 000..a0c31ae >> > --- /dev/null >> > +++ b/hw/riscv/Makefile.objs >> > @@ -0,0 +1,12 @@ >> > +obj-y += riscv_elf.o >> > +obj-y += riscv_htif.o >> > +obj-y += riscv_hart.o >> > +obj-y += sifive_e300.o >> > +obj-y += sifive_clint.o >> > +obj-y += sifive_prci.o >> > +obj-y += sifive_plic.o >> > +obj-y += sifive_u500.o >> > +obj-y += sifive_uart.o >> > +obj-y += spike_v1_09.o >> > +obj-y += spike_v1_10.o >> > +obj-y += virt.o >> >> According to https://www.sifive.com/products/freedom/ >> Freedom E300 Platform uses RV32IMAC Architecture >> and Freedom U500 Platform uses RV64GC Architecture. >> >> Which means that qemu-system-riscv32 has to have E300 support but not >> U500 support. >> qemu-system-riscv64 has to have U500 support but not E300 support. >> >> However please see this log: >> >> riscv-qemu$ ./riscv32-softmmu/qemu-system-riscv32 -M ? >> Supported machines are: >> none empty machine >> sifive_e300 RISC-V Board compatible with SiFive E300 SDK >> sifive_u500 RISC-V Board compatible with SiFive U500 SDK << >> U500 in 32-bit mode >> spike_v1.10 RISC-V Spike Board (Privileged ISA v1.10) >> spike_v1.9 RISC-V Spike Board (Privileged ISA v1.9.1) (default) >> virt RISC-V VirtIO Board (Privileged spec v1.10) >> riscv-qemu$ ./riscv64-softmmu/qemu-system-riscv64 -M ? >> Supported machines are: >> none empty machine >> sifive_e300 RISC-V Board compatible with SiFive E300 SDK << >> E300 in 64-bit mode >> sifive_u500 RISC-V Board compatible with SiFive U500 SDK >> spike_v1.10 RISC-V Spike Board (Privileged ISA v1.10) >> spike_v1.9 RISC-V Spike Board (Privileged ISA v1.9.1) (default) >> virt RISC-V VirtIO Board (Privileged spec v1.10) >> >> I propose at least this fixup: >> >> diff --git a/default-configs/riscv32-softmmu.mak >> b/default-configs/riscv32-softmmu.mak >> index f9e742120c..6a807f5f96 100644 >> --- a/default-configs/riscv32-softmmu.mak >> +++ b/default-configs/riscv32-softmmu.mak >> @@ -1,4 +1,5 @@ >> -# Default configuration for riscv-softmmu >> +# Default configuration for riscv32-softmmu >> >> CONFIG_SERIAL=y >> CONFIG_VIRTIO=y >> +CONFIG_SIFIVE_E300=y >> diff --git a/default-configs/riscv64-softmmu.mak >> b/default-configs/riscv64-softmmu.mak >> index f9e742120c..1a0349fe27 100644 >> --- a/default-configs/riscv64-softmmu.mak >> +++ b/default-configs/riscv64-softmmu.mak >> @@ -1,4 +1,5 @@ >> -# Default configuration for riscv-softmmu >> +# Default configuration for riscv64-softmmu >> >> CONFIG_SERIAL=y >> CONFIG_VIRTIO=y >> +CONFIG_SIFIVE_U500=y >> diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs >> index a0c31ae25e..bac5faa603 100644 >> --- a/hw/riscv/Makefile.objs >> +++ b/hw/riscv/Makefile.objs >> @@ -1,11 +1,11 @@ >> obj-y += riscv_elf.o >> obj-y += riscv_htif.o >> obj-y += riscv_hart.o >> -obj-y += sifive_e300.o >> +obj-$(CONFIG_SIFIVE_E300) += sifive_e300.o >> obj-y += sifive_clint.o >> obj-y += sifive_prci.o >> obj-y += sifive_plic.o >> -obj-y += sifive_u500.o >> +obj-$(CONFIG_SIFIVE_U500) += sifive_u500.o >> obj-y += sifive_uart.o >> obj-y += spike_v1_09.o >> obj-y += spike_v1_10.o > > > I’ll check whether there are 64-bit E series chips. Actually the key > distinction is no MMU and we don’t yet disable the MMU in the machine. > > I’ll ask SiFive whether they want to restrict the “bitness”. There is > actually no reason why the machine can’t be invoked as 64-bit. > > As far as I know the RTL is parametiaz
Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
Eric Blake writes:
> On 01/05/2018 12:47 AM, Michael Clark wrote:
>
>>>
+##
+{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
>>>
>>> Should this be 'uint64' or other specific type, rather than the generic
>>> 'int' (which happens to be 64 bits, but signed)? Other architectures
>>> use 'int' because of history, but we could use this chance to improve
>>> things if desired.
>>>
>>
>> I'll have to defer to your better judgement as to whether we need to change
>> this. I like consistency. Is it a change that needs to be made to multiple
>> arches? It sounds relatively low risk. You decide.
>>
>> QAPI Schema
>> M: Eric Blake
>> M: Markus Armbruster
>
> I'm fine if this patch uses 'int' for consistency, and will wait for
Me too.
> Markus to chime in on whether changing CpuInfo to use specific integer
> types in general is worth a separate series later on.
I guess it is.
Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
On 01/02/2018 06:44 PM, Michael Clark wrote:
> This adds RISC-V into the build system enabling the following targets:
>
> - riscv32-softmmu
> - riscv64-softmmu
> - riscv32-linux-user
> - riscv64-linux-user
>
> This adds defaults configs for RISC-V, enables the build for the RISC-V
> CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
> script is updated to add the RISC-V ELF magic.
>
> Expected checkpatch errors for consistency reasons:
>
> ERROR: line over 90 characters
> FILE: scripts/qemu-binfmt-conf.sh
> Signed-off-by: Michael Clark
> ---
> +++ b/qapi-schema.json
> @@ -413,7 +413,7 @@
> # Since: 2.6
> ##
> { 'enum': 'CpuInfoArch',
> - 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
> + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ] }
Missing documentation that riscv was added in 2.12 (see QKeyCode in
qapi/ui.json for an enum that serves as an example of documenting
changes over time).
>
> ##
> +# @CpuInfoRISCV:
> +#
> +# Additional information about a virtual RISCV CPU
> +#
> +# @pc: the instruction pointer
> +#
> +# Since 2.8
2.12, actually.
> +##
> +{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
Should this be 'uint64' or other specific type, rather than the generic
'int' (which happens to be 64 bits, but signed)? Other architectures
use 'int' because of history, but we could use this chance to improve
things if desired.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
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Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
On Wed, 3 Jan 2018 13:44:25 +1300 Michael Clark wrote: > This adds RISC-V into the build system enabling the following targets: > > - riscv32-softmmu > - riscv64-softmmu > - riscv32-linux-user > - riscv64-linux-user > ... > diff --git a/default-configs/riscv32-softmmu.mak > b/default-configs/riscv32-softmmu.mak > new file mode 100644 > index 000..f9e7421 > --- /dev/null > +++ b/default-configs/riscv32-softmmu.mak > @@ -0,0 +1,4 @@ > +# Default configuration for riscv-softmmu > + > +CONFIG_SERIAL=y > +CONFIG_VIRTIO=y > diff --git a/default-configs/riscv64-linux-user.mak > b/default-configs/riscv64-linux-user.mak > new file mode 100644 > index 000..865b362 > --- /dev/null > +++ b/default-configs/riscv64-linux-user.mak > @@ -0,0 +1 @@ > +# Default configuration for riscv-linux-user > diff --git a/default-configs/riscv64-softmmu.mak > b/default-configs/riscv64-softmmu.mak > new file mode 100644 > index 000..f9e7421 > --- /dev/null > +++ b/default-configs/riscv64-softmmu.mak > @@ -0,0 +1,4 @@ > +# Default configuration for riscv-softmmu > + > +CONFIG_SERIAL=y > +CONFIG_VIRTIO=y > diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs > new file mode 100644 > index 000..a0c31ae > --- /dev/null > +++ b/hw/riscv/Makefile.objs > @@ -0,0 +1,12 @@ > +obj-y += riscv_elf.o > +obj-y += riscv_htif.o > +obj-y += riscv_hart.o > +obj-y += sifive_e300.o > +obj-y += sifive_clint.o > +obj-y += sifive_prci.o > +obj-y += sifive_plic.o > +obj-y += sifive_u500.o > +obj-y += sifive_uart.o > +obj-y += spike_v1_09.o > +obj-y += spike_v1_10.o > +obj-y += virt.o According to https://www.sifive.com/products/freedom/ Freedom E300 Platform uses RV32IMAC Architecture and Freedom U500 Platform uses RV64GC Architecture. Which means that qemu-system-riscv32 has to have E300 support but not U500 support. qemu-system-riscv64 has to have U500 support but not E300 support. However please see this log: riscv-qemu$ ./riscv32-softmmu/qemu-system-riscv32 -M ? Supported machines are: none empty machine sifive_e300 RISC-V Board compatible with SiFive E300 SDK sifive_u500 RISC-V Board compatible with SiFive U500 SDK << U500 in 32-bit mode spike_v1.10 RISC-V Spike Board (Privileged ISA v1.10) spike_v1.9 RISC-V Spike Board (Privileged ISA v1.9.1) (default) virt RISC-V VirtIO Board (Privileged spec v1.10) riscv-qemu$ ./riscv64-softmmu/qemu-system-riscv64 -M ? Supported machines are: none empty machine sifive_e300 RISC-V Board compatible with SiFive E300 SDK << E300 in 64-bit mode sifive_u500 RISC-V Board compatible with SiFive U500 SDK spike_v1.10 RISC-V Spike Board (Privileged ISA v1.10) spike_v1.9 RISC-V Spike Board (Privileged ISA v1.9.1) (default) virt RISC-V VirtIO Board (Privileged spec v1.10) I propose at least this fixup: diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index f9e742120c..6a807f5f96 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -1,4 +1,5 @@ -# Default configuration for riscv-softmmu +# Default configuration for riscv32-softmmu CONFIG_SERIAL=y CONFIG_VIRTIO=y +CONFIG_SIFIVE_E300=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index f9e742120c..1a0349fe27 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -1,4 +1,5 @@ -# Default configuration for riscv-softmmu +# Default configuration for riscv64-softmmu CONFIG_SERIAL=y CONFIG_VIRTIO=y +CONFIG_SIFIVE_U500=y diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index a0c31ae25e..bac5faa603 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -1,11 +1,11 @@ obj-y += riscv_elf.o obj-y += riscv_htif.o obj-y += riscv_hart.o -obj-y += sifive_e300.o +obj-$(CONFIG_SIFIVE_E300) += sifive_e300.o obj-y += sifive_clint.o obj-y += sifive_prci.o obj-y += sifive_plic.o -obj-y += sifive_u500.o +obj-$(CONFIG_SIFIVE_U500) += sifive_u500.o obj-y += sifive_uart.o obj-y += spike_v1_09.o obj-y += spike_v1_10.o -- Best regards, Antony Pavlov
Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
On Fri, 5 Jan 2018 at 5:55 AM, Antony Pavlov wrote: > On Wed, 3 Jan 2018 13:44:25 +1300 > Michael Clark wrote: > > > This adds RISC-V into the build system enabling the following targets: > > > > - riscv32-softmmu > > - riscv64-softmmu > > - riscv32-linux-user > > - riscv64-linux-user > > > > ... > > > diff --git a/default-configs/riscv32-softmmu.mak > b/default-configs/riscv32-softmmu.mak > > new file mode 100644 > > index 000..f9e7421 > > --- /dev/null > > +++ b/default-configs/riscv32-softmmu.mak > > @@ -0,0 +1,4 @@ > > +# Default configuration for riscv-softmmu > > + > > +CONFIG_SERIAL=y > > +CONFIG_VIRTIO=y > > diff --git a/default-configs/riscv64-linux-user.mak > b/default-configs/riscv64-linux-user.mak > > new file mode 100644 > > index 000..865b362 > > --- /dev/null > > +++ b/default-configs/riscv64-linux-user.mak > > @@ -0,0 +1 @@ > > +# Default configuration for riscv-linux-user > > diff --git a/default-configs/riscv64-softmmu.mak > b/default-configs/riscv64-softmmu.mak > > new file mode 100644 > > index 000..f9e7421 > > --- /dev/null > > +++ b/default-configs/riscv64-softmmu.mak > > @@ -0,0 +1,4 @@ > > +# Default configuration for riscv-softmmu > > + > > +CONFIG_SERIAL=y > > +CONFIG_VIRTIO=y > > diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs > > new file mode 100644 > > index 000..a0c31ae > > --- /dev/null > > +++ b/hw/riscv/Makefile.objs > > @@ -0,0 +1,12 @@ > > +obj-y += riscv_elf.o > > +obj-y += riscv_htif.o > > +obj-y += riscv_hart.o > > +obj-y += sifive_e300.o > > +obj-y += sifive_clint.o > > +obj-y += sifive_prci.o > > +obj-y += sifive_plic.o > > +obj-y += sifive_u500.o > > +obj-y += sifive_uart.o > > +obj-y += spike_v1_09.o > > +obj-y += spike_v1_10.o > > +obj-y += virt.o > > According to https://www.sifive.com/products/freedom/ > Freedom E300 Platform uses RV32IMAC Architecture > and Freedom U500 Platform uses RV64GC Architecture. > > Which means that qemu-system-riscv32 has to have E300 support but not U500 > support. > qemu-system-riscv64 has to have U500 support but not E300 support. > > However please see this log: > > riscv-qemu$ ./riscv32-softmmu/qemu-system-riscv32 -M ? > Supported machines are: > none empty machine > sifive_e300 RISC-V Board compatible with SiFive E300 SDK > sifive_u500 RISC-V Board compatible with SiFive U500 SDK << > U500 in 32-bit mode > spike_v1.10 RISC-V Spike Board (Privileged ISA v1.10) > spike_v1.9 RISC-V Spike Board (Privileged ISA v1.9.1) (default) > virt RISC-V VirtIO Board (Privileged spec v1.10) > riscv-qemu$ ./riscv64-softmmu/qemu-system-riscv64 -M ? > Supported machines are: > none empty machine > sifive_e300 RISC-V Board compatible with SiFive E300 SDK << > E300 in 64-bit mode > sifive_u500 RISC-V Board compatible with SiFive U500 SDK > spike_v1.10 RISC-V Spike Board (Privileged ISA v1.10) > spike_v1.9 RISC-V Spike Board (Privileged ISA v1.9.1) (default) > virt RISC-V VirtIO Board (Privileged spec v1.10) > > I propose at least this fixup: > > diff --git a/default-configs/riscv32-softmmu.mak > b/default-configs/riscv32-softmmu.mak > index f9e742120c..6a807f5f96 100644 > --- a/default-configs/riscv32-softmmu.mak > +++ b/default-configs/riscv32-softmmu.mak > @@ -1,4 +1,5 @@ > -# Default configuration for riscv-softmmu > +# Default configuration for riscv32-softmmu > > CONFIG_SERIAL=y > CONFIG_VIRTIO=y > +CONFIG_SIFIVE_E300=y > diff --git a/default-configs/riscv64-softmmu.mak > b/default-configs/riscv64-softmmu.mak > index f9e742120c..1a0349fe27 100644 > --- a/default-configs/riscv64-softmmu.mak > +++ b/default-configs/riscv64-softmmu.mak > @@ -1,4 +1,5 @@ > -# Default configuration for riscv-softmmu > +# Default configuration for riscv64-softmmu > > CONFIG_SERIAL=y > CONFIG_VIRTIO=y > +CONFIG_SIFIVE_U500=y > diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs > index a0c31ae25e..bac5faa603 100644 > --- a/hw/riscv/Makefile.objs > +++ b/hw/riscv/Makefile.objs > @@ -1,11 +1,11 @@ > obj-y += riscv_elf.o > obj-y += riscv_htif.o > obj-y += riscv_hart.o > -obj-y += sifive_e300.o > +obj-$(CONFIG_SIFIVE_E300) += sifive_e300.o > obj-y += sifive_clint.o > obj-y += sifive_prci.o > obj-y += sifive_plic.o > -obj-y += sifive_u500.o > +obj-$(CONFIG_SIFIVE_U500) += sifive_u500.o > obj-y += sifive_uart.o > obj-y += spike_v1_09.o > obj-y += spike_v1_10.o I’ll check whether there are 64-bit E series chips. Actually the key distinction is no MMU and we don’t yet disable the MMU in the machine. I’ll ask SiFive whether they want to restrict the “bitness”. There is actually no reason why the machine can’t be invoked as 64-bit. As far as I know the RTL is parametiazable and the 32-bit cores are generated from the same RTL source using the rocket chip generator however that’s something i’ll have to check. i.e. we may not want to restrict the options here. The machines are
Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
On Thu, Jan 4, 2018 at 12:23 PM, Eric Blake wrote:
> On 01/02/2018 06:44 PM, Michael Clark wrote:
> > This adds RISC-V into the build system enabling the following targets:
> >
> > - riscv32-softmmu
> > - riscv64-softmmu
> > - riscv32-linux-user
> > - riscv64-linux-user
> >
> > This adds defaults configs for RISC-V, enables the build for the RISC-V
> > CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
> > script is updated to add the RISC-V ELF magic.
> >
> > Expected checkpatch errors for consistency reasons:
> >
> > ERROR: line over 90 characters
> > FILE: scripts/qemu-binfmt-conf.sh
> > Signed-off-by: Michael Clark
> > ---
>
> > +++ b/qapi-schema.json
> > @@ -413,7 +413,7 @@
> > # Since: 2.6
> > ##
> > { 'enum': 'CpuInfoArch',
> > - 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
> > + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ]
> }
>
> Missing documentation that riscv was added in 2.12 (see QKeyCode in
> qapi/ui.json for an enum that serves as an example of documenting
> changes over time).
OK. Will add this in the next spin.
>
> > ##
> > +# @CpuInfoRISCV:
> > +#
> > +# Additional information about a virtual RISCV CPU
> > +#
> > +# @pc: the instruction pointer
> > +#
> > +# Since 2.8
>
> 2.12, actually.
>
> > +##
> > +{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
>
> Should this be 'uint64' or other specific type, rather than the generic
> 'int' (which happens to be 64 bits, but signed)? Other architectures
> use 'int' because of history, but we could use this chance to improve
> things if desired.
>
I'll have to defer to your better judgement as to whether we need to change
this. I like consistency. Is it a change that needs to be made to multiple
arches? It sounds relatively low risk. You decide.
QAPI Schema
M: Eric Blake
M: Markus Armbruster
S: Supported
F: qapi-schema.json
F: qapi/*.json
T: git git://repo.or.cz/qemu/armbru.git qapi-next
Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure
On 01/05/2018 12:47 AM, Michael Clark wrote:
>>
>>> +##
>>> +{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
>>
>> Should this be 'uint64' or other specific type, rather than the generic
>> 'int' (which happens to be 64 bits, but signed)? Other architectures
>> use 'int' because of history, but we could use this chance to improve
>> things if desired.
>>
>
> I'll have to defer to your better judgement as to whether we need to change
> this. I like consistency. Is it a change that needs to be made to multiple
> arches? It sounds relatively low risk. You decide.
>
> QAPI Schema
> M: Eric Blake
> M: Markus Armbruster
I'm fine if this patch uses 'int' for consistency, and will wait for
Markus to chime in on whether changing CpuInfo to use specific integer
types in general is worth a separate series later on.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
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