[Qemu-devel] [PATCH v5 3/9] i386: Initialize cache information for EPYC family processors
Initialize pre-determined cache information for EPYC processors.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eec4a97..67faa53 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2299,6 +2299,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x800A,
.model_id = "AMD EPYC Processor",
+.cache_info.valid = 1,
+.cache_info.l1d_cache = {
+.type = DCACHE,
+.level = 1,
+.size = 32 * KiB,
+.line_size = 64,
+.associativity = 8,
+.partitions = 1,
+.sets = 64,
+.lines_per_tag = 1,
+.self_init = 1,
+.no_invd_sharing = true,
+},
+.cache_info.l1i_cache = {
+.type = ICACHE,
+.level = 1,
+.size = 64 * KiB,
+.line_size = 64,
+.associativity = 4,
+.partitions = 1,
+.sets = 256,
+.lines_per_tag = 1,
+.self_init = 1,
+.no_invd_sharing = true,
+},
+.cache_info.l2_cache = {
+.type = UNIFIED_CACHE,
+.level = 2,
+.size = 512 * KiB,
+.line_size = 64,
+.associativity = 8,
+.partitions = 1,
+.sets = 1024,
+.lines_per_tag = 1,
+},
+.cache_info.l3_cache = {
+.type = UNIFIED_CACHE,
+.level = 3,
+.size = 16 * MiB,
+.line_size = 64,
+.associativity = 16,
+.partitions = 1,
+.sets = 16384,
+.lines_per_tag = 1,
+.self_init = true,
+.inclusive = true,
+.complex_indexing = true,
+},
},
{
.name = "EPYC-IBPB",
@@ -2345,6 +2393,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x800A,
.model_id = "AMD EPYC Processor (with IBPB)",
+.cache_info.valid = 1,
+.cache_info.l1d_cache = {
+.type = DCACHE,
+.level = 1,
+.size = 32 * KiB,
+.line_size = 64,
+.associativity = 8,
+.partitions = 1,
+.sets = 64,
+.lines_per_tag = 1,
+.self_init = 1,
+.no_invd_sharing = true,
+},
+.cache_info.l1i_cache = {
+.type = ICACHE,
+.level = 1,
+.size = 64 * KiB,
+.line_size = 64,
+.associativity = 4,
+.partitions = 1,
+.sets = 256,
+.lines_per_tag = 1,
+.self_init = 1,
+.no_invd_sharing = true,
+},
+.cache_info.l2_cache = {
+.type = UNIFIED_CACHE,
+.level = 2,
+.size = 512 * KiB,
+.line_size = 64,
+.associativity = 8,
+.partitions = 1,
+.sets = 1024,
+.lines_per_tag = 1,
+},
+.cache_info.l3_cache = {
+.type = UNIFIED_CACHE,
+.level = 3,
+.size = 16 * MiB,
+.line_size = 64,
+.associativity = 16,
+.partitions = 1,
+.sets = 16384,
+.lines_per_tag = 1,
+.self_init = true,
+.inclusive = true,
+.complex_indexing = true,
+},
},
};
--
1.8.3.1
[Qemu-devel] [PATCH v5 6/9] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 91 +++
target/i386/kvm.c | 29 --
2 files changed, 117 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 738927d..f69f551 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -307,6 +307,14 @@ static uint32_t encode_cache_cpuid8005(CPUCacheInfo
*cache)
a == ASSOC_FULL ? 0xF : \
0 /* invalid value */)
+/* Definitions used on CPUID Leaf 0x801D */
+/* Number of logical cores in a complex */
+#define CORES_IN_CMPLX 4
+/* Number of logical processors sharing cache */
+#define NUM_SHARING_CACHE(threads) (threads ? \
+ (((CORES_IN_CMPLX - 1) * 2) + 1) : \
+ (CORES_IN_CMPLX - 1))
+
/*
* Encode cache info for CPUID[0x8006].ECX and CPUID[0x8006].EDX
* @l3 can be NULL.
@@ -336,6 +344,40 @@ static void encode_cache_cpuid8006(CPUCacheInfo *l2,
}
}
+/* Encode cache info for CPUID[801D] */
+static void encode_cache_cpuid801d(CPUCacheInfo *cache, int nr_threads,
+uint32_t *eax, uint32_t *ebx,
+uint32_t *ecx, uint32_t *edx)
+{
+assert(cache->size == cache->line_size * cache->associativity *
+ cache->partitions * cache->sets);
+
+*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
+ (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
+
+if (CACHE_TYPE(cache->type) == UNIFIED_CACHE) {
+*eax |= (NUM_SHARING_CACHE(nr_threads - 1) << 14);
+} else {
+*eax |= ((nr_threads - 1) << 14);
+}
+
+assert(cache->line_size > 0);
+assert(cache->partitions > 0);
+assert(cache->associativity > 0);
+/* We don't implement fully-associative caches */
+assert(cache->associativity < cache->sets);
+*ebx = (cache->line_size - 1) |
+ ((cache->partitions - 1) << 12) |
+ ((cache->associativity - 1) << 22);
+
+assert(cache->sets > 0);
+*ecx = cache->sets - 1;
+
+*edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
+ (cache->inclusive ? CACHE_INCLUSIVE : 0) |
+ (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
+}
+
/* Definitions of the hardcoded cache entries we expose: */
/* L1 data cache: */
@@ -4010,6 +4052,55 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*edx = 0;
}
break;
+case 0x801D:
+*eax = 0;
+switch (count) {
+case 0: /* L1 dcache info */
+if (env->cache_info.valid && !cpu->legacy_cache) {
+encode_cache_cpuid801d(>cache_info.l1d_cache,
+ cs->nr_threads,
+ eax, ebx, ecx, edx);
+} else {
+encode_cache_cpuid801d(_cache_amd, cs->nr_threads,
+ eax, ebx, ecx, edx);
+}
+break;
+case 1: /* L1 icache info */
+if (env->cache_info.valid && !cpu->legacy_cache) {
+encode_cache_cpuid801d(>cache_info.l1i_cache,
+ cs->nr_threads,
+ eax, ebx, ecx, edx);
+} else {
+encode_cache_cpuid801d(_cache_amd,
+ cs->nr_threads,
+ eax, ebx, ecx, edx);
+}
+break;
+case 2: /* L2 cache info */
+if (env->cache_info.valid && !cpu->legacy_cache) {
+encode_cache_cpuid801d(>cache_info.l2_cache,
+ cs->nr_threads,
+ eax, ebx, ecx, edx);
+} else {
+encode_cache_cpuid801d(_cache_amd, cs->nr_threads,
+ eax, ebx, ecx, edx);
+}
+break;
+case 3: /* L3 cache info */
+if (env->cache_info.valid && !cpu->legacy_cache) {
+encode_cache_cpuid801d(>cache_info.l3_cache,
+ cs->nr_threads,
+ eax, ebx, ecx, edx);
+} else {
+encode_cache_cpuid801d(_c
[Qemu-devel] [PATCH v5 9/9] i386: Remove generic SMT thread check
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f8e7325..e216d54 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4824,17 +4824,20 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
**errp)
qemu_init_vcpu(cs);
-/* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
- * issue by adjusting CPUID__0001_EBX and CPUID_8000_0008_ECX
- * based on inputs (sockets,cores,threads), it is still better to gives
+/* Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
+ * fixes this issue by adjusting CPUID__0001_EBX and
CPUID_8000_0008_ECX
+ * based on inputs (sockets,cores,threads), it is still better to give
* users a warning.
*
* NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
* cs->nr_threads hasn't be populated yet and the checking is incorrect.
*/
-if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
-error_report("AMD CPU doesn't support hyperthreading. Please configure"
- " -smp options properly.");
+ if (IS_AMD_CPU(env) &&
+ !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
+ cs->nr_threads > 1 && !ht_warned) {
+error_report("This family of AMD CPU doesn't support "
+ "hyperthreading. Please configure -smp "
+ "options properly.");
ht_warned = true;
}
--
1.8.3.1
[Qemu-devel] [PATCH v5 5/9] i386: Use the statically loaded cache definitions
Use the statically loaded cache definitions if available
and legacy-cache parameter is not set.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f4fbe3a..738927d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3938,8 +3938,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
-*ecx = encode_cache_cpuid8005(_cache_amd);
-*edx = encode_cache_cpuid8005(_cache_amd);
+if (env->cache_info.valid && !cpu->legacy_cache) {
+*ecx = encode_cache_cpuid8005(>cache_info.l1d_cache);
+*edx = encode_cache_cpuid8005(>cache_info.l1i_cache);
+} else {
+*ecx = encode_cache_cpuid8005(_cache_amd);
+*edx = encode_cache_cpuid8005(_cache_amd);
+}
break;
case 0x8006:
/* cache info (L2 cache) */
@@ -3955,9 +3960,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
(L2_DTLB_4K_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
(L2_ITLB_4K_ENTRIES);
-encode_cache_cpuid8006(_cache_amd,
- cpu->enable_l3_cache ? _cache : NULL,
- ecx, edx);
+if (env->cache_info.valid && !cpu->legacy_cache) {
+encode_cache_cpuid8006(>cache_info.l2_cache,
+ cpu->enable_l3_cache ?
+ >cache_info.l3_cache : NULL,
+ ecx, edx);
+} else {
+encode_cache_cpuid8006(_cache_amd,
+ cpu->enable_l3_cache ? _cache : NULL,
+ ecx, edx);
+}
break;
case 0x8007:
*eax = 0;
--
1.8.3.1
[Qemu-devel] [PATCH v5 8/9] i386: Enable TOPOEXT feature on AMD EPYC CPU
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6f3ad44..f8e7325 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2330,7 +2330,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
-CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
+CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+CPUID_EXT3_TOPOEXT,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
@@ -2422,7 +2423,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
-CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
+CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+CPUID_EXT3_TOPOEXT,
.features[FEAT_8000_0008_EBX] =
CPUID_8000_0008_EBX_IBPB,
.features[FEAT_7_0_EBX] =
@@ -4575,6 +4577,11 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error
**errp)
x86_cpu_adjust_level(cpu, >cpuid_min_xlevel, 0x800A);
}
+/* TOPOEXT feature requires 0x801E */
+if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) {
+x86_cpu_adjust_level(cpu, >cpuid_min_xlevel, 0x801E);
+}
+
/* SEV requires CPUID[0x801F] */
if (sev_enabled()) {
x86_cpu_adjust_level(cpu, >cpuid_min_xlevel, 0x801F);
--
1.8.3.1
[Qemu-devel] [PATCH v5 4/9] i386: Add new property to control cache info
This will be used to control the cache information.
By default new information will be displayed. If user
passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
include/hw/i386/pc.h | 6 +-
target/i386/cpu.c| 1 +
target/i386/cpu.h| 5 +
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ffee841..9cda1ab 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -327,7 +327,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = "q35-pcihost",\
.property = "x-pci-hole64-fix",\
.value= "off",\
-},
+},{\
+.driver = TYPE_X86_CPU,\
+.property = "legacy-cache",\
+.value= "off",\
+},\
#define PC_COMPAT_2_9 \
HW_COMPAT_2_9 \
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 67faa53..f4fbe3a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5132,6 +5132,7 @@ static Property x86_cpu_properties[] = {
false),
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
+DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false),
/*
* From "Requirements for Implementing the Microsoft
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 806c34b..bbe13f2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1394,6 +1394,11 @@ struct X86CPU {
*/
bool enable_l3_cache;
+/* Compatibility bits for old machine types.
+ * If true present the old cache topology information
+ */
+bool legacy_cache;
+
/* Compatibility bits for old machine types: */
bool enable_cpuid_0xb;
--
1.8.3.1
[Qemu-devel] [PATCH v5 7/9] i386: Add support for CPUID_8000_001E for AMD
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT feature is supported. This is required to support hyperthreading feature on AMD CPUs. This is supported via CPUID_8000_001E extended functions. Signed-off-by: Babu Moger <babu.mo...@amd.com> --- target/i386/cpu.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f69f551..6f3ad44 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -315,6 +315,12 @@ static uint32_t encode_cache_cpuid8005(CPUCacheInfo *cache) (((CORES_IN_CMPLX - 1) * 2) + 1) : \ (CORES_IN_CMPLX - 1)) +/* Definitions used on CPUID Leaf 0x801E */ +#define EXTENDED_APIC_ID(threads, socket_id, core_id, thread_id) \ +((threads) ? \ + ((socket_id << 6) | (core_id << 1) | thread_id) : \ + ((socket_id << 6) | core_id)) + /* * Encode cache info for CPUID[0x8006].ECX and CPUID[0x8006].EDX * @l3 can be NULL. @@ -4101,6 +4107,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; } break; +case 0x801E: +assert(cpu->core_id <= 255); +*eax = EXTENDED_APIC_ID((cs->nr_threads - 1), + cpu->socket_id, cpu->core_id, cpu->thread_id); +*ebx = (cs->nr_threads - 1) << 8 | cpu->core_id; +*ecx = cpu->socket_id; +*edx = 0; +break; case 0xC000: *eax = env->cpuid_xlevel2; *ebx = 0; -- 1.8.3.1
[Qemu-devel] [PATCH v3 4/5] target/i386: Enable TOPOEXT feature on AMD EPYC CPU
Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x801E.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 555ab83..88941d9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1955,7 +1955,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
-CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
+CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+CPUID_EXT3_TOPOEXT,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
@@ -1970,7 +1971,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_XSAVE_XGETBV1,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
-.xlevel = 0x800A,
+.xlevel = 0x801E,
.model_id = "AMD EPYC Processor",
},
{
--
1.8.3.1
[Qemu-devel] [PATCH v3 3/5] target/i386: Add support for CPUID_8000_001E for AMD
From: Stanislav Lanci <p...@polepetko.eu>
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1485175..555ab83 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3666,6 +3666,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*edx = 0;
}
break;
+case 0x801E:
+if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) {
+assert(cpu->core_id <= 255);
+*eax = cpu->apic_id;
+*ebx = (cs->nr_threads - 1) << 8 | cpu->core_id;
+*ecx = cpu->socket_id;
+*edx = 0;
+}
+break;
case 0xC000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
--
1.8.3.1
[Qemu-devel] [PATCH v3 5/5] target/i386: Remove generic SMT thread check
Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.
CPU family with TOPOEXT feature can support hyperthreading now.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 88941d9..0eb319d 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4337,17 +4337,20 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
**errp)
qemu_init_vcpu(cs);
-/* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
- * issue by adjusting CPUID__0001_EBX and CPUID_8000_0008_ECX
- * based on inputs (sockets,cores,threads), it is still better to gives
+/* Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
+ * fixes this issue by adjusting CPUID__0001_EBX and
CPUID_8000_0008_ECX
+ * based on inputs (sockets,cores,threads), it is still better to give
* users a warning.
*
* NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
* cs->nr_threads hasn't be populated yet and the checking is incorrect.
*/
-if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
-error_report("AMD CPU doesn't support hyperthreading. Please configure"
- " -smp options properly.");
+ if (IS_AMD_CPU(env) &&
+ !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
+ cs->nr_threads > 1 && !ht_warned) {
+error_report("This family of AMD CPU doesn't support "
+ "hyperthreading. Please configure -smp "
+ "options properly.");
ht_warned = true;
}
--
1.8.3.1
[Qemu-devel] [PATCH v3 1/5] target/i386: Generalize some of the macro definitions
Generalize some of the macro definitions which are generic cache
properties that are common between CPUID 4 and CPUID 0x801D
in preparation for adding support for 0x801D.
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 52 ++--
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b5e431e..42dd381 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -66,22 +66,22 @@
#define CPUID_2_L3_16MB_16WAY_64B 0x4d
-/* CPUID Leaf 4 constants: */
+/* Cache specific constants: */
/* EAX: */
-#define CPUID_4_TYPE_DCACHE 1
-#define CPUID_4_TYPE_ICACHE 2
-#define CPUID_4_TYPE_UNIFIED 3
+#define TYPE_DCACHE 1
+#define TYPE_ICACHE 2
+#define TYPE_UNIFIED 3
-#define CPUID_4_LEVEL(l) ((l) << 5)
+#define CACHE_LEVEL(l) ((l) << 5)
-#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
-#define CPUID_4_FULLY_ASSOC (1 << 9)
+#define CACHE_SELF_INIT_LEVEL (1 << 8)
+#define CACHE_FULLY_ASSOC (1 << 9)
/* EDX: */
-#define CPUID_4_NO_INVD_SHARING (1 << 0)
-#define CPUID_4_INCLUSIVE (1 << 1)
-#define CPUID_4_COMPLEX_IDX (1 << 2)
+#define CACHE_NO_INVD_SHARING (1 << 0)
+#define CACHE_INCLUSIVE (1 << 1)
+#define CACHE_COMPLEX_IDX (1 << 2)
#define ASSOC_FULL 0xFF
@@ -3273,29 +3273,29 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*eax = 0;
switch (count) {
case 0: /* L1 dcache info */
-*eax |= CPUID_4_TYPE_DCACHE | \
-CPUID_4_LEVEL(1) | \
-CPUID_4_SELF_INIT_LEVEL;
+*eax |= TYPE_DCACHE | \
+CACHE_LEVEL(1) | \
+CACHE_SELF_INIT_LEVEL;
*ebx = (L1D_LINE_SIZE - 1) | \
((L1D_PARTITIONS - 1) << 12) | \
((L1D_ASSOCIATIVITY - 1) << 22);
*ecx = L1D_SETS - 1;
-*edx = CPUID_4_NO_INVD_SHARING;
+*edx = CACHE_NO_INVD_SHARING;
break;
case 1: /* L1 icache info */
-*eax |= CPUID_4_TYPE_ICACHE | \
-CPUID_4_LEVEL(1) | \
-CPUID_4_SELF_INIT_LEVEL;
+*eax |= TYPE_ICACHE | \
+CACHE_LEVEL(1) | \
+CACHE_SELF_INIT_LEVEL;
*ebx = (L1I_LINE_SIZE - 1) | \
((L1I_PARTITIONS - 1) << 12) | \
((L1I_ASSOCIATIVITY - 1) << 22);
*ecx = L1I_SETS - 1;
-*edx = CPUID_4_NO_INVD_SHARING;
+*edx = CACHE_NO_INVD_SHARING;
break;
case 2: /* L2 cache info */
-*eax |= CPUID_4_TYPE_UNIFIED | \
-CPUID_4_LEVEL(2) | \
-CPUID_4_SELF_INIT_LEVEL;
+*eax |= TYPE_UNIFIED | \
+CACHE_LEVEL(2) | \
+CACHE_SELF_INIT_LEVEL;
if (cs->nr_threads > 1) {
*eax |= (cs->nr_threads - 1) << 14;
}
@@ -3303,7 +3303,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
((L2_PARTITIONS - 1) << 12) | \
((L2_ASSOCIATIVITY - 1) << 22);
*ecx = L2_SETS - 1;
-*edx = CPUID_4_NO_INVD_SHARING;
+*edx = CACHE_NO_INVD_SHARING;
break;
case 3: /* L3 cache info */
if (!cpu->enable_l3_cache) {
@@ -3313,16 +3313,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*edx = 0;
break;
}
-*eax |= CPUID_4_TYPE_UNIFIED | \
-CPUID_4_LEVEL(3) | \
-CPUID_4_SELF_INIT_LEVEL;
+*eax |= TYPE_UNIFIED | \
+CACHE_LEVEL(3) | \
+CACHE_SELF_INIT_LEVEL;
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
*eax |= ((1 << pkg_offset) - 1) << 14;
*ebx = (L3_N_LINE_SIZE - 1) | \
((L3_N_PARTITIONS - 1) << 12) | \
((L3_N_ASSOCIATIVITY - 1) << 22);
*ecx = L3_N_SETS - 1;
-*edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
+*edx = CACHE_INCLUSIVE | CACHE_COMPLEX_IDX;
break;
default: /* end of info */
*eax = 0;
--
1.8.3.1
[Qemu-devel] [PATCH v3 0/5] Enable TOPOEXT to support hyperthreading on AMD CPU
This series enables the TOPOEXT feature for AMD CPUs. This is required to support hyperthreading on kvm guests. This addresses the issues reported in these bugs: https://bugzilla.redhat.com/show_bug.cgi?id=1481253 https://bugs.launchpad.net/qemu/+bug/1703506 v3: 1.Removed the patch #1. Radim mentioned that original typo problem is in linux kernel header. qemu is just copying those files. 2.In previous version, I used the cpuid 4 definitions for AMDs cpuid leaf 0x801D. CPUID 4 is very intel specific and we dont want to expose those details under AMD. I have renamed some of these definitions as generic. These changes are in patch#1. Radim, let me know if this is what you intended. 3.Added assert to for core_id(Suggested by Radim Krčmář). 4.Changed the if condition under "L3 cache info"(Suggested by Gary Hook). 5.Addressed few more text correction and code cleanup(Suggested by Thomas Lendacky). v2: Fixed few more minor issues per Gary Hook's comments. Thank you Gary. Removed the patch#1. We need to handle the instruction cache associativity seperately. It varies based on the cpu family. I will comeback to that later. Added two more typo corrections in patch#1 and patch#5. v1: Stanislav Lanci posted few patches earlier. https://patchwork.kernel.org/patch/10040903/ Rebased his patches with few changes. 1.Spit the patches into two, separating cpuid functions 0x801D and 0x801E (Patch 2 and 3). 2.Removed the generic non-intel check and made a separate patch with some changes(Patch 5). 3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn801D_ECX_x03. Added 2 more patches. Patch 1. Fixes cache associativity. Patch 4. Adds TOPOEXT feature on AMD EPYC CPU. Babu Moger (3): target/i386: Generalize some of the macro definitions target/i386: Enable TOPOEXT feature on AMD EPYC CPU target/i386: Remove generic SMT thread check Stanislav Lanci (2): target/i386: Populate AMD Processor Cache Information target/i386: Add support for CPUID_8000_001E for AMD target/i386/cpu.c | 157 ++ target/i386/kvm.c | 29 -- 2 files changed, 149 insertions(+), 37 deletions(-) -- 1.8.3.1
[Qemu-devel] [PATCH v3 2/5] target/i386: Populate AMD Processor Cache Information
From: Stanislav Lanci <p...@polepetko.eu>
Add information for cpuid 0x801D leaf. Populate cache topology information
for different cache types(Data Cache, Instruction Cache, L2 and L3) supported
by 0x801D leaf. Please refer Processor Programming Reference (PPR) for AMD
Family 17h Model for more details.
Signed-off-by: Stanislav Lanci <p...@polepetko.eu>
Signed-off-by: Babu Moger <babu.mo...@amd.com>
---
target/i386/cpu.c | 76 +++
target/i386/kvm.c | 29 ++---
2 files changed, 102 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 42dd381..1485175 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -118,6 +118,7 @@
#define L1I_LINE_SIZE 64
#define L1I_ASSOCIATIVITY 8
#define L1I_SETS 64
+#define L1I_SETS_AMD 256
#define L1I_PARTITIONS 1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
@@ -129,7 +130,9 @@
/* Level 2 unified cache: */
#define L2_LINE_SIZE 64
#define L2_ASSOCIATIVITY 16
+#define L2_ASSOCIATIVITY_AMD 8
#define L2_SETS 4096
+#define L2_SETS_AMD 1024
#define L2_PARTITIONS 1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
@@ -146,6 +149,7 @@
#define L3_N_LINE_SIZE 64
#define L3_N_ASSOCIATIVITY 16
#define L3_N_SETS 16384
+#define L3_N_SETS_AMD8192
#define L3_N_PARTITIONS 1
#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
#define L3_N_LINES_PER_TAG 1
@@ -3590,6 +3594,78 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*edx = 0;
}
break;
+case 0x801D: /* AMD TOPOEXT cache info */
+if (cpu->cache_info_passthrough) {
+host_cpuid(index, count, eax, ebx, ecx, edx);
+break;
+} else if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) {
+*eax = 0;
+switch (count) {
+case 0: /* L1 dcache info */
+*eax |= TYPE_DCACHE | \
+CACHE_LEVEL(1) | \
+CACHE_SELF_INIT_LEVEL | \
+((cs->nr_threads - 1) << 14);
+*ebx = (L1D_LINE_SIZE - 1) | \
+ ((L1D_PARTITIONS - 1) << 12) | \
+ ((L1D_ASSOCIATIVITY - 1) << 22);
+*ecx = L1D_SETS - 1;
+*edx = 0;
+break;
+case 1: /* L1 icache info */
+*eax |= TYPE_ICACHE | \
+CACHE_LEVEL(1) | \
+CACHE_SELF_INIT_LEVEL | \
+((cs->nr_threads - 1) << 14);
+*ebx = (L1I_LINE_SIZE - 1) | \
+ ((L1I_PARTITIONS - 1) << 12) | \
+ ((L1I_ASSOCIATIVITY_AMD - 1) << 22);
+*ecx = L1I_SETS_AMD - 1;
+*edx = 0;
+break;
+case 2: /* L2 cache info */
+*eax |= TYPE_UNIFIED | \
+CACHE_LEVEL(2) | \
+CACHE_SELF_INIT_LEVEL | \
+((cs->nr_threads - 1) << 14);
+*ebx = (L2_LINE_SIZE - 1) | \
+ ((L2_PARTITIONS - 1) << 12) | \
+ ((L2_ASSOCIATIVITY_AMD - 1) << 22);
+*ecx = L2_SETS_AMD - 1;
+*edx = CACHE_INCLUSIVE;
+break;
+case 3: /* L3 cache info */
+if (cpu->enable_l3_cache) {
+*eax |= TYPE_UNIFIED | \
+CACHE_LEVEL(3) | \
+CACHE_SELF_INIT_LEVEL | \
+((cs->nr_cores * cs->nr_threads - 1) << 14);
+*ebx = (L3_N_LINE_SIZE - 1) | \
+ ((L3_N_PARTITIONS - 1) << 12) | \
+ ((L3_N_ASSOCIATIVITY - 1) << 22);
+*ecx = L3_N_SETS_AMD - 1;
+*edx = CACHE_NO_INVD_SHARING;
+} else {
+*eax = 0;
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
+}
+break;
+default: /* end of info */
+*eax = 0;
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
+break;
+}
+} else {
+*eax = 0;
+*ebx = 0;
+*ecx = 0;
+*edx = 0;
+}
+break;
case 0xC000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index ad4b159..0eb39b52 100644
--- a/
[PATCH v3 15/18] hw/i386: Introduce apic_id_from_topo_ids handler in PCMachineState
Add function pointer apic_id_from_topo_ids in PCMachineState.
Initialize with correct handler based on the mode selected.
Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids
for consistency. x86_apicid_from_topo_ids will be the default handler.
Signed-off-by: Babu Moger llc_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = apicid_from_topo_ids(_info, _ids);
+cpu->apic_id = pcms->apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
@@ -2682,6 +2682,7 @@ static void pc_machine_initfn(Object *obj)
/* Initialize the apic id related handlers */
pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid;
+pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids;
pc_system_flash_create(pcms);
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index ffc5c78164..0789f8b5ea 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -73,6 +73,8 @@ struct PCMachineState {
unsigned cpu_index);
void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
X86CPUTopoIDs *topo_ids);
+apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids);
/* Address space used by IOAPIC device. All IOAPIC interrupts
* will be translated to MSI messages in the address space. */
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index adb92fe9ce..b2b9e93a06 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -206,7 +206,7 @@ static inline apic_id_t
x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info,
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
-static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
+static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
const X86CPUTopoIDs *topo_ids)
{
return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
@@ -259,7 +259,7 @@ static inline apic_id_t
x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
{
X86CPUTopoIDs topo_ids;
x86_topo_ids_from_idx(topo_info, cpu_index, _ids);
-return apicid_from_topo_ids(topo_info, _ids);
+return x86_apicid_from_topo_ids(topo_info, _ids);
}
#endif /* HW_I386_TOPOLOGY_H */
[PATCH v3 13/18] hw/i386: Introduce apicid_from_cpu_idx in PCMachineState
Add function pointers in PCMachineState to handle apic id specific
functionalities. This will be used to initialize with correct handlers based on
the cpu model selected.
x86_apicid_from_cpu_idx will be default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |5 -
include/hw/i386/pc.h |5 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 7f30104a6b..52aea4a652 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -894,7 +894,7 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState
*pcms,
initialize_topo_info(_info, pcms, ms);
-correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
+correct_id = pcms->apicid_from_cpu_idx(_info, cpu_index);
if (pcmc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -2679,6 +2679,9 @@ static void pc_machine_initfn(Object *obj)
pcms->pit_enabled = true;
pcms->smp_dies = 1;
+/* Initialize the apic id related handlers */
+pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
+
pc_system_flash_create(pcms);
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 37bfd95113..56aa0e45b5 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -16,6 +16,7 @@
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/acpi/acpi_dev_interface.h"
+#include "hw/i386/topology.h"
#define HPET_INTCAP "hpet-intcap"
@@ -67,6 +68,10 @@ struct PCMachineState {
uint64_t numa_nodes;
uint64_t *node_mem;
+/* Apic id specific handlers */
+uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
+unsigned cpu_index);
+
/* Address space used by IOAPIC device. All IOAPIC interrupts
* will be translated to MSI messages in the address space. */
AddressSpace *ioapic_as;
[PATCH v3 06/18] hw/core: Add core complex id in X86CPU topology
Introduce last level cache id(llc_id) in x86CPU topology. This information is
required to build the topology in EPIC mode.
Signed-off-by: Babu Moger
---
hw/core/machine-hmp-cmds.c |3 +++
hw/core/machine.c | 13 +
hw/i386/pc.c | 10 ++
include/hw/i386/topology.h |1 +
qapi/machine.json |7 +--
target/i386/cpu.c |2 ++
target/i386/cpu.h |1 +
7 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index cd970cc4c5..59c91d1ce1 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -90,6 +90,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
if (c->has_die_id) {
monitor_printf(mon, "die-id: \"%" PRIu64 "\"\n", c->die_id);
}
+if (c->has_llc_id) {
+monitor_printf(mon, "llc-id: \"%" PRIu64 "\"\n", c->llc_id);
+}
if (c->has_core_id) {
monitor_printf(mon, "core-id: \"%" PRIu64 "\"\n", c->core_id);
}
diff --git a/hw/core/machine.c b/hw/core/machine.c
index e59b181ead..ff991e6ab5 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -683,6 +683,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
return;
}
+if (props->has_llc_id && !slot->props.has_llc_id) {
+error_setg(errp, "llc-id is not supported");
+return;
+}
+
/* skip slots with explicit mismatch */
if (props->has_thread_id && props->thread_id != slot->props.thread_id)
{
continue;
@@ -696,6 +701,10 @@ void machine_set_cpu_numa_node(MachineState *machine,
continue;
}
+if (props->has_llc_id && props->llc_id != slot->props.llc_id) {
+continue;
+}
+
if (props->has_socket_id && props->socket_id != slot->props.socket_id)
{
continue;
}
@@ -1034,6 +1043,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
if (cpu->props.has_die_id) {
g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
}
+
+if (cpu->props.has_llc_id) {
+g_string_append_printf(s, "llc-id: %"PRId64, cpu->props.llc_id);
+}
if (cpu->props.has_core_id) {
if (s->len) {
g_string_append_printf(s, ", ");
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 17de152a77..df5339c102 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2294,6 +2294,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.pkg_id = cpu->socket_id;
topo_ids.die_id = cpu->die_id;
+topo_ids.llc_id = cpu->llc_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
cpu->apic_id = apicid_from_topo_ids(_info, _ids);
@@ -2339,6 +2340,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
}
cpu->die_id = topo_ids.die_id;
+if (cpu->llc_id != -1 && cpu->llc_id != topo_ids.llc_id) {
+error_setg(errp, "property llc-id: %u doesn't match set apic-id:"
+" 0x%x (llc-id: %u)", cpu->llc_id, cpu->apic_id, topo_ids.llc_id);
+return;
+}
+cpu->llc_id = topo_ids.llc_id;
+
if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
topo_ids.core_id);
@@ -2752,6 +2760,8 @@ static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].props.has_die_id = true;
ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
}
+ms->possible_cpus->cpus[i].props.has_llc_id = true;
+ms->possible_cpus->cpus[i].props.llc_id = topo_ids.llc_id;
ms->possible_cpus->cpus[i].props.has_core_id = true;
ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
ms->possible_cpus->cpus[i].props.has_thread_id = true;
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index ba52d49079..1238006208 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -48,6 +48,7 @@ typedef uint32_t apic_id_t;
typedef struct X86CPUTopoIDs {
unsigned pkg_id;
unsigned die_id;
+unsigned llc_id;
unsigned core_id;
unsigned smt_id;
} X86CPUTopoIDs;
diff --git a/qapi/machine.json b/qapi/machine.json
index ca26779f1a..1ca5b73418 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -646,9 +646,11 @@
[PATCH v3 03/18] hw/i386: Consolidate topology functions
Now that we have all the parameters in X86CPUTopoInfo, we can just pass the
structure to calculate the offsets and width.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 64 ++--
target/i386/cpu.c | 23
2 files changed, 32 insertions(+), 55 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index cf1935d548..ba52d49079 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
/* Bit width of the SMT_ID (thread ID) field on the APIC ID
*/
-static inline unsigned apicid_smt_width(unsigned nr_dies,
-unsigned nr_cores,
-unsigned nr_threads)
+static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_threads);
+return apicid_bitwidth_for_count(topo_info->threads_per_core);
}
/* Bit width of the Core_ID field
*/
-static inline unsigned apicid_core_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_cores);
+return apicid_bitwidth_for_count(topo_info->cores_per_die);
}
/* Bit width of the Die_ID field */
-static inline unsigned apicid_die_width(unsigned nr_dies,
-unsigned nr_cores,
-unsigned nr_threads)
+static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_dies);
+return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
/* Bit offset of the Core_ID field
*/
-static inline unsigned apicid_core_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_smt_width(nr_dies, nr_cores, nr_threads);
+return apicid_smt_width(topo_info);
}
/* Bit offset of the Die_ID field */
-static inline unsigned apicid_die_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_core_offset(nr_dies, nr_cores, nr_threads) +
- apicid_core_width(nr_dies, nr_cores, nr_threads);
+return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
}
/* Bit offset of the Pkg_ID (socket ID) field
*/
-static inline unsigned apicid_pkg_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_die_offset(nr_dies, nr_cores, nr_threads) +
- apicid_die_width(nr_dies, nr_cores, nr_threads);
+return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
@@ -128,13 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
const X86CPUTopoIDs *topo_ids)
{
-unsigned nr_dies = topo_info->dies_per_pkg;
-unsigned nr_cores = topo_info->cores_per_die;
-unsigned nr_threads = topo_info->threads_per_core;
-
-return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores,
nr_threads)) |
- (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores,
nr_threads)) |
- (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores,
nr_threads)) |
+return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
topo_ids->smt_id;
}
@@ -162,19 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t
apicid,
X86CPUTopoInfo *topo_info,
X86CPUTopoIDs *topo_ids)
{
-unsigned nr_dies = topo_info->dies_per_pkg;
-unsigned nr_cores = topo_info->cores_per_die;
-unsigned nr_threads = topo_info->threads_per_core;
-
topo_ids->smt_id = apicid &
-~(0xUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
+~(0xUL << apicid_smt_width(topo_info));
topo_ids->core_id =
-(apicid >> apicid_core_offset(nr_dies, nr_cores, nr_thr
[PATCH v3 02/18] hw/i386: Introduce X86CPUTopoInfo to contain topology info
This is an effort to re-arrange few data structure for better readability.
Add X86CPUTopoInfo which will have all the topology informations required
to build the cpu topology. There is no functional changes.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 40 +++-
include/hw/i386/topology.h | 38 --
2 files changed, 51 insertions(+), 27 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 5bd2ffccb7..8c23b1e8c9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -878,11 +878,15 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState
*pcms,
{
MachineState *ms = MACHINE(pcms);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
+X86CPUTopoInfo topo_info;
uint32_t correct_id;
static bool warned;
-correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
- ms->smp.threads, cpu_index);
+topo_info.dies_per_pkg = pcms->smp_dies;
+topo_info.cores_per_die = ms->smp.cores;
+topo_info.threads_per_core = ms->smp.threads;
+
+correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
if (pcmc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -2219,6 +2223,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
PCMachineState *pcms = PC_MACHINE(hotplug_dev);
unsigned int smp_cores = ms->smp.cores;
unsigned int smp_threads = ms->smp.threads;
+X86CPUTopoInfo topo_info;
if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
@@ -2226,6 +2231,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
+topo_info.dies_per_pkg = pcms->smp_dies;
+topo_info.cores_per_die = smp_cores;
+topo_info.threads_per_core = smp_threads;
+
env->nr_dies = pcms->smp_dies;
/*
@@ -2281,16 +2290,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
-smp_threads, _ids);
+cpu->apic_id = apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
-x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
- smp_cores, smp_threads, _ids);
+x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -2311,8 +2318,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
-x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
- smp_cores, smp_threads, _ids);
+x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo_ids.pkg_id);
@@ -2694,19 +2700,28 @@ static int64_t pc_get_default_cpu_node_id(const
MachineState *ms, int idx)
{
X86CPUTopoIDs topo_ids;
PCMachineState *pcms = PC_MACHINE(ms);
+ X86CPUTopoInfo topo_info;
+
+ topo_info.dies_per_pkg = pcms->smp_dies;
+ topo_info.cores_per_die = ms->smp.cores;
+ topo_info.threads_per_core = ms->smp.threads;
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
-pcms->smp_dies, ms->smp.cores,
-ms->smp.threads, _ids);
+_info, _ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
{
PCMachineState *pcms = PC_MACHINE(ms);
-int i;
unsigned int max_cpus = ms->smp.max_cpus;
+X86CPUTopoInfo topo_info;
+int i;
+
+topo_info.dies_per_pkg = pcms->smp_dies;
+topo_info.cores_per_die = ms->smp.cores;
+topo_info.threads_per_core = ms->smp.threads;
if (ms->possible_cpus) {
[PATCH v3 10/18] hw/386: Add EPYC mode topology decoding functions
These functions add support for building EPYC mode topology given the smp
details like numa nodes, cores, threads and sockets.
The new apic id decoding is mostly similar to current apic id decoding
except that it adds a new field llc_id when numa configured. Removes all
the hardcoded values. Subsequent patches will use these functions to build
the topology.
Following functions are added.
apicid_llc_width_epyc
apicid_llc_offset_epyc
apicid_pkg_offset_epyc
apicid_from_topo_ids_epyc
x86_topo_ids_from_idx_epyc
x86_topo_ids_from_apicid_epyc
x86_apicid_from_cpu_idx_epyc
The topology details are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors.
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 93
1 file changed, 93 insertions(+)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index cfb09312fe..adb92fe9ce 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -89,6 +89,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo
*topo_info)
return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
+/* Bit width of the llc_ID field per socket */
+static inline unsigned apicid_llc_width_epyc(X86CPUTopoInfo *topo_info)
+{
+return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1));
+}
/* Bit offset of the Core_ID field
*/
static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
@@ -109,6 +114,94 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo
*topo_info)
return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
+#define LLC_OFFSET 3 /* Minimum LLC offset if numa configured */
+
+/* Bit offset of the llc_ID field */
+static inline unsigned apicid_llc_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+unsigned offset = apicid_die_offset(topo_info) +
+ apicid_die_width(topo_info);
+
+if (topo_info->nodes_per_pkg) {
+return MAX(LLC_OFFSET, offset);
+} else {
+return offset;
+}
+}
+
+/* Bit offset of the Pkg_ID (socket ID) field */
+static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+return apicid_llc_offset_epyc(topo_info) +
apicid_llc_width_epyc(topo_info);
+}
+
+/*
+ * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
+ *
+ * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
+ */
+static inline apic_id_t apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs
*topo_ids)
+{
+return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
+ (topo_ids->llc_id << apicid_llc_offset_epyc(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
+ topo_ids->smt_id;
+}
+
+static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info,
+ unsigned cpu_index,
+ X86CPUTopoIDs *topo_ids)
+{
+unsigned nr_nodes = MAX(topo_info->nodes_per_pkg, 1);
+unsigned nr_dies = topo_info->dies_per_pkg;
+unsigned nr_cores = topo_info->cores_per_die;
+unsigned nr_threads = topo_info->threads_per_core;
+unsigned cores_per_node = DIV_ROUND_UP((nr_dies * nr_cores * nr_threads),
+nr_nodes);
+
+topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
+topo_ids->llc_id = (cpu_index / cores_per_node) % nr_nodes;
+topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
+topo_ids->core_id = cpu_index / nr_threads % nr_cores;
+topo_ids->smt_id = cpu_index % nr_threads;
+}
+
+/*
+ * Calculate thread/core/package IDs for a specific topology,
+ * based on APIC ID
+ */
+static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid,
+X86CPUTopoInfo *topo_info,
+X86CPUTopoIDs *topo_ids)
+{
+topo_ids->smt_id = apicid &
+~(0xUL << apicid_smt_width(topo_info));
+topo_ids->core_id =
+(apicid >> apicid_core_offset(topo_info)) &
+~(0xUL << apicid_core_width(topo_info));
+topo_ids->die_id =
+(apicid >> apicid_die_offset(topo_info)) &
+~(0xUL << apicid_die_width(topo_info));
+topo_ids->llc_id =
+(apicid >> apicid_llc_offset_epyc(topo_info)) &
+~(0xUL << apicid_llc_width_epyc(topo_info));
+topo_ids->pkg_id = apicid >> apicid_pkg_offset_epyc(topo_info);
+}
+
+/*
+ * Make APIC ID for the CPU
[PATCH v3 17/18] i386: Fix pkg_id offset for epyc mode
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e87487bae3..0eaedeb848 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4456,7 +4456,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
{
X86CPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
-uint32_t die_offset;
+uint32_t die_offset, pkg_offset;
uint32_t limit;
uint32_t signature[3];
X86CPUTopoInfo topo_info;
@@ -4466,6 +4466,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
topo_info.cores_per_die = cs->nr_cores;
topo_info.threads_per_core = cs->nr_threads;
+if (env->family_type == CPUX86FAMILY_EPYC)
+pkg_offset = apicid_pkg_offset_epyc(_info);
+else
+pkg_offset = apicid_pkg_offset(_info);
+
/* Calculate & apply limits for different index ranges */
if (index >= 0xC000) {
limit = env->cpuid_xlevel2;
@@ -4647,7 +4652,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
-*eax = apicid_pkg_offset(_info);
+*eax = pkg_offset;
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
@@ -4681,7 +4686,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
-*eax = apicid_pkg_offset(_info);
+*eax = pkg_offset;
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
[PATCH v3 16/18] hw/i386: Introduce EPYC mode function handlers
Introduce following handlers for new epyc mode.
x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index.
x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id.
x86_apicid_from_topo_ids_epyc: Generate apicid from topo ids.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 12
include/hw/i386/topology.h |4 ++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index e6c8a458e7..64e3658873 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2819,6 +2819,17 @@ static bool pc_hotplug_allowed(MachineState *ms,
DeviceState *dev, Error **errp)
return true;
}
+static void pc_init_apicid_fn(MachineState *ms)
+{
+PCMachineState *pcms = PC_MACHINE(ms);
+
+if (!strncmp(ms->cpu_type, "EPYC", 4)) {
+pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc;
+pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc;
+pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc;
+}
+}
+
static void pc_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -2847,6 +2858,7 @@ static void pc_machine_class_init(ObjectClass *oc, void
*data)
mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
+mc->init_apicid_fn = pc_init_apicid_fn;
mc->auto_enable_numa_with_memhp = true;
mc->has_hotpluggable_cpus = true;
mc->default_boot_order = "cad";
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index b2b9e93a06..f028d2332a 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -140,7 +140,7 @@ static inline unsigned
apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
-static inline apic_id_t apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
+static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo
*topo_info,
const X86CPUTopoIDs
*topo_ids)
{
return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
@@ -200,7 +200,7 @@ static inline apic_id_t
x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info,
{
X86CPUTopoIDs topo_ids;
x86_topo_ids_from_idx_epyc(topo_info, cpu_index, _ids);
-return apicid_from_topo_ids_epyc(topo_info, _ids);
+return x86_apicid_from_topo_ids_epyc(topo_info, _ids);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
*
[PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models
This series fixes APIC ID encoding problems on AMD EPYC CPUs.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
Currently, the APIC ID is decoded based on the sequence
sockets->dies->cores->threads. This works for most standard AMD and other
vendors' configurations, but this decoding sequence does not follow that of
AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
inconsistency. When booting a guest VM, the kernel tries to validate the
topology, and finds it inconsistent with the enumeration of EPYC cpu models.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. It is available at
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
v3:
1. Consolidated the topology information in structure X86CPUTopoInfo.
2. Changed the ccx_id to llc_id as commented by upstream.
3. Generalized the apic id decoding. It is mostly similar to current apic id
except that it adds new field llc_id when numa configured. Removes all the
hardcoded values.
4. Removed the earlier parse_numa split. And moved the numa node
initialization
inside the numa_complete_configuration. This is bit cleaner as commented
by
Eduardo.
5. Added new function init_apicid_fn inside machine_class structure. This
will be used to update the apic id handler specific to cpu model.
6. Updated the cpuid unit tests.
7. TODO : Need to figure out how to dynamically update the handlers using cpu
models.
I might some guidance on that.
v2:
https://lore.kernel.org/qemu-devel/156779689013.21957.1631551572950676212.stgit@localhost.localdomain/
1. Introduced the new property epyc to enable new epyc mode.
2. Separated the epyc mode and non epyc mode function.
3. Introduced function pointers in PCMachineState to handle the
differences.
4. Mildly tested different combinations to make things are working as
expected.
5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
supported only on AMD EPYC models. I may need some guidance on that.
v1:
https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.mo...@amd.com/
---
Babu Moger (18):
hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
hw/i386: Introduce X86CPUTopoInfo to contain topology info
hw/i386: Consolidate topology functions
hw/i386: Introduce initialize_topo_info to initialize X86CPUTopoInfo
machine: Add SMP Sockets in CpuTopology
hw/core: Add core complex id in X86CPU topology
machine: Add a new function init_apicid_fn in MachineClass
hw/i386: Update structures for nodes_per_pkg
i386: Add CPUX86Family type in CPUX86State
hw/386: Add EPYC mode topology decoding functions
i386: Cleanup and use the EPYC mode topology functions
numa: Split the numa initialization
hw/i386: Introduce apicid_from_cpu_idx in PCMachineState
hw/i386: Introduce topo_ids_from_apicid handler PCMachineState
hw/i386: Introduce apic_id_from_topo_ids handler in PCMachineState
hw/i386: Introduce EPYC mode function handlers
i386: Fix pkg_id offset for epyc mode
tests: Update the Unit tests
hw/core/machine-hmp-cmds.c |3 +
hw/core/machine.c | 14 +++
hw/core/numa.c | 62 +
hw/i386/pc.c | 132 +++-
include/hw/boards.h|3 +
include/hw/i386/pc.h |9 ++
include/hw/i386/topology.h | 209 +++-
include/sysemu/numa.h |5 +
qapi/machine.json |7 +
target/i386/cpu.c | 196 -
target/i386/cpu.h |9 ++
tests/test-x86-cpuid.c | 115 ++--
vl.c |4 +
13 files changed, 455 insertions(+), 313 deletions(-)
--
[PATCH v3 01/18] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c | 60 ++--
include/hw/i386/topology.h | 40 +++--
2 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 51b72439b4..5bd2ffccb7 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2212,7 +2212,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
int idx;
CPUState *cs;
CPUArchId *cpu_slot;
-X86CPUTopoInfo topo;
+X86CPUTopoIDs topo_ids;
X86CPU *cpu = X86_CPU(dev);
CPUX86State *env = >env;
MachineState *ms = MACHINE(hotplug_dev);
@@ -2277,12 +2277,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
-topo.pkg_id = cpu->socket_id;
-topo.die_id = cpu->die_id;
-topo.core_id = cpu->core_id;
-topo.smt_id = cpu->thread_id;
+topo_ids.pkg_id = cpu->socket_id;
+topo_ids.die_id = cpu->die_id;
+topo_ids.core_id = cpu->core_id;
+topo_ids.smt_id = cpu->thread_id;
cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
-smp_threads, );
+smp_threads, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
@@ -2290,11 +2290,11 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
MachineState *ms = MACHINE(pcms);
x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
- smp_cores, smp_threads, );
+ smp_cores, smp_threads, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
-topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
+topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id,
topo_ids.smt_id,
cpu->apic_id, ms->possible_cpus->len - 1);
return;
}
@@ -2312,34 +2312,34 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
- smp_cores, smp_threads, );
-if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
+ smp_cores, smp_threads, _ids);
+if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
-" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo.pkg_id);
+" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo_ids.pkg_id);
return;
}
-cpu->socket_id = topo.pkg_id;
+cpu->socket_id = topo_ids.pkg_id;
-if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
+if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
error_setg(errp, "property die-id: %u doesn't match set apic-id:"
-" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
+" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
return;
}
-cpu->die_id = topo.die_id;
+cpu->die_id = topo_ids.die_id;
-if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
+if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
-" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
+" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
topo_ids.core_id);
return;
}
-cpu->core_id = topo.core_id;
+cpu->core_id = topo_ids.core_id;
-if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
+if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
-" 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
topo.smt_id);
+" 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
topo_ids.smt_id);
return;
}
-cpu->thread_id = topo.smt_id;
+cpu->thread_id = topo_ids.smt_id;
if (
[PATCH v3 11/18] i386: Cleanup and use the EPYC mode topology functions
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162 +++--
1 file changed, 35 insertions(+), 127 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5629c6d4c1..e87487bae3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -338,68 +338,15 @@ static void encode_cache_cpuid8006(CPUCacheInfo *l2,
}
}
-/*
- * Definitions used for building CPUID Leaf 0x801D and 0x801E
- * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
- * Define the constants to build the cpu topology. Right now, TOPOEXT
- * feature is enabled only on EPYC. So, these constants are based on
- * EPYC supported configurations. We may need to handle the cases if
- * these values change in future.
- */
-/* Maximum core complexes in a node */
-#define MAX_CCX 2
-/* Maximum cores in a core complex */
-#define MAX_CORES_IN_CCX 4
-/* Maximum cores in a node */
-#define MAX_CORES_IN_NODE 8
-/* Maximum nodes in a socket */
-#define MAX_NODES_PER_SOCKET 4
-
-/*
- * Figure out the number of nodes required to build this config.
- * Max cores in a node is 8
- */
-static int nodes_in_socket(int nr_cores)
-{
-int nodes;
-
-nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
-
- /* Hardware does not support config with 3 nodes, return 4 in that case */
-return (nodes == 3) ? 4 : nodes;
-}
-
-/*
- * Decide the number of cores in a core complex with the given nr_cores using
- * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
- * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
- * L3 cache is shared across all cores in a core complex. So, this will also
- * tell us how many cores are sharing the L3 cache.
- */
-static int cores_in_core_complex(int nr_cores)
-{
-int nodes;
-
-/* Check if we can fit all the cores in one core complex */
-if (nr_cores <= MAX_CORES_IN_CCX) {
-return nr_cores;
-}
-/* Get the number of nodes required to build this config */
-nodes = nodes_in_socket(nr_cores);
-
-/*
- * Divide the cores accros all the core complexes
- * Return rounded up value
- */
-return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
-}
-
/* Encode cache info for CPUID[801D] */
-static void encode_cache_cpuid801d(CPUCacheInfo *cache, CPUState *cs,
-uint32_t *eax, uint32_t *ebx,
-uint32_t *ecx, uint32_t *edx)
+static void encode_cache_cpuid801d(CPUCacheInfo *cache,
+ X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
{
uint32_t l3_cores;
+unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
+
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
@@ -408,10 +355,13 @@ static void encode_cache_cpuid801d(CPUCacheInfo
*cache, CPUState *cs,
/* L3 is shared among multiple cores */
if (cache->level == 3) {
-l3_cores = cores_in_core_complex(cs->nr_cores);
-*eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
+l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
+ topo_info->cores_per_die *
+ topo_info->threads_per_core),
+ nodes);
+*eax |= (l3_cores - 1) << 14;
} else {
-*eax |= ((cs->nr_threads - 1) << 14);
+*eax |= ((topo_info->threads_per_core - 1) << 14);
}
assert(cache->line_size > 0);
@@ -431,55 +381,17 @@ static void encode_cache_cpuid801d(CPUCacheInfo
*cache, CPUState *cs,
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
-/* Data structure to hold the configuration info for a given core index */
-struct core_topology {
-/* core complex id of the current core index */
-int ccx_id;
-/*
- * Adjusted core index for this core in the topology
- * This can be 0,1,2,3 with max 4 cores in a core complex
- */
-int core_id;
-/* Node id for this core index */
-int node_id;
-/* Number of nodes in this config */
-int num_nodes;
-};
-
-/*
- * Build the configuration closely match the EPYC hardware. Using the EPYC
- * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
- * right now. This could change in future.
- * nr_cores : Total number of cores in the config
- * core_id : Core index of the current CPU
- * topo : Data structure to hold all the config info for this core index
- */
-static void build_core_topology(int nr_c
[PATCH v3 14/18] hw/i386: Introduce topo_ids_from_apicid handler PCMachineState
Add function pointer topo_ids_from_apicid in PCMachineState.
Initialize with correct handler based on mode selected.
x86_apicid_from_cpu_idx will be the default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 13 +++--
include/hw/i386/pc.h |2 ++
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 52aea4a652..b0d58515dd 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2312,7 +2312,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
-x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
+pcms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -2333,7 +2333,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
-x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
+pcms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo_ids.pkg_id);
@@ -2681,6 +2681,7 @@ static void pc_machine_initfn(Object *obj)
/* Initialize the apic id related handlers */
pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
+pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid;
pc_system_flash_create(pcms);
}
@@ -2730,8 +2731,8 @@ static int64_t pc_get_default_cpu_node_id(const
MachineState *ms, int idx)
initialize_topo_info(_info, pcms, ms);
assert(idx < ms->possible_cpus->len);
- x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
-_info, _ids);
+ pcms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
+ _info, _ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
@@ -2763,8 +2764,8 @@ static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].type = ms->cpu_type;
ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms,
i);
-x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- _info, _ids);
+pcms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
+ _info, _ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
if (pcms->smp_dies > 1) {
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 56aa0e45b5..ffc5c78164 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -71,6 +71,8 @@ struct PCMachineState {
/* Apic id specific handlers */
uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
unsigned cpu_index);
+void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
+ X86CPUTopoIDs *topo_ids);
/* Address space used by IOAPIC device. All IOAPIC interrupts
* will be translated to MSI messages in the address space. */
[PATCH v3 18/18] tests: Update the Unit tests
Since the topology routines have changed, update
the unit tests to use the new APIs.
Signed-off-by: Babu Moger
---
tests/test-x86-cpuid.c | 115
1 file changed, 68 insertions(+), 47 deletions(-)
diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c
index 1942287f33..00553c1d77 100644
--- a/tests/test-x86-cpuid.c
+++ b/tests/test-x86-cpuid.c
@@ -28,79 +28,100 @@
static void test_topo_bits(void)
{
+X86CPUTopoInfo topo_info = {0};
+
/* simple tests for 1 thread per core, 1 core per die, 1 die per package */
-g_assert_cmpuint(apicid_smt_width(1, 1, 1), ==, 0);
-g_assert_cmpuint(apicid_core_width(1, 1, 1), ==, 0);
-g_assert_cmpuint(apicid_die_width(1, 1, 1), ==, 0);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 1};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 0);
+g_assert_cmpuint(apicid_core_width(_info), ==, 0);
+g_assert_cmpuint(apicid_die_width(_info), ==, 0);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), ==, 0);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), ==, 1);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), ==, 2);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), ==, 3);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 0), ==, 0);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 1), ==, 1);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 2), ==, 2);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 3), ==, 3);
/* Test field width calculation for multiple values
*/
-g_assert_cmpuint(apicid_smt_width(1, 1, 2), ==, 1);
-g_assert_cmpuint(apicid_smt_width(1, 1, 3), ==, 2);
-g_assert_cmpuint(apicid_smt_width(1, 1, 4), ==, 2);
-
-g_assert_cmpuint(apicid_smt_width(1, 1, 14), ==, 4);
-g_assert_cmpuint(apicid_smt_width(1, 1, 15), ==, 4);
-g_assert_cmpuint(apicid_smt_width(1, 1, 16), ==, 4);
-g_assert_cmpuint(apicid_smt_width(1, 1, 17), ==, 5);
-
-
-g_assert_cmpuint(apicid_core_width(1, 30, 2), ==, 5);
-g_assert_cmpuint(apicid_core_width(1, 31, 2), ==, 5);
-g_assert_cmpuint(apicid_core_width(1, 32, 2), ==, 5);
-g_assert_cmpuint(apicid_core_width(1, 33, 2), ==, 6);
-
-g_assert_cmpuint(apicid_die_width(1, 30, 2), ==, 0);
-g_assert_cmpuint(apicid_die_width(2, 30, 2), ==, 1);
-g_assert_cmpuint(apicid_die_width(3, 30, 2), ==, 2);
-g_assert_cmpuint(apicid_die_width(4, 30, 2), ==, 2);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 2};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 1);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 3};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 2);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 4};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 2);
+
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 14};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 4);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 15};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 4);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 16};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 4);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 17};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 5);
+
+
+topo_info = (X86CPUTopoInfo) {0, 1, 30, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 5);
+topo_info = (X86CPUTopoInfo) {0, 1, 31, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 5);
+topo_info = (X86CPUTopoInfo) {0, 1, 32, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 5);
+topo_info = (X86CPUTopoInfo) {0, 1, 33, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 6);
+
+topo_info = (X86CPUTopoInfo) {0, 1, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 0);
+topo_info = (X86CPUTopoInfo) {0, 2, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 1);
+topo_info = (X86CPUTopoInfo) {0, 3, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 2);
+topo_info = (X86CPUTopoInfo) {0, 4, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 2);
/* build a weird topology and see if IDs are calculated correctly
*/
/* This will use 2 bits for thread ID and 3 bits for core ID
*/
-g_assert_cmpuint(apicid_smt_width(1, 6, 3), ==, 2);
-g_assert_cmpuint(apicid_core_offset(1, 6, 3), ==, 2);
-g_assert_cmpuint(apicid_die_offset(1, 6, 3), ==, 5);
-g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), ==, 5);
-
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), ==, 0);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), ==, 1);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), ==, 2);
-
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), ==,
+topo_info = (X86CPUTopoInfo) {0, 1, 6, 3};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 2);
+g_assert_cmpuint(apicid_core_offset(_info), ==, 2);
+g_assert_cmpuint(apicid_die_offset(_info), ==, 5);
+g_assert_cmpuint(apicid_pkg_offset(_info), ==, 5);
+
+topo_info = (X86CPUTopoInfo) {0, 1
[PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass
Add a new function init_apicid_fn in MachineClass to initialize the mode
specific handlers to decode the apic ids.
Signed-off-by: Babu Moger
---
include/hw/boards.h |1 +
vl.c|3 +++
2 files changed, 4 insertions(+)
diff --git a/include/hw/boards.h b/include/hw/boards.h
index d4fab218e6..ce5aa365cb 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -238,6 +238,7 @@ struct MachineClass {
unsigned cpu_index);
const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine);
int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx);
+void (*init_apicid_fn)(MachineState *ms);
};
/**
diff --git a/vl.c b/vl.c
index a42c24a77f..b6af604e11 100644
--- a/vl.c
+++ b/vl.c
@@ -4318,6 +4318,9 @@ int main(int argc, char **argv, char **envp)
current_machine->cpu_type = machine_class->default_cpu_type;
if (cpu_option) {
current_machine->cpu_type = parse_cpu_option(cpu_option);
+if (machine_class->init_apicid_fn) {
+machine_class->init_apicid_fn(current_machine);
+}
}
parse_numa_opts(current_machine);
[PATCH v3 04/18] hw/i386: Introduce initialize_topo_info to initialize X86CPUTopoInfo
Initialize all the parameters in one function initialize_topo_info.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 8c23b1e8c9..cafbdafa76 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -866,6 +866,15 @@ static void handle_a20_line_change(void *opaque, int irq,
int level)
x86_cpu_set_a20(cpu, level);
}
+static inline void initialize_topo_info(X86CPUTopoInfo *topo_info,
+PCMachineState *pcms,
+const MachineState *ms)
+{
+topo_info->dies_per_pkg = pcms->smp_dies;
+topo_info->cores_per_die = ms->smp.cores;
+topo_info->threads_per_core = ms->smp.threads;
+}
+
/* Calculates initial APIC ID for a specific CPU index
*
* Currently we need to be able to calculate the APIC ID from the CPU index
@@ -882,9 +891,7 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState
*pcms,
uint32_t correct_id;
static bool warned;
-topo_info.dies_per_pkg = pcms->smp_dies;
-topo_info.cores_per_die = ms->smp.cores;
-topo_info.threads_per_core = ms->smp.threads;
+initialize_topo_info(_info, pcms, ms);
correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
if (pcmc->compat_apic_id_mode) {
@@ -2231,9 +2238,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
-topo_info.dies_per_pkg = pcms->smp_dies;
-topo_info.cores_per_die = smp_cores;
-topo_info.threads_per_core = smp_threads;
+initialize_topo_info(_info, pcms, ms);
env->nr_dies = pcms->smp_dies;
@@ -2702,9 +2707,7 @@ static int64_t pc_get_default_cpu_node_id(const
MachineState *ms, int idx)
PCMachineState *pcms = PC_MACHINE(ms);
X86CPUTopoInfo topo_info;
- topo_info.dies_per_pkg = pcms->smp_dies;
- topo_info.cores_per_die = ms->smp.cores;
- topo_info.threads_per_core = ms->smp.threads;
+ initialize_topo_info(_info, pcms, ms);
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
@@ -2719,10 +2722,6 @@ static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState *ms)
X86CPUTopoInfo topo_info;
int i;
-topo_info.dies_per_pkg = pcms->smp_dies;
-topo_info.cores_per_die = ms->smp.cores;
-topo_info.threads_per_core = ms->smp.threads;
-
if (ms->possible_cpus) {
/*
* make sure that max_cpus hasn't changed since the first use, i.e.
@@ -2734,6 +2733,9 @@ static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
sizeof(CPUArchId) * max_cpus);
+
+initialize_topo_info(_info, pcms, ms);
+
ms->possible_cpus->len = max_cpus;
for (i = 0; i < ms->possible_cpus->len; i++) {
X86CPUTopoIDs topo_ids;
[PATCH v3 09/18] i386: Add CPUX86Family type in CPUX86State
Add CPUX86Family type in CPUX86State. This will be used to differentiate
generic x86 and x86 EPYC based cpu models.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |4
target/i386/cpu.c |1 +
target/i386/cpu.h |7 +++
3 files changed, 12 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 5dc11df922..7f30104a6b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1398,6 +1398,8 @@ static void pc_new_cpu(PCMachineState *pcms, int64_t
apic_id, Error **errp)
env = _CPU(cpu)->env;
env->nr_dies = pcms->smp_dies;
env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
+env->family_type = strncmp(ms->cpu_type, "EPYC", 4) ? CPUX86FAMILY_DEFAULT
:
+ CPUX86FAMILY_EPYC;
object_property_set_uint(cpu, apic_id, "apic-id", _err);
object_property_set_bool(cpu, true, "realized", _err);
@@ -2246,6 +2248,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
env->nr_dies = pcms->smp_dies;
env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
+env->family_type = strncmp(ms->cpu_type, "EPYC", 4) ? CPUX86FAMILY_DEFAULT
:
+ CPUX86FAMILY_EPYC;
/*
* If APIC ID is not set,
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9b2608a4c8..5629c6d4c1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5997,6 +5997,7 @@ static void x86_cpu_initfn(Object *obj)
env->nr_dies = 1;
env->nr_nodes = 1;
+env->family_type = CPUX86FAMILY_DEFAULT;
cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "family", "int",
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0ef4fdb55f..105744430b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1284,6 +1284,11 @@ typedef enum TPRAccess {
TPR_ACCESS_WRITE,
} TPRAccess;
+typedef enum CPUX86Family {
+CPUX86FAMILY_DEFAULT = 0,
+CPUX86FAMILY_EPYC,
+} CPUX86Family;
+
/* Cache information data structures: */
enum CacheType {
@@ -1590,6 +1595,8 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
+CPUX86Family family_type;
+
unsigned nr_dies;
unsigned nr_nodes;
} CPUX86State;
[PATCH v3 12/18] numa: Split the numa initialization
To generate the apic id for EPYC cpu models correctly, we need to know the
number of numa nodes in advance. At present numa node initialization and cpu
initialization happens at the same time. Apic id generation happens during the
cpu initialization. At this point it is not known how many numa nodes are
configured. So, save the cpu indexes and move the cpu initialization inside the
numa_complete_configuration. Cpu initialization is done in new function
numa_node_complete_configuration.
Signed-off-by: Babu Moger
---
hw/core/numa.c| 62 -
include/sysemu/numa.h |5
2 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 038c96d4ab..ba02a41421 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -33,6 +33,7 @@
#include "qapi/error.h"
#include "qapi/opts-visitor.h"
#include "qapi/qapi-visit-machine.h"
+#include "qapi/clone-visitor.h"
#include "sysemu/qtest.h"
#include "hw/core/cpu.h"
#include "hw/mem/pc-dimm.h"
@@ -59,11 +60,8 @@ static int max_numa_nodeid; /* Highest specified NUMA node
ID, plus one.
static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
Error **errp)
{
-Error *err = NULL;
uint16_t nodenr;
-uint16List *cpus = NULL;
MachineClass *mc = MACHINE_GET_CLASS(ms);
-unsigned int max_cpus = ms->smp.max_cpus;
NodeInfo *numa_info = ms->numa_state->nodes;
if (node->has_nodeid) {
@@ -87,24 +85,8 @@ static void parse_numa_node(MachineState *ms,
NumaNodeOptions *node,
error_setg(errp, "NUMA is not supported by this machine-type");
return;
}
-for (cpus = node->cpus; cpus; cpus = cpus->next) {
-CpuInstanceProperties props;
-if (cpus->value >= max_cpus) {
-error_setg(errp,
- "CPU index (%" PRIu16 ")"
- " should be smaller than maxcpus (%d)",
- cpus->value, max_cpus);
-return;
-}
-props = mc->cpu_index_to_instance_props(ms, cpus->value);
-props.node_id = nodenr;
-props.has_node_id = true;
-machine_set_cpu_numa_node(ms, , );
-if (err) {
-error_propagate(errp, err);
-return;
-}
-}
+
+numa_info[nodenr].cpu_indexes = QAPI_CLONE(uint16List, node->cpus);
have_memdevs = have_memdevs ? : node->has_memdev;
have_mem = have_mem ? : node->has_mem;
@@ -360,12 +342,50 @@ void numa_default_auto_assign_ram(MachineClass *mc,
NodeInfo *nodes,
nodes[i].node_mem = size - usedmem;
}
+
+void numa_node_complete_configuration(MachineState *ms, NodeInfo *node,
+ uint16_t nodenr)
+{
+Error *err = NULL;
+uint16List *cpus = NULL;
+MachineClass *mc = MACHINE_GET_CLASS(ms);
+unsigned int max_cpus = ms->smp.max_cpus;
+
+for (cpus = node->cpu_indexes; cpus; cpus = cpus->next) {
+CpuInstanceProperties props;
+if (cpus->value >= max_cpus) {
+error_report("CPU index (%" PRIu16 ")"
+ " should be smaller than maxcpus (%d)",
+ cpus->value, max_cpus);
+return;
+}
+props = mc->cpu_index_to_instance_props(ms, cpus->value);
+props.node_id = nodenr;
+props.has_node_id = true;
+machine_set_cpu_numa_node(ms, , );
+if (err) {
+error_report("Numa node initialization failed");
+return;
+}
+}
+}
+
void numa_complete_configuration(MachineState *ms)
{
int i;
MachineClass *mc = MACHINE_GET_CLASS(ms);
NodeInfo *numa_info = ms->numa_state->nodes;
+for (i = 0; i < ms->numa_state->num_nodes; i++) {
+/*
+ * numa_node_complete_configuration() needs to be called after all
+ * nodes were already parsed, because to support new epyc mode, we
+ * need to know the number of numa nodes in advance to generate
+ * apic id correctly.
+ */
+numa_node_complete_configuration(ms, _info[i], i);
+}
+
/*
* If memory hotplug is enabled (slots > 0) but without '-numa'
* options explicitly on CLI, guestes will break.
diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index ae9c41d02b..91794d685f 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -19,6 +19,9 @@ struct NodeInfo {
struct HostMemoryBackend *node_memdev;
bool present;
uint8_t distance[MAX_NODES];
+
+/* These indexes are saved for numa node initialization later */
+uint16List *cpu_indexes;
};
struct NumaNodeMem {
@@ -41,6 +44,8 @@ typedef struct NumaState NumaState;
void se
[PATCH v3 08/18] hw/i386: Update structures for nodes_per_pkg
Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg. This
is required to build EPYC mode topology.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |4
include/hw/i386/topology.h |1 +
target/i386/cpu.c |1 +
target/i386/cpu.h |1 +
4 files changed, 7 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index df5339c102..5dc11df922 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -870,6 +870,7 @@ static inline void initialize_topo_info(X86CPUTopoInfo
*topo_info,
PCMachineState *pcms,
const MachineState *ms)
{
+topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
topo_info->dies_per_pkg = pcms->smp_dies;
topo_info->cores_per_die = ms->smp.cores;
topo_info->threads_per_core = ms->smp.threads;
@@ -1390,11 +1391,13 @@ static void pc_new_cpu(PCMachineState *pcms, int64_t
apic_id, Error **errp)
Object *cpu = NULL;
Error *local_err = NULL;
CPUX86State *env = NULL;
+MachineState *ms = MACHINE(pcms);
cpu = object_new(MACHINE(pcms)->cpu_type);
env = _CPU(cpu)->env;
env->nr_dies = pcms->smp_dies;
+env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
object_property_set_uint(cpu, apic_id, "apic-id", _err);
object_property_set_bool(cpu, true, "realized", _err);
@@ -2242,6 +2245,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
initialize_topo_info(_info, pcms, ms);
env->nr_dies = pcms->smp_dies;
+env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
/*
* If APIC ID is not set,
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 1238006208..cfb09312fe 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -54,6 +54,7 @@ typedef struct X86CPUTopoIDs {
} X86CPUTopoIDs;
typedef struct X86CPUTopoInfo {
+unsigned nodes_per_pkg;
unsigned dies_per_pkg;
unsigned cores_per_die;
unsigned threads_per_core;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3c81aa3ecd..9b2608a4c8 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5996,6 +5996,7 @@ static void x86_cpu_initfn(Object *obj)
FeatureWord w;
env->nr_dies = 1;
+env->nr_nodes = 1;
cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "family", "int",
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a56d44e405..0ef4fdb55f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1591,6 +1591,7 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
unsigned nr_dies;
+unsigned nr_nodes;
} CPUX86State;
struct kvm_msrs;
[PATCH v3 05/18] machine: Add SMP Sockets in CpuTopology
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/core/machine.c |1 +
hw/i386/pc.c|1 +
include/hw/boards.h |2 ++
vl.c|1 +
4 files changed, 5 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 1689ad3bf8..e59b181ead 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -784,6 +784,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ms->smp.sockets = sockets;
}
if (ms->smp.cpus > 1) {
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index cafbdafa76..17de152a77 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1473,6 +1473,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ms->smp.sockets = sockets;
pcms->smp_dies = dies;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index de45087f34..d4fab218e6 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -256,12 +256,14 @@ typedef struct DeviceMemoryState {
* @cpus: the number of present logical processors on the machine
* @cores: the number of cores in one package
* @threads: the number of threads in one core
+ * @sockets: the number of sockets on the machine
* @max_cpus: the maximum number of logical processors on the machine
*/
typedef struct CpuTopology {
unsigned int cpus;
unsigned int cores;
unsigned int threads;
+unsigned int sockets;
unsigned int max_cpus;
} CpuTopology;
diff --git a/vl.c b/vl.c
index 4489cfb2bb..a42c24a77f 100644
--- a/vl.c
+++ b/vl.c
@@ -3962,6 +3962,7 @@ int main(int argc, char **argv, char **envp)
current_machine->smp.max_cpus = machine_class->default_cpus;
current_machine->smp.cores = 1;
current_machine->smp.threads = 1;
+current_machine->smp.sockets = 1;
machine_class->smp_parse(current_machine,
qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
Re: [Qemu-devel] [RFC 2 PATCH 03/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info
On 10/10/19 9:29 PM, Eduardo Habkost wrote:
> On Fri, Sep 06, 2019 at 07:11:57PM +, Moger, Babu wrote:
>> This is an effort to re-arrange few data structure for better
>> readability. Add X86CPUTopoInfo which will have all the topology
>> informations required to build the cpu topology. There is no
>> functional changes.
>>
>> Signed-off-by: Babu Moger
>> ---
>> hw/i386/pc.c | 40 +++-
>> include/hw/i386/topology.h | 40 ++--
>> 2 files changed, 53 insertions(+), 27 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index ada445f8f3..95aab8e5e7 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -930,11 +930,15 @@ static uint32_t
>> x86_cpu_apic_id_from_index(PCMachineState *pcms,
>> {
>> MachineState *ms = MACHINE(pcms);
>> PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
>> +X86CPUTopoInfo topo_info;
>> uint32_t correct_id;
>> static bool warned;
>>
>> -correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
>> - ms->smp.threads, cpu_index);
>> +topo_info.nr_dies = pcms->smp_dies;
>> +topo_info.nr_cores = ms->smp.cores;
>> +topo_info.nr_threads = ms->smp.threads;
>> +
>> +correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
>
> If you are using the struct in function calls, please make sure
> all fields are filled correctly, so we won't introduce bugs
> accidentally if we start using the new fields inside the topology
> functions.
>
> Alternatively, you can leave the struct without the numa_nodes
> and nr_sockets fields by now (because they are unused), and add
> the fields in another patch.
Yes. Separated the patches and added the new fields separately.
>
> Except for this, the patch looks good. However, I don't
> understand yet the use case for the `numa_nodes` field yet. I
> will probably comment on the `numa_nodes` field once I see the
> patches that use the new field.
>
Re: [Qemu-devel] [RFC 2 PATCH 03/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info
On 10/10/19 10:54 PM, Eduardo Habkost wrote:
> On Fri, Sep 06, 2019 at 07:11:57PM +, Moger, Babu wrote:
>> This is an effort to re-arrange few data structure for better
>> readability. Add X86CPUTopoInfo which will have all the topology
>> informations required to build the cpu topology. There is no
>> functional changes.
>>
>> Signed-off-by: Babu Moger
>> ---
> [...]
>> +typedef struct X86CPUTopoInfo {
>> +unsigned numa_nodes;
>> +unsigned nr_sockets;
>> +unsigned nr_dies;
>> +unsigned nr_cores;
>> +unsigned nr_threads;
>> +} X86CPUTopoInfo;
>
> With more complex topologies, the meaning of each of those fields
> may be ambiguous. e.g.: is nr_cores cores per die, cores per
> ccx, or cores per socket? Maybe we should use this opportunity
> to use more explicit names like threads_per_core, cores_per_die,
> dies_per_socket.
Yes. Changed it to
typedef struct X86CPUTopoInfo {
unsigned nodes_per_pkg;
unsigned dies_per_pkg;
unsigned cores_per_die;
unsigned threads_per_core;
} X86CPUTopoInfo;
Re: [Qemu-devel] [RFC 2 PATCH 16/16] hw/core: Fix up the machine_set_cpu_numa_node for epyc
On 10/10/19 11:10 PM, Eduardo Habkost wrote:
> On Fri, Sep 06, 2019 at 07:13:29PM +, Moger, Babu wrote:
>> Current topology id match will not work for epyc mode when setting
>> the node id. In epyc mode, ids like smt_id, thread_id, core_id,
>> ccx_id, socket_id can be same for more than one CPUs with across
>> two numa nodes.
>>
>> For example, we can have two CPUs with following ids on two different node.
>> 1. smt_id=0, thread_id=0, core_id=0, ccx_id=0, socket_id=0, node_id=0
>> 2. smt_id=0, thread_id=0, core_id=0, ccx_id=0, socket_id=0, node_id=1
>
> I don't understand how that could happen. If all IDs are the
> same, how is it possible that those two cases should match two
> different CPUs?
>
> cpu_index_to_instance_props() must always return an unique
> identifier for a single CPU.
Simplified apic id decoding in v3 version. We don't need these changes
anymore.
>
>>
>> The function machine_set_cpu_numa_node will fail to find a match to assign
>> the node. Added new function machine_set_cpu_numa_node_epyc to set the
>> node_id
>> directly in epyc mode.
>>
>> Signed-off-by: Babu Moger
>> ---
>> hw/core/machine.c | 24
>> hw/core/numa.c |6 +-
>> include/hw/boards.h |4
>> 3 files changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/core/machine.c b/hw/core/machine.c
>> index 9a8586cf30..6bceefc6f3 100644
>> --- a/hw/core/machine.c
>> +++ b/hw/core/machine.c
>> @@ -741,6 +741,30 @@ void machine_set_cpu_numa_node(MachineState *machine,
>> }
>> }
>>
>> +void machine_set_cpu_numa_node_epyc(MachineState *machine,
>> +const CpuInstanceProperties *props,
>> +unsigned index,
>> +Error **errp)
>> +{
>> +MachineClass *mc = MACHINE_GET_CLASS(machine);
>> +CPUArchId *slot;
>> +
>> +if (!mc->possible_cpu_arch_ids) {
>> +error_setg(errp, "mapping of CPUs to NUMA node is not supported");
>> +return;
>> +}
>> +
>> +/* disabling node mapping is not supported, forbid it */
>> +assert(props->has_node_id);
>> +
>> +/* force board to initialize possible_cpus if it hasn't been done yet */
>> +mc->possible_cpu_arch_ids(machine);
>> +
>> +slot = >possible_cpus->cpus[index];
>> +slot->props.node_id = props->node_id;
>> +slot->props.has_node_id = props->has_node_id;
>> +}
>> +
>> static void smp_parse(MachineState *ms, QemuOpts *opts)
>> {
>> if (opts) {
>> diff --git a/hw/core/numa.c b/hw/core/numa.c
>> index 27fa6b5e1d..a9e835aea6 100644
>> --- a/hw/core/numa.c
>> +++ b/hw/core/numa.c
>> @@ -247,7 +247,11 @@ void set_numa_node_options(MachineState *ms,
>> NumaOptions *object, Error **errp)
>> props = mc->cpu_index_to_instance_props(ms, cpus->value);
>> props.node_id = nodenr;
>> props.has_node_id = true;
>> - machine_set_cpu_numa_node(ms, , );
>> + if (ms->epyc) {
>> + machine_set_cpu_numa_node_epyc(ms, , cpus->value, );
>> + } else {
>> + machine_set_cpu_numa_node(ms, , );
>> + }
>> if (err) {
>> error_propagate(errp, err);
>> return;
>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>> index 0001d42e50..ec1b1c5a85 100644
>> --- a/include/hw/boards.h
>> +++ b/include/hw/boards.h
>> @@ -74,6 +74,10 @@ HotpluggableCPUList
>> *machine_query_hotpluggable_cpus(MachineState *machine);
>> void machine_set_cpu_numa_node(MachineState *machine,
>> const CpuInstanceProperties *props,
>> Error **errp);
>> +void machine_set_cpu_numa_node_epyc(MachineState *machine,
>> +const CpuInstanceProperties *props,
>> +unsigned index,
>> +Error **errp);
>>
>> void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char
>> *type);
>>
>>
>
Re: [Qemu-devel] [RFC 2 PATCH 01/16] numa: Split the numa functionality
Eduardo,
Sorry taking time to respond to your comments earlier. Started working on
something else so it took a while to come back.
Working on v3 right now and taken care most of your comments on v2. Will
plan to submit v3 sometime this week.
On 10/9/19 10:25 PM, Eduardo Habkost wrote:
> Hi,
>
> First of all, sorry for taking more than a month to start
> reviewing this.
>
> On Fri, Sep 06, 2019 at 07:11:43PM +, Moger, Babu wrote:
>> To support new epyc mode, we need to know the number of numa nodes
>> in advance to generate apic id correctly. [...]
>
> This explains that we need to initialize numa_info earlier than
> something...
>
>> [...] So, split the numa
>> initialization into two. The function parse_numa initializes numa_info
>> and updates nb_numa_nodes. And then parse_numa_node does the numa node
>> initialization.
>
> ...but I miss what "something" is.
>
> The sequence of events here will be:
>
> * parse_numa_opts()
> * for each -numa option:
> * parse_numa()
> * set_numa_options()
> * parse_numa_info()
> * here ms->numa_state->num_nodes is incremented [1]
> * parse_numa_node_opts()
> * for each -numa option:
> * parse_numa_node()
> * set_numa_node_options()
> * here are the operations that are being delayed by this
> patch [2]
>
> What exactly makes it necessary for [2] to happen after [1] is
> done for all NUMA nodes?
We dont need these changes anymore. Look at my comments below.
>
> This needs to be clear in the code, otherwise somebody will try to refactor
> this in the future and merge set_numa_node_options() and parse_numa_info()
> again, not knowing why ordering between [1] and [2] is so important.
>
> In addition to documenting it better, I suggest saving the CPU
> index list in NodeInfo, instead of calling qemu_opts_foreach()
> twice. (Probably a good idea to document the new field as
> internal, though. We don't want machine-specific code to be
> looking at the CPU index list.)
>
> Also, would it work if the delayed initialization is done at
> numa_complete_configuration() instead of a new
> parse_numa_node_opts() function? We already have 2 separate
> steps in NUMA initialization (parse_numa_node() and
> numa_complete_configuration()), so it would be nice to avoid
> adding a 3rd one.
>
> Putting all the suggestions together, the code would look like this:
>
>
> static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
> Error **errp)
> {
> /* ... */
> numa_info[nodenr].cpu_indexes = QAPI_CLONE(node->cpus, uint16List);
> /* ... */
> }
>
> void numa_complete_configuration(MachineState *ms)
> {
> /* ... */
> for (i = 0; i < ms->numa_state->num_nodes; i++) {
> /*
> * numa_node_complete_configuration() needs to be called after all
> * nodes were already parsed, because ,
> */
> numa_node_complete_configuration(numa_info[i]);
> }
> }
>
> void numa_node_complete_configuration(MachineState *ms, NodeInfo *node)
> {
> for (cpu_index = node->cpu_indexes; cpu_index; cpu_index =
> cpu_index->next) {
> CpuInstanceProperties props;
> props = mc->cpu_index_to_instance_props(ms, cpu_index->value);
> props.node_id = nodenr;
> props.has_node_id = true;
> machine_set_cpu_numa_node(ms, , );
> }
> }
Yes. I this works fine. Also makes the code simple. Only requirement was
to know the number of numa nodes in advance. Thanks
>
>
>>
>> Signed-off-by: Babu Moger
>> ---
>> hw/core/numa.c| 106
>> +++--
>> include/sysemu/numa.h |2 +
>> vl.c |2 +
>> 3 files changed, 80 insertions(+), 30 deletions(-)
>>
>> diff --git a/hw/core/numa.c b/hw/core/numa.c
>> index a11431483c..27fa6b5e1d 100644
>> --- a/hw/core/numa.c
>> +++ b/hw/core/numa.c
>> @@ -55,14 +55,10 @@ bool have_numa_distance;
>> NodeInfo numa_info[MAX_NODES];
>>
>>
>> -static void parse_numa_node(MachineState *ms, NumaNodeOptions *node,
>> +static void parse_numa_info(MachineState *ms, NumaNodeOptions *node,
>> Error **errp)
>> {
>> -Error *err = NULL;
>> uint16_t nodenr;
>> -uint16List *cpus = NULL;
>> -MachineClass *mc = MACHINE_GET_CLASS(ms);
>> -unsigned int max_cpus = ms->smp.max_cpus;
>>
>> if (node->has_nodeid) {
>> noden
Re: [Qemu-devel] [RFC 2 PATCH 05/16] hw/i386: Simplify topology Offset/width Calculation
On 10/10/19 9:32 PM, Eduardo Habkost wrote: > On Fri, Sep 06, 2019 at 07:12:11PM +, Moger, Babu wrote: >> Some parameters are unnecessarily passed for offset/width >> calculation. Remove those parameters from function prototypes. >> No functional change. >> >> Signed-off-by: Babu Moger > > Isn't it simpler to use the new X86CPUTopoInfo struct, to make > hard-to-spot mistakes less likely when calling those functions? > Yes. Passed X86CPUTopoInfo for all the offset and width calculation.
Re: [Qemu-devel] [RFC 2 PATCH 07/16] hw/386: Add new epyc mode topology decoding functions
On 10/10/19 10:29 PM, Eduardo Habkost wrote:
> On Fri, Sep 06, 2019 at 07:12:25PM +, Moger, Babu wrote:
>> These functions add support for building new epyc mode topology
>> given smp details like numa nodes, cores, threads and sockets.
>> Subsequent patches will use these functions to build the topology.
>>
>> The topology details are available in Processor Programming Reference (PPR)
>> for AMD Family 17h Model 01h, Revision B1 Processors.
>> It is available at https://www.amd.com/en/support/tech-docs
>>
>> Signed-off-by: Babu Moger
>> ---
>> include/hw/i386/topology.h | 174
>>
>> 1 file changed, 174 insertions(+)
>>
>> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
>> index 5a61d53f05..6fd4184f07 100644
>> --- a/include/hw/i386/topology.h
>> +++ b/include/hw/i386/topology.h
>> @@ -62,6 +62,22 @@ typedef struct X86CPUTopoInfo {
>> unsigned nr_threads;
>> } X86CPUTopoInfo;
>>
>> +/*
>> + * Definitions used for building CPUID Leaf 0x801D and 0x801E
>> + * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
>> + * Define the constants to build the cpu topology. Right now, TOPOEXT
>> + * feature is enabled only on EPYC. So, these constants are based on
>> + * EPYC supported configurations. We may need to handle the cases if
>> + * these values change in future.
>> + */
>> +
>> +/* Maximum core complexes in a node */
>> +#define MAX_CCX 2
>
> I suggest a more explicit name like MAX_CCX_IN_NODE.
>
>> +/* Maximum cores in a core complex */
>> +#define MAX_CORES_IN_CCX 4
>> +/* Maximum cores in a node */
>> +#define MAX_CORES_IN_NODE8
>> +
>
> Having limits isn't necessarily bad, but if we look at the code
> that use those constants below:
>
> [...]
>> +/*
>> + * Figure out the number of nodes required to build this config.
>> + * Max cores in a nodes is 8
>> + */
>> +static inline int nodes_in_pkg(X86CPUTopoInfo *topo_info)
>> +{
>> +/*
>> + * Create a config with user given (nr_nodes > 1) numa node config,
>> + * else go with a standard configuration
>> + */
>> +if (topo_info->numa_nodes > 1) {
>> +return DIV_ROUND_UP(topo_info->numa_nodes, topo_info->nr_sockets);
>> +} else {
>> +return DIV_ROUND_UP(topo_info->nr_cores, MAX_CORES_IN_NODE);
>> +}
>> +}
>
> Here we are trying to choose a default value for the number of
> nodes, but it's better to let the CPU or machine code choose it.
> Otherwise, this will be very painful to maintain if new CPUs with
> different limits appear. I would just let the number of nodes
> per package to be configurable in the command-line.
>
>> +
>> +/*
>> + * Decide the number of cores in a core complex with the given nr_cores
>> using
>> + * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_DIE and
>> + * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
>> + * L3 cache is shared across all cores in a core complex. So, this will also
>> + * tell us how many cores are sharing the L3 cache.
>> + */
>> +static inline int cores_in_ccx(X86CPUTopoInfo *topo_info)
>> +{
>> +int nodes;
>> +
>> +/* Get the number of nodes required to build this config */
>> +nodes = nodes_in_pkg(topo_info);
>> +
>> +/*
>> + * Divide the cores accros all the core complexes
>> + * Return rounded up value
>> + */
>> +return DIV_ROUND_UP(topo_info->nr_cores, nodes * MAX_CCX);
>> +}
>
> Same here. This will become painful to maintain if CPUs with a
> different CCX-per-node limit appear. I suggest just letting the
> number of cores per CCX to be configurable in the command-line.
> The "cores" option is already defined as "cores per die" when
> nr_dies > 1. We can easily define it to mean "cores per CCX"
> when nr_ccxs > 1.
>
> If you still want to impose limits to some of those parameters, I
> suggest placing those limits in the CPU model table, not in
> global constants.
>
>
>> +
>> +/*
>> + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
>> + *
>> + * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
>> + */
>> +static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo
>> *topo_info,
>> + con
[Bug 1856335] Re: Cache Layout wrong on many Zen Arch CPUs
Damir,
We normally test Linux guests here. Can you please give me exact qemu command
line. Even the SMP parameters(sockets,cores,threads,dies) will also work. I
will try to recreate it locally first.
Give me example what works and what does not work.
I have recently sent few more patches to fix another bug. Please check if this
makes any difference.
https://patchwork.kernel.org/cover/11272063/
https://lore.kernel.org/qemu-devel/157541968844.46157.17994918142533791313.st...@naples-babu.amd.com/
This should apply cleanly on git://github.com/ehabkost/qemu.git (branch
x86-next)
Note: I will be on vacation until first week of Jan. Responses will be
delayed.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1856335
Title:
Cache Layout wrong on many Zen Arch CPUs
Status in QEMU:
New
Bug description:
AMD CPUs have L3 cache per 2, 3 or 4 cores. Currently, TOPOEXT seems
to always map Cache ass if it was an 4-Core per CCX CPU, which is
incorrect, and costs upwards 30% performance (more realistically 10%)
in L3 Cache Layout aware applications.
Example on a 4-CCX CPU (1950X /w 8 Cores and no SMT):
EPYC-IBPB
AMD
In windows, coreinfo reports correctly:
Unified Cache 1, Level 3,8 MB, Assoc 16, LineSize 64
Unified Cache 6, Level 3,8 MB, Assoc 16, LineSize 64
On a 3-CCX CPU (3960X /w 6 cores and no SMT):
EPYC-IBPB
AMD
in windows, coreinfo reports incorrectly:
-- Unified Cache 1, Level 3,8 MB, Assoc 16, LineSize 64
** Unified Cache 6, Level 3,8 MB, Assoc 16, LineSize 64
Validated against 3.0, 3.1, 4.1 and 4.2 versions of qemu-kvm.
With newer Qemu there is a fix (that does behave correctly) in using the dies
parameter:
The problem is that the dies are exposed differently than how AMD does
it natively, they are exposed to Windows as sockets, which means, that
if you are nto a business user, you can't ever have a machine with
more than two CCX (6 cores) as consumer versions of Windows only
supports two sockets. (Should this be reported as a separate bug?)
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1856335/+subscriptions
[PATCH v4 14/16] hw/i386: Move arch_id decode inside x86_cpus_init
Apicid calculation depends on knowing the total number of numa nodes
for EPYC cpu models. Right now, we are calculating the arch_id while
parsing the numa(parse_numa). At this time, it is not known how many
total numa nodes are configured in the system.
Move the arch_id inside x86_cpus_init. At this time smp parameter is already
completed and numa node information is available.
Signed-off-by: Babu Moger
---
hw/i386/x86.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index b825861b85..472dc3eb77 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -127,6 +127,9 @@ void x86_cpus_init(X86MachineState *x86ms, int
default_cpu_version)
MachineState *ms = MACHINE(x86ms);
MachineClass *mc = MACHINE_GET_CLASS(x86ms);
+/* Initialize apicid handlers first */
+x86_check_apicid_handlers(ms);
+
x86_cpu_set_default_version(default_cpu_version);
/*
@@ -140,6 +143,11 @@ void x86_cpus_init(X86MachineState *x86ms, int
default_cpu_version)
x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
ms->smp.max_cpus - 1) +
1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
+
+for (i = 0; i < ms->smp.cpus; i++) {
+ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(x86ms,
i);
+}
+
for (i = 0; i < ms->smp.cpus; i++) {
x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, _fatal);
}
@@ -164,8 +172,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms,
int idx)
init_topo_info(_info, x86ms);
assert(idx < ms->possible_cpus->len);
- x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- _info, _ids);
+ x86_topo_ids_from_idx(_info, idx, _ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
@@ -199,10 +206,7 @@ const CPUArchIdList
*x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].type = ms->cpu_type;
ms->possible_cpus->cpus[i].vcpus_count = 1;
-ms->possible_cpus->cpus[i].arch_id =
-x86_cpu_apic_id_from_index(x86ms, i);
-x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- _info, _ids);
+x86_topo_ids_from_idx(_info, i, _ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
if (x86ms->smp_dies > 1) {
[PATCH v4 00/16] APIC ID fixes for AMD EPYC CPU model
This series fixes APIC ID encoding problem reported on AMD EPYC cpu model.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
Currently, the APIC ID is decoded based on the sequence
sockets->dies->cores->threads. This works for most standard AMD and other
vendors' configurations, but this decoding sequence does not follow that of
AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
inconsistency. When booting a guest VM, the kernel tries to validate the
topology, and finds it inconsistent with the enumeration of EPYC cpu models.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. It is available at
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
v4:
Generated the patches on top of git://github.com/ehabkost/qemu.git (x86-next).
Changes from v3.
1. Moved the arch_id calculation inside the function x86_cpus_init. With this
change,
we dont need to change common numa code(suggested by Igor).
2. Introduced the model specific handlers inside X86CPUDefinitions.
These handlers are loaded into X86MachineState during the init(suggested by
Eduardo).
Removed the string comparison for EPYC model.
3. Removed llc_id from x86CPU. Added node_id inside X86CPUTopoIDs to take care
of
EPYC apicid decoding.
4. Removed init_apicid_fn hanlder from MachineClass. Kept all the code changes
inside the x86.
5. Added new handler function apicid_pkg_offset for pkg_offset calculation.
6. And some other minor changes.
v3:
https://lore.kernel.org/qemu-devel/157541968844.46157.17994918142533791313.st...@naples-babu.amd.com/
1. Consolidated the topology information in structure X86CPUTopoInfo.
2. Changed the ccx_id to llc_id as commented by upstream.
3. Generalized the apic id decoding. It is mostly similar to current apic id
except that it adds new field llc_id when numa configured. Removes all the
hardcoded values.
4. Removed the earlier parse_numa split. And moved the numa node
initialization
inside the numa_complete_configuration. This is bit cleaner as commented
by
Eduardo.
5. Added new function init_apicid_fn inside machine_class structure. This
will be used to update the apic id handler specific to cpu model.
6. Updated the cpuid unit tests.
7. TODO : Need to figure out how to dynamically update the handlers using cpu
models.
I might some guidance on that.
v2:
https://lore.kernel.org/qemu-devel/156779689013.21957.1631551572950676212.stgit@localhost.localdomain/
1. Introduced the new property epyc to enable new epyc mode.
2. Separated the epyc mode and non epyc mode function.
3. Introduced function pointers in PCMachineState to handle the
differences.
4. Mildly tested different combinations to make things are working as
expected.
5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
supported only on AMD EPYC models. I may need some guidance on that.
v1:
https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.mo...@amd.com/
---
Babu Moger (16):
hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
hw/i386: Introduce X86CPUTopoInfo to contain topology info
hw/i386: Consolidate topology functions
hw/i386: Introduce init_topo_info to initialize X86CPUTopoInfo
machine: Add SMP Sockets in CpuTopology
hw/i386: Update structures for nodes_per_pkg
hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
hw/386: Add EPYC mode topology decoding functions
target/i386: Cleanup and use the EPYC mode topology functions
hw/i386: Introduce apicid functions inside X86MachineState
target/i386: Load apicid model specific handlers from X86CPUDefinition
hw/i386: Use the apicid handlers from X86MachineState
target/i386: Add EPYC model specific handlers
hw/i386: Move arch_id decode inside x86_cpus_init
i386: Fix pkg_id offset for EPYC cpu models
tests: Update the Unit tests
hw/core/machine.c |1
hw/i386/pc.c | 51 +-
hw/i386/x86.c | 73 ++
include/hw
[PATCH v4 05/16] machine: Add SMP Sockets in CpuTopology
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/core/machine.c |1 +
hw/i386/pc.c|1 +
include/hw/boards.h |2 ++
vl.c|1 +
4 files changed, 5 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 023548b4f3..ea03c25565 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -789,6 +789,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ms->smp.sockets = sockets;
}
if (ms->smp.cpus > 1) {
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 9803413dd9..f13721ac43 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -978,6 +978,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ms->smp.sockets = sockets;
x86ms->smp_dies = dies;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 24cbeecbae..a50a2d779e 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -256,12 +256,14 @@ typedef struct DeviceMemoryState {
* @cpus: the number of present logical processors on the machine
* @cores: the number of cores in one package
* @threads: the number of threads in one core
+ * @sockets: the number of sockets on the machine
* @max_cpus: the maximum number of logical processors on the machine
*/
typedef struct CpuTopology {
unsigned int cpus;
unsigned int cores;
unsigned int threads;
+unsigned int sockets;
unsigned int max_cpus;
} CpuTopology;
diff --git a/vl.c b/vl.c
index 94508300c3..3f6d396a95 100644
--- a/vl.c
+++ b/vl.c
@@ -3819,6 +3819,7 @@ int main(int argc, char **argv, char **envp)
current_machine->smp.max_cpus = machine_class->default_cpus;
current_machine->smp.cores = 1;
current_machine->smp.threads = 1;
+current_machine->smp.sockets = 1;
machine_class->smp_parse(current_machine,
qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
[PATCH v4 06/16] hw/i386: Update structures for nodes_per_pkg
Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg.
This is required to build EPYC mode topology.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
hw/i386/x86.c |2 ++
include/hw/i386/topology.h |2 ++
include/hw/i386/x86.h |1 +
target/i386/cpu.c |1 +
target/i386/cpu.h |1 +
6 files changed, 8 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f13721ac43..02fdb3d506 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1753,6 +1753,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
init_topo_info(_info, x86ms);
env->nr_dies = x86ms->smp_dies;
+env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
/*
* If APIC ID is not set,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 083effb2f5..3d944f68e6 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -89,11 +89,13 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id,
Error **errp)
Object *cpu = NULL;
Error *local_err = NULL;
CPUX86State *env = NULL;
+MachineState *ms = MACHINE(x86ms);
cpu = object_new(MACHINE(x86ms)->cpu_type);
env = _CPU(cpu)->env;
env->nr_dies = x86ms->smp_dies;
+env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
object_property_set_uint(cpu, apic_id, "apic-id", _err);
object_property_set_bool(cpu, true, "realized", _err);
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index ef0ab0b6a3..522c77e6a9 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -41,12 +41,14 @@
#include "qemu/bitops.h"
#include "hw/i386/x86.h"
+#include "sysemu/numa.h"
static inline void init_topo_info(X86CPUTopoInfo *topo_info,
const X86MachineState *x86ms)
{
MachineState *ms = MACHINE(x86ms);
+topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
topo_info->dies_per_pkg = x86ms->smp_dies;
topo_info->cores_per_die = ms->smp.cores;
topo_info->threads_per_core = ms->smp.threads;
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index ad62b01cf2..d76fd0bbb1 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -48,6 +48,7 @@ typedef struct X86CPUTopoIDs {
} X86CPUTopoIDs;
typedef struct X86CPUTopoInfo {
+unsigned nodes_per_pkg;
unsigned dies_per_pkg;
unsigned cores_per_die;
unsigned threads_per_core;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7e630f47ac..5d6edfd09b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6761,6 +6761,7 @@ static void x86_cpu_initfn(Object *obj)
FeatureWord w;
env->nr_dies = 1;
+env->nr_nodes = 1;
cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "family", "int",
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index af282936a7..627a8cb9be 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1603,6 +1603,7 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
unsigned nr_dies;
+unsigned nr_nodes;
} CPUX86State;
struct kvm_msrs;
[PATCH v4 04/16] hw/i386: Introduce init_topo_info to initialize X86CPUTopoInfo
Initialize all the parameters in one function init_topo_info.
Move the data structure X86CPUTopoIDs and X86CPUTopoInfo into
x86.h.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c |4 +---
hw/i386/x86.c | 14 +++---
include/hw/i386/topology.h | 26 ++
include/hw/i386/x86.h | 17 +
4 files changed, 31 insertions(+), 30 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2adf7f6afa..9803413dd9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1749,9 +1749,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
-topo_info.dies_per_pkg = x86ms->smp_dies;
-topo_info.cores_per_die = smp_cores;
-topo_info.threads_per_core = smp_threads;
+init_topo_info(_info, x86ms);
env->nr_dies = x86ms->smp_dies;
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index f18cab8e5c..083effb2f5 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -63,15 +63,12 @@ static size_t pvh_start_addr;
uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
unsigned int cpu_index)
{
-MachineState *ms = MACHINE(x86ms);
X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
X86CPUTopoInfo topo_info;
uint32_t correct_id;
static bool warned;
-topo_info.dies_per_pkg = x86ms->smp_dies;
-topo_info.cores_per_die = ms->smp.cores;
-topo_info.threads_per_core = ms->smp.threads;
+init_topo_info(_info, x86ms);
correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
if (x86mc->compat_apic_id_mode) {
@@ -146,10 +143,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState
*ms, int idx)
X86MachineState *x86ms = X86_MACHINE(ms);
X86CPUTopoInfo topo_info;
- topo_info.dies_per_pkg = x86ms->smp_dies;
- topo_info.cores_per_die = ms->smp.cores;
- topo_info.threads_per_core = ms->smp.threads;
-
+ init_topo_info(_info, x86ms);
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
@@ -177,9 +171,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState
*ms)
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
-topo_info.dies_per_pkg = x86ms->smp_dies;
-topo_info.cores_per_die = ms->smp.cores;
-topo_info.threads_per_core = ms->smp.threads;
+init_topo_info(_info, x86ms);
for (i = 0; i < ms->possible_cpus->len; i++) {
X86CPUTopoIDs topo_ids;
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index ba52d49079..ef0ab0b6a3 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -40,23 +40,17 @@
#include "qemu/bitops.h"
+#include "hw/i386/x86.h"
-/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
- */
-typedef uint32_t apic_id_t;
-
-typedef struct X86CPUTopoIDs {
-unsigned pkg_id;
-unsigned die_id;
-unsigned core_id;
-unsigned smt_id;
-} X86CPUTopoIDs;
-
-typedef struct X86CPUTopoInfo {
-unsigned dies_per_pkg;
-unsigned cores_per_die;
-unsigned threads_per_core;
-} X86CPUTopoInfo;
+static inline void init_topo_info(X86CPUTopoInfo *topo_info,
+ const X86MachineState *x86ms)
+{
+MachineState *ms = MACHINE(x86ms);
+
+topo_info->dies_per_pkg = x86ms->smp_dies;
+topo_info->cores_per_die = ms->smp.cores;
+topo_info->threads_per_core = ms->smp.threads;
+}
/* Return the bit width needed for 'count' IDs
*/
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 4b84917885..ad62b01cf2 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -36,6 +36,23 @@ typedef struct {
bool compat_apic_id_mode;
} X86MachineClass;
+/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
+ */
+typedef uint32_t apic_id_t;
+
+typedef struct X86CPUTopoIDs {
+unsigned pkg_id;
+unsigned die_id;
+unsigned core_id;
+unsigned smt_id;
+} X86CPUTopoIDs;
+
+typedef struct X86CPUTopoInfo {
+unsigned dies_per_pkg;
+unsigned cores_per_die;
+unsigned threads_per_core;
+} X86CPUTopoInfo;
+
typedef struct {
/*< private >*/
MachineState parent;
[PATCH v4 15/16] i386: Fix pkg_id offset for EPYC cpu models
If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
hw/i386/x86.c |4
target/i386/cpu.c |4 ++--
target/i386/cpu.h |1 +
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 93063af6a8..e56780b1f0 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1754,6 +1754,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
env->nr_dies = x86ms->smp_dies;
env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
+env->pkg_offset = x86ms->apicid_pkg_offset(_info);
/*
* If APIC ID is not set,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 472dc3eb77..99f2a67d69 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -106,12 +106,16 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id,
Error **errp)
Error *local_err = NULL;
CPUX86State *env = NULL;
MachineState *ms = MACHINE(x86ms);
+X86CPUTopoInfo topo_info;
+
+init_topo_info(_info, x86ms);
cpu = object_new(MACHINE(x86ms)->cpu_type);
env = _CPU(cpu)->env;
env->nr_dies = x86ms->smp_dies;
env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
+env->pkg_offset = x86ms->apicid_pkg_offset(_info);
object_property_set_uint(cpu, apic_id, "apic-id", _err);
object_property_set_bool(cpu, true, "realized", _err);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 082865d72b..b793da7c6e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5454,7 +5454,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
-*eax = apicid_pkg_offset(_info);
+*eax = env->pkg_offset;
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
@@ -5488,7 +5488,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
-*eax = apicid_pkg_offset(_info);
+*eax = env->pkg_offset;
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 64a1cca690..641e1cacdf 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1604,6 +1604,7 @@ typedef struct CPUX86State {
unsigned nr_dies;
unsigned nr_nodes;
+unsigned pkg_offset;
} CPUX86State;
struct kvm_msrs;
[PATCH v4 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info
This is an effort to re-arrange few data structure for better readability.
Add X86CPUTopoInfo which will have all the topology informations required
to build the cpu topology. There is no functional changes.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
hw/i386/pc.c | 14 --
hw/i386/x86.c | 28 +---
include/hw/i386/topology.h | 38 --
3 files changed, 53 insertions(+), 27 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 3a580f6a60..2adf7f6afa 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1741,6 +1741,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
X86MachineState *x86ms = X86_MACHINE(pcms);
unsigned int smp_cores = ms->smp.cores;
unsigned int smp_threads = ms->smp.threads;
+X86CPUTopoInfo topo_info;
if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
@@ -1748,6 +1749,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
+topo_info.dies_per_pkg = x86ms->smp_dies;
+topo_info.cores_per_die = smp_cores;
+topo_info.threads_per_core = smp_threads;
+
env->nr_dies = x86ms->smp_dies;
/*
@@ -1803,16 +1808,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
-smp_threads, _ids);
+cpu->apic_id = apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
-x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, _ids);
+x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -1833,8 +1836,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
-x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, _ids);
+x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo_ids.pkg_id);
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 4a112c8e30..f18cab8e5c 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -65,11 +65,15 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
{
MachineState *ms = MACHINE(x86ms);
X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
+X86CPUTopoInfo topo_info;
uint32_t correct_id;
static bool warned;
-correct_id = x86_apicid_from_cpu_idx(x86ms->smp_dies, ms->smp.cores,
- ms->smp.threads, cpu_index);
+topo_info.dies_per_pkg = x86ms->smp_dies;
+topo_info.cores_per_die = ms->smp.cores;
+topo_info.threads_per_core = ms->smp.threads;
+
+correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
if (x86mc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -140,19 +144,25 @@ int64_t x86_get_default_cpu_node_id(const MachineState
*ms, int idx)
{
X86CPUTopoIDs topo_ids;
X86MachineState *x86ms = X86_MACHINE(ms);
+ X86CPUTopoInfo topo_info;
+
+ topo_info.dies_per_pkg = x86ms->smp_dies;
+ topo_info.cores_per_die = ms->smp.cores;
+ topo_info.threads_per_core = ms->smp.threads;
+
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
-x86ms->smp_dies, ms->smp.cores,
-ms->smp.threads, _ids);
+_info, _ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms)
{
X86MachineState *x86ms = X86_MACHINE(ms);
-int i;
unsigned int max_cpus = ms->smp.max_cpus;
+X86CPUTopoInfo topo_info;
+int i;
if (ms->possible_cpus) {
[PATCH v4 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |2 +-
include/hw/i386/topology.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 02fdb3d506..be72a49716 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1808,7 +1808,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = apicid_from_topo_ids(_info, _ids);
+cpu->apic_id = x86_apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 522c77e6a9..3158157430 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -107,8 +107,8 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo
*topo_info)
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
-static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
- const X86CPUTopoIDs *topo_ids)
+static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids)
{
return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
(topo_ids->die_id << apicid_die_offset(topo_info)) |
@@ -160,7 +160,7 @@ static inline apic_id_t
x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
{
X86CPUTopoIDs topo_ids;
x86_topo_ids_from_idx(topo_info, cpu_index, _ids);
-return apicid_from_topo_ids(topo_info, _ids);
+return x86_apicid_from_topo_ids(topo_info, _ids);
}
#endif /* HW_I386_TOPOLOGY_H */
[PATCH v4 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c | 42 +-
hw/i386/x86.c | 18 +-
include/hw/i386/topology.h | 40
3 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 58867f987d..3a580f6a60 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1733,7 +1733,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
int idx;
CPUState *cs;
CPUArchId *cpu_slot;
-X86CPUTopoInfo topo;
+X86CPUTopoIDs topo_ids;
X86CPU *cpu = X86_CPU(dev);
CPUX86State *env = >env;
MachineState *ms = MACHINE(hotplug_dev);
@@ -1799,12 +1799,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
-topo.pkg_id = cpu->socket_id;
-topo.die_id = cpu->die_id;
-topo.core_id = cpu->core_id;
-topo.smt_id = cpu->thread_id;
+topo_ids.pkg_id = cpu->socket_id;
+topo_ids.die_id = cpu->die_id;
+topo_ids.core_id = cpu->core_id;
+topo_ids.smt_id = cpu->thread_id;
cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
-smp_threads, );
+smp_threads, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
@@ -1812,11 +1812,11 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
MachineState *ms = MACHINE(pcms);
x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, );
+ smp_cores, smp_threads, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
-topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
+topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id,
topo_ids.smt_id,
cpu->apic_id, ms->possible_cpus->len - 1);
return;
}
@@ -1834,34 +1834,34 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, );
-if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
+ smp_cores, smp_threads, _ids);
+if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
-" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo.pkg_id);
+" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo_ids.pkg_id);
return;
}
-cpu->socket_id = topo.pkg_id;
+cpu->socket_id = topo_ids.pkg_id;
-if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
+if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
error_setg(errp, "property die-id: %u doesn't match set apic-id:"
-" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
+" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
return;
}
-cpu->die_id = topo.die_id;
+cpu->die_id = topo_ids.die_id;
-if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
+if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
-" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
+" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
topo_ids.core_id);
return;
}
-cpu->core_id = topo.core_id;
+cpu->core_id = topo_ids.core_id;
-if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
+if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
-" 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
topo.smt_id);
+" 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
topo_ids.smt_id);
return;
}
-cpu->thread_id = topo
[PATCH v4 03/16] hw/i386: Consolidate topology functions
Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
include/hw/i386/topology.h | 64 ++--
target/i386/cpu.c | 23
2 files changed, 32 insertions(+), 55 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index cf1935d548..ba52d49079 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
/* Bit width of the SMT_ID (thread ID) field on the APIC ID
*/
-static inline unsigned apicid_smt_width(unsigned nr_dies,
-unsigned nr_cores,
-unsigned nr_threads)
+static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_threads);
+return apicid_bitwidth_for_count(topo_info->threads_per_core);
}
/* Bit width of the Core_ID field
*/
-static inline unsigned apicid_core_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_cores);
+return apicid_bitwidth_for_count(topo_info->cores_per_die);
}
/* Bit width of the Die_ID field */
-static inline unsigned apicid_die_width(unsigned nr_dies,
-unsigned nr_cores,
-unsigned nr_threads)
+static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_dies);
+return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
/* Bit offset of the Core_ID field
*/
-static inline unsigned apicid_core_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_smt_width(nr_dies, nr_cores, nr_threads);
+return apicid_smt_width(topo_info);
}
/* Bit offset of the Die_ID field */
-static inline unsigned apicid_die_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_core_offset(nr_dies, nr_cores, nr_threads) +
- apicid_core_width(nr_dies, nr_cores, nr_threads);
+return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
}
/* Bit offset of the Pkg_ID (socket ID) field
*/
-static inline unsigned apicid_pkg_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_die_offset(nr_dies, nr_cores, nr_threads) +
- apicid_die_width(nr_dies, nr_cores, nr_threads);
+return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
@@ -128,13 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
const X86CPUTopoIDs *topo_ids)
{
-unsigned nr_dies = topo_info->dies_per_pkg;
-unsigned nr_cores = topo_info->cores_per_die;
-unsigned nr_threads = topo_info->threads_per_core;
-
-return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores,
nr_threads)) |
- (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores,
nr_threads)) |
- (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores,
nr_threads)) |
+return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
topo_ids->smt_id;
}
@@ -162,19 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t
apicid,
X86CPUTopoInfo *topo_info,
X86CPUTopoIDs *topo_ids)
{
-unsigned nr_dies = topo_info->dies_per_pkg;
-unsigned nr_cores = topo_info->cores_per_die;
-unsigned nr_threads = topo_info->threads_per_core;
-
topo_ids->smt_id = apicid &
-~(0xUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
+~(0xUL << apicid_smt_width(topo_info));
topo_ids->core_id =
-(apicid >> apicid_core_offset(n
[PATCH v4 13/16] target/i386: Add EPYC model specific handlers
Add the new EPYC model specific handlers to fix the apicid decoding.
The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
strictly. In some cases this can cause CPU topology inconsistency.
When booting a guest VM, the kernel tries to validate the topology, and finds
it inconsistent with the enumeration of EPYC cpu models. The more details are
in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors.
It is available at https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
Signed-off-by: Babu Moger
---
target/i386/cpu.c |4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 389b68d765..082865d72b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3835,6 +3835,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x801E,
.model_id = "AMD EPYC Processor",
.cache_info = _cache_info,
+.apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc,
+.topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc,
+.apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc,
+.apicid_pkg_offset = apicid_pkg_offset_epyc,
.versions = (X86CPUVersionDefinition[]) {
{ .version = 1 },
{
[PATCH v4 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition
Load the model specific handlers if available or else default handlers
will be loaded. Add the model specific handlers if apicid decoding
differs from the standard sequential numbering.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 38 ++
target/i386/cpu.h |1 +
2 files changed, 39 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 19675eb696..389b68d765 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1614,6 +1614,16 @@ typedef struct X86CPUDefinition {
FeatureWordArray features;
const char *model_id;
CPUCaches *cache_info;
+
+/* Apic id specific handlers */
+uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
+unsigned cpu_index);
+void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
+ X86CPUTopoIDs *topo_ids);
+apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids);
+uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
+
/*
* Definitions for alternative versions of CPU model.
* List is terminated by item with version == 0.
@@ -1654,6 +1664,34 @@ static const X86CPUVersionDefinition
*x86_cpu_def_get_versions(X86CPUDefinition
return def->versions ?: default_version_list;
}
+void cpu_x86_init_apicid_fns(MachineState *machine)
+{
+X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(machine->cpu_type));
+X86CPUModel *model = xcc->model;
+X86CPUDefinition *def = model->cpudef;
+X86MachineState *x86ms = X86_MACHINE(machine);
+
+if (def) {
+if (def->apicid_from_cpu_idx) {
+x86ms->apicid_from_cpu_idx = def->apicid_from_cpu_idx;
+}
+if (def->topo_ids_from_apicid) {
+x86ms->topo_ids_from_apicid = def->topo_ids_from_apicid;
+}
+if (def->apicid_from_topo_ids) {
+x86ms->apicid_from_topo_ids = def->apicid_from_topo_ids;
+}
+if (def->apicid_pkg_offset) {
+x86ms->apicid_pkg_offset = def->apicid_pkg_offset;
+}
+} else {
+x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
+x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid;
+x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids;
+x86ms->apicid_pkg_offset = apicid_pkg_offset;
+}
+}
+
static CPUCaches epyc_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
.type = DATA_CACHE,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 627a8cb9be..64a1cca690 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1889,6 +1889,7 @@ void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
+void cpu_x86_init_apicid_fns(MachineState *machine);
/* helper.c */
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
[PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
Check and Load the apicid handlers from X86CPUDefinition if available.
Update the calling convention for the apicid handlers.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |6 +++---
hw/i386/x86.c | 27 +++
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index be72a49716..93063af6a8 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1808,14 +1808,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = x86_apicid_from_topo_ids(_info, _ids);
+cpu->apic_id = x86ms->apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
-x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
+x86ms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -1836,7 +1836,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
-x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
+x86ms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo_ids.pkg_id);
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 3d944f68e6..b825861b85 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -52,6 +52,22 @@
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
+/*
+ * Check for apicid handlers in X86MachineState. Load them if
+ * not loaded already. These handlers are loaded from X86CPUDefinition.
+ */
+static void x86_check_apicid_handlers(MachineState *ms)
+{
+X86MachineState *x86ms = X86_MACHINE(ms);
+
+if (!x86ms->apicid_from_cpu_idx ||
+!x86ms->topo_ids_from_apicid ||
+!x86ms->apicid_from_topo_ids ||
+!x86ms->apicid_pkg_offset) {
+cpu_x86_init_apicid_fns(ms);
+}
+}
+
/*
* Calculates initial APIC ID for a specific CPU index
*
@@ -70,7 +86,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
init_topo_info(_info, x86ms);
-correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
+correct_id = x86ms->apicid_from_cpu_idx(_info, cpu_index);
if (x86mc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -148,8 +164,8 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms,
int idx)
init_topo_info(_info, x86ms);
assert(idx < ms->possible_cpus->len);
- x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
-_info, _ids);
+ x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
+ _info, _ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
@@ -169,6 +185,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState
*ms)
return ms->possible_cpus;
}
+/* Initialize apicid handlers */
+x86_check_apicid_handlers(ms);
+
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
@@ -182,7 +201,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState
*ms)
ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id =
x86_cpu_apic_id_from_index(x86ms, i);
-x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
+x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
_info, _ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
Re: [PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
On 2/24/20 11:19 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:46 -0600
> Babu Moger wrote:
>
>> Check and Load the apicid handlers from X86CPUDefinition if available.
>> Update the calling convention for the apicid handlers.
>
> Previous and this patch look too complicated for the task at the hand.
> In particular, cpu_x86_init_apicid_fns() from previous patch adds 1 more
> reference to Machine into i386/cpu.c (even though it's just a helper function)
> and I think un-necessary hooks to X86CPUDefinition (it's not really CPU's
> businesses to make up APIC-IDs).
>
> I'd rather do opposite and get rid of the last explicit dependency to
> ms->smp.cpus from cpu.c. But well, it's out of scope of this series,
> so for this series I'd just try to avoid adding more Machine dependencies.
>
> All 11/16 does is basically using hooks as a switch "I'm EPYC" to
> set epyc specific encoding topo routines.
>
> It could be accomplished by a simple Boolean flag like
> X86CPUDefinition::use_epyc_apic_id_encoding
>
> and then cpu_x86_init_apicid_fns() could be replaced with trivial
> helper like:
>
> x86_use_epyc_apic_id_encoding(char *cpu_type)
> {
> X86CPUClass *xcc = ... cpu_type ...
> return xcc->model->cpudef->use_epyc_apic_id_encoding
> }
>
> then machine could override default[1] hooks using this helper
> as the trigger
> x86_cpus_init()
> {
> // no need in dedicated function as it's the only instance it's going
> to be called ever
> if (x86_use_epyc_apic_id_encoding(ms->cpu_type)) {
> x86ms->apicid_from_cpu_idx = ...epyc...
> x86ms->topo_ids_from_apicid = ...epyc...
> x86ms->apicid_from_topo_ids = ...epyc...
> x86ms->apicid_pkg_offset = ...epyc...
> }
> }
>
> That would be less invasive and won't create non necessary dependencies.
Yes. We can achieve the task here with your approach mentioned above. But,
we still will have a scaling issue. In future if a "new cpu model" comes
up its own decoding, then we need to add another bolean flag use_new
_cpu_apic_id_encoding. And then do that same check again. In that sense,
the current approach is bit generic. Lets also hear from Eduardo.
>
> ---
> 1) defaults should be set in x86_machine_class_init()
>
> Eduardo, what's your take on this?
>
>> Signed-off-by: Babu Moger
>> ---
>> hw/i386/pc.c |6 +++---
>> hw/i386/x86.c | 27 +++
>> 2 files changed, 26 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index be72a49716..93063af6a8 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -1808,14 +1808,14 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> topo_ids.die_id = cpu->die_id;
>> topo_ids.core_id = cpu->core_id;
>> topo_ids.smt_id = cpu->thread_id;
>> -cpu->apic_id = x86_apicid_from_topo_ids(_info, _ids);
>> +cpu->apic_id = x86ms->apicid_from_topo_ids(_info, _ids);
>> }
>>
>> cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
>> if (!cpu_slot) {
>> MachineState *ms = MACHINE(pcms);
>>
>> -x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
>> +x86ms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
>> error_setg(errp,
>> "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
>> " APIC ID %" PRIu32 ", valid index range 0:%d",
>> @@ -1836,7 +1836,7 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> /* TODO: move socket_id/core_id/thread_id checks into
>> x86_cpu_realizefn()
>> * once -smp refactoring is complete and there will be CPU private
>> * CPUState::nr_cores and CPUState::nr_threads fields instead of
>> globals */
>> -x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
>> +x86ms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
>> if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
>> error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
>> " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
>> topo_ids.pkg_id);
>> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
>> index 3d944f68e6..b825861b85 100644
>> --- a/hw/i386/x86.c
>> +++ b/hw/i386/x86.c
>> @@ -52,6 +52,22 @@
>> /* Physical Address of PVH entry point read from kernel ELF NOTE */
>>
Re: [PATCH v4 08/16] hw/386: Add EPYC mode topology decoding functions
On 2/24/20 2:50 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:18 -0600
> Babu Moger wrote:
>
>> These functions add support for building EPYC mode topology given the smp
>> details like numa nodes, cores, threads and sockets.
>>
>> The new apic id decoding is mostly similar to current apic id decoding
>> except that it adds a new field llc_id when numa configured. Removes all
>
> llc_id/nodes_per_pkg
Good catch. Thanks.
>
>> the hardcoded values. Subsequent patches will use these functions to build
>> the topology.
>>
>> Following functions are added.
>> apicid_llc_width_epyc
>> apicid_llc_offset_epyc
>> apicid_pkg_offset_epyc
>> apicid_from_topo_ids_epyc
>> x86_topo_ids_from_idx_epyc
>> x86_topo_ids_from_apicid_epyc
>> x86_apicid_from_cpu_idx_epyc
>>
>> The topology details are available in Processor Programming Reference (PPR)
>> for AMD Family 17h Model 01h, Revision B1 Processors.
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zipdata=02%7C01%7Cbabu.moger%40amd.com%7C07f6ec6272fa4a0bb44608d7b9069ef6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637181310409402221sdata=nPUTNqiXVSihj8mHt%2FO6sSGCL4uTtPsfvIiEJ0WosaM%3Dreserved=0
>
> also checkpatch doesn't like this patch for too long strings.
Yes. I saw that. Some are bit tricky. I may need to break the definitions
like this below.
static inline apic_id_t
x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
const X86CPUTopoIDs *topo_ids)
> with that fixed
> Acked-by: Igor Mammedov
>
>
> PS:
> similar checkpatch warnings should be fixed in preceding patches
Sure. Will take care.
>
>
>>
>> Signed-off-by: Babu Moger
>> ---
>> include/hw/i386/topology.h | 93
>>
>> include/hw/i386/x86.h |1
>> 2 files changed, 94 insertions(+)
>>
>> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
>> index 3158157430..d9319dc2ac 100644
>> --- a/include/hw/i386/topology.h
>> +++ b/include/hw/i386/topology.h
>> @@ -83,6 +83,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo
>> *topo_info)
>> return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
>> }
>>
>> +/* Bit width of the node_id field per socket */
>> +static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info)
>> +{
>> +return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1));
>> +}
>> /* Bit offset of the Core_ID field
>> */
>> static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
>> @@ -103,6 +108,94 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo
>> *topo_info)
>> return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
>> }
>>
>> +#define LLC_OFFSET 3 /* Minimum LLC offset if numa configured */
>> +
>> +/* Bit offset of the node_id field */
>> +static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info)
>> +{
>> +unsigned offset = apicid_die_offset(topo_info) +
>> + apicid_die_width(topo_info);
>> +
>> +if (topo_info->nodes_per_pkg) {
>> +return MAX(LLC_OFFSET, offset);
>> +} else {
>> +return offset;
>> +}
>> +}
>> +
>> +/* Bit offset of the Pkg_ID (socket ID) field */
>> +static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
>> +{
>> +return apicid_node_offset_epyc(topo_info) +
>> apicid_node_width_epyc(topo_info);
>> +}
>> +
>> +/*
>> + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
>> + *
>> + * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
>> + */
>> +static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo
>> *topo_info,
>> + const X86CPUTopoIDs
>> *topo_ids)
>> +{
>> +return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
>> + (topo_ids->node_id << apicid_node_offset_epyc(topo_info)) |
>> + (topo_ids->die_id << apicid_die_offset(topo_info)) |
>> + (topo_ids->core_id << apicid_core_offset(topo_info)) |
>> + topo_ids->smt_id;
>> +}
>> +
>> +static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info,
>> + unsigned cpu_index,
>> +
Re: [PATCH v4 06/16] hw/i386: Update structures for nodes_per_pkg
On 2/24/20 2:34 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:04 -0600
> Babu Moger wrote:
>
>> Update structures X86CPUTopoIDs and CPUX86State to hold the nodes_per_pkg.
>> This is required to build EPYC mode topology.
>>
>> Signed-off-by: Babu Moger
>> ---
>> hw/i386/pc.c |1 +
>> hw/i386/x86.c |2 ++
>> include/hw/i386/topology.h |2 ++
>> include/hw/i386/x86.h |1 +
>> target/i386/cpu.c |1 +
>> target/i386/cpu.h |1 +
>> 6 files changed, 8 insertions(+)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index f13721ac43..02fdb3d506 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -1753,6 +1753,7 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> init_topo_info(_info, x86ms);
>>
>> env->nr_dies = x86ms->smp_dies;
>> +env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
>
> it would be better if calculation would result in valid result
> so you won't have to later scatter MAX(env->nr_nodes, 1) everywhere.
Ok. Sure.
>
> also I'd use earlier intialized:
> env->nr_nodes = topo_info->nodes_per_pkg
> to avoid repeating calculation
yes. Will do it.
>
>> /*
>> * If APIC ID is not set,
>> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
>> index 083effb2f5..3d944f68e6 100644
>> --- a/hw/i386/x86.c
>> +++ b/hw/i386/x86.c
>> @@ -89,11 +89,13 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t
>> apic_id, Error **errp)
>> Object *cpu = NULL;
>> Error *local_err = NULL;
>> CPUX86State *env = NULL;
>> +MachineState *ms = MACHINE(x86ms);
>>
>> cpu = object_new(MACHINE(x86ms)->cpu_type);
>>
>> env = _CPU(cpu)->env;
>> env->nr_dies = x86ms->smp_dies;
>> +env->nr_nodes = ms->numa_state->num_nodes / ms->smp.sockets;
>
> Is this really necessary? (I think pc_cpu_pre_plug should take care of
> setting it)
This does not seem necessary. I can add as a separate patch to remove env
initialization from x86_cpu_new.
>
>> object_property_set_uint(cpu, apic_id, "apic-id", _err);
>> object_property_set_bool(cpu, true, "realized", _err);
>> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
>> index ef0ab0b6a3..522c77e6a9 100644
>> --- a/include/hw/i386/topology.h
>> +++ b/include/hw/i386/topology.h
>> @@ -41,12 +41,14 @@
>>
>> #include "qemu/bitops.h"
>> #include "hw/i386/x86.h"
>> +#include "sysemu/numa.h"
>>
>> static inline void init_topo_info(X86CPUTopoInfo *topo_info,
>>const X86MachineState *x86ms)
>> {
>> MachineState *ms = MACHINE(x86ms);
>>
>> +topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
>> topo_info->dies_per_pkg = x86ms->smp_dies;
>> topo_info->cores_per_die = ms->smp.cores;
>> topo_info->threads_per_core = ms->smp.threads;
>> diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
>> index ad62b01cf2..d76fd0bbb1 100644
>> --- a/include/hw/i386/x86.h
>> +++ b/include/hw/i386/x86.h
>> @@ -48,6 +48,7 @@ typedef struct X86CPUTopoIDs {
>> } X86CPUTopoIDs;
>>
>> typedef struct X86CPUTopoInfo {
>> +unsigned nodes_per_pkg;
>> unsigned dies_per_pkg;
>> unsigned cores_per_die;
>> unsigned threads_per_core;
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 7e630f47ac..5d6edfd09b 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -6761,6 +6761,7 @@ static void x86_cpu_initfn(Object *obj)
>> FeatureWord w;
>>
>> env->nr_dies = 1;
>> +env->nr_nodes = 1;
>> cpu_set_cpustate_pointers(cpu);
>>
>> object_property_add(obj, "family", "int",
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index af282936a7..627a8cb9be 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -1603,6 +1603,7 @@ typedef struct CPUX86State {
>> TPRAccess tpr_access_type;
>>
>> unsigned nr_dies;
>> +unsigned nr_nodes;
>> } CPUX86State;
>>
>> struct kvm_msrs;
>>
>
Re: [PATCH v4 10/16] hw/i386: Introduce apicid functions inside X86MachineState
On 2/24/20 11:01 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:32 -0600
> Babu Moger wrote:
>
>> Introduce model specific apicid functions inside X86MachineState.
>> These functions will be loaded from X86CPUDefinition.
>>
>> Signed-off-by: Babu Moger
>> ---
>> include/hw/i386/x86.h |9 +
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
>> index 38c2d27910..75c2462770 100644
>> --- a/include/hw/i386/x86.h
>> +++ b/include/hw/i386/x86.h
>> @@ -79,6 +79,15 @@ typedef struct {
>> uint16_t boot_cpus;
>> unsigned smp_dies;
>>
>> +/* Apic id specific handlers */
>> +uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
>> +unsigned cpu_index);
>> +void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo
>> *topo_info,
>> + X86CPUTopoIDs *topo_ids);
>> +apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
>> + const X86CPUTopoIDs *topo_ids);
>> +uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
>> +
>> /*
>> * Address space used by IOAPIC device. All IOAPIC interrupts
>> * will be translated to MSI messages in the address space.
>>
>>
>
> Suggest to move defaults into this patch as well. i.e.
> move parts that replace direct calls with hooks from 12/16
> and set default hooks (i.e. non EPYC ones) in x86's machine_class_init().
>
> This way It's immediately obvious what you are changing and then
> followup EPYC related patch won't be cluttered by non related defaults
> conversion.
>
Ok. Sure.
Re: [PATCH v4 09/16] target/i386: Cleanup and use the EPYC mode topology functions
On 2/24/20 2:52 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:17:25 -0600
> Babu Moger wrote:
>
>> Use the new functions from topology.h and delete the unused code. Given the
>> sockets, nodes, cores and threads, the new functions generate apic id for
>> EPYC
>> mode. Removes all the hardcoded values.
>>
>> Signed-off-by: Babu Moger
>
> modulo MAX() macro, looks fine to me
Igor, Sorry. What do you mean here?
>
>> ---
>> target/i386/cpu.c | 162
>> +++--
>> 1 file changed, 35 insertions(+), 127 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 5d6edfd09b..19675eb696 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -338,68 +338,15 @@ static void encode_cache_cpuid8006(CPUCacheInfo
>> *l2,
>> }
>> }
>>
>> -/*
>> - * Definitions used for building CPUID Leaf 0x801D and 0x801E
>> - * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
>> - * Define the constants to build the cpu topology. Right now, TOPOEXT
>> - * feature is enabled only on EPYC. So, these constants are based on
>> - * EPYC supported configurations. We may need to handle the cases if
>> - * these values change in future.
>> - */
>> -/* Maximum core complexes in a node */
>> -#define MAX_CCX 2
>> -/* Maximum cores in a core complex */
>> -#define MAX_CORES_IN_CCX 4
>> -/* Maximum cores in a node */
>> -#define MAX_CORES_IN_NODE 8
>> -/* Maximum nodes in a socket */
>> -#define MAX_NODES_PER_SOCKET 4
>> -
>> -/*
>> - * Figure out the number of nodes required to build this config.
>> - * Max cores in a node is 8
>> - */
>> -static int nodes_in_socket(int nr_cores)
>> -{
>> -int nodes;
>> -
>> -nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
>> -
>> - /* Hardware does not support config with 3 nodes, return 4 in that case
>> */
>> -return (nodes == 3) ? 4 : nodes;
>> -}
>> -
>> -/*
>> - * Decide the number of cores in a core complex with the given nr_cores
>> using
>> - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
>> - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
>> - * L3 cache is shared across all cores in a core complex. So, this will also
>> - * tell us how many cores are sharing the L3 cache.
>> - */
>> -static int cores_in_core_complex(int nr_cores)
>> -{
>> -int nodes;
>> -
>> -/* Check if we can fit all the cores in one core complex */
>> -if (nr_cores <= MAX_CORES_IN_CCX) {
>> -return nr_cores;
>> -}
>> -/* Get the number of nodes required to build this config */
>> -nodes = nodes_in_socket(nr_cores);
>> -
>> -/*
>> - * Divide the cores accros all the core complexes
>> - * Return rounded up value
>> - */
>> -return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
>> -}
>> -
>> /* Encode cache info for CPUID[801D] */
>> -static void encode_cache_cpuid801d(CPUCacheInfo *cache, CPUState *cs,
>> -uint32_t *eax, uint32_t *ebx,
>> -uint32_t *ecx, uint32_t *edx)
>> +static void encode_cache_cpuid801d(CPUCacheInfo *cache,
>> + X86CPUTopoInfo *topo_info,
>> + uint32_t *eax, uint32_t *ebx,
>> + uint32_t *ecx, uint32_t *edx)
>> {
>> uint32_t l3_cores;
>> +unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
>> +
>> assert(cache->size == cache->line_size * cache->associativity *
>>cache->partitions * cache->sets);
>>
>> @@ -408,10 +355,13 @@ static void encode_cache_cpuid801d(CPUCacheInfo
>> *cache, CPUState *cs,
>>
>> /* L3 is shared among multiple cores */
>> if (cache->level == 3) {
>> -l3_cores = cores_in_core_complex(cs->nr_cores);
>> -*eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
>> +l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
>> + topo_info->cores_per_die *
>> + topo_info->threads_per_core),
>> + nodes);
>> +*eax |= (l3_cores - 1) << 14;
>> } else {
>> -*eax |= ((cs->nr_threads - 1) <
Re: [PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
On 2/25/20 9:32 AM, Eduardo Habkost wrote:
> On Mon, Feb 24, 2020 at 05:13:18PM -0600, Babu Moger wrote:
>>
>>
>> On 2/24/20 4:31 PM, Eduardo Habkost wrote:
>>> On Mon, Feb 24, 2020 at 11:58:09AM -0600, Babu Moger wrote:
>>>>
>>>>
>>>> On 2/24/20 11:19 AM, Igor Mammedov wrote:
>>>>> On Thu, 13 Feb 2020 12:17:46 -0600
>>>>> Babu Moger wrote:
>>>>>
>>>>>> Check and Load the apicid handlers from X86CPUDefinition if available.
>>>>>> Update the calling convention for the apicid handlers.
>>>>>
>>>>> Previous and this patch look too complicated for the task at the hand.
>>>>> In particular, cpu_x86_init_apicid_fns() from previous patch adds 1 more
>>>>> reference to Machine into i386/cpu.c (even though it's just a helper
>>>>> function)
>>>>> and I think un-necessary hooks to X86CPUDefinition (it's not really CPU's
>>>>> businesses to make up APIC-IDs).
>>>>>
>>>>> I'd rather do opposite and get rid of the last explicit dependency to
>>>>> ms->smp.cpus from cpu.c. But well, it's out of scope of this series,
>>>>> so for this series I'd just try to avoid adding more Machine dependencies.
>>>>>
>>>>> All 11/16 does is basically using hooks as a switch "I'm EPYC" to
>>>>> set epyc specific encoding topo routines.
>>>>>
>>>>> It could be accomplished by a simple Boolean flag like
>>>>> X86CPUDefinition::use_epyc_apic_id_encoding
>>>>>
>>>>> and then cpu_x86_init_apicid_fns() could be replaced with trivial
>>>>> helper like:
>>>>>
>>>>> x86_use_epyc_apic_id_encoding(char *cpu_type)
>>>>> {
>>>>> X86CPUClass *xcc = ... cpu_type ...
>>>>> return xcc->model->cpudef->use_epyc_apic_id_encoding
>>>>> }
>>>>>
>>>>> then machine could override default[1] hooks using this helper
>>>>> as the trigger
>>>>> x86_cpus_init()
>>>>> {
>>>>> // no need in dedicated function as it's the only instance it's
>>>>> going to be called ever
>>>>> if (x86_use_epyc_apic_id_encoding(ms->cpu_type)) {
>>>>> x86ms->apicid_from_cpu_idx = ...epyc...
>>>>> x86ms->topo_ids_from_apicid = ...epyc...
>>>>> x86ms->apicid_from_topo_ids = ...epyc...
>>>>> x86ms->apicid_pkg_offset = ...epyc...
>>>>> }
>>>>> }
>>>>>
>>>>> That would be less invasive and won't create non necessary dependencies.
>>>>
>>>> Yes. We can achieve the task here with your approach mentioned above. But,
>>>> we still will have a scaling issue. In future if a "new cpu model" comes
>>>> up its own decoding, then we need to add another bolean flag use_new
>>>> _cpu_apic_id_encoding. And then do that same check again. In that sense,
>>>> the current approach is bit generic. Lets also hear from Eduardo.
>>>
>>> To be honest, I really hope the number of APIC ID initialization
>>> variations won't grow in the future.
>>>
>>> In either case, X86MachineState really doesn't seem to be the
>>> right place to save the function pointers. Whether we choose a
>>> boolean flag or a collection of function pointers, model-specific
>>> information belong to x86CPUClass and/or X86CPUDefinition, not
>>> MachineState.
>>
>> My bad. I completely missed that part. Yes. You mentioned that earlier.
>> I can move the functions pointers to X86CPUClass and initialize the
>> pointers from X86CPUDefinition. Thanks
>
> See my reply to Igor before doing that.
>
> Summary is: if the function implementations are provided by the
> CPU, the pointers belong to X86CPUClass. If the APIC ID
> calculation logic lives in pc.c, the pointers probably can stay
> in X86MachineState.
>
Ok. Sure. I will leave those pointers in X86MachineState.
Re: [PATCH v4 12/16] hw/i386: Use the apicid handlers from X86MachineState
On 2/24/20 4:31 PM, Eduardo Habkost wrote:
> On Mon, Feb 24, 2020 at 11:58:09AM -0600, Babu Moger wrote:
>>
>>
>> On 2/24/20 11:19 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:17:46 -0600
>>> Babu Moger wrote:
>>>
>>>> Check and Load the apicid handlers from X86CPUDefinition if available.
>>>> Update the calling convention for the apicid handlers.
>>>
>>> Previous and this patch look too complicated for the task at the hand.
>>> In particular, cpu_x86_init_apicid_fns() from previous patch adds 1 more
>>> reference to Machine into i386/cpu.c (even though it's just a helper
>>> function)
>>> and I think un-necessary hooks to X86CPUDefinition (it's not really CPU's
>>> businesses to make up APIC-IDs).
>>>
>>> I'd rather do opposite and get rid of the last explicit dependency to
>>> ms->smp.cpus from cpu.c. But well, it's out of scope of this series,
>>> so for this series I'd just try to avoid adding more Machine dependencies.
>>>
>>> All 11/16 does is basically using hooks as a switch "I'm EPYC" to
>>> set epyc specific encoding topo routines.
>>>
>>> It could be accomplished by a simple Boolean flag like
>>> X86CPUDefinition::use_epyc_apic_id_encoding
>>>
>>> and then cpu_x86_init_apicid_fns() could be replaced with trivial
>>> helper like:
>>>
>>> x86_use_epyc_apic_id_encoding(char *cpu_type)
>>> {
>>> X86CPUClass *xcc = ... cpu_type ...
>>> return xcc->model->cpudef->use_epyc_apic_id_encoding
>>> }
>>>
>>> then machine could override default[1] hooks using this helper
>>> as the trigger
>>> x86_cpus_init()
>>> {
>>> // no need in dedicated function as it's the only instance it's going
>>> to be called ever
>>> if (x86_use_epyc_apic_id_encoding(ms->cpu_type)) {
>>> x86ms->apicid_from_cpu_idx = ...epyc...
>>> x86ms->topo_ids_from_apicid = ...epyc...
>>> x86ms->apicid_from_topo_ids = ...epyc...
>>> x86ms->apicid_pkg_offset = ...epyc...
>>> }
>>> }
>>>
>>> That would be less invasive and won't create non necessary dependencies.
>>
>> Yes. We can achieve the task here with your approach mentioned above. But,
>> we still will have a scaling issue. In future if a "new cpu model" comes
>> up its own decoding, then we need to add another bolean flag use_new
>> _cpu_apic_id_encoding. And then do that same check again. In that sense,
>> the current approach is bit generic. Lets also hear from Eduardo.
>
> To be honest, I really hope the number of APIC ID initialization
> variations won't grow in the future.
>
> In either case, X86MachineState really doesn't seem to be the
> right place to save the function pointers. Whether we choose a
> boolean flag or a collection of function pointers, model-specific
> information belong to x86CPUClass and/or X86CPUDefinition, not
> MachineState.
My bad. I completely missed that part. Yes. You mentioned that earlier.
I can move the functions pointers to X86CPUClass and initialize the
pointers from X86CPUDefinition. Thanks
>
> See the reply I sent at:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F20200128200438.GJ18770%40habkost.net%2Fdata=02%7C01%7Cbabu.moger%40amd.com%7Cda1d1c9f34af4475596108d7b9795fef%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637181803279890359sdata=Z%2B%2BA2%2FMIVQZfGtUe1aBLzttCQnCpZKEwshOhoVAg1%2BU%3Dreserved=0
>
> ] If you need a CPU model to provide special behavior,
> ] you have two options:
> ]
> ] * Add a method pointer to X86CPUClass and/or X86CPUDefinition
> ] * Add a QOM property to enable/disable special behavior, and
> ] include the property in the CPU model definition.
> ]
> ] The second option might be preferable long term, but might
> ] require more work because the property would become visible in
> ] query-cpu-model-expansion and in the command line. The first
> ] option may be acceptable to avoid extra user-visible complexity
> ] in the first version.
> ]
> ]
> ]
> ] > +pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc;
> ] > +pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc;
> ] > +pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc;
> ]
> ] Why do you need to override the function pointers in
> ] PCMachineState instead of just looking up the relevant info at
> ] X86CPUClass?
>
Re: [PATCH v4 09/16] target/i386: Cleanup and use the EPYC mode topology functions
On 2/25/20 1:49 AM, Igor Mammedov wrote:
> On Mon, 24 Feb 2020 11:29:37 -0600
> Babu Moger wrote:
>
>> On 2/24/20 2:52 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:17:25 -0600
>>> Babu Moger wrote:
>>>
>>>> Use the new functions from topology.h and delete the unused code. Given the
>>>> sockets, nodes, cores and threads, the new functions generate apic id for
>>>> EPYC
>>>> mode. Removes all the hardcoded values.
>>>>
>>>> Signed-off-by: Babu Moger
>>>
>>> modulo MAX() macro, looks fine to me
>>
>> Igor, Sorry. What do you mean here?
>
> I meant s/MAX(topo_info->nodes_per_pkg, 1)/topo_info->nodes_per_pkg/
>
> after it's made sure that topo_info->nodes_per_pkg is always valid.
>
Noticed that we cannot change it in all the places and assign to valid
value 1. We need this information to know weather the system is numa
configured in topology.h. This is similar to ms->numa_state->num_nodes.
This value is > 0 if system is numa configured else it is 0. I need this
information while generating the apicid. I have added comments about it in
topology.h. Hope this is not a problem.
>
> (I believe I've commented on that somewhere. Series isn't split nicely,
> so I've ended up applying it all and then reviewing so comments might
> look out of the place sometimes, hopefully next revision will be easier
> to review)
>
>>>
>>>> ---
>>>> target/i386/cpu.c | 162
>>>> +++--
>>>> 1 file changed, 35 insertions(+), 127 deletions(-)
>>>>
>>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>>> index 5d6edfd09b..19675eb696 100644
>>>> --- a/target/i386/cpu.c
>>>> +++ b/target/i386/cpu.c
>>>> @@ -338,68 +338,15 @@ static void encode_cache_cpuid8006(CPUCacheInfo
>>>> *l2,
>>>> }
>>>> }
>>>>
>>>> -/*
>>>> - * Definitions used for building CPUID Leaf 0x801D and 0x801E
>>>> - * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
>>>> - * Define the constants to build the cpu topology. Right now, TOPOEXT
>>>> - * feature is enabled only on EPYC. So, these constants are based on
>>>> - * EPYC supported configurations. We may need to handle the cases if
>>>> - * these values change in future.
>>>> - */
>>>> -/* Maximum core complexes in a node */
>>>> -#define MAX_CCX 2
>>>> -/* Maximum cores in a core complex */
>>>> -#define MAX_CORES_IN_CCX 4
>>>> -/* Maximum cores in a node */
>>>> -#define MAX_CORES_IN_NODE 8
>>>> -/* Maximum nodes in a socket */
>>>> -#define MAX_NODES_PER_SOCKET 4
>>>> -
>>>> -/*
>>>> - * Figure out the number of nodes required to build this config.
>>>> - * Max cores in a node is 8
>>>> - */
>>>> -static int nodes_in_socket(int nr_cores)
>>>> -{
>>>> -int nodes;
>>>> -
>>>> -nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
>>>> -
>>>> - /* Hardware does not support config with 3 nodes, return 4 in that
>>>> case */
>>>> -return (nodes == 3) ? 4 : nodes;
>>>> -}
>>>> -
>>>> -/*
>>>> - * Decide the number of cores in a core complex with the given nr_cores
>>>> using
>>>> - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE
>>>> and
>>>> - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
>>>> - * L3 cache is shared across all cores in a core complex. So, this will
>>>> also
>>>> - * tell us how many cores are sharing the L3 cache.
>>>> - */
>>>> -static int cores_in_core_complex(int nr_cores)
>>>> -{
>>>> -int nodes;
>>>> -
>>>> -/* Check if we can fit all the cores in one core complex */
>>>> -if (nr_cores <= MAX_CORES_IN_CCX) {
>>>> -return nr_cores;
>>>> -}
>>>> -/* Get the number of nodes required to build this config */
>>>> -nodes = nodes_in_socket(nr_cores);
>>>> -
>>>> -/*
>>>> - * Divide the cores accros all the core complexes
>>>> - * Return rounded up value
>>>> - */
>>>> -return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
>>
[PATCH v5 09/16] target/i386: Cleanup and use the EPYC mode topology functions
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162 +++--
1 file changed, 35 insertions(+), 127 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 40670f8aca..c75cf744ab 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -338,68 +338,15 @@ static void encode_cache_cpuid8006(CPUCacheInfo *l2,
}
}
-/*
- * Definitions used for building CPUID Leaf 0x801D and 0x801E
- * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
- * Define the constants to build the cpu topology. Right now, TOPOEXT
- * feature is enabled only on EPYC. So, these constants are based on
- * EPYC supported configurations. We may need to handle the cases if
- * these values change in future.
- */
-/* Maximum core complexes in a node */
-#define MAX_CCX 2
-/* Maximum cores in a core complex */
-#define MAX_CORES_IN_CCX 4
-/* Maximum cores in a node */
-#define MAX_CORES_IN_NODE 8
-/* Maximum nodes in a socket */
-#define MAX_NODES_PER_SOCKET 4
-
-/*
- * Figure out the number of nodes required to build this config.
- * Max cores in a node is 8
- */
-static int nodes_in_socket(int nr_cores)
-{
-int nodes;
-
-nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
-
- /* Hardware does not support config with 3 nodes, return 4 in that case */
-return (nodes == 3) ? 4 : nodes;
-}
-
-/*
- * Decide the number of cores in a core complex with the given nr_cores using
- * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
- * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
- * L3 cache is shared across all cores in a core complex. So, this will also
- * tell us how many cores are sharing the L3 cache.
- */
-static int cores_in_core_complex(int nr_cores)
-{
-int nodes;
-
-/* Check if we can fit all the cores in one core complex */
-if (nr_cores <= MAX_CORES_IN_CCX) {
-return nr_cores;
-}
-/* Get the number of nodes required to build this config */
-nodes = nodes_in_socket(nr_cores);
-
-/*
- * Divide the cores accros all the core complexes
- * Return rounded up value
- */
-return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
-}
-
/* Encode cache info for CPUID[801D] */
-static void encode_cache_cpuid801d(CPUCacheInfo *cache, CPUState *cs,
-uint32_t *eax, uint32_t *ebx,
-uint32_t *ecx, uint32_t *edx)
+static void encode_cache_cpuid801d(CPUCacheInfo *cache,
+ X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
{
uint32_t l3_cores;
+unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
+
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
@@ -408,10 +355,13 @@ static void encode_cache_cpuid801d(CPUCacheInfo
*cache, CPUState *cs,
/* L3 is shared among multiple cores */
if (cache->level == 3) {
-l3_cores = cores_in_core_complex(cs->nr_cores);
-*eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
+l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
+ topo_info->cores_per_die *
+ topo_info->threads_per_core),
+ nodes);
+*eax |= (l3_cores - 1) << 14;
} else {
-*eax |= ((cs->nr_threads - 1) << 14);
+*eax |= ((topo_info->threads_per_core - 1) << 14);
}
assert(cache->line_size > 0);
@@ -431,55 +381,17 @@ static void encode_cache_cpuid801d(CPUCacheInfo
*cache, CPUState *cs,
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
-/* Data structure to hold the configuration info for a given core index */
-struct core_topology {
-/* core complex id of the current core index */
-int ccx_id;
-/*
- * Adjusted core index for this core in the topology
- * This can be 0,1,2,3 with max 4 cores in a core complex
- */
-int core_id;
-/* Node id for this core index */
-int node_id;
-/* Number of nodes in this config */
-int num_nodes;
-};
-
-/*
- * Build the configuration closely match the EPYC hardware. Using the EPYC
- * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
- * right now. This could change in future.
- * nr_cores : Total number of cores in the config
- * core_id : Core index of the current CPU
- * topo : Data structure to hold all the config info for this core index
- */
-static void build_core_topology(int nr_c
[PATCH v5 06/16] hw/i386: Update structures to save the number of nodes per package
Update structures X86CPUTopoIDs and CPUX86State to hold the number of
nodes per package. This is required to build EPYC mode topology.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
hw/i386/x86.c |1 +
include/hw/i386/topology.h |1 +
target/i386/cpu.c |1 +
target/i386/cpu.h |1 +
5 files changed, 5 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 68bf08f285..3d13cd46d6 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1526,6 +1526,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
init_topo_info(_info, x86ms);
env->nr_dies = x86ms->smp_dies;
+env->nr_nodes = topo_info.nodes_per_pkg;
/*
* If APIC ID is not set,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 79badcc4ec..929b80c9c7 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -62,6 +62,7 @@ inline void init_topo_info(X86CPUTopoInfo *topo_info,
{
MachineState *ms = MACHINE(x86ms);
+topo_info->nodes_per_pkg = ms->numa_state->num_nodes / ms->smp.sockets;
topo_info->dies_per_pkg = x86ms->smp_dies;
topo_info->cores_per_die = ms->smp.cores;
topo_info->threads_per_core = ms->smp.threads;
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index ba52d49079..04f01e2a09 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -53,6 +53,7 @@ typedef struct X86CPUTopoIDs {
} X86CPUTopoIDs;
typedef struct X86CPUTopoInfo {
+unsigned nodes_per_pkg;
unsigned dies_per_pkg;
unsigned cores_per_die;
unsigned threads_per_core;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1263271edd..40670f8aca 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6829,6 +6829,7 @@ static void x86_cpu_initfn(Object *obj)
FeatureWord w;
env->nr_dies = 1;
+env->nr_nodes = 1;
cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "family", "int",
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 576f309bbf..20abbda647 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1607,6 +1607,7 @@ typedef struct CPUX86State {
TPRAccess tpr_access_type;
unsigned nr_dies;
+unsigned nr_nodes;
} CPUX86State;
struct kvm_msrs;
[PATCH v5 00/16] APIC ID fixes for AMD EPYC CPU model
This series fixes APIC ID encoding problem reported on AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
Currently, the APIC ID is decoded based on the sequence
sockets->dies->cores->threads. This works for most standard AMD and other
vendors' configurations, but this decoding sequence does not follow that of
AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
inconsistency. When booting a guest VM, the kernel tries to validate the
topology, and finds it inconsistent with the enumeration of EPYC cpu models.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. The documentation is available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
v5:
Generated the patches on top of git://github.com/ehabkost/qemu.git (x86-next).
Changes from v4.
1. Re-arranged the patches 2 and 4 as suggested by Igor.
2. Kept the apicid handler functions inside X86MachineState as discussed.
These handlers are loaded from X86CPUDefinitions.
3. Removed unnecessary X86CPUstate initialization from x86_cpu_new. Suggested
by Igor.
4. And other minor changes related to patch format.
v4:
https://lore.kernel.org/qemu-devel/158161767653.48948.10578064482878399556.st...@naples-babu.amd.com/
Changes from v3.
1. Moved the arch_id calculation inside the function x86_cpus_init. With this
change,
we dont need to change common numa code.(suggested by Igor)
2. Introduced the model specific handlers inside X86CPUDefinitions.
These handlers are loaded into X86MachineState during the init.
3. Removed llc_id from x86CPU.
4. Removed init_apicid_fn hanlder from MachineClass. Kept all the code changes
inside the x86.
5. Added new handler function apicid_pkg_offset for pkg_offset calculation.
6. And some Other minor changes.
v3:
https://lore.kernel.org/qemu-devel/157541968844.46157.17994918142533791313.st...@naples-babu.amd.com/
1. Consolidated the topology information in structure X86CPUTopoInfo.
2. Changed the ccx_id to llc_id as commented by upstream.
3. Generalized the apic id decoding. It is mostly similar to current apic id
except that it adds new field llc_id when numa configured. Removes all the
hardcoded values.
4. Removed the earlier parse_numa split. And moved the numa node
initialization
inside the numa_complete_configuration. This is bit cleaner as commented
by
Eduardo.
5. Added new function init_apicid_fn inside machine_class structure. This
will be used to update the apic id handler specific to cpu model.
6. Updated the cpuid unit tests.
7. TODO : Need to figure out how to dynamically update the handlers using cpu
models.
I might some guidance on that.
v2:
https://lore.kernel.org/qemu-devel/156779689013.21957.1631551572950676212.stgit@localhost.localdomain/
1. Introduced the new property epyc to enable new epyc mode.
2. Separated the epyc mode and non epyc mode function.
3. Introduced function pointers in PCMachineState to handle the
differences.
4. Mildly tested different combinations to make things are working as
expected.
5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
supported only on AMD EPYC models. I may need some guidance on that.
v1:
https://lore.kernel.org/qemu-devel/20190731232032.51786-1-babu.mo...@amd.com/
---
Babu Moger (16):
hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
hw/i386: Introduce X86CPUTopoInfo to contain topology info
hw/i386: Consolidate topology functions
machine: Add SMP Sockets in CpuTopology
hw/i386: Remove unnecessary initialization in x86_cpu_new
hw/i386: Update structures to save the number of nodes per package
hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
hw/386: Add EPYC mode topology decoding functions
target/i386: Cleanup and use the EPYC mode topology functions
hw/i386: Introduce apicid functions inside X86MachineState
target/i386: Load apicid model specific handlers from X86CPUDefinition
hw/i386: Use the apicid hand
[PATCH v5 01/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
Rename few data structures related to X86 topology. X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
---
hw/i386/pc.c | 45 +++-
hw/i386/x86.c | 18 +-
include/hw/i386/topology.h | 44 +++
3 files changed, 57 insertions(+), 50 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2ddce4230a..715f79f58c 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1506,7 +1506,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
int idx;
CPUState *cs;
CPUArchId *cpu_slot;
-X86CPUTopoInfo topo;
+X86CPUTopoIDs topo_ids;
X86CPU *cpu = X86_CPU(dev);
CPUX86State *env = >env;
MachineState *ms = MACHINE(hotplug_dev);
@@ -1572,12 +1572,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
-topo.pkg_id = cpu->socket_id;
-topo.die_id = cpu->die_id;
-topo.core_id = cpu->core_id;
-topo.smt_id = cpu->thread_id;
+topo_ids.pkg_id = cpu->socket_id;
+topo_ids.die_id = cpu->die_id;
+topo_ids.core_id = cpu->core_id;
+topo_ids.smt_id = cpu->thread_id;
cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
-smp_threads, );
+smp_threads, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
@@ -1585,11 +1585,11 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
MachineState *ms = MACHINE(pcms);
x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, );
+ smp_cores, smp_threads, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
-topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
+topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id,
topo_ids.smt_id,
cpu->apic_id, ms->possible_cpus->len - 1);
return;
}
@@ -1607,34 +1607,37 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, );
-if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
+ smp_cores, smp_threads, _ids);
+if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
-" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
topo.pkg_id);
+" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
+topo_ids.pkg_id);
return;
}
-cpu->socket_id = topo.pkg_id;
+cpu->socket_id = topo_ids.pkg_id;
-if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
+if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
error_setg(errp, "property die-id: %u doesn't match set apic-id:"
-" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
+" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
return;
}
-cpu->die_id = topo.die_id;
+cpu->die_id = topo_ids.die_id;
-if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
+if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
-" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
+" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
+topo_ids.core_id);
return;
}
-cpu->core_id = topo.core_id;
+cpu->core_id = topo_ids.core_id;
-if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
+if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
-" 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
topo.smt_id);
+" 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
+topo_ids.smt_id);
retu
[PATCH v5 03/16] hw/i386: Consolidate topology functions
Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
include/hw/i386/topology.h | 68 ++--
target/i386/cpu.c | 23 +++
2 files changed, 32 insertions(+), 59 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 7ea507f376..ba52d49079 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
/* Bit width of the SMT_ID (thread ID) field on the APIC ID
*/
-static inline unsigned apicid_smt_width(unsigned nr_dies,
-unsigned nr_cores,
-unsigned nr_threads)
+static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_threads);
+return apicid_bitwidth_for_count(topo_info->threads_per_core);
}
/* Bit width of the Core_ID field
*/
-static inline unsigned apicid_core_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_cores);
+return apicid_bitwidth_for_count(topo_info->cores_per_die);
}
/* Bit width of the Die_ID field */
-static inline unsigned apicid_die_width(unsigned nr_dies,
-unsigned nr_cores,
-unsigned nr_threads)
+static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
{
-return apicid_bitwidth_for_count(nr_dies);
+return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
/* Bit offset of the Core_ID field
*/
-static inline unsigned apicid_core_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_smt_width(nr_dies, nr_cores, nr_threads);
+return apicid_smt_width(topo_info);
}
/* Bit offset of the Die_ID field */
-static inline unsigned apicid_die_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_core_offset(nr_dies, nr_cores, nr_threads) +
- apicid_core_width(nr_dies, nr_cores, nr_threads);
+return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
}
/* Bit offset of the Pkg_ID (socket ID) field
*/
-static inline unsigned apicid_pkg_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
{
-return apicid_die_offset(nr_dies, nr_cores, nr_threads) +
- apicid_die_width(nr_dies, nr_cores, nr_threads);
+return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
@@ -128,16 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
const X86CPUTopoIDs *topo_ids)
{
-unsigned nr_dies = topo_info->dies_per_pkg;
-unsigned nr_cores = topo_info->cores_per_die;
-unsigned nr_threads = topo_info->threads_per_core;
-
-return (topo_ids->pkg_id <<
- apicid_pkg_offset(nr_dies, nr_cores, nr_threads)) |
- (topo_ids->die_id <<
- apicid_die_offset(nr_dies, nr_cores, nr_threads)) |
- (topo_ids->core_id <<
- apicid_core_offset(nr_dies, nr_cores, nr_threads)) |
+return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
topo_ids->smt_id;
}
@@ -165,20 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t
apicid,
X86CPUTopoInfo *topo_info,
X86CPUTopoIDs *topo_ids)
{
-unsigned nr_dies = topo_info->dies_per_pkg;
-unsigned nr_cores = topo_info->cores_per_die;
-unsigned nr_threads = topo_info->threads_per_core;
-
topo_ids->smt_id = apicid &
-~(0xUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
+~(0xUL << apicid_smt_width(topo_info));
topo_ids->core_id
[PATCH v5 16/16] tests: Update the Unit tests
Since the topology routines have changed, update
the unit tests to use the new APIs.
Signed-off-by: Babu Moger
---
tests/test-x86-cpuid.c | 115
1 file changed, 68 insertions(+), 47 deletions(-)
diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c
index 1942287f33..00553c1d77 100644
--- a/tests/test-x86-cpuid.c
+++ b/tests/test-x86-cpuid.c
@@ -28,79 +28,100 @@
static void test_topo_bits(void)
{
+X86CPUTopoInfo topo_info = {0};
+
/* simple tests for 1 thread per core, 1 core per die, 1 die per package */
-g_assert_cmpuint(apicid_smt_width(1, 1, 1), ==, 0);
-g_assert_cmpuint(apicid_core_width(1, 1, 1), ==, 0);
-g_assert_cmpuint(apicid_die_width(1, 1, 1), ==, 0);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 1};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 0);
+g_assert_cmpuint(apicid_core_width(_info), ==, 0);
+g_assert_cmpuint(apicid_die_width(_info), ==, 0);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), ==, 0);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), ==, 1);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), ==, 2);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), ==, 3);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 0), ==, 0);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 1), ==, 1);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 2), ==, 2);
+g_assert_cmpuint(x86_apicid_from_cpu_idx(_info, 3), ==, 3);
/* Test field width calculation for multiple values
*/
-g_assert_cmpuint(apicid_smt_width(1, 1, 2), ==, 1);
-g_assert_cmpuint(apicid_smt_width(1, 1, 3), ==, 2);
-g_assert_cmpuint(apicid_smt_width(1, 1, 4), ==, 2);
-
-g_assert_cmpuint(apicid_smt_width(1, 1, 14), ==, 4);
-g_assert_cmpuint(apicid_smt_width(1, 1, 15), ==, 4);
-g_assert_cmpuint(apicid_smt_width(1, 1, 16), ==, 4);
-g_assert_cmpuint(apicid_smt_width(1, 1, 17), ==, 5);
-
-
-g_assert_cmpuint(apicid_core_width(1, 30, 2), ==, 5);
-g_assert_cmpuint(apicid_core_width(1, 31, 2), ==, 5);
-g_assert_cmpuint(apicid_core_width(1, 32, 2), ==, 5);
-g_assert_cmpuint(apicid_core_width(1, 33, 2), ==, 6);
-
-g_assert_cmpuint(apicid_die_width(1, 30, 2), ==, 0);
-g_assert_cmpuint(apicid_die_width(2, 30, 2), ==, 1);
-g_assert_cmpuint(apicid_die_width(3, 30, 2), ==, 2);
-g_assert_cmpuint(apicid_die_width(4, 30, 2), ==, 2);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 2};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 1);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 3};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 2);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 4};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 2);
+
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 14};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 4);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 15};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 4);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 16};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 4);
+topo_info = (X86CPUTopoInfo) {0, 1, 1, 17};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 5);
+
+
+topo_info = (X86CPUTopoInfo) {0, 1, 30, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 5);
+topo_info = (X86CPUTopoInfo) {0, 1, 31, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 5);
+topo_info = (X86CPUTopoInfo) {0, 1, 32, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 5);
+topo_info = (X86CPUTopoInfo) {0, 1, 33, 2};
+g_assert_cmpuint(apicid_core_width(_info), ==, 6);
+
+topo_info = (X86CPUTopoInfo) {0, 1, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 0);
+topo_info = (X86CPUTopoInfo) {0, 2, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 1);
+topo_info = (X86CPUTopoInfo) {0, 3, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 2);
+topo_info = (X86CPUTopoInfo) {0, 4, 30, 2};
+g_assert_cmpuint(apicid_die_width(_info), ==, 2);
/* build a weird topology and see if IDs are calculated correctly
*/
/* This will use 2 bits for thread ID and 3 bits for core ID
*/
-g_assert_cmpuint(apicid_smt_width(1, 6, 3), ==, 2);
-g_assert_cmpuint(apicid_core_offset(1, 6, 3), ==, 2);
-g_assert_cmpuint(apicid_die_offset(1, 6, 3), ==, 5);
-g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), ==, 5);
-
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), ==, 0);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), ==, 1);
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), ==, 2);
-
-g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), ==,
+topo_info = (X86CPUTopoInfo) {0, 1, 6, 3};
+g_assert_cmpuint(apicid_smt_width(_info), ==, 2);
+g_assert_cmpuint(apicid_core_offset(_info), ==, 2);
+g_assert_cmpuint(apicid_die_offset(_info), ==, 5);
+g_assert_cmpuint(apicid_pkg_offset(_info), ==, 5);
+
+topo_info = (X86CPUTopoInfo) {0, 1
[PATCH v5 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
For consistancy rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
hw/i386/pc.c |2 +-
include/hw/i386/topology.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 3d13cd46d6..17cce3f074 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1581,7 +1581,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = apicid_from_topo_ids(_info, _ids);
+cpu->apic_id = x86_apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 04f01e2a09..b9593b9905 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -112,8 +112,8 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo
*topo_info)
*
* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
*/
-static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
- const X86CPUTopoIDs *topo_ids)
+static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids)
{
return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
(topo_ids->die_id << apicid_die_offset(topo_info)) |
@@ -165,7 +165,7 @@ static inline apic_id_t
x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
{
X86CPUTopoIDs topo_ids;
x86_topo_ids_from_idx(topo_info, cpu_index, _ids);
-return apicid_from_topo_ids(topo_info, _ids);
+return x86_apicid_from_topo_ids(topo_info, _ids);
}
#endif /* HW_I386_TOPOLOGY_H */
[PATCH v5 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info
This is an effort to re-arrange few data structure for better readability.
1. Add X86CPUTopoInfo which will have all the topology informations
required to build the cpu topology. There is no functional changes.
2. Introduce init_topo_info to initialize X86CPUTopoInfo members from
X86MachineState.
There is no functional changes.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 12 ++--
hw/i386/x86.c | 32
include/hw/i386/topology.h | 38 --
include/hw/i386/x86.h |3 +++
4 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 715f79f58c..ef23ae2af5 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1514,6 +1514,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
X86MachineState *x86ms = X86_MACHINE(pcms);
unsigned int smp_cores = ms->smp.cores;
unsigned int smp_threads = ms->smp.threads;
+X86CPUTopoInfo topo_info;
if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
@@ -1521,6 +1522,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
return;
}
+init_topo_info(_info, x86ms);
+
env->nr_dies = x86ms->smp_dies;
/*
@@ -1576,16 +1579,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores,
-smp_threads, _ids);
+cpu->apic_id = apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
-x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, _ids);
+x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -1606,8 +1607,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
-x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies,
- smp_cores, smp_threads, _ids);
+x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 322fb6abbc..03b8962c98 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -57,6 +57,16 @@
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
+inline void init_topo_info(X86CPUTopoInfo *topo_info,
+ const X86MachineState *x86ms)
+{
+MachineState *ms = MACHINE(x86ms);
+
+topo_info->dies_per_pkg = x86ms->smp_dies;
+topo_info->cores_per_die = ms->smp.cores;
+topo_info->threads_per_core = ms->smp.threads;
+}
+
/*
* Calculates initial APIC ID for a specific CPU index
*
@@ -68,13 +78,14 @@ static size_t pvh_start_addr;
uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
unsigned int cpu_index)
{
-MachineState *ms = MACHINE(x86ms);
X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
+X86CPUTopoInfo topo_info;
uint32_t correct_id;
static bool warned;
-correct_id = x86_apicid_from_cpu_idx(x86ms->smp_dies, ms->smp.cores,
- ms->smp.threads, cpu_index);
+init_topo_info(_info, x86ms);
+
+correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
if (x86mc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -145,19 +156,22 @@ int64_t x86_get_default_cpu_node_id(const MachineState
*ms, int idx)
{
X86CPUTopoIDs topo_ids;
X86MachineState *x86ms = X86_MACHINE(ms);
+ X86CPUTopoInfo topo_info;
+
+ init_topo_info(_info, x86ms);
assert(idx < ms->possible_cpus->len);
x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
-x86ms->smp_dies, ms->smp.cores,
-ms->
[PATCH v5 04/16] machine: Add SMP Sockets in CpuTopology
Store the smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.
Signed-off-by: Babu Moger
Reviewed-by: Eduardo Habkost
Reviewed-by: Igor Mammedov
---
hw/core/machine.c |1 +
hw/i386/pc.c|1 +
include/hw/boards.h |2 ++
vl.c|1 +
4 files changed, 5 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index d8e30e4895..2582ce94f6 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -728,6 +728,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ms->smp.sockets = sockets;
}
if (ms->smp.cpus > 1) {
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index ef23ae2af5..68bf08f285 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -780,6 +780,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts)
ms->smp.cpus = cpus;
ms->smp.cores = cores;
ms->smp.threads = threads;
+ms->smp.sockets = sockets;
x86ms->smp_dies = dies;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index fb1b43d5b9..320dd14e02 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -252,12 +252,14 @@ typedef struct DeviceMemoryState {
* @cpus: the number of present logical processors on the machine
* @cores: the number of cores in one package
* @threads: the number of threads in one core
+ * @sockets: the number of sockets on the machine
* @max_cpus: the maximum number of logical processors on the machine
*/
typedef struct CpuTopology {
unsigned int cpus;
unsigned int cores;
unsigned int threads;
+unsigned int sockets;
unsigned int max_cpus;
} CpuTopology;
diff --git a/vl.c b/vl.c
index 7dcb0879c4..f77b1285c6 100644
--- a/vl.c
+++ b/vl.c
@@ -3949,6 +3949,7 @@ int main(int argc, char **argv, char **envp)
current_machine->smp.max_cpus = machine_class->default_cpus;
current_machine->smp.cores = 1;
current_machine->smp.threads = 1;
+current_machine->smp.sockets = 1;
machine_class->smp_parse(current_machine,
qemu_opts_find(qemu_find_opts("smp-opts"), NULL));
[PATCH v5 05/16] hw/i386: Remove unnecessary initialization in x86_cpu_new
The function pc_cpu_pre_plug takes care of initialization of CPUX86State.
So, remove the initialization here.
Suggested-by: Igor Mammedov
Signed-off-by: Babu Moger
---
hw/i386/x86.c |4
1 file changed, 4 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 03b8962c98..79badcc4ec 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -103,13 +103,9 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic_id,
Error **errp)
{
Object *cpu = NULL;
Error *local_err = NULL;
-CPUX86State *env = NULL;
cpu = object_new(MACHINE(x86ms)->cpu_type);
-env = _CPU(cpu)->env;
-env->nr_dies = x86ms->smp_dies;
-
object_property_set_uint(cpu, apic_id, "apic-id", _err);
object_property_set_bool(cpu, true, "realized", _err);
[PATCH v5 12/16] hw/i386: Use the apicid handlers from X86MachineState
Check and Load the apicid handlers from X86CPUDefinition if available.
Update the calling convention for the apicid handlers.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |6 +++---
hw/i386/x86.c | 11 +++
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 17cce3f074..c600ba0432 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1581,14 +1581,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.die_id = cpu->die_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
-cpu->apic_id = x86_apicid_from_topo_ids(_info, _ids);
+cpu->apic_id = x86ms->apicid_from_topo_ids(_info, _ids);
}
cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
if (!cpu_slot) {
MachineState *ms = MACHINE(pcms);
-x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
+x86ms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
error_setg(errp,
"Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
" APIC ID %" PRIu32 ", valid index range 0:%d",
@@ -1609,7 +1609,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
/* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
* once -smp refactoring is complete and there will be CPU private
* CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
-x86_topo_ids_from_apicid(cpu->apic_id, _info, _ids);
+x86ms->topo_ids_from_apicid(cpu->apic_id, _info, _ids);
if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 15b7815bb0..d46dd4ad9e 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -86,7 +86,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
init_topo_info(_info, x86ms);
-correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
+correct_id = x86ms->apicid_from_cpu_idx(_info, cpu_index);
if (x86mc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
@@ -158,8 +158,8 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms,
int idx)
init_topo_info(_info, x86ms);
assert(idx < ms->possible_cpus->len);
- x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
-_info, _ids);
+ x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
+ _info, _ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
@@ -179,6 +179,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState
*ms)
return ms->possible_cpus;
}
+/* Initialize apicid handlers */
+cpu_x86_init_apicid_fns(ms);
+
ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
sizeof(CPUArchId) * max_cpus);
ms->possible_cpus->len = max_cpus;
@@ -192,7 +195,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState
*ms)
ms->possible_cpus->cpus[i].vcpus_count = 1;
ms->possible_cpus->cpus[i].arch_id =
x86_cpu_apic_id_from_index(x86ms, i);
-x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
+x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
_info, _ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
[PATCH v5 15/16] i386: Fix pkg_id offset for EPYC cpu models
If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 +
target/i386/cpu.c |4 ++--
target/i386/cpu.h |1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c600ba0432..b6237a3a14 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1527,6 +1527,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
env->nr_dies = x86ms->smp_dies;
env->nr_nodes = topo_info.nodes_per_pkg;
+env->pkg_offset = x86ms->apicid_pkg_offset(_info);
/*
* If APIC ID is not set,
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f870f7c55b..9b160cbdd1 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5503,7 +5503,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
-*eax = apicid_pkg_offset(_info);
+*eax = env->pkg_offset;
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
@@ -5537,7 +5537,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
case 2:
-*eax = apicid_pkg_offset(_info);
+*eax = env->pkg_offset;
*ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
break;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 34f0d994ef..aac86af5cf 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1608,6 +1608,7 @@ typedef struct CPUX86State {
unsigned nr_dies;
unsigned nr_nodes;
+unsigned pkg_offset;
} CPUX86State;
struct kvm_msrs;
[PATCH v5 08/16] hw/386: Add EPYC mode topology decoding functions
These functions add support for building EPYC mode topology given the smp
details like numa nodes, cores, threads and sockets.
The new apic id decoding is mostly similar to current apic id decoding
except that it adds a new field node_id when numa configured. Removes all
the hardcoded values. Subsequent patches will use these functions to build
the topology.
Following functions are added.
apicid_llc_width_epyc
apicid_llc_offset_epyc
apicid_pkg_offset_epyc
apicid_from_topo_ids_epyc
x86_topo_ids_from_idx_epyc
x86_topo_ids_from_apicid_epyc
x86_apicid_from_cpu_idx_epyc
The topology details are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors. The revision guides are
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
Acked-by: Igor Mammedov
---
include/hw/i386/topology.h | 100
1 file changed, 100 insertions(+)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index b9593b9905..07239f95f4 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -47,6 +47,7 @@ typedef uint32_t apic_id_t;
typedef struct X86CPUTopoIDs {
unsigned pkg_id;
+unsigned node_id;
unsigned die_id;
unsigned core_id;
unsigned smt_id;
@@ -88,6 +89,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo
*topo_info)
return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
+/* Bit width of the node_id field per socket */
+static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info)
+{
+return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1));
+}
/* Bit offset of the Core_ID field
*/
static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
@@ -108,6 +114,100 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo
*topo_info)
return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
+#define NODE_ID_OFFSET 3 /* Minimum node_id offset if numa configured */
+
+/*
+ * Bit offset of the node_id field
+ *
+ * Make sure nodes_per_pkg > 0 if numa configured else zero.
+ */
+static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+unsigned offset = apicid_die_offset(topo_info) +
+ apicid_die_width(topo_info);
+
+if (topo_info->nodes_per_pkg) {
+return MAX(NODE_ID_OFFSET, offset);
+} else {
+return offset;
+}
+}
+
+/* Bit offset of the Pkg_ID (socket ID) field */
+static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+return apicid_node_offset_epyc(topo_info) +
+ apicid_node_width_epyc(topo_info);
+}
+
+/*
+ * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
+ *
+ * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
+ */
+static inline apic_id_t
+x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids)
+{
+return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
+ (topo_ids->node_id << apicid_node_offset_epyc(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
+ topo_ids->smt_id;
+}
+
+static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info,
+ unsigned cpu_index,
+ X86CPUTopoIDs *topo_ids)
+{
+unsigned nr_nodes = MAX(topo_info->nodes_per_pkg, 1);
+unsigned nr_dies = topo_info->dies_per_pkg;
+unsigned nr_cores = topo_info->cores_per_die;
+unsigned nr_threads = topo_info->threads_per_core;
+unsigned cores_per_node = DIV_ROUND_UP((nr_dies * nr_cores * nr_threads),
+nr_nodes);
+
+topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
+topo_ids->node_id = (cpu_index / cores_per_node) % nr_nodes;
+topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
+topo_ids->core_id = cpu_index / nr_threads % nr_cores;
+topo_ids->smt_id = cpu_index % nr_threads;
+}
+
+/*
+ * Calculate thread/core/package IDs for a specific topology,
+ * based on APIC ID
+ */
+static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid,
+X86CPUTopoInfo *topo_info,
+X86CPUTopoIDs *topo_ids)
+{
+topo_ids->smt_id = apicid &
+~(0xUL << apicid_smt_width(topo_info));
+topo_ids->core_id =
+(apicid >> apicid_core_offset(topo_info)) &
+~(0xUL << apicid_core_width(topo_info));
+topo_ids->die_id =
+(apicid >> apicid_die_offset(topo_info)) &
+~
[PATCH v5 13/16] target/i386: Add EPYC model specific handlers
Add the new EPYC model specific handlers to fix the apicid decoding.
The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
strictly. In some cases this can cause CPU topology inconsistency.
When booting a guest VM, the kernel tries to validate the topology, and finds
it inconsistent with the enumeration of EPYC cpu models. The more details are
in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.
To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors.
It is available at https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}
Signed-off-by: Babu Moger
---
target/i386/cpu.c |4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f33d8b77f5..f870f7c55b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3884,6 +3884,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x801E,
.model_id = "AMD EPYC Processor",
.cache_info = _cache_info,
+.apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc,
+.topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc,
+.apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc,
+.apicid_pkg_offset = apicid_pkg_offset_epyc,
.versions = (X86CPUVersionDefinition[]) {
{ .version = 1 },
{
[PATCH v5 10/16] hw/i386: Introduce apicid functions inside X86MachineState
Introduce model specific apicid functions inside X86MachineState.
These functions will be loaded from X86CPUDefinition.
Signed-off-by: Babu Moger
---
hw/i386/x86.c |5 +
include/hw/i386/x86.h |9 +
2 files changed, 14 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 929b80c9c7..15b7815bb0 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -911,6 +911,11 @@ static void x86_machine_initfn(Object *obj)
x86ms->smm = ON_OFF_AUTO_AUTO;
x86ms->max_ram_below_4g = 0; /* use default */
x86ms->smp_dies = 1;
+
+x86ms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx;
+x86ms->topo_ids_from_apicid = x86_topo_ids_from_apicid;
+x86ms->apicid_from_topo_ids = x86_apicid_from_topo_ids;
+x86ms->apicid_pkg_offset = apicid_pkg_offset;
}
static void x86_machine_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
index 22babcb3bb..2643b57629 100644
--- a/include/hw/i386/x86.h
+++ b/include/hw/i386/x86.h
@@ -65,6 +65,15 @@ typedef struct {
OnOffAuto smm;
+/* Apic id specific handlers */
+uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
+unsigned cpu_index);
+void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
+ X86CPUTopoIDs *topo_ids);
+apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids);
+uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
+
/*
* Address space used by IOAPIC device. All IOAPIC interrupts
* will be translated to MSI messages in the address space.
[PATCH v5 14/16] hw/i386: Move arch_id decode inside x86_cpus_init
Apicid calculation depends on knowing the total number of numa nodes
for EPYC cpu models. Right now, we are calculating the arch_id while
parsing the numa(parse_numa). At this time, it is not known how many
total numa nodes are configured in the system.
Move the arch_id inside x86_cpus_init. At this time smp parameter is already
completed and numa node information is available.
Signed-off-by: Babu Moger
---
hw/i386/x86.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index d46dd4ad9e..66998b065c 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -121,6 +121,9 @@ void x86_cpus_init(X86MachineState *x86ms, int
default_cpu_version)
MachineState *ms = MACHINE(x86ms);
MachineClass *mc = MACHINE_GET_CLASS(x86ms);
+/* Initialize apicid handlers first */
+cpu_x86_init_apicid_fns(ms);
+
x86_cpu_set_default_version(default_cpu_version);
/*
@@ -134,6 +137,12 @@ void x86_cpus_init(X86MachineState *x86ms, int
default_cpu_version)
x86ms->apic_id_limit = x86_cpu_apic_id_from_index(x86ms,
ms->smp.max_cpus - 1) +
1;
possible_cpus = mc->possible_cpu_arch_ids(ms);
+
+for (i = 0; i < ms->smp.cpus; i++) {
+ms->possible_cpus->cpus[i].arch_id =
+x86_cpu_apic_id_from_index(x86ms, i);
+}
+
for (i = 0; i < ms->smp.cpus; i++) {
x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, _fatal);
}
@@ -158,8 +167,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState *ms,
int idx)
init_topo_info(_info, x86ms);
assert(idx < ms->possible_cpus->len);
- x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
- _info, _ids);
+ x86_topo_ids_from_idx(_info, idx, _ids);
return topo_ids.pkg_id % ms->numa_state->num_nodes;
}
@@ -193,10 +201,7 @@ const CPUArchIdList
*x86_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].type = ms->cpu_type;
ms->possible_cpus->cpus[i].vcpus_count = 1;
-ms->possible_cpus->cpus[i].arch_id =
-x86_cpu_apic_id_from_index(x86ms, i);
-x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
- _info, _ids);
+x86_topo_ids_from_idx(_info, i, _ids);
ms->possible_cpus->cpus[i].props.has_socket_id = true;
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
if (x86ms->smp_dies > 1) {
[PATCH v5 11/16] target/i386: Load apicid model specific handlers from X86CPUDefinition
Load the model specific handlers if available or else default handlers
will be loaded. Add the model specific handlers if apicid decoding
differs from the standard sequential numbering.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 34 ++
target/i386/cpu.h |1 +
2 files changed, 35 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c75cf744ab..f33d8b77f5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -51,6 +51,7 @@
#include "sysemu/sysemu.h"
#include "sysemu/tcg.h"
#include "hw/qdev-properties.h"
+#include "hw/i386/x86.h"
#include "hw/i386/topology.h"
#ifndef CONFIG_USER_ONLY
#include "exec/address-spaces.h"
@@ -1614,6 +1615,16 @@ typedef struct X86CPUDefinition {
FeatureWordArray features;
const char *model_id;
CPUCaches *cache_info;
+
+/* Apic id specific handlers */
+uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
+unsigned cpu_index);
+void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
+ X86CPUTopoIDs *topo_ids);
+apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs *topo_ids);
+uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
+
/*
* Definitions for alternative versions of CPU model.
* List is terminated by item with version == 0.
@@ -1654,6 +1665,29 @@ static const X86CPUVersionDefinition
*x86_cpu_def_get_versions(X86CPUDefinition
return def->versions ?: default_version_list;
}
+void cpu_x86_init_apicid_fns(MachineState *machine)
+{
+X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(machine->cpu_type));
+X86CPUModel *model = xcc->model;
+X86CPUDefinition *def = model->cpudef;
+X86MachineState *x86ms = X86_MACHINE(machine);
+
+if (def) {
+if (def->apicid_from_cpu_idx) {
+x86ms->apicid_from_cpu_idx = def->apicid_from_cpu_idx;
+}
+if (def->topo_ids_from_apicid) {
+x86ms->topo_ids_from_apicid = def->topo_ids_from_apicid;
+}
+if (def->apicid_from_topo_ids) {
+x86ms->apicid_from_topo_ids = def->apicid_from_topo_ids;
+}
+if (def->apicid_pkg_offset) {
+x86ms->apicid_pkg_offset = def->apicid_pkg_offset;
+}
+}
+}
+
static CPUCaches epyc_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
.type = DATA_CACHE,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 20abbda647..34f0d994ef 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1895,6 +1895,7 @@ void cpu_clear_apic_feature(CPUX86State *env);
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
+void cpu_x86_init_apicid_fns(MachineState *machine);
/* helper.c */
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
Re: [PATCH v4 09/16] target/i386: Cleanup and use the EPYC mode topology functions
On 2/25/20 1:49 AM, Igor Mammedov wrote:
> On Mon, 24 Feb 2020 11:29:37 -0600
> Babu Moger wrote:
>
>> On 2/24/20 2:52 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:17:25 -0600
>>> Babu Moger wrote:
>>>
>>>> Use the new functions from topology.h and delete the unused code. Given the
>>>> sockets, nodes, cores and threads, the new functions generate apic id for
>>>> EPYC
>>>> mode. Removes all the hardcoded values.
>>>>
>>>> Signed-off-by: Babu Moger
>>>
>>> modulo MAX() macro, looks fine to me
>>
>> Igor, Sorry. What do you mean here?
>
> I meant s/MAX(topo_info->nodes_per_pkg, 1)/topo_info->nodes_per_pkg/
>
> after it's made sure that topo_info->nodes_per_pkg is always valid.
>
>
> (I believe I've commented on that somewhere. Series isn't split nicely,
> so I've ended up applying it all and then reviewing so comments might
> look out of the place sometimes, hopefully next revision will be easier
> to review)
Ok. I got it. Thanks
>
>>>
>>>> ---
>>>> target/i386/cpu.c | 162
>>>> +++--
>>>> 1 file changed, 35 insertions(+), 127 deletions(-)
>>>>
>>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>>> index 5d6edfd09b..19675eb696 100644
>>>> --- a/target/i386/cpu.c
>>>> +++ b/target/i386/cpu.c
>>>> @@ -338,68 +338,15 @@ static void encode_cache_cpuid8006(CPUCacheInfo
>>>> *l2,
>>>> }
>>>> }
>>>>
>>>> -/*
>>>> - * Definitions used for building CPUID Leaf 0x801D and 0x801E
>>>> - * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
>>>> - * Define the constants to build the cpu topology. Right now, TOPOEXT
>>>> - * feature is enabled only on EPYC. So, these constants are based on
>>>> - * EPYC supported configurations. We may need to handle the cases if
>>>> - * these values change in future.
>>>> - */
>>>> -/* Maximum core complexes in a node */
>>>> -#define MAX_CCX 2
>>>> -/* Maximum cores in a core complex */
>>>> -#define MAX_CORES_IN_CCX 4
>>>> -/* Maximum cores in a node */
>>>> -#define MAX_CORES_IN_NODE 8
>>>> -/* Maximum nodes in a socket */
>>>> -#define MAX_NODES_PER_SOCKET 4
>>>> -
>>>> -/*
>>>> - * Figure out the number of nodes required to build this config.
>>>> - * Max cores in a node is 8
>>>> - */
>>>> -static int nodes_in_socket(int nr_cores)
>>>> -{
>>>> -int nodes;
>>>> -
>>>> -nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
>>>> -
>>>> - /* Hardware does not support config with 3 nodes, return 4 in that
>>>> case */
>>>> -return (nodes == 3) ? 4 : nodes;
>>>> -}
>>>> -
>>>> -/*
>>>> - * Decide the number of cores in a core complex with the given nr_cores
>>>> using
>>>> - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE
>>>> and
>>>> - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
>>>> - * L3 cache is shared across all cores in a core complex. So, this will
>>>> also
>>>> - * tell us how many cores are sharing the L3 cache.
>>>> - */
>>>> -static int cores_in_core_complex(int nr_cores)
>>>> -{
>>>> -int nodes;
>>>> -
>>>> -/* Check if we can fit all the cores in one core complex */
>>>> -if (nr_cores <= MAX_CORES_IN_CCX) {
>>>> -return nr_cores;
>>>> -}
>>>> -/* Get the number of nodes required to build this config */
>>>> -nodes = nodes_in_socket(nr_cores);
>>>> -
>>>> -/*
>>>> - * Divide the cores accros all the core complexes
>>>> - * Return rounded up value
>>>> - */
>>>> -return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
>>>> -}
>>>> -
>>>> /* Encode cache info for CPUID[801D] */
>>>> -static void encode_cache_cpuid801d(CPUCacheInfo *cache, CPUState *cs,
>>>> -uint32_t *eax, uint32_t *ebx,
>>>> -uint32_t *ecx, uint32_t *edx)
>>>> +static void encode_
Re: [PATCH v4 04/16] hw/i386: Introduce init_topo_info to initialize X86CPUTopoInfo
On 2/24/20 2:18 AM, Igor Mammedov wrote:
> On Fri, 21 Feb 2020 11:51:15 -0600
> Babu Moger wrote:
>
>> On 2/21/20 11:05 AM, Igor Mammedov wrote:
>>> On Thu, 13 Feb 2020 12:16:51 -0600
>>> Babu Moger wrote:
>>>
>>>> Initialize all the parameters in one function init_topo_info.
>>>
>>> is it possible to squash it in 2/16
>>>
>> Sure. We can do that.
>>>
>>>>
>>>> Move the data structure X86CPUTopoIDs and X86CPUTopoInfo into
>>>> x86.h.
>>> A reason why it's moved should be here.
>>
>> Apicid functions will be part of X86MachineState data structure(patches
>> introduced later).These functions will use X86CPUTopoIDs and
>> X86CPUTopoInfo definition. Will add these details. Thanks
>
> why not just include topology.h into the X86MachineState header,
> and keep topo structures/functions where they are now?
> (I dislike a little scattering consolidated pieces across multiple files,
> but what worries me more is that it makes target/i386/cpu.c via
> topology.h -> x86.h chain pull in a lot of unrelated dependencies)
>
> So I'd keep X86CPUTopoIDs and X86CPUTopoInfo in topology.h
Ok. Sure. we can do that.
>
> [...]
>>>> +static inline void init_topo_info(X86CPUTopoInfo *topo_info,
>>>> + const X86MachineState *x86ms)
>>>> +{
>>>> +MachineState *ms = MACHINE(x86ms);
>>>> +
>>>> +topo_info->dies_per_pkg = x86ms->smp_dies;
>>>> +topo_info->cores_per_die = ms->smp.cores;
>>>> +topo_info->threads_per_core = ms->smp.threads;
>>>> +}
>
> this is pure machine specific helper, and aren't used anywhere else
> beside machine code.
> Suggest to put it in pc.c or x86.c to keep topology.h machine independent.
Ok. Will do.
>
>>>>
>>>> /* Return the bit width needed for 'count' IDs
>>>> */
>>>> diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
>>>> index 4b84917885..ad62b01cf2 100644
>>>> --- a/include/hw/i386/x86.h
>>>> +++ b/include/hw/i386/x86.h
>>>> @@ -36,6 +36,23 @@ typedef struct {
>>>> bool compat_apic_id_mode;
>>>> } X86MachineClass;
>>>>
>>>> +/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC
>>>> support
>>>> + */
>>>> +typedef uint32_t apic_id_t;
>>>> +
>>>> +typedef struct X86CPUTopoIDs {
>>>> +unsigned pkg_id;
>>>> +unsigned die_id;
>>>> +unsigned core_id;
>>>> +unsigned smt_id;
>>>> +} X86CPUTopoIDs;
>>>> +
>>>> +typedef struct X86CPUTopoInfo {
>>>> +unsigned dies_per_pkg;
>>>> +unsigned cores_per_die;
>>>> +unsigned threads_per_core;
>>>> +} X86CPUTopoInfo;
>>>> +
>>>> typedef struct {
>>>> /*< private >*/
>>>> MachineState parent;
>>>>
>>>
>>
>
Re: [PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass
On 1/29/20 10:51 AM, Eduardo Habkost wrote:
> On Wed, Jan 29, 2020 at 10:32:01AM -0600, Babu Moger wrote:
>>
>>
>> On 1/29/20 3:14 AM, Igor Mammedov wrote:
>>> On Tue, 28 Jan 2020 13:45:31 -0600
>>> Babu Moger wrote:
>>>
>>>> On 1/28/20 10:29 AM, Igor Mammedov wrote:
>>>>> On Tue, 03 Dec 2019 18:37:42 -0600
>>>>> Babu Moger wrote:
>>>>>
>>>>>> Add a new function init_apicid_fn in MachineClass to initialize the mode
>>>>>> specific handlers to decode the apic ids.
>>>>>>
>>>>>> Signed-off-by: Babu Moger
>>>>>> ---
>>>>>> include/hw/boards.h |1 +
>>>>>> vl.c|3 +++
>>>>>> 2 files changed, 4 insertions(+)
>>>>>>
>>>>>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>>>>>> index d4fab218e6..ce5aa365cb 100644
>>>>>> --- a/include/hw/boards.h
>>>>>> +++ b/include/hw/boards.h
>>>>>> @@ -238,6 +238,7 @@ struct MachineClass {
>>>>>> unsigned
>>>>>> cpu_index);
>>>>>> const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState
>>>>>> *machine);
>>>>>> int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx);
>>>>>> +void (*init_apicid_fn)(MachineState *ms);
>>>>> it's x86 specific, so why it wasn put into PCMachineClass?
>>>>
>>>> Yes. It is x86 specific for now. I tried to make it generic function so
>>>> other OSes can use it if required(like we have done in
>>>> possible_cpu_arch_ids). It initializes functions required to build the
>>>> apicid for each CPUs. We need these functions much early in the
>>>> initialization. It should be initialized before parse_numa_opts or
>>>> machine_run_board_init(in v1.c) which are called from generic context. We
>>>> cannot use PCMachineClass at this time.
>>>
>>> could you point to specific patches in this series that require
>>> apic ids being initialized before parse_numa_opts and elaborate why?
>>>
>>> we already have possible_cpu_arch_ids() which could be called very
>>> early and calculates APIC IDs in x86 case, so why not reuse it?
>>
>> Forgot to respond to this. The possible_cpu_arch_ids does not use the numa
>> information to build the apic id. We cannot re-use it without changing it
>> drastically.
>
> I don't get it. I see multiple patches in this series changing
> pc_possible_cpu_arch_ids() (which is really expected, if you are
> changing how APIC IDs are generated).
>
My bad. I mispoke on that.I should have said the current decoding
logic(x86_apicid_from_cpu_idx, x86_topo_ids_from_apicid,
x86_apicid_from_topo_ids) cannot be used as is.
Re: [PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass
On 1/29/20 3:14 AM, Igor Mammedov wrote:
> On Tue, 28 Jan 2020 13:45:31 -0600
> Babu Moger wrote:
>
>> On 1/28/20 10:29 AM, Igor Mammedov wrote:
>>> On Tue, 03 Dec 2019 18:37:42 -0600
>>> Babu Moger wrote:
>>>
>>>> Add a new function init_apicid_fn in MachineClass to initialize the mode
>>>> specific handlers to decode the apic ids.
>>>>
>>>> Signed-off-by: Babu Moger
>>>> ---
>>>> include/hw/boards.h |1 +
>>>> vl.c|3 +++
>>>> 2 files changed, 4 insertions(+)
>>>>
>>>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>>>> index d4fab218e6..ce5aa365cb 100644
>>>> --- a/include/hw/boards.h
>>>> +++ b/include/hw/boards.h
>>>> @@ -238,6 +238,7 @@ struct MachineClass {
>>>> unsigned
>>>> cpu_index);
>>>> const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine);
>>>> int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx);
>>>> +void (*init_apicid_fn)(MachineState *ms);
>>> it's x86 specific, so why it wasn put into PCMachineClass?
>>
>> Yes. It is x86 specific for now. I tried to make it generic function so
>> other OSes can use it if required(like we have done in
>> possible_cpu_arch_ids). It initializes functions required to build the
>> apicid for each CPUs. We need these functions much early in the
>> initialization. It should be initialized before parse_numa_opts or
>> machine_run_board_init(in v1.c) which are called from generic context. We
>> cannot use PCMachineClass at this time.
>
> could you point to specific patches in this series that require
> apic ids being initialized before parse_numa_opts and elaborate why?
>
> we already have possible_cpu_arch_ids() which could be called very
> early and calculates APIC IDs in x86 case, so why not reuse it?
Forgot to respond to this. The possible_cpu_arch_ids does not use the numa
information to build the apic id. We cannot re-use it without changing it
drastically.
>
>>
>>>
>>>
>>>> };
>>>>
>>>> /**
>>>> diff --git a/vl.c b/vl.c
>>>> index a42c24a77f..b6af604e11 100644
>>>> --- a/vl.c
>>>> +++ b/vl.c
>>>> @@ -4318,6 +4318,9 @@ int main(int argc, char **argv, char **envp)
>>>> current_machine->cpu_type = machine_class->default_cpu_type;
>>>> if (cpu_option) {
>>>> current_machine->cpu_type = parse_cpu_option(cpu_option);
>>>> +if (machine_class->init_apicid_fn) {
>>>> +machine_class->init_apicid_fn(current_machine);
>>>> +}
>>>> }
>>>> parse_numa_opts(current_machine);
>>>>
>>>>
>>>>
>>>
>>
>
Re: [PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass
On 1/29/20 3:14 AM, Igor Mammedov wrote:
> On Tue, 28 Jan 2020 13:45:31 -0600
> Babu Moger wrote:
>
>> On 1/28/20 10:29 AM, Igor Mammedov wrote:
>>> On Tue, 03 Dec 2019 18:37:42 -0600
>>> Babu Moger wrote:
>>>
>>>> Add a new function init_apicid_fn in MachineClass to initialize the mode
>>>> specific handlers to decode the apic ids.
>>>>
>>>> Signed-off-by: Babu Moger
>>>> ---
>>>> include/hw/boards.h |1 +
>>>> vl.c|3 +++
>>>> 2 files changed, 4 insertions(+)
>>>>
>>>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>>>> index d4fab218e6..ce5aa365cb 100644
>>>> --- a/include/hw/boards.h
>>>> +++ b/include/hw/boards.h
>>>> @@ -238,6 +238,7 @@ struct MachineClass {
>>>> unsigned
>>>> cpu_index);
>>>> const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine);
>>>> int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx);
>>>> +void (*init_apicid_fn)(MachineState *ms);
>>> it's x86 specific, so why it wasn put into PCMachineClass?
>>
>> Yes. It is x86 specific for now. I tried to make it generic function so
>> other OSes can use it if required(like we have done in
>> possible_cpu_arch_ids). It initializes functions required to build the
>> apicid for each CPUs. We need these functions much early in the
>> initialization. It should be initialized before parse_numa_opts or
>> machine_run_board_init(in v1.c) which are called from generic context. We
>> cannot use PCMachineClass at this time.
>
> could you point to specific patches in this series that require
> apic ids being initialized before parse_numa_opts and elaborate why?
>
> we already have possible_cpu_arch_ids() which could be called very
> early and calculates APIC IDs in x86 case, so why not reuse it?
The current code(before this series) parses the numa information and then
sequentially builds the apicid. Both are done together.
But this series separates the numa parsing and apicid generation. Numa
parsing is done first and after that the apicid is generated. Reason is we
need to know the number of numa nodes in advance to decode the apicid.
Look at this patch.
https://lore.kernel.org/qemu-devel/157541988471.46157.6587693720990965800.st...@naples-babu.amd.com/
static inline apic_id_t apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
+ const X86CPUTopoIDs
*topo_ids)
+{
+return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
+ (topo_ids->llc_id << apicid_llc_offset_epyc(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
+ topo_ids->smt_id;
+}
The function apicid_from_topo_ids_epyc builds the apicid. New decode adds
llc_id(which is numa id here) to the current decoding. Other fields are
mostly remains same.
Details from the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166
Processor Programming Reference (PPR) for AMD Family 17h Model 01h,
Revision B1 Processors:
"""
2.1.10.2.1.3
ApicId Enumeration Requirements
Operating systems are expected to use
Core::X86::Cpuid::SizeId[ApicIdCoreIdSize], the number of least
significant bits in the Initial APIC ID that indicate core ID within a
processor, in constructing per-core CPUID
masks. Core::X86::Cpuid::SizeId[ApicIdCoreIdSize] determines the maximum
number of cores (MNC) that the
processor could theoretically support, not the actual number of cores that
are actually implemented or enabled on
the processor, as indicated by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
{1'b0,LogicalCoreID[1:0]}.
"""
>
>>
>>>
>>>
>>>> };
>>>>
>>>> /**
>>>> diff --git a/vl.c b/vl.c
>>>> index a42c24a77f..b6af604e11 100644
>>>> --- a/vl.c
>>>> +++ b/vl.c
>>>> @@ -4318,6 +4318,9 @@ int main(int argc, char **argv, char **envp)
>>>> current_machine->cpu_type = machine_class->default_cpu_type;
>>>> if (cpu_option) {
>>>> current_machine->cpu_type = parse_cpu_option(cpu_option);
>>>> +if (machine_class->init_apicid_fn) {
>>>> +machine_class->init_apicid_fn(current_machine);
>>>> +}
>>>> }
>>>> parse_numa_opts(current_machine);
>>>>
>>>>
>>>>
>>>
>>
>
Re: [PATCH v3 16/18] hw/i386: Introduce EPYC mode function handlers
On 1/28/20 2:04 PM, Eduardo Habkost wrote:
> Hi,
>
> Sorry for taking so long. I was away from the office for a
> month, and now I'm finally back.
no worries.
>
> On Tue, Dec 03, 2019 at 06:38:46PM -0600, Babu Moger wrote:
>> Introduce following handlers for new epyc mode.
>> x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index.
>> x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id.
>> x86_apicid_from_topo_ids_epyc: Generate apicid from topo ids.
>>
>> Signed-off-by: Babu Moger
>> ---
>> hw/i386/pc.c | 12
>> include/hw/i386/topology.h |4 ++--
>> 2 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index e6c8a458e7..64e3658873 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -2819,6 +2819,17 @@ static bool pc_hotplug_allowed(MachineState *ms,
>> DeviceState *dev, Error **errp)
>> return true;
>> }
>>
>> +static void pc_init_apicid_fn(MachineState *ms)
>> +{
>> +PCMachineState *pcms = PC_MACHINE(ms);
>> +
>> +if (!strncmp(ms->cpu_type, "EPYC", 4)) {
>
> Please never use string comparison to introduce device-specific
> behavior. I had already pointed this out at
Yes. you did mention before. I was not sure how to achieve without
comparing the model string
>
> If you need a CPU model to provide special behavior,
> you have two options:
>
> * Add a method pointer to X86CPUClass and/or X86CPUDefinition
> * Add a QOM property to enable/disable special behavior, and
> include the property in the CPU model definition.
>
> The second option might be preferable long term, but might
> require more work because the property would become visible in
> query-cpu-model-expansion and in the command line. The first
> option may be acceptable to avoid extra user-visible complexity
> in the first version.
Yes. We need to have a special behavior for specific model.
I will look at both these above approaches closely. Challenge is this
needs to be done much early in the initialization(before parse_numa_opts
or machine_run_board_init). Will research more on this.
>
>
>
>> +pcms->apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc;
>> +pcms->topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc;
>> +pcms->apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc;
>
> Why do you need to override the function pointers in
> PCMachineState instead of just looking up the relevant info at
> X86CPUClass?
>
> If both machine-types and CPU models are supposed to override the
> APIC ID calculation functions, the interaction between
> machine-type and CPU model needs to be better documented
> (preferably with simple test cases) to ensure we won't break
> compatibility later.
>
>> +}
>> +}
>> +
>> static void pc_machine_class_init(ObjectClass *oc, void *data)
>> {
>> MachineClass *mc = MACHINE_CLASS(oc);
>> @@ -2847,6 +2858,7 @@ static void pc_machine_class_init(ObjectClass *oc,
>> void *data)
>> mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
>> mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
>> mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
>> +mc->init_apicid_fn = pc_init_apicid_fn;
>> mc->auto_enable_numa_with_memhp = true;
>> mc->has_hotpluggable_cpus = true;
>> mc->default_boot_order = "cad";
>> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
>> index b2b9e93a06..f028d2332a 100644
>> --- a/include/hw/i386/topology.h
>> +++ b/include/hw/i386/topology.h
>> @@ -140,7 +140,7 @@ static inline unsigned
>> apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
>> *
>> * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
>> */
>> -static inline apic_id_t apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
>> +static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo
>> *topo_info,
>>const X86CPUTopoIDs
>> *topo_ids)
>> {
>> return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
>> @@ -200,7 +200,7 @@ static inline apic_id_t
>> x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info,
>> {
>> X86CPUTopoIDs topo_ids;
>> x86_topo_ids_from_idx_epyc(topo_info, cpu_index, _ids);
>> -return apicid_from_topo_ids_epyc(topo_info, _ids);
>> +return x86_apicid_from_topo_ids_epyc(topo_info, _ids);
>> }
>> /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
>> *
>>
>>
>
Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models
On 2/4/20 2:02 AM, Igor Mammedov wrote:
> On Mon, 3 Feb 2020 13:31:29 -0600
> Babu Moger wrote:
>
>> On 2/3/20 8:59 AM, Igor Mammedov wrote:
>>> On Tue, 03 Dec 2019 18:36:54 -0600
>>> Babu Moger wrote:
>>>
>>>> This series fixes APIC ID encoding problems on AMD EPYC CPUs.
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166data=02%7C01%7Cbabu.moger%40amd.com%7Cbbd1693802184161c8c308d7a9489ee9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637164001686545394sdata=UtYAoTk4RfZZ1VfaP%2FhcYrCSNTcubEB7cB%2BoYlRLfhc%3Dreserved=0
>>>>
>>>> Currently, the APIC ID is decoded based on the sequence
>>>> sockets->dies->cores->threads. This works for most standard AMD and other
>>>> vendors' configurations, but this decoding sequence does not follow that of
>>>> AMD's APIC ID enumeration strictly. In some cases this can cause CPU
>>>> topology
>>>> inconsistency. When booting a guest VM, the kernel tries to validate the
>>>> topology, and finds it inconsistent with the enumeration of EPYC cpu
>>>> models.
>>>>
>>>> To fix the problem we need to build the topology as per the Processor
>>>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>>>> Processors. It is available at
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zipdata=02%7C01%7Cbabu.moger%40amd.com%7Cbbd1693802184161c8c308d7a9489ee9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637164001686555390sdata=oHONRiXtpstKqwrxyzqR20bYDDr3zvmwq91a%2Br6iDqc%3Dreserved=0
>>>>
>>>> Here is the text from the PPR.
>>>> Operating systems are expected to use
>>>> Core::X86::Cpuid::SizeId[ApicIdSize], the
>>>> number of least significant bits in the Initial APIC ID that indicate core
>>>> ID
>>>> within a processor, in constructing per-core CPUID masks.
>>>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
>>>> (MNC) that the processor could theoretically support, not the actual
>>>> number of
>>>> cores that are actually implemented or enabled on the processor, as
>>>> indicated
>>>> by Core::X86::Cpuid::SizeId[NC].
>>>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>>>> • ApicId[6] = Socket ID.
>>>> • ApicId[5:4] = Node ID.
>>>> • ApicId[3] = Logical CCX L3 complex ID
>>>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
>>>> {1'b0,LogicalCoreID[1:0]}
>>>
>>>
>>> After checking out all patches and some pondering, used here approach
>>> looks to me too intrusive for the task at hand especially where it
>>> comes to generic code.
>>>
>>> (Ignore till to see suggestion how to simplify without reading
>>> reasoning behind it first)
>>>
>>> Lets look for a way to simplify it a little bit.
>>>
>>> So problem we are trying to solve,
>>> 1: calculate APIC IDs based on cpu type (to e more specific: for EPYC
>>> based CPUs)
>>> 2: it depends on knowing total number of numa nodes.
>>>
>>> Externally workflow looks like following:
>>> 1. user provides -smp x,sockets,cores,...,maxcpus
>>> that's used by possible_cpu_arch_ids() singleton to build list of
>>> possible CPUs (which is available to user via command
>>> 'hotpluggable-cpus')
>>>
>>> Hook could be called very early and possible_cpus data might be
>>> not complete. It builds a list of possible CPUs which user could
>>> modify later.
>>>
>>> 2.1 user uses "-numa cpu,node-id=x,..." or legacy "-numa
>>> node,node_id=x,cpus="
>>> options to assign cpus to nodes, which is one way or another calling
>>> machine_set_cpu_numa_node(). The later updates 'possible_cpus' list
>>> with node information. It happens early when total number of nodes
>>> is not available.
>>>
>>> 2.2 user does not provide explicit node mappings for CPUs.
>>> QEMU steps in and assigns possible cpus to nodes in
>>> machine_numa_finish_cpu_init()
>>> (using the same machine_set_cpu_numa_node()) right before calling
>>> boards
>>> specific machine init(). At that time total number of nodes is known.
>>>
>&
Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models
On 2/5/20 10:56 AM, Igor Mammedov wrote:
> On Wed, 5 Feb 2020 10:10:06 -0600
> Babu Moger wrote:
>
>> On 2/5/20 3:38 AM, Igor Mammedov wrote:
>>> On Tue, 4 Feb 2020 13:08:58 -0600
>>> Babu Moger wrote:
>>>
>>>> On 2/4/20 2:02 AM, Igor Mammedov wrote:
>>>>> On Mon, 3 Feb 2020 13:31:29 -0600
>>>>> Babu Moger wrote:
>>>>>
>>>>>> On 2/3/20 8:59 AM, Igor Mammedov wrote:
>>>>>>> On Tue, 03 Dec 2019 18:36:54 -0600
>>>>>>> Babu Moger wrote:
>>>>>>>
>>>>>>>> This series fixes APIC ID encoding problems on AMD EPYC CPUs.
>>>>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166data=02%7C01%7Cbabu.moger%40amd.com%7C6b6d6af79fee45cc904808d7aa5c5f37%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637165186049856500sdata=vDAkIxR3U6LX%2FmnYjZPRC55smMqLend%2FHQjbfYWydBk%3Dreserved=0
>>>>>>>>
>>>>>>>> Currently, the APIC ID is decoded based on the sequence
>>>>>>>> sockets->dies->cores->threads. This works for most standard AMD and
>>>>>>>> other
>>>>>>>> vendors' configurations, but this decoding sequence does not follow
>>>>>>>> that of
>>>>>>>> AMD's APIC ID enumeration strictly. In some cases this can cause CPU
>>>>>>>> topology
>>>>>>>> inconsistency. When booting a guest VM, the kernel tries to validate
>>>>>>>> the
>>>>>>>> topology, and finds it inconsistent with the enumeration of EPYC cpu
>>>>>>>> models.
>>>>>>>>
>>>>>>>> To fix the problem we need to build the topology as per the Processor
>>>>>>>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>>>>>>>> Processors. It is available at
>>>>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zipdata=02%7C01%7Cbabu.moger%40amd.com%7C6b6d6af79fee45cc904808d7aa5c5f37%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637165186049856500sdata=rVMRN%2BbUeGWEksKO5uQ3Wxc71eeHCXMrkLVRbo4JHHI%3Dreserved=0
>>>>>>>>
>>>>>>>> Here is the text from the PPR.
>>>>>>>> Operating systems are expected to use
>>>>>>>> Core::X86::Cpuid::SizeId[ApicIdSize], the
>>>>>>>> number of least significant bits in the Initial APIC ID that indicate
>>>>>>>> core ID
>>>>>>>> within a processor, in constructing per-core CPUID masks.
>>>>>>>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of
>>>>>>>> cores
>>>>>>>> (MNC) that the processor could theoretically support, not the actual
>>>>>>>> number of
>>>>>>>> cores that are actually implemented or enabled on the processor, as
>>>>>>>> indicated
>>>>>>>> by Core::X86::Cpuid::SizeId[NC].
>>>>>>>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>>>>>>>> • ApicId[6] = Socket ID.
>>>>>>>> • ApicId[5:4] = Node ID.
>>>>>>>> • ApicId[3] = Logical CCX L3 complex ID
>>>>>>>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
>>>>>>>> {1'b0,LogicalCoreID[1:0]}
>>>>>>>
>>>>>>>
>>>>>>> After checking out all patches and some pondering, used here approach
>>>>>>> looks to me too intrusive for the task at hand especially where it
>>>>>>> comes to generic code.
>>>>>>>
>>>>>>> (Ignore till to see suggestion how to simplify without reading
>>>>>>> reasoning behind it first)
>>>>>>>
>>>>>>> Lets look for a way to simplify it a little bit.
>>>>>>>
>>>>>>> So problem we are trying to solve,
>>>>>>> 1: calculate APIC IDs based on cpu type (to e more specific: for EPYC
>>>>>>> based CPUs)
>>>>>>> 2: it depends on knowing total number of numa nodes.
>>>>>>>
>>>>>>> E
Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models
On 2/6/20 7:08 AM, Igor Mammedov wrote:
> On Wed, 5 Feb 2020 13:07:31 -0600
> Babu Moger wrote:
>
>> On 2/5/20 10:56 AM, Igor Mammedov wrote:
>>> On Wed, 5 Feb 2020 10:10:06 -0600
>>> Babu Moger wrote:
>>>
>>>> On 2/5/20 3:38 AM, Igor Mammedov wrote:
>>>>> On Tue, 4 Feb 2020 13:08:58 -0600
>>>>> Babu Moger wrote:
>>>>>
>>>>>> On 2/4/20 2:02 AM, Igor Mammedov wrote:
>>>>>>> On Mon, 3 Feb 2020 13:31:29 -0600
>>>>>>> Babu Moger wrote:
>>>>>>>
>>>>>>>> On 2/3/20 8:59 AM, Igor Mammedov wrote:
>>>>>>>>> On Tue, 03 Dec 2019 18:36:54 -0600
>>>>>>>>> Babu Moger wrote:
>>>>>>>>>
>>>>>>>>>> This series fixes APIC ID encoding problems on AMD EPYC CPUs.
>>>>>>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166data=02%7C01%7Cbabu.moger%40amd.com%7C76bf8434899b41de094f08d7ab05bdf3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637165913481441118sdata=34fZQpUjScKbbc35c7ot433HA1Rz03YG6aP1ucyGUsQ%3Dreserved=0
>>>>>>>>>>
>>>>>>>>>> Currently, the APIC ID is decoded based on the sequence
>>>>>>>>>> sockets->dies->cores->threads. This works for most standard AMD and
>>>>>>>>>> other
>>>>>>>>>> vendors' configurations, but this decoding sequence does not follow
>>>>>>>>>> that of
>>>>>>>>>> AMD's APIC ID enumeration strictly. In some cases this can cause CPU
>>>>>>>>>> topology
>>>>>>>>>> inconsistency. When booting a guest VM, the kernel tries to
>>>>>>>>>> validate the
>>>>>>>>>> topology, and finds it inconsistent with the enumeration of EPYC cpu
>>>>>>>>>> models.
>>>>>>>>>>
>>>>>>>>>> To fix the problem we need to build the topology as per the Processor
>>>>>>>>>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>>>>>>>>>> Processors. It is available at
>>>>>>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zipdata=02%7C01%7Cbabu.moger%40amd.com%7C76bf8434899b41de094f08d7ab05bdf3%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637165913481451075sdata=4YXG%2BrCP5UUXcCQX4Ly8B%2FXdlvZoFrPCgonjy0IwG0U%3Dreserved=0
>>>>>>>>>>
>>>>>>>>>> Here is the text from the PPR.
>>>>>>>>>> Operating systems are expected to use
>>>>>>>>>> Core::X86::Cpuid::SizeId[ApicIdSize], the
>>>>>>>>>> number of least significant bits in the Initial APIC ID that
>>>>>>>>>> indicate core ID
>>>>>>>>>> within a processor, in constructing per-core CPUID masks.
>>>>>>>>>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number
>>>>>>>>>> of cores
>>>>>>>>>> (MNC) that the processor could theoretically support, not the actual
>>>>>>>>>> number of
>>>>>>>>>> cores that are actually implemented or enabled on the processor, as
>>>>>>>>>> indicated
>>>>>>>>>> by Core::X86::Cpuid::SizeId[NC].
>>>>>>>>>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>>>>>>>>>> • ApicId[6] = Socket ID.
>>>>>>>>>> • ApicId[5:4] = Node ID.
>>>>>>>>>> • ApicId[3] = Logical CCX L3 complex ID
>>>>>>>>>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
>>>>>>>>>> {1'b0,LogicalCoreID[1:0]}
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> After checking out all patches and some pondering, used here approach
>>>>>>>>> looks to me too intrusive for the task at hand especially where it
>>>>>>>>> comes to generic code.
>>>>>>>>>
>>>>>&g
Re: [PATCH] i386: pass CLZERO to guests with EPYC CPU model on AMD ZEN platform
On 2/6/20 9:52 AM, Eduardo Habkost wrote: > On Thu, Feb 06, 2020 at 12:00:04AM +, Moger, Babu wrote: >> [AMD Official Use Only - Internal Distribution Only] > > Considering that this was posted to qemu-devel, I'm assuming this > notice was added by accident. Yes. I noticed that after sending out the email. Please ignore that line.
Re: [PATCH] i386: pass CLZERO to guests with EPYC CPU model on AMD ZEN platform
On 2/5/20 11:53 PM, Ani Sinha wrote: > > >> On Feb 6, 2020, at 11:16 AM, Ani Sinha wrote: >> >> >> >>> On Feb 6, 2020, at 5:30 AM, Moger, Babu wrote: >>> >>> Ani, I am already working on it. >> >> Wow, I see a whole new AMD-Rome CPU model with it’s own cache info data : >> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F157314966312.23828.17684821666338093910.stgit%40naples-babu.amd.com%2Fdata=02%7C01%7CBabu.Moger%40amd.com%7Cc566dc5cf3cc407b5ee608d7aac8d9bc%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637165651955089264sdata=tlafWD6m5%2BZ12cqd4vqJcWh0%2FIgly%2FPVMgAbjxK5Mog%3Dreserved=0 > > Do you think the ROME specific guest cpu cache data will have significant > impact on performance? I have not done performance benchmarks myself. Yes. Rome is expected to perform better than its previous generations.
Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models
On 2/3/20 8:59 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:36:54 -0600
> Babu Moger wrote:
>
>> This series fixes APIC ID encoding problems on AMD EPYC CPUs.
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166data=02%7C01%7Cbabu.moger%40amd.com%7C50685202e372472d7b2c08d7a8b9afa6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637163387802886193sdata=N%2FaBBZ8G3D1gCNvabVQ%2FraHvINazcVeEc9FWdxQAWmg%3Dreserved=0
>>
>> Currently, the APIC ID is decoded based on the sequence
>> sockets->dies->cores->threads. This works for most standard AMD and other
>> vendors' configurations, but this decoding sequence does not follow that of
>> AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology
>> inconsistency. When booting a guest VM, the kernel tries to validate the
>> topology, and finds it inconsistent with the enumeration of EPYC cpu models.
>>
>> To fix the problem we need to build the topology as per the Processor
>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>> Processors. It is available at
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zipdata=02%7C01%7Cbabu.moger%40amd.com%7C50685202e372472d7b2c08d7a8b9afa6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637163387802886193sdata=McjyMS3A3x5Jr57VxJmHDyh5jumdybzW%2FwLtE4FAKHQ%3Dreserved=0
>>
>> Here is the text from the PPR.
>> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize],
>> the
>> number of least significant bits in the Initial APIC ID that indicate core ID
>> within a processor, in constructing per-core CPUID masks.
>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
>> (MNC) that the processor could theoretically support, not the actual number
>> of
>> cores that are actually implemented or enabled on the processor, as indicated
>> by Core::X86::Cpuid::SizeId[NC].
>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>> • ApicId[6] = Socket ID.
>> • ApicId[5:4] = Node ID.
>> • ApicId[3] = Logical CCX L3 complex ID
>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
>> {1'b0,LogicalCoreID[1:0]}
>
>
> After checking out all patches and some pondering, used here approach
> looks to me too intrusive for the task at hand especially where it
> comes to generic code.
>
> (Ignore till to see suggestion how to simplify without reading
> reasoning behind it first)
>
> Lets look for a way to simplify it a little bit.
>
> So problem we are trying to solve,
> 1: calculate APIC IDs based on cpu type (to e more specific: for EPYC based
> CPUs)
> 2: it depends on knowing total number of numa nodes.
>
> Externally workflow looks like following:
> 1. user provides -smp x,sockets,cores,...,maxcpus
> that's used by possible_cpu_arch_ids() singleton to build list of
> possible CPUs (which is available to user via command
> 'hotpluggable-cpus')
>
> Hook could be called very early and possible_cpus data might be
> not complete. It builds a list of possible CPUs which user could
> modify later.
>
> 2.1 user uses "-numa cpu,node-id=x,..." or legacy "-numa
> node,node_id=x,cpus="
> options to assign cpus to nodes, which is one way or another calling
> machine_set_cpu_numa_node(). The later updates 'possible_cpus' list
> with node information. It happens early when total number of nodes
> is not available.
>
> 2.2 user does not provide explicit node mappings for CPUs.
> QEMU steps in and assigns possible cpus to nodes in
> machine_numa_finish_cpu_init()
> (using the same machine_set_cpu_numa_node()) right before calling boards
> specific machine init(). At that time total number of nodes is known.
>
> In 1 -- 2.1 cases, 'arch_id' in 'possible_cpus' list doesn't have to be
> defined before
> boards init() is run.
>
> In 2.2 case it calls get_default_cpu_node_id() ->
> x86_get_default_cpu_node_id()
> which uses arch_id calculate numa node.
> But then question is: does it have to use APIC id or could it infer 'pkg_id',
> it's after, from ms->possible_cpus->cpus[i].props data?
Not sure if I got the question right. In this case because the numa
information is not provided all the cpus are assigned to only one node.
The apic id is used here to get the correct pkg_id.
>
> With that out of the way APIC ID will be used only during board's init(),
> so board could update possible_cpus with valid APIC IDs at the start of
> x8
Re: [PATCH v3 01/18] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
On 2/3/20 9:08 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:01 -0600
> Babu Moger wrote:
>
>> Rename few data structures related to X86 topology. X86CPUTopoIDs will
>> have individual arch ids. Next patch introduces X86CPUTopoInfo which will
>> have all topology information(like cores, threads etc..).
>
> On what commit series was based on?
> (it doesn't apply to master anymore)
I used git://github.com/ehabkost/qemu.git (x86-next) to generate the
patches. It may be bit off right now.
>
>
>> Signed-off-by: Babu Moger
>> Reviewed-by: Eduardo Habkost
>> ---
>> hw/i386/pc.c | 60
>> ++--
>> include/hw/i386/topology.h | 40 +++--
>> 2 files changed, 50 insertions(+), 50 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index 51b72439b4..5bd2ffccb7 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -2212,7 +2212,7 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> int idx;
>> CPUState *cs;
>> CPUArchId *cpu_slot;
>> -X86CPUTopoInfo topo;
>> +X86CPUTopoIDs topo_ids;
>> X86CPU *cpu = X86_CPU(dev);
>> CPUX86State *env = >env;
>> MachineState *ms = MACHINE(hotplug_dev);
>> @@ -2277,12 +2277,12 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> return;
>> }
>>
>> -topo.pkg_id = cpu->socket_id;
>> -topo.die_id = cpu->die_id;
>> -topo.core_id = cpu->core_id;
>> -topo.smt_id = cpu->thread_id;
>> +topo_ids.pkg_id = cpu->socket_id;
>> +topo_ids.die_id = cpu->die_id;
>> +topo_ids.core_id = cpu->core_id;
>> +topo_ids.smt_id = cpu->thread_id;
>> cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
>> -smp_threads, );
>> +smp_threads, _ids);
>> }
>>
>> cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, );
>> @@ -2290,11 +2290,11 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> MachineState *ms = MACHINE(pcms);
>>
>> x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
>> - smp_cores, smp_threads, );
>> + smp_cores, smp_threads, _ids);
>> error_setg(errp,
>> "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
>> " APIC ID %" PRIu32 ", valid index range 0:%d",
>> -topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
>> +topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id,
>> topo_ids.smt_id,
>> cpu->apic_id, ms->possible_cpus->len - 1);
>> return;
>> }
>> @@ -2312,34 +2312,34 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> * once -smp refactoring is complete and there will be CPU private
>> * CPUState::nr_cores and CPUState::nr_threads fields instead of
>> globals */
>> x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
>> - smp_cores, smp_threads, );
>> -if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
>> + smp_cores, smp_threads, _ids);
>> +if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
>> error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
>> -" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
>> topo.pkg_id);
>> +" 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
>> topo_ids.pkg_id);
>> return;
>> }
>> -cpu->socket_id = topo.pkg_id;
>> +cpu->socket_id = topo_ids.pkg_id;
>>
>> -if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
>> +if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
>> error_setg(errp, "property die-id: %u doesn't match set apic-id:"
>> -" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
>> +" 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id,
>> topo_ids.die_id);
>> return;
>> }
>> -cpu->die_id = topo.die_id;
>> +cpu->
Re: [PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass
On 2/3/20 9:17 AM, Igor Mammedov wrote:
> On Wed, 29 Jan 2020 10:17:11 -0600
> Babu Moger wrote:
>
>> On 1/29/20 3:14 AM, Igor Mammedov wrote:
>>> On Tue, 28 Jan 2020 13:45:31 -0600
>>> Babu Moger wrote:
>>>
>>>> On 1/28/20 10:29 AM, Igor Mammedov wrote:
>>>>> On Tue, 03 Dec 2019 18:37:42 -0600
>>>>> Babu Moger wrote:
>>>>>
>>>>>> Add a new function init_apicid_fn in MachineClass to initialize the mode
>>>>>> specific handlers to decode the apic ids.
>>>>>>
>>>>>> Signed-off-by: Babu Moger
>>>>>> ---
>>>>>> include/hw/boards.h |1 +
>>>>>> vl.c|3 +++
>>>>>> 2 files changed, 4 insertions(+)
>>>>>>
>>>>>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>>>>>> index d4fab218e6..ce5aa365cb 100644
>>>>>> --- a/include/hw/boards.h
>>>>>> +++ b/include/hw/boards.h
>>>>>> @@ -238,6 +238,7 @@ struct MachineClass {
>>>>>> unsigned
>>>>>> cpu_index);
>>>>>> const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState
>>>>>> *machine);
>>>>>> int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx);
>>>>>> +void (*init_apicid_fn)(MachineState *ms);
>>>>> it's x86 specific, so why it wasn put into PCMachineClass?
>>>>
>>>> Yes. It is x86 specific for now. I tried to make it generic function so
>>>> other OSes can use it if required(like we have done in
>>>> possible_cpu_arch_ids). It initializes functions required to build the
>>>> apicid for each CPUs. We need these functions much early in the
>>>> initialization. It should be initialized before parse_numa_opts or
>>>> machine_run_board_init(in v1.c) which are called from generic context. We
>>>> cannot use PCMachineClass at this time.
>>>
>>> could you point to specific patches in this series that require
>>> apic ids being initialized before parse_numa_opts and elaborate why?
>>>
>>> we already have possible_cpu_arch_ids() which could be called very
>>> early and calculates APIC IDs in x86 case, so why not reuse it?
>>
>>
>> The current code(before this series) parses the numa information and then
>> sequentially builds the apicid. Both are done together.
>>
>> But this series separates the numa parsing and apicid generation. Numa
>> parsing is done first and after that the apicid is generated. Reason is we
>> need to know the number of numa nodes in advance to decode the apicid.
>>
>> Look at this patch.
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F157541988471.46157.6587693720990965800.stgit%40naples-babu.amd.com%2Fdata=02%7C01%7Cbabu.moger%40amd.com%7C0a643dd978f149acf9d108d7a8bc487a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637163398941923379sdata=sP2TnNaqNXRGEeQNhJMna3wyeBqN0XbNKqgsCTVDaOQ%3Dreserved=0
>>
>> static inline apic_id_t apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
>> + const X86CPUTopoIDs
>> *topo_ids)
>> +{
>> +return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
>> + (topo_ids->llc_id << apicid_llc_offset_epyc(topo_info)) |
>> + (topo_ids->die_id << apicid_die_offset(topo_info)) |
>> + (topo_ids->core_id << apicid_core_offset(topo_info)) |
>> + topo_ids->smt_id;
>> +}
>>
>>
>> The function apicid_from_topo_ids_epyc builds the apicid. New decode adds
>> llc_id(which is numa id here) to the current decoding. Other fields are
>> mostly remains same.
>
> If llc_id is the same as numa id, why not reuse CpuInstanceProperties::node-id
> instead of llc_id you are adding in previous patch 6/18?
>
I tried to use that earlier. But dropped the idea as it required some
changes. Don't remember exactly now. I am going to investigate again if we
can use the node_id for our purpose here. Will let you know if I have any
issues.
Re: [PATCH v2 0/2] Add support for 2nd generation AMD EPYC processors
Its been a while. Pinging again. Please review. On 11/7/19 12:00 PM, Moger, Babu wrote: > The following series adds the support for 2nd generation AMD EPYC Processors > on qemu guests. The model display name for 2nd generation will be EPYC-Rome. > > Also fixes few missed cpu feature bits in 1st generation EPYC models. > > The Reference documents are available at > https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf > https://www.amd.com/system/files/TechDocs/24594.pdf > > --- > v2: Used the versioned CPU models instead of machine-type-based CPU > compatibility (commented by Eduardo). > > Babu Moger (2): > i386: Add missing cpu feature bits in EPYC model > i386: Add 2nd Generation AMD EPYC processors > > > target/i386/cpu.c | 119 > +++-- > target/i386/cpu.h |2 + > 2 files changed, 116 insertions(+), 5 deletions(-) > > -- >
Re: [PATCH v3 06/18] hw/core: Add core complex id in X86CPU topology
On 1/28/20 10:31 AM, Eric Blake wrote:
> On 12/3/19 6:37 PM, Babu Moger wrote:
>> Introduce last level cache id(llc_id) in x86CPU topology. This
>> information is
>> required to build the topology in EPIC mode.
>>
>> Signed-off-by: Babu Moger
>> ---
>
>> +++ b/qapi/machine.json
>> @@ -646,9 +646,11 @@
>> # @node-id: NUMA node ID the CPU belongs to
>> # @socket-id: socket number within node/board the CPU belongs to
>> # @die-id: die number within node/board the CPU belongs to (Since 4.1)
>> -# @core-id: core number within die the CPU belongs to# @thread-id:
>> thread number within core the CPU belongs to
>> +# @llc-id: last level cache number within node/board the CPU belongs to
>> (Since 4.2)
>
> s/4.2/5.0/
Sure. Will change it. Thanks
>
>> +# @core-id: core number within die the CPU belongs to
>> +# @thread-id: thread number within core the CPU belongs to
>> #
>> -# Note: currently there are 5 properties that could be present
>> +# Note: currently there are 6 properties that could be present
>> # but management should be prepared to pass through other
>> # properties with device_add command to allow for future
>> # interface extension. This also requires the filed names to be kept in
>> @@ -660,6 +662,7 @@
>> 'data': { '*node-id': 'int',
>> '*socket-id': 'int',
>> '*die-id': 'int',
>> + '*llc-id': 'int',
>> '*core-id': 'int',
>> '*thread-id': 'int'
>> }
Re: [PATCH v3 06/18] hw/core: Add core complex id in X86CPU topology
On 1/28/20 10:27 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:35 -0600
> Babu Moger wrote:
>
>> Introduce last level cache id(llc_id) in x86CPU topology. This information
>> is
>> required to build the topology in EPIC mode.
> can you add a reference to spec here so one could look for
> detailed information about this?
Yes. Will add it next series.
>
>
>> Signed-off-by: Babu Moger
>> ---
>> hw/core/machine-hmp-cmds.c |3 +++
>> hw/core/machine.c | 13 +
>> hw/i386/pc.c | 10 ++
>> include/hw/i386/topology.h |1 +
>> qapi/machine.json |7 +--
>> target/i386/cpu.c |2 ++
>> target/i386/cpu.h |1 +
>> 7 files changed, 35 insertions(+), 2 deletions(-)
>>
>> diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
>> index cd970cc4c5..59c91d1ce1 100644
>> --- a/hw/core/machine-hmp-cmds.c
>> +++ b/hw/core/machine-hmp-cmds.c
>> @@ -90,6 +90,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict
>> *qdict)
>> if (c->has_die_id) {
>> monitor_printf(mon, "die-id: \"%" PRIu64 "\"\n", c->die_id);
>> }
>> +if (c->has_llc_id) {
>> +monitor_printf(mon, "llc-id: \"%" PRIu64 "\"\n", c->llc_id);
>> +}
>> if (c->has_core_id) {
>> monitor_printf(mon, "core-id: \"%" PRIu64 "\"\n",
>> c->core_id);
>> }
>> diff --git a/hw/core/machine.c b/hw/core/machine.c
>> index e59b181ead..ff991e6ab5 100644
>> --- a/hw/core/machine.c
>> +++ b/hw/core/machine.c
>> @@ -683,6 +683,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
>> return;
>> }
>>
>> +if (props->has_llc_id && !slot->props.has_llc_id) {
>> +error_setg(errp, "llc-id is not supported");
>> +return;
>> +}
>> +
>> /* skip slots with explicit mismatch */
>> if (props->has_thread_id && props->thread_id !=
>> slot->props.thread_id) {
>> continue;
>> @@ -696,6 +701,10 @@ void machine_set_cpu_numa_node(MachineState *machine,
>> continue;
>> }
>>
>> +if (props->has_llc_id && props->llc_id != slot->props.llc_id) {
>> +continue;
>> +}
>> +
>> if (props->has_socket_id && props->socket_id !=
>> slot->props.socket_id) {
>> continue;
>> }
>> @@ -1034,6 +1043,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
>> if (cpu->props.has_die_id) {
>> g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
>> }
>> +
>> +if (cpu->props.has_llc_id) {
>> +g_string_append_printf(s, "llc-id: %"PRId64, cpu->props.llc_id);
>> +}
>> if (cpu->props.has_core_id) {
>> if (s->len) {
>> g_string_append_printf(s, ", ");
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index 17de152a77..df5339c102 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -2294,6 +2294,7 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>>
>> topo_ids.pkg_id = cpu->socket_id;
>> topo_ids.die_id = cpu->die_id;
>> +topo_ids.llc_id = cpu->llc_id;
>> topo_ids.core_id = cpu->core_id;
>> topo_ids.smt_id = cpu->thread_id;
>> cpu->apic_id = apicid_from_topo_ids(_info, _ids);
>> @@ -2339,6 +2340,13 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> }
>> cpu->die_id = topo_ids.die_id;
>>
>> +if (cpu->llc_id != -1 && cpu->llc_id != topo_ids.llc_id) {
>> +error_setg(errp, "property llc-id: %u doesn't match set apic-id:"
>> +" 0x%x (llc-id: %u)", cpu->llc_id, cpu->apic_id,
>> topo_ids.llc_id);
>> +return;
>> +}
>> +cpu->llc_id = topo_ids.llc_id;
>> +
>> if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
>> error_setg(errp, "property core-id: %u doesn't match set apic-id:"
>> " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
&g
Re: [PATCH v3 04/18] hw/i386: Introduce initialize_topo_info to initialize X86CPUTopoInfo
Igor,
On 1/28/20 9:49 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:21 -0600
> Babu Moger wrote:
>
>> Initialize all the parameters in one function initialize_topo_info.
>>
>> Signed-off-by: Babu Moger
>> Reviewed-by: Eduardo Habkost
>> ---
>> hw/i386/pc.c | 28 +++-
>> 1 file changed, 15 insertions(+), 13 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index 8c23b1e8c9..cafbdafa76 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -866,6 +866,15 @@ static void handle_a20_line_change(void *opaque, int
>> irq, int level)
>> x86_cpu_set_a20(cpu, level);
>> }
>>
>> +static inline void initialize_topo_info(X86CPUTopoInfo *topo_info,
>> +PCMachineState *pcms,
>
> maybe use 'const'
>
>> +const MachineState *ms)
> 'ms' is the same thing as 'pcms', so why pass it around separately?
>
> you can just do
>MachineState *ms = MACHINE(pcms)
> inside of function
Yes. We can do that. Thanks
>
>> +{
>> +topo_info->dies_per_pkg = pcms->smp_dies;
>> +topo_info->cores_per_die = ms->smp.cores;
>> +topo_info->threads_per_core = ms->smp.threads;
>> +}
>> +
>> /* Calculates initial APIC ID for a specific CPU index
>> *
>> * Currently we need to be able to calculate the APIC ID from the CPU index
>> @@ -882,9 +891,7 @@ static uint32_t
>> x86_cpu_apic_id_from_index(PCMachineState *pcms,
>> uint32_t correct_id;
>> static bool warned;
>>
>> -topo_info.dies_per_pkg = pcms->smp_dies;
>> -topo_info.cores_per_die = ms->smp.cores;
>> -topo_info.threads_per_core = ms->smp.threads;
>> +initialize_topo_info(_info, pcms, ms);
>>
>> correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
>> if (pcmc->compat_apic_id_mode) {
>> @@ -2231,9 +2238,7 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> return;
>> }
>>
>> -topo_info.dies_per_pkg = pcms->smp_dies;
>> -topo_info.cores_per_die = smp_cores;
>> -topo_info.threads_per_core = smp_threads;
>> +initialize_topo_info(_info, pcms, ms);
>>
>> env->nr_dies = pcms->smp_dies;
>>
>> @@ -2702,9 +2707,7 @@ static int64_t pc_get_default_cpu_node_id(const
>> MachineState *ms, int idx)
>> PCMachineState *pcms = PC_MACHINE(ms);
>> X86CPUTopoInfo topo_info;
>>
>> - topo_info.dies_per_pkg = pcms->smp_dies;
>> - topo_info.cores_per_die = ms->smp.cores;
>> - topo_info.threads_per_core = ms->smp.threads;
>> + initialize_topo_info(_info, pcms, ms);
>>
>> assert(idx < ms->possible_cpus->len);
>> x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
>> @@ -2719,10 +2722,6 @@ static const CPUArchIdList
>> *pc_possible_cpu_arch_ids(MachineState *ms)
>> X86CPUTopoInfo topo_info;
>> int i;
>>
>> -topo_info.dies_per_pkg = pcms->smp_dies;
>> -topo_info.cores_per_die = ms->smp.cores;
>> -topo_info.threads_per_core = ms->smp.threads;
>> -
>> if (ms->possible_cpus) {
>> /*
>> * make sure that max_cpus hasn't changed since the first use, i.e.
>> @@ -2734,6 +2733,9 @@ static const CPUArchIdList
>> *pc_possible_cpu_arch_ids(MachineState *ms)
>>
>> ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
>>sizeof(CPUArchId) * max_cpus);
>> +
>> +initialize_topo_info(_info, pcms, ms);
>> +
>> ms->possible_cpus->len = max_cpus;
>> for (i = 0; i < ms->possible_cpus->len; i++) {
>> X86CPUTopoIDs topo_ids;
>>
>
Re: [PATCH v3 07/18] machine: Add a new function init_apicid_fn in MachineClass
On 1/28/20 10:29 AM, Igor Mammedov wrote:
> On Tue, 03 Dec 2019 18:37:42 -0600
> Babu Moger wrote:
>
>> Add a new function init_apicid_fn in MachineClass to initialize the mode
>> specific handlers to decode the apic ids.
>>
>> Signed-off-by: Babu Moger
>> ---
>> include/hw/boards.h |1 +
>> vl.c|3 +++
>> 2 files changed, 4 insertions(+)
>>
>> diff --git a/include/hw/boards.h b/include/hw/boards.h
>> index d4fab218e6..ce5aa365cb 100644
>> --- a/include/hw/boards.h
>> +++ b/include/hw/boards.h
>> @@ -238,6 +238,7 @@ struct MachineClass {
>> unsigned
>> cpu_index);
>> const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine);
>> int64_t (*get_default_cpu_node_id)(const MachineState *ms, int idx);
>> +void (*init_apicid_fn)(MachineState *ms);
> it's x86 specific, so why it wasn put into PCMachineClass?
Yes. It is x86 specific for now. I tried to make it generic function so
other OSes can use it if required(like we have done in
possible_cpu_arch_ids). It initializes functions required to build the
apicid for each CPUs. We need these functions much early in the
initialization. It should be initialized before parse_numa_opts or
machine_run_board_init(in v1.c) which are called from generic context. We
cannot use PCMachineClass at this time.
>
>
>> };
>>
>> /**
>> diff --git a/vl.c b/vl.c
>> index a42c24a77f..b6af604e11 100644
>> --- a/vl.c
>> +++ b/vl.c
>> @@ -4318,6 +4318,9 @@ int main(int argc, char **argv, char **envp)
>> current_machine->cpu_type = machine_class->default_cpu_type;
>> if (cpu_option) {
>> current_machine->cpu_type = parse_cpu_option(cpu_option);
>> +if (machine_class->init_apicid_fn) {
>> +machine_class->init_apicid_fn(current_machine);
>> +}
>> }
>> parse_numa_opts(current_machine);
>>
>>
>>
>
Re: [PATCH v3 00/18] APIC ID fixes for AMD EPYC CPU models
On 2/5/20 3:38 AM, Igor Mammedov wrote:
> On Tue, 4 Feb 2020 13:08:58 -0600
> Babu Moger wrote:
>
>> On 2/4/20 2:02 AM, Igor Mammedov wrote:
>>> On Mon, 3 Feb 2020 13:31:29 -0600
>>> Babu Moger wrote:
>>>
>>>> On 2/3/20 8:59 AM, Igor Mammedov wrote:
>>>>> On Tue, 03 Dec 2019 18:36:54 -0600
>>>>> Babu Moger wrote:
>>>>>
>>>>>> This series fixes APIC ID encoding problems on AMD EPYC CPUs.
>>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.redhat.com%2Fshow_bug.cgi%3Fid%3D1728166data=02%7C01%7Cbabu.moger%40amd.com%7Cdbfd059a060a4851aad908d7aa1f3532%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63716492568238sdata=P0I547X5r0s9emWu3ptIcm1U%2FhCMZmnMQOQ0IgLPzzQ%3Dreserved=0
>>>>>>
>>>>>> Currently, the APIC ID is decoded based on the sequence
>>>>>> sockets->dies->cores->threads. This works for most standard AMD and other
>>>>>> vendors' configurations, but this decoding sequence does not follow that
>>>>>> of
>>>>>> AMD's APIC ID enumeration strictly. In some cases this can cause CPU
>>>>>> topology
>>>>>> inconsistency. When booting a guest VM, the kernel tries to validate the
>>>>>> topology, and finds it inconsistent with the enumeration of EPYC cpu
>>>>>> models.
>>>>>>
>>>>>> To fix the problem we need to build the topology as per the Processor
>>>>>> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
>>>>>> Processors. It is available at
>>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F55570-B1_PUB.zipdata=02%7C01%7Cbabu.moger%40amd.com%7Cdbfd059a060a4851aad908d7aa1f3532%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63716492568238sdata=AO6m%2FEI17iLoAa3gNnRSJKJAdvBRKh0Dmbr7bCVA0us%3Dreserved=0
>>>>>>
>>>>>> Here is the text from the PPR.
>>>>>> Operating systems are expected to use
>>>>>> Core::X86::Cpuid::SizeId[ApicIdSize], the
>>>>>> number of least significant bits in the Initial APIC ID that indicate
>>>>>> core ID
>>>>>> within a processor, in constructing per-core CPUID masks.
>>>>>> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of
>>>>>> cores
>>>>>> (MNC) that the processor could theoretically support, not the actual
>>>>>> number of
>>>>>> cores that are actually implemented or enabled on the processor, as
>>>>>> indicated
>>>>>> by Core::X86::Cpuid::SizeId[NC].
>>>>>> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
>>>>>> • ApicId[6] = Socket ID.
>>>>>> • ApicId[5:4] = Node ID.
>>>>>> • ApicId[3] = Logical CCX L3 complex ID
>>>>>> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
>>>>>> {1'b0,LogicalCoreID[1:0]}
>>>>>
>>>>>
>>>>> After checking out all patches and some pondering, used here approach
>>>>> looks to me too intrusive for the task at hand especially where it
>>>>> comes to generic code.
>>>>>
>>>>> (Ignore till to see suggestion how to simplify without reading
>>>>> reasoning behind it first)
>>>>>
>>>>> Lets look for a way to simplify it a little bit.
>>>>>
>>>>> So problem we are trying to solve,
>>>>> 1: calculate APIC IDs based on cpu type (to e more specific: for EPYC
>>>>> based CPUs)
>>>>> 2: it depends on knowing total number of numa nodes.
>>>>>
>>>>> Externally workflow looks like following:
>>>>> 1. user provides -smp x,sockets,cores,...,maxcpus
>>>>> that's used by possible_cpu_arch_ids() singleton to build list of
>>>>> possible CPUs (which is available to user via command
>>>>> 'hotpluggable-cpus')
>>>>>
>>>>> Hook could be called very early and possible_cpus data might be
>>>>> not complete. It builds a list of possible CPUs which user could
>>>>> modify later.
>>>>>
>>>>> 2.1 user uses "-numa cpu,node-id=x,..." or legacy "-numa
>&g
Re: [PATCH v4 04/16] hw/i386: Introduce init_topo_info to initialize X86CPUTopoInfo
On 2/21/20 11:05 AM, Igor Mammedov wrote:
> On Thu, 13 Feb 2020 12:16:51 -0600
> Babu Moger wrote:
>
>> Initialize all the parameters in one function init_topo_info.
>
> is it possible to squash it in 2/16
>
Sure. We can do that.
>
>>
>> Move the data structure X86CPUTopoIDs and X86CPUTopoInfo into
>> x86.h.
> A reason why it's moved should be here.
Apicid functions will be part of X86MachineState data structure(patches
introduced later).These functions will use X86CPUTopoIDs and
X86CPUTopoInfo definition. Will add these details. Thanks
>
>>
>> Signed-off-by: Babu Moger
>> Reviewed-by: Eduardo Habkost
>> ---
>> hw/i386/pc.c |4 +---
>> hw/i386/x86.c | 14 +++---
>> include/hw/i386/topology.h | 26 ++
>> include/hw/i386/x86.h | 17 +
>> 4 files changed, 31 insertions(+), 30 deletions(-)
>>
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index 2adf7f6afa..9803413dd9 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -1749,9 +1749,7 @@ static void pc_cpu_pre_plug(HotplugHandler
>> *hotplug_dev,
>> return;
>> }
>>
>> -topo_info.dies_per_pkg = x86ms->smp_dies;
>> -topo_info.cores_per_die = smp_cores;
>> -topo_info.threads_per_core = smp_threads;
>> +init_topo_info(_info, x86ms);
>>
>> env->nr_dies = x86ms->smp_dies;
>>
>> diff --git a/hw/i386/x86.c b/hw/i386/x86.c
>> index f18cab8e5c..083effb2f5 100644
>> --- a/hw/i386/x86.c
>> +++ b/hw/i386/x86.c
>> @@ -63,15 +63,12 @@ static size_t pvh_start_addr;
>> uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms,
>> unsigned int cpu_index)
>> {
>> -MachineState *ms = MACHINE(x86ms);
>> X86MachineClass *x86mc = X86_MACHINE_GET_CLASS(x86ms);
>> X86CPUTopoInfo topo_info;
>> uint32_t correct_id;
>> static bool warned;
>>
>> -topo_info.dies_per_pkg = x86ms->smp_dies;
>> -topo_info.cores_per_die = ms->smp.cores;
>> -topo_info.threads_per_core = ms->smp.threads;
>> +init_topo_info(_info, x86ms);
>>
>> correct_id = x86_apicid_from_cpu_idx(_info, cpu_index);
>> if (x86mc->compat_apic_id_mode) {
>> @@ -146,10 +143,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState
>> *ms, int idx)
>> X86MachineState *x86ms = X86_MACHINE(ms);
>> X86CPUTopoInfo topo_info;
>>
>> - topo_info.dies_per_pkg = x86ms->smp_dies;
>> - topo_info.cores_per_die = ms->smp.cores;
>> - topo_info.threads_per_core = ms->smp.threads;
>> -
>> + init_topo_info(_info, x86ms);
>>
>> assert(idx < ms->possible_cpus->len);
>> x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
>> @@ -177,9 +171,7 @@ const CPUArchIdList
>> *x86_possible_cpu_arch_ids(MachineState *ms)
>>sizeof(CPUArchId) * max_cpus);
>> ms->possible_cpus->len = max_cpus;
>>
>> -topo_info.dies_per_pkg = x86ms->smp_dies;
>> -topo_info.cores_per_die = ms->smp.cores;
>> -topo_info.threads_per_core = ms->smp.threads;
>> +init_topo_info(_info, x86ms);
>>
>> for (i = 0; i < ms->possible_cpus->len; i++) {
>> X86CPUTopoIDs topo_ids;
>> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
>> index ba52d49079..ef0ab0b6a3 100644
>> --- a/include/hw/i386/topology.h
>> +++ b/include/hw/i386/topology.h
>> @@ -40,23 +40,17 @@
>>
>>
>> #include "qemu/bitops.h"
>> +#include "hw/i386/x86.h"
>>
>> -/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
>> - */
>> -typedef uint32_t apic_id_t;
>> -
>> -typedef struct X86CPUTopoIDs {
>> -unsigned pkg_id;
>> -unsigned die_id;
>> -unsigned core_id;
>> -unsigned smt_id;
>> -} X86CPUTopoIDs;
>> -
>> -typedef struct X86CPUTopoInfo {
>> -unsigned dies_per_pkg;
>> -unsigned cores_per_die;
>> -unsigned threads_per_core;
>> -} X86CPUTopoInfo;
>> +static inline void init_topo_info(X86CPUTopoInfo *topo_info,
>> + const X86MachineState *x86ms)
>> +{
>> +MachineState *ms = MACHINE(x86ms);
>> +
>> +topo_info->dies_per_pkg = x86ms->smp_dies;
>> +topo_info->cores_per_die = ms->
[PATCH v4 08/16] hw/386: Add EPYC mode topology decoding functions
These functions add support for building EPYC mode topology given the smp
details like numa nodes, cores, threads and sockets.
The new apic id decoding is mostly similar to current apic id decoding
except that it adds a new field llc_id when numa configured. Removes all
the hardcoded values. Subsequent patches will use these functions to build
the topology.
Following functions are added.
apicid_llc_width_epyc
apicid_llc_offset_epyc
apicid_pkg_offset_epyc
apicid_from_topo_ids_epyc
x86_topo_ids_from_idx_epyc
x86_topo_ids_from_apicid_epyc
x86_apicid_from_cpu_idx_epyc
The topology details are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors.
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 93
include/hw/i386/x86.h |1
2 files changed, 94 insertions(+)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 3158157430..d9319dc2ac 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -83,6 +83,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo
*topo_info)
return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
}
+/* Bit width of the node_id field per socket */
+static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info)
+{
+return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1));
+}
/* Bit offset of the Core_ID field
*/
static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
@@ -103,6 +108,94 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo
*topo_info)
return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
}
+#define LLC_OFFSET 3 /* Minimum LLC offset if numa configured */
+
+/* Bit offset of the node_id field */
+static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+unsigned offset = apicid_die_offset(topo_info) +
+ apicid_die_width(topo_info);
+
+if (topo_info->nodes_per_pkg) {
+return MAX(LLC_OFFSET, offset);
+} else {
+return offset;
+}
+}
+
+/* Bit offset of the Pkg_ID (socket ID) field */
+static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
+{
+return apicid_node_offset_epyc(topo_info) +
apicid_node_width_epyc(topo_info);
+}
+
+/*
+ * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
+ *
+ * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
+ */
+static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo
*topo_info,
+ const X86CPUTopoIDs
*topo_ids)
+{
+return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
+ (topo_ids->node_id << apicid_node_offset_epyc(topo_info)) |
+ (topo_ids->die_id << apicid_die_offset(topo_info)) |
+ (topo_ids->core_id << apicid_core_offset(topo_info)) |
+ topo_ids->smt_id;
+}
+
+static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info,
+ unsigned cpu_index,
+ X86CPUTopoIDs *topo_ids)
+{
+unsigned nr_nodes = MAX(topo_info->nodes_per_pkg, 1);
+unsigned nr_dies = topo_info->dies_per_pkg;
+unsigned nr_cores = topo_info->cores_per_die;
+unsigned nr_threads = topo_info->threads_per_core;
+unsigned cores_per_node = DIV_ROUND_UP((nr_dies * nr_cores * nr_threads),
+nr_nodes);
+
+topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
+topo_ids->node_id = (cpu_index / cores_per_node) % nr_nodes;
+topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
+topo_ids->core_id = cpu_index / nr_threads % nr_cores;
+topo_ids->smt_id = cpu_index % nr_threads;
+}
+
+/*
+ * Calculate thread/core/package IDs for a specific topology,
+ * based on APIC ID
+ */
+static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid,
+X86CPUTopoInfo *topo_info,
+X86CPUTopoIDs *topo_ids)
+{
+topo_ids->smt_id = apicid &
+~(0xUL << apicid_smt_width(topo_info));
+topo_ids->core_id =
+(apicid >> apicid_core_offset(topo_info)) &
+~(0xUL << apicid_core_width(topo_info));
+topo_ids->die_id =
+(apicid >> apicid_die_offset(topo_info)) &
+~(0xUL << apicid_die_width(topo_info));
+topo_ids->node_id =
+(apicid >> apicid_node_offset_epyc(topo_info)) &
+~(0xUL << apicid_node_width_epyc(topo_info));
+topo_ids->pkg_id = apicid >> apicid_pkg_offset_epyc(topo_info);
+}
+
+/*
+ *
[PATCH v4 09/16] target/i386: Cleanup and use the EPYC mode topology functions
Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 162 +++--
1 file changed, 35 insertions(+), 127 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5d6edfd09b..19675eb696 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -338,68 +338,15 @@ static void encode_cache_cpuid8006(CPUCacheInfo *l2,
}
}
-/*
- * Definitions used for building CPUID Leaf 0x801D and 0x801E
- * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
- * Define the constants to build the cpu topology. Right now, TOPOEXT
- * feature is enabled only on EPYC. So, these constants are based on
- * EPYC supported configurations. We may need to handle the cases if
- * these values change in future.
- */
-/* Maximum core complexes in a node */
-#define MAX_CCX 2
-/* Maximum cores in a core complex */
-#define MAX_CORES_IN_CCX 4
-/* Maximum cores in a node */
-#define MAX_CORES_IN_NODE 8
-/* Maximum nodes in a socket */
-#define MAX_NODES_PER_SOCKET 4
-
-/*
- * Figure out the number of nodes required to build this config.
- * Max cores in a node is 8
- */
-static int nodes_in_socket(int nr_cores)
-{
-int nodes;
-
-nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
-
- /* Hardware does not support config with 3 nodes, return 4 in that case */
-return (nodes == 3) ? 4 : nodes;
-}
-
-/*
- * Decide the number of cores in a core complex with the given nr_cores using
- * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
- * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
- * L3 cache is shared across all cores in a core complex. So, this will also
- * tell us how many cores are sharing the L3 cache.
- */
-static int cores_in_core_complex(int nr_cores)
-{
-int nodes;
-
-/* Check if we can fit all the cores in one core complex */
-if (nr_cores <= MAX_CORES_IN_CCX) {
-return nr_cores;
-}
-/* Get the number of nodes required to build this config */
-nodes = nodes_in_socket(nr_cores);
-
-/*
- * Divide the cores accros all the core complexes
- * Return rounded up value
- */
-return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
-}
-
/* Encode cache info for CPUID[801D] */
-static void encode_cache_cpuid801d(CPUCacheInfo *cache, CPUState *cs,
-uint32_t *eax, uint32_t *ebx,
-uint32_t *ecx, uint32_t *edx)
+static void encode_cache_cpuid801d(CPUCacheInfo *cache,
+ X86CPUTopoInfo *topo_info,
+ uint32_t *eax, uint32_t *ebx,
+ uint32_t *ecx, uint32_t *edx)
{
uint32_t l3_cores;
+unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
+
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
@@ -408,10 +355,13 @@ static void encode_cache_cpuid801d(CPUCacheInfo
*cache, CPUState *cs,
/* L3 is shared among multiple cores */
if (cache->level == 3) {
-l3_cores = cores_in_core_complex(cs->nr_cores);
-*eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
+l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
+ topo_info->cores_per_die *
+ topo_info->threads_per_core),
+ nodes);
+*eax |= (l3_cores - 1) << 14;
} else {
-*eax |= ((cs->nr_threads - 1) << 14);
+*eax |= ((topo_info->threads_per_core - 1) << 14);
}
assert(cache->line_size > 0);
@@ -431,55 +381,17 @@ static void encode_cache_cpuid801d(CPUCacheInfo
*cache, CPUState *cs,
(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
}
-/* Data structure to hold the configuration info for a given core index */
-struct core_topology {
-/* core complex id of the current core index */
-int ccx_id;
-/*
- * Adjusted core index for this core in the topology
- * This can be 0,1,2,3 with max 4 cores in a core complex
- */
-int core_id;
-/* Node id for this core index */
-int node_id;
-/* Number of nodes in this config */
-int num_nodes;
-};
-
-/*
- * Build the configuration closely match the EPYC hardware. Using the EPYC
- * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
- * right now. This could change in future.
- * nr_cores : Total number of cores in the config
- * core_id : Core index of the current CPU
- * topo : Data structure to hold all the config info for this core index
- */
-static void build_core_topology(int nr_c
