CVS commit: src/lib/libc/arch/mips
Module Name:src
Committed By: thorpej
Date: Thu Nov 18 04:33:20 UTC 2021
Modified Files:
src/lib/libc/arch/mips: genassym.cf
src/lib/libc/arch/mips/sys: __sigtramp2.S
Log Message:
Decorate the MIPS signal trampoline with the appropriate .cfi
directives to allow exception unwind / backtrace across a signal
handler.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/mips/genassym.cf
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/mips/sys/__sigtramp2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/mips/genassym.cf
diff -u src/lib/libc/arch/mips/genassym.cf:1.4 src/lib/libc/arch/mips/genassym.cf:1.5
--- src/lib/libc/arch/mips/genassym.cf:1.4 Thu Oct 15 05:27:53 2020
+++ src/lib/libc/arch/mips/genassym.cf Thu Nov 18 04:33:20 2021
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.4 2020/10/15 05:27:53 skrll Exp $
+# $NetBSD: genassym.cf,v 1.5 2021/11/18 04:33:20 thorpej Exp $
#
# Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -40,9 +40,46 @@ define _UC_GREGS_V0 offsetof(ucontext_t,
define _UC_GREGS_GP offsetof(ucontext_t, uc_mcontext.__gregs[_REG_GP])
define _UC_GREGS_SP offsetof(ucontext_t, uc_mcontext.__gregs[_REG_SP])
define _UC_GREGS_EPC offsetof(ucontext_t, uc_mcontext.__gregs[_REG_EPC])
+define _UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0])
define _UC_LINK offsetof(ucontext_t, uc_link)
define UCONTEXT_SIZE sizeof(ucontext_t)
+define _REG_R0 _REG_R0
+define _REG_AT _REG_AT
+define _REG_V0 _REG_V0
+define _REG_V1 _REG_V1
+define _REG_A0 _REG_A0
+define _REG_A1 _REG_A1
+define _REG_A2 _REG_A2
+define _REG_A3 _REG_A3
+define _REG_T0 _REG_T0
+define _REG_T1 _REG_T1
+define _REG_T2 _REG_T2
+define _REG_T3 _REG_T3
+define _REG_T4 _REG_T4
+define _REG_T5 _REG_T5
+define _REG_T6 _REG_T6
+define _REG_T7 _REG_T7
+define _REG_S0 _REG_S0
+define _REG_S1 _REG_S1
+define _REG_S2 _REG_S2
+define _REG_S3 _REG_S3
+define _REG_S4 _REG_S4
+define _REG_S5 _REG_S5
+define _REG_S6 _REG_S6
+define _REG_S7 _REG_S7
+define _REG_T8 _REG_T8
+define _REG_T9 _REG_T9
+define _REG_K0 _REG_K0
+define _REG_K1 _REG_K1
+define _REG_GP _REG_GP
+define _REG_SP _REG_SP
+define _REG_S8 _REG_S8
+define _REG_RA _REG_RA
+define _REG_EPC _REG_EPC
+define _REG_MDLO _REG_MDLO
+define _REG_MDHI _REG_MDHI
+
define _SC_REGS offsetof(struct sigcontext, sc_regs[0])
define _SC_REGS_V0 offsetof(struct sigcontext, sc_regs[_R_V0])
define _SC_REGS_S0 offsetof(struct sigcontext, sc_regs[_R_S0])
Index: src/lib/libc/arch/mips/sys/__sigtramp2.S
diff -u src/lib/libc/arch/mips/sys/__sigtramp2.S:1.3 src/lib/libc/arch/mips/sys/__sigtramp2.S:1.4
--- src/lib/libc/arch/mips/sys/__sigtramp2.S:1.3 Mon Dec 14 01:07:42 2009
+++ src/lib/libc/arch/mips/sys/__sigtramp2.S Thu Nov 18 04:33:20 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.3 2009/12/14 01:07:42 matt Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.4 2021/11/18 04:33:20 thorpej Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "assym.h"
#if defined(SYSLIBC_SCCS) && !defined(lint)
- RCSID("$NetBSD: __sigtramp2.S,v 1.3 2009/12/14 01:07:42 matt Exp $")
+ RCSID("$NetBSD: __sigtramp2.S,v 1.4 2021/11/18 04:33:20 thorpej Exp $")
#endif /* SYSLIBC_SCCS and not lint */
@@ -43,12 +43,80 @@
*
* On entry, stack looks like:
*
- * sp -> siginfo_t structure
- * sp + SIGINFO_SIZE -> ucontext_t structure
+ * ucontext structure sp + sizeof(siginfo_t)
+ * sp-> siginfo structure
+ *
+ * The DWARF register numbers for the general purpose registers are the
+ * same as the architected register numbers. For MIPS, there is a DWARF
+ * psuedo-register for signal handler return addresses, as well as for the
+ * MDLO and MDHI registers.
*/
+
+#define DWARF_MDHI_REG 64
+#define DWARF_MDLO_REG 65
+
+#if defined(__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__)
+#define DWARF_SIGRETURN_REG __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__
+#else
+#define DWARF_SIGRETURN_REG 66
+#endif
+
+#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r * SZREG
+#define CFI_OFFSET(r) CFI_OFFSET_DWARF_REG(r, r)
+
+ .text
+ .cfi_startproc
+ .cfi_signal_frame
+ .cfi_def_cfa _REG_SP, SIGINFO_SIZE + _UC_GREGS
+ CFI_OFFSET(_REG_R0)
+ CFI_OFFSET(_REG_AT)
+ CFI_OFFSET(_REG_V0)
+ CFI_OFFSET(_REG_V1)
+ CFI_OFFSET(_REG_A0)
+ CFI_OFFSET(_REG_A1)
+ CFI_OFFSET(_REG_A2)
+ CFI_OFFSET(_REG_A3)
+ CFI_OFFSET(_REG_T0)
+ CFI_OFFSET(_REG_T1)
+ CFI_OFFSET(_REG_T2)
+ CFI_OFFSET(_REG_T3)
+ CFI_OFFSET(_REG_T4)
+ CFI_OFFSET(_REG_T5)
+ CFI_OFFSET(_REG_T6)
+ CFI_OFFSET(_REG_T7)
+ CFI_OFFSET(_REG_S0)
+ CFI_OFFSET(_REG_S1)
+ CFI_OFFSET(_REG_S2)
+ CFI_OFFSET(_REG_S3)
+ CFI_OFFSET(_REG_S4)
+ CFI_OFFSET(_REG_S5)
+ CFI_OFFSET(_REG_S6)
+ CFI_OFFSET(_REG_S7)
+ CFI_OFFSET(_REG_T8)
+ CFI_OFFSET(_REG_T9)
+ CFI_OFFSET(_REG_K0)
+ CFI_OFFSET(_REG_K1)
+ CFI_OFFSET(_REG_GP)
+ CFI_OFFSET(_REG_SP)
+ CFI_OFFSET(_REG_S8)
+
CVS commit: src/lib/libc/arch/mips
Module Name:src Committed By: thorpej Date: Thu Nov 18 04:33:20 UTC 2021 Modified Files: src/lib/libc/arch/mips: genassym.cf src/lib/libc/arch/mips/sys: __sigtramp2.S Log Message: Decorate the MIPS signal trampoline with the appropriate .cfi directives to allow exception unwind / backtrace across a signal handler. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/mips/genassym.cf cvs rdiff -u -r1.3 -r1.4 src/lib/libc/arch/mips/sys/__sigtramp2.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/lib/libunwind
Module Name:src
Committed By: thorpej
Date: Thu Nov 18 04:20:11 UTC 2021
Modified Files:
src/sys/lib/libunwind: Registers.hpp
Log Message:
- Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined
by GCC for MIPS to hold the MDHI and MDLO registers, as well as the return
address where the signal trampoline will resume. XXX Same treatment is
needed for MIPS64, but not done as part of this commit.
- In the MIPS validFloatVectorRegister(), compare against the internal
register numbers, not the DWARF register numbers.
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/lib/libunwind/Registers.hpp
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/lib/libunwind/Registers.hpp
diff -u src/sys/lib/libunwind/Registers.hpp:1.28 src/sys/lib/libunwind/Registers.hpp:1.29
--- src/sys/lib/libunwind/Registers.hpp:1.28 Mon May 31 21:31:33 2021
+++ src/sys/lib/libunwind/Registers.hpp Thu Nov 18 04:20:11 2021
@@ -936,20 +936,29 @@ enum {
DWARF_MIPS_R31 = 31,
DWARF_MIPS_F0 = 32,
DWARF_MIPS_F31 = 63,
+ // DWARF Pseudo-registers used by GCC on MIPS for MD{HI,LO} and
+ // signal handler return address.
+ DWARF_MIPS_MDHI = 64,
+ DWARF_MIPS_MDLO = 65,
+ DWARF_MIPS_SIGRETURN = 66,
REGNO_MIPS_PC = 0,
REGNO_MIPS_R1 = 0,
REGNO_MIPS_R29 = 29,
REGNO_MIPS_R31 = 31,
REGNO_MIPS_F0 = 33,
- REGNO_MIPS_F31 = 64
+ REGNO_MIPS_F31 = 64,
+ // these live in other_reg[]
+ REGNO_MIPS_MDHI = 65,
+ REGNO_MIPS_MDLO = 66,
+ REGNO_MIPS_SIGRETURN = 67
};
class Registers_MIPS {
public:
enum {
-LAST_REGISTER = REGNO_MIPS_F31,
-LAST_RESTORE_REG = REGNO_MIPS_F31,
+LAST_REGISTER = REGNO_MIPS_SIGRETURN,
+LAST_RESTORE_REG = REGNO_MIPS_SIGRETURN,
RETURN_OFFSET = 0,
RETURN_MASK = 0,
};
@@ -961,21 +970,29 @@ public:
return REGNO_MIPS_R1 + (num - DWARF_MIPS_R1);
if (num >= DWARF_MIPS_F0 && num <= DWARF_MIPS_F31)
return REGNO_MIPS_F0 + (num - DWARF_MIPS_F0);
+if (num >= DWARF_MIPS_MDHI && num <= DWARF_MIPS_SIGRETURN)
+ return REGNO_MIPS_MDHI + (num - DWARF_MIPS_MDHI);
return LAST_REGISTER + 1;
}
bool validRegister(int num) const {
-return num >= REGNO_MIPS_PC && num <= REGNO_MIPS_R31;
+return (num >= REGNO_MIPS_PC && num <= REGNO_MIPS_R31) ||
+ (num >= REGNO_MIPS_MDHI && num <= REGNO_MIPS_SIGRETURN);
}
uint64_t getRegister(int num) const {
assert(validRegister(num));
+if (num >= REGNO_MIPS_MDHI && num <= REGNO_MIPS_SIGRETURN)
+ return other_reg[num - REGNO_MIPS_MDHI];
return reg[num];
}
void setRegister(int num, uint64_t value) {
assert(validRegister(num));
-reg[num] = value;
+if (num >= REGNO_MIPS_MDHI && num <= REGNO_MIPS_SIGRETURN)
+ other_reg[num - REGNO_MIPS_MDHI] = value;
+else
+ reg[num] = value;
}
uint64_t getIP() const { return reg[REGNO_MIPS_PC]; }
@@ -987,7 +1004,7 @@ public:
void setSP(uint64_t value) { reg[REGNO_MIPS_R29] = value; }
bool validFloatVectorRegister(int num) const {
-return num >= DWARF_MIPS_F0 && num <= DWARF_MIPS_F31;
+return num >= REGNO_MIPS_F0 && num <= REGNO_MIPS_F31;
}
void copyFloatVectorRegister(int num, uint64_t addr_) {
@@ -1001,6 +1018,7 @@ public:
private:
uint32_t reg[REGNO_MIPS_R31 + 1];
uint64_t fpreg[32];
+ uint32_t other_reg[3];
};
enum {
CVS commit: src/sys/lib/libunwind
Module Name:src Committed By: thorpej Date: Thu Nov 18 04:20:11 UTC 2021 Modified Files: src/sys/lib/libunwind: Registers.hpp Log Message: - Teach the LLVM-derived unwinder about the DWARF pseudo-registers defined by GCC for MIPS to hold the MDHI and MDLO registers, as well as the return address where the signal trampoline will resume. XXX Same treatment is needed for MIPS64, but not done as part of this commit. - In the MIPS validFloatVectorRegister(), compare against the internal register numbers, not the DWARF register numbers. To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29 src/sys/lib/libunwind/Registers.hpp Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/fdt
Module Name:src
Committed By: jmcneill
Date: Wed Nov 17 21:46:12 UTC 2021
Modified Files:
src/sys/arch/arm/fdt: gicv3_fdt.c
Log Message:
gicv3: add support for mbi-alias property
The mbi-alias property, if present, contains the base address of a GICD
alias frame that contains only SET/CLRSPI registers. Use this instead of
the GICD register frame if present.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/fdt/gicv3_fdt.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/fdt/gicv3_fdt.c
diff -u src/sys/arch/arm/fdt/gicv3_fdt.c:1.15 src/sys/arch/arm/fdt/gicv3_fdt.c:1.16
--- src/sys/arch/arm/fdt/gicv3_fdt.c:1.15 Wed Jan 27 03:10:19 2021
+++ src/sys/arch/arm/fdt/gicv3_fdt.c Wed Nov 17 21:46:12 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3_fdt.c,v 1.15 2021/01/27 03:10:19 thorpej Exp $ */
+/* $NetBSD: gicv3_fdt.c,v 1.16 2021/11/17 21:46:12 jmcneill Exp $ */
/*-
* Copyright (c) 2015-2018 Jared McNeill
@@ -31,7 +31,7 @@
#define _INTR_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: gicv3_fdt.c,v 1.15 2021/01/27 03:10:19 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_fdt.c,v 1.16 2021/11/17 21:46:12 jmcneill Exp $");
#include
#include
@@ -273,14 +273,18 @@ gicv3_fdt_attach_mbi(struct gicv3_fdt_so
bus_addr_t addr;
int len, frame_count;
- if (of_hasprop(sc->sc_phandle, "mbi-alias")) {
- aprint_error_dev(sc->sc_gic.sc_dev, "'mbi-alias' property not supported\n");
+ /*
+ * If a GICD alias frame containing only the SET/CLRSPI registers
+ * exists, the base address will be reported by the 'mbi-alias'
+ * property. If this doesn't exist, use the GICD register frame
+ * instead.
+ */
+ if (of_getprop_uint64(sc->sc_phandle, "mbi-alias", ) != 0 &&
+ fdtbus_get_reg(sc->sc_phandle, 0, , NULL) != 0) {
+ aprint_error_dev(sc->sc_gic.sc_dev, "couldn't find MBI register frame\n");
return;
}
- if (fdtbus_get_reg(sc->sc_phandle, 0, , NULL) != 0)
- return;
-
ranges = fdtbus_get_prop(sc->sc_phandle, "mbi-ranges", );
if (ranges == NULL) {
aprint_error_dev(sc->sc_gic.sc_dev, "missing 'mbi-ranges' property\n");
CVS commit: src/sys/arch/arm/fdt
Module Name:src Committed By: jmcneill Date: Wed Nov 17 21:46:12 UTC 2021 Modified Files: src/sys/arch/arm/fdt: gicv3_fdt.c Log Message: gicv3: add support for mbi-alias property The mbi-alias property, if present, contains the base address of a GICD alias frame that contains only SET/CLRSPI registers. Use this instead of the GICD register frame if present. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/fdt/gicv3_fdt.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/amlogic
Module Name:src Committed By: jdc Date: Wed Nov 17 11:57:27 UTC 2021 Modified Files: src/sys/arch/arm/amlogic: meson_dwmac.c Log Message: PR port-evbarm/50416 Also check the "reset_gpios", "reset-assert-us", and "reset-deassert-us" properties for ethernet MAC reset information. Makes the built-in ethernet work on Odroid C1 and Odroid C2 (with mesongxbb_pinctrl.c >= r1.3). Based on a hint from Jared. C2 tested by Martin. To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/amlogic/meson_dwmac.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/arm/amlogic
Module Name:src
Committed By: jdc
Date: Wed Nov 17 11:57:27 UTC 2021
Modified Files:
src/sys/arch/arm/amlogic: meson_dwmac.c
Log Message:
PR port-evbarm/50416
Also check the "reset_gpios", "reset-assert-us", and "reset-deassert-us"
properties for ethernet MAC reset information. Makes the built-in ethernet
work on Odroid C1 and Odroid C2 (with mesongxbb_pinctrl.c >= r1.3).
Based on a hint from Jared. C2 tested by Martin.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/amlogic/meson_dwmac.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/amlogic/meson_dwmac.c
diff -u src/sys/arch/arm/amlogic/meson_dwmac.c:1.12 src/sys/arch/arm/amlogic/meson_dwmac.c:1.13
--- src/sys/arch/arm/amlogic/meson_dwmac.c:1.12 Sun Nov 7 19:21:32 2021
+++ src/sys/arch/arm/amlogic/meson_dwmac.c Wed Nov 17 11:57:27 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_dwmac.c,v 1.12 2021/11/07 19:21:32 jmcneill Exp $ */
+/* $NetBSD: meson_dwmac.c,v 1.13 2021/11/17 11:57:27 jdc Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill
@@ -28,7 +28,7 @@
#include
-__KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.12 2021/11/07 19:21:32 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.13 2021/11/17 11:57:27 jdc Exp $");
#include
#include
@@ -70,29 +70,68 @@ meson_dwmac_reset(const int phandle)
{
struct fdtbus_gpio_pin *pin_reset;
const u_int *reset_delay_us;
+ const u_int *reset_assert_us, *reset_deassert_us, *reset_gpios;
bool reset_active_low;
int len, val;
- pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT);
- if (pin_reset == NULL)
+ /*
+ * Depending on the DTS, we need to check either the "snps,...",
+ * or the "reset-..." properties for the MAC reset information.
+ */
+
+ pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio",
+ GPIO_PIN_OUTPUT);
+ if (pin_reset != NULL) {
+
+ reset_delay_us = fdtbus_get_prop(phandle,
+ "snps,reset-delays-us", );
+ if (reset_delay_us == NULL || len != 12)
+ return ENXIO;
+
+ reset_active_low = of_hasprop(phandle, "snps,reset-active-low");
+
+ val = reset_active_low ? 1 : 0;
+
+ fdtbus_gpio_write(pin_reset, val);
+ delay(be32toh(reset_delay_us[0]));
+ fdtbus_gpio_write(pin_reset, !val);
+ delay(be32toh(reset_delay_us[1]));
+ fdtbus_gpio_write(pin_reset, val);
+ delay(be32toh(reset_delay_us[2]));
+
return 0;
+ }
+
+ pin_reset = fdtbus_gpio_acquire(phandle, "reset-gpios",
+ GPIO_PIN_OUTPUT);
+ if (pin_reset != NULL) {
+ reset_assert_us = fdtbus_get_prop(phandle,
+ "reset-assert-us", );
+ if (reset_assert_us == NULL || len != 4)
+ return ENXIO;
+ reset_deassert_us = fdtbus_get_prop(phandle,
+ "reset-deassert-us", );
+ if (reset_deassert_us == NULL || len != 4)
+ return ENXIO;
+ reset_gpios = fdtbus_get_prop(phandle,
+ "reset-gpios", );
+ if (reset_gpios == NULL || len != 12)
+ return ENXIO;
+
+ reset_active_low = be32toh(reset_gpios[2]);
+
+ val = reset_active_low ? 1 : 0;
+
+
+ fdtbus_gpio_write(pin_reset, val);
+ delay(be32toh(reset_assert_us[0]));
+ fdtbus_gpio_write(pin_reset, !val);
+ delay(be32toh(reset_deassert_us[0]));
- reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", );
- if (reset_delay_us == NULL || len != 12)
- return ENXIO;
-
- reset_active_low = of_hasprop(phandle, "snps,reset-active-low");
-
- val = reset_active_low ? 1 : 0;
-
- fdtbus_gpio_write(pin_reset, val);
- delay(be32toh(reset_delay_us[0]));
- fdtbus_gpio_write(pin_reset, !val);
- delay(be32toh(reset_delay_us[1]));
- fdtbus_gpio_write(pin_reset, val);
- delay(be32toh(reset_delay_us[2]));
+ return 0;
+ }
- return 0;
+ return ENXIO;
}
static void
CVS commit: src/sys/arch/arm/amlogic
Module Name:src Committed By: jmcneill Date: Wed Nov 17 11:31:12 UTC 2021 Modified Files: src/sys/arch/arm/amlogic: mesongxbb_pinctrl.c Log Message: Add missing GPIOZ direction / input / output register defs. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/amlogic/mesongxbb_pinctrl.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/amlogic/mesongxbb_pinctrl.c diff -u src/sys/arch/arm/amlogic/mesongxbb_pinctrl.c:1.2 src/sys/arch/arm/amlogic/mesongxbb_pinctrl.c:1.3 --- src/sys/arch/arm/amlogic/mesongxbb_pinctrl.c:1.2 Tue Feb 26 21:55:28 2019 +++ src/sys/arch/arm/amlogic/mesongxbb_pinctrl.c Wed Nov 17 11:31:12 2021 @@ -1,4 +1,4 @@ -/* $NetBSD: mesongxbb_pinctrl.c,v 1.2 2019/02/26 21:55:28 jmcneill Exp $ */ +/* $NetBSD: mesongxbb_pinctrl.c,v 1.3 2021/11/17 11:31:12 jmcneill Exp $ */ /*- * Copyright (c) 2019 Jared McNeill @@ -27,7 +27,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: mesongxbb_pinctrl.c,v 1.2 2019/02/26 21:55:28 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: mesongxbb_pinctrl.c,v 1.3 2021/11/17 11:31:12 jmcneill Exp $"); #include @@ -309,7 +309,25 @@ static const struct meson_pinctrl_gpio m CBUS_GPIO(CARD_5, 2, 25), CBUS_GPIO(CARD_6, 2, 26), - /* CARD */ + /* GPIOZ */ + CBUS_GPIO(GPIOZ_0, 3, 0), + CBUS_GPIO(GPIOZ_1, 3, 1), + CBUS_GPIO(GPIOZ_2, 3, 2), + CBUS_GPIO(GPIOZ_3, 3, 3), + CBUS_GPIO(GPIOZ_4, 3, 4), + CBUS_GPIO(GPIOZ_5, 3, 5), + CBUS_GPIO(GPIOZ_6, 3, 6), + CBUS_GPIO(GPIOZ_7, 3, 7), + CBUS_GPIO(GPIOZ_8, 3, 8), + CBUS_GPIO(GPIOZ_9, 3, 9), + CBUS_GPIO(GPIOZ_10, 3, 10), + CBUS_GPIO(GPIOZ_11, 3, 11), + CBUS_GPIO(GPIOZ_12, 3, 12), + CBUS_GPIO(GPIOZ_13, 3, 13), + CBUS_GPIO(GPIOZ_14, 3, 14), + CBUS_GPIO(GPIOZ_15, 3, 15), + + /* CLK */ CBUS_GPIO(GPIOCLK_0, 3, 28), CBUS_GPIO(GPIOCLK_1, 3, 29), CBUS_GPIO(GPIOCLK_2, 3, 30),
CVS commit: src/sys/arch/arm/amlogic
Module Name:src Committed By: jmcneill Date: Wed Nov 17 11:31:12 UTC 2021 Modified Files: src/sys/arch/arm/amlogic: mesongxbb_pinctrl.c Log Message: Add missing GPIOZ direction / input / output register defs. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/amlogic/mesongxbb_pinctrl.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
