CVS commit: othersrc/external/bsd/elex
Module Name:othersrc
Committed By: agc
Date: Thu Feb 23 19:36:08 UTC 2023
Modified Files:
othersrc/external/bsd/elex/dist: agcre.c elex.c elex.h main.c striter.c
othersrc/external/bsd/elex/dist/tests: 28.expected
Added Files:
othersrc/external/bsd/elex: namespace.mk
Log Message:
Update elex to version 20230223
+ add introspection - add a "namespace" action to elex_exec_str to return any
embedded library namespace used when compiling
+ move LIB_NAMESPACE from embedded definitions to be defined in Makefiles, and
include the makefile snippet if it exists
+ README typo fixes and added clarification from Brad Harder
+ bump version to 20230223
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 othersrc/external/bsd/elex/namespace.mk
cvs rdiff -u -r1.2 -r1.3 othersrc/external/bsd/elex/dist/agcre.c \
othersrc/external/bsd/elex/dist/elex.c \
othersrc/external/bsd/elex/dist/elex.h \
othersrc/external/bsd/elex/dist/main.c \
othersrc/external/bsd/elex/dist/striter.c
cvs rdiff -u -r1.2 -r1.3 othersrc/external/bsd/elex/dist/tests/28.expected
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: othersrc/external/bsd/elex/dist/agcre.c
diff -u othersrc/external/bsd/elex/dist/agcre.c:1.2 othersrc/external/bsd/elex/dist/agcre.c:1.3
--- othersrc/external/bsd/elex/dist/agcre.c:1.2 Wed Feb 22 01:01:39 2023
+++ othersrc/external/bsd/elex/dist/agcre.c Thu Feb 23 19:36:07 2023
@@ -36,7 +36,6 @@
#include
#include
-#define LIB_NAMESPACE elex_
#include "agcre.h"
/* callback struct */
Index: othersrc/external/bsd/elex/dist/elex.c
diff -u othersrc/external/bsd/elex/dist/elex.c:1.2 othersrc/external/bsd/elex/dist/elex.c:1.3
--- othersrc/external/bsd/elex/dist/elex.c:1.2 Wed Feb 22 01:01:39 2023
+++ othersrc/external/bsd/elex/dist/elex.c Thu Feb 23 19:36:07 2023
@@ -33,7 +33,6 @@
#include
#include
-#define LIB_NAMESPACE elex_
#include "agcre.h"
#include "striter.h"
#include "elex.h"
@@ -672,13 +671,17 @@ elex_exec(elex_t *elex, const char *info
return 0;
}
+/* used to stringify the namespace we're using */
+#define ELEX_STRINGIFY(_x) ELEX_STRINGIFY2(_x)
+#define ELEX_STRINGIFY2(_x) #_x
+
/* one function to access string values */
void *
elex_exec_str(elex_t *elex, const char *info, uint64_t n, uint64_t *size)
{
uint64_t len;
- if (elex == NULL || info == NULL) {
+ if (elex == NULL || info == NULL || size == NULL) {
return NULL;
}
switch(djbhash(info)) {
@@ -698,6 +701,9 @@ elex_exec_str(elex_t *elex, const char *
return allocate(elex->states[elex->yystate].name, strlen(elex->states[elex->yystate].name), size);
case /* "get-yytext" */ 0x88065864:
return allocate(elex->yytext, elex->yyleng, size);
+ case /* "namespace" */ 0x41041c23:
+ return allocate(ELEX_STRINGIFY(LIB_NAMESPACE),
+ strlen(ELEX_STRINGIFY(LIB_NAMESPACE)), size);
}
return NULL;
}
Index: othersrc/external/bsd/elex/dist/elex.h
diff -u othersrc/external/bsd/elex/dist/elex.h:1.2 othersrc/external/bsd/elex/dist/elex.h:1.3
--- othersrc/external/bsd/elex/dist/elex.h:1.2 Wed Feb 22 01:01:39 2023
+++ othersrc/external/bsd/elex/dist/elex.h Thu Feb 23 19:36:07 2023
@@ -23,7 +23,7 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef ELEX_H_
-#define ELEX_H_ 20230221
+#define ELEX_H_ 20230223
#include
Index: othersrc/external/bsd/elex/dist/main.c
diff -u othersrc/external/bsd/elex/dist/main.c:1.2 othersrc/external/bsd/elex/dist/main.c:1.3
--- othersrc/external/bsd/elex/dist/main.c:1.2 Wed Feb 22 01:01:39 2023
+++ othersrc/external/bsd/elex/dist/main.c Thu Feb 23 19:36:07 2023
@@ -32,7 +32,6 @@
#include
#include
-#define LIB_NAMESPACE elex_
#include "elex.h"
#define STRINGIFY(x) #x
Index: othersrc/external/bsd/elex/dist/striter.c
diff -u othersrc/external/bsd/elex/dist/striter.c:1.2 othersrc/external/bsd/elex/dist/striter.c:1.3
--- othersrc/external/bsd/elex/dist/striter.c:1.2 Wed Feb 22 01:20:52 2023
+++ othersrc/external/bsd/elex/dist/striter.c Thu Feb 23 19:36:07 2023
@@ -33,7 +33,6 @@
#include
#include
-#define LIB_NAMESPACE elex_
#include "striter.h"
/* a string iterator structure */
Index: othersrc/external/bsd/elex/dist/tests/28.expected
diff -u othersrc/external/bsd/elex/dist/tests/28.expected:1.2 othersrc/external/bsd/elex/dist/tests/28.expected:1.3
--- othersrc/external/bsd/elex/dist/tests/28.expected:1.2 Wed Feb 22 01:01:40 2023
+++ othersrc/external/bsd/elex/dist/tests/28.expected Thu Feb 23 19:36:08 2023
@@ -1 +1 @@
-elex version 20230221
+elex version 20230223
Added files:
Index: othersrc/external/bsd/elex/namespace.mk
diff -u /dev/null othersrc/external/bsd/elex/namespace.mk:1.1
--- /dev/null Thu Feb 23 19:36:08 2023
+++ othersrc/external/bsd/elex/namespace.mk Thu Feb 23 19:36:07 2023
@@ -0,0 +1 @@
+CPPFLAGS+= -DLIB_NAMESPACE="elex_"
CVS commit: othersrc/external/bsd/elex
Module Name:othersrc Committed By: agc Date: Thu Feb 23 19:36:08 UTC 2023 Modified Files: othersrc/external/bsd/elex/dist: agcre.c elex.c elex.h main.c striter.c othersrc/external/bsd/elex/dist/tests: 28.expected Added Files: othersrc/external/bsd/elex: namespace.mk Log Message: Update elex to version 20230223 + add introspection - add a "namespace" action to elex_exec_str to return any embedded library namespace used when compiling + move LIB_NAMESPACE from embedded definitions to be defined in Makefiles, and include the makefile snippet if it exists + README typo fixes and added clarification from Brad Harder + bump version to 20230223 To generate a diff of this commit: cvs rdiff -u -r0 -r1.1 othersrc/external/bsd/elex/namespace.mk cvs rdiff -u -r1.2 -r1.3 othersrc/external/bsd/elex/dist/agcre.c \ othersrc/external/bsd/elex/dist/elex.c \ othersrc/external/bsd/elex/dist/elex.h \ othersrc/external/bsd/elex/dist/main.c \ othersrc/external/bsd/elex/dist/striter.c cvs rdiff -u -r1.2 -r1.3 othersrc/external/bsd/elex/dist/tests/28.expected Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: othersrc/external/bsd/elex
Module Name:othersrc Committed By: agc Date: Thu Feb 23 19:16:31 UTC 2023 Modified Files: othersrc/external/bsd/elex: README Log Message: Fix typos and case issues, and properly hyphenate words. From Brad Harder. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 othersrc/external/bsd/elex/README Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: othersrc/external/bsd/elex
Module Name:othersrc
Committed By: agc
Date: Thu Feb 23 19:16:31 UTC 2023
Modified Files:
othersrc/external/bsd/elex: README
Log Message:
Fix typos and case issues, and properly hyphenate words. From Brad Harder.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 othersrc/external/bsd/elex/README
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: othersrc/external/bsd/elex/README
diff -u othersrc/external/bsd/elex/README:1.1 othersrc/external/bsd/elex/README:1.2
--- othersrc/external/bsd/elex/README:1.1 Thu Dec 9 04:15:25 2021
+++ othersrc/external/bsd/elex/README Thu Feb 23 19:16:31 2023
@@ -3,7 +3,7 @@ Elex - an embeddable regexp-based lexer
I have found myself fairly often needing a lexer utility to tokenise
input (for configuration files, for various file-scanning utilities,
-and for other applciations), but using full-blown lex(1) program to do
+and for other applications), but using full-blown lex(1) program to do
this is overkill, or designed for a separate process, which doesn't fit
well with the design - syntax-coloring editors, for example.
@@ -35,13 +35,13 @@ another side effect is the ability to us
such as perl escapes, UTF-8 matching, in-subexpression ignore case, etc.
elex implements start states, similar to flex. These are useful for
-recognising multiline comments (almost any language), or multi-line
+recognising multi-line comments (almost any language), or multi-line
strings (perl, python, lua etc).
elex dynamically sizes the regmatch arrays used to accommodate the
largest regexp in the input, and matching subexpressions can be
returned to the caller. The 0'th subexpression is the whole matching
-expression, and is the same as "yytext".
+expression, and is the same as "yytext" in lex(1).
And so on to an elex definition which recognises C and some C++:
@@ -81,7 +81,7 @@ And so on to an elex definition which re
#[ \t]*(define|el(se|if)|endif|error|if|ifn?def|include|line|pragma|undef)[^\n]* { return PREPROC; }
Start states are explicitly used for rules, since it is easier to read
-in practice. Elex comments are eol-style comments, beginning '#' and
+in practice. elex comments are eol-style comments, beginning '#' and
ending with '\n'. Types can be defined using the "%type" directive,
and the unsigned 32bit value they take will be returned. This is more
work than using magic constants, but much more readable in practice -
@@ -102,7 +102,7 @@ Start states can be defined using the %s
transitioned to using the BEGIN() action, in the same way as standard
lex(1).
-Elex provides bookmarks, which are numbered numerically from 0.
+elex provides bookmarks, which are numbered numerically from 0.
Assuming a mark has already been successfully created using
"set-mark", the bookmark offset can be retrieved by using its index
using "get-mark", and the user can then seek to that offset. This
@@ -300,7 +300,7 @@ return to the calling program. Since a
input, it is advised to define return types starting at 1.
Historically, in lex definitions, the user-defined types started at
256, and it was common to return ASCII values for single characters up
-to 256. Since this is no longer acceptable in a world with multibyte
+to 256. Since this is no longer acceptable in a world with multi-byte
characters, and because we tend to tokenise based on types of input
tokens, hopefully this practice will never be used again.
@@ -330,7 +330,7 @@ in this.
Usually, when tokenising programming language, there would be a number
of definitions for reserved words, and standard identifiers. There would
also be definitions for punctuation, and numeric and string constants.
-Some languages have definitions for multiline strings.
+Some languages have definitions for multi-line strings.
Alistair Croooks
Thu Nov 18 16:57:44 PST 2021
CVS commit: src/sys/kern
Module Name:src
Committed By: riastradh
Date: Thu Feb 23 14:57:29 UTC 2023
Modified Files:
src/sys/kern: kern_lock.c kern_mutex.c
Log Message:
KERNEL_LOCK(9): Minor tweaks to ci->ci_biglock_wanted access.
1. Use atomic_load_relaxed to read ci->ci_biglock_wanted from another
CPU, for clarity and to avoid the appearance of data races in thread
sanitizers. (Reading ci->ci_biglock_wanted on the local CPU need
not be atomic because no other CPU can be writing to it.)
2. Use atomic_store_relaxed to update ci->ci_biglock_wanted when we
start to spin, to avoid the appearance of data races.
3. Add comments to explain what's going on and cross-reference the
specific matching membars in mutex_vector_enter.
related to PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.182 -r1.183 src/sys/kern/kern_lock.c
cvs rdiff -u -r1.102 -r1.103 src/sys/kern/kern_mutex.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/kern/kern_lock.c
diff -u src/sys/kern/kern_lock.c:1.182 src/sys/kern/kern_lock.c:1.183
--- src/sys/kern/kern_lock.c:1.182 Fri Jan 27 09:28:41 2023
+++ src/sys/kern/kern_lock.c Thu Feb 23 14:57:29 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: kern_lock.c,v 1.182 2023/01/27 09:28:41 ozaki-r Exp $ */
+/* $NetBSD: kern_lock.c,v 1.183 2023/02/23 14:57:29 riastradh Exp $ */
/*-
* Copyright (c) 2002, 2006, 2007, 2008, 2009, 2020 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: kern_lock.c,v 1.182 2023/01/27 09:28:41 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: kern_lock.c,v 1.183 2023/02/23 14:57:29 riastradh Exp $");
#ifdef _KERNEL_OPT
#include "opt_lockdebug.h"
@@ -235,10 +235,18 @@ _kernel_lock(int nlocks)
* is required to ensure that the result of any mutex_exit()
* by the current LWP becomes visible on the bus before the set
* of ci->ci_biglock_wanted becomes visible.
+ *
+ * This membar_producer matches the membar_consumer in
+ * mutex_vector_enter.
+ *
+ * That way, if l has just released a mutex, mutex_vector_enter
+ * can't see this store ci->ci_biglock_wanted := l until it
+ * will also see the mutex_exit store mtx->mtx_owner := 0 which
+ * clears the has-waiters bit.
*/
membar_producer();
owant = ci->ci_biglock_wanted;
- ci->ci_biglock_wanted = l;
+ atomic_store_relaxed(>ci_biglock_wanted, l);
#if defined(DIAGNOSTIC) && !defined(LOCKDEBUG)
l->l_ld_wanted = __builtin_return_address(0);
#endif
@@ -286,22 +294,20 @@ _kernel_lock(int nlocks)
/*
* Now that we have kernel_lock, reset ci_biglock_wanted. This
- * store must be unbuffered (immediately visible on the bus) in
- * order for non-interlocked mutex release to work correctly.
- * It must be visible before a mutex_exit() can execute on this
- * processor.
+ * store must be visible on other CPUs before a mutex_exit() on
+ * this CPU can test the has-waiters bit.
+ *
+ * This membar_enter matches the membar_enter in
+ * mutex_vector_enter. (Yes, not membar_exit -- the legacy
+ * naming is confusing, but store-before-load usually pairs
+ * with store-before-load, in the extremely rare cases where it
+ * is used at all.)
*
- * Note: only where CAS is available in hardware will this be
- * an unbuffered write, but non-interlocked release cannot be
- * done on CPUs without CAS in hardware.
+ * That way, mutex_vector_enter can't see this store
+ * ci->ci_biglock_wanted := owant until it has set the
+ * has-waiters bit.
*/
(void)atomic_swap_ptr(>ci_biglock_wanted, owant);
-
- /*
- * Issue a memory barrier as we have acquired a lock. This also
- * prevents stores from a following mutex_exit() being reordered
- * to occur before our store to ci_biglock_wanted above.
- */
#ifndef __HAVE_ATOMIC_AS_MEMBAR
membar_enter();
#endif
Index: src/sys/kern/kern_mutex.c
diff -u src/sys/kern/kern_mutex.c:1.102 src/sys/kern/kern_mutex.c:1.103
--- src/sys/kern/kern_mutex.c:1.102 Fri Jan 27 09:28:41 2023
+++ src/sys/kern/kern_mutex.c Thu Feb 23 14:57:29 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: kern_mutex.c,v 1.102 2023/01/27 09:28:41 ozaki-r Exp $ */
+/* $NetBSD: kern_mutex.c,v 1.103 2023/02/23 14:57:29 riastradh Exp $ */
/*-
* Copyright (c) 2002, 2006, 2007, 2008, 2019 The NetBSD Foundation, Inc.
@@ -40,7 +40,7 @@
#define __MUTEX_PRIVATE
#include
-__KERNEL_RCSID(0, "$NetBSD: kern_mutex.c,v 1.102 2023/01/27 09:28:41 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: kern_mutex.c,v 1.103 2023/02/23 14:57:29 riastradh Exp $");
#include
#include
@@ -427,7 +427,7 @@ mutex_oncpu(uintptr_t owner)
if (ci && ci->ci_curlwp == l) {
/* Target is running; do we need to block? */
- return (ci->ci_biglock_wanted != l);
+ return (atomic_load_relaxed(>ci_biglock_wanted) != l);
}
/* Not running. It may be safe to block now. */
CVS commit: src/sys/kern
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:57:29 UTC 2023 Modified Files: src/sys/kern: kern_lock.c kern_mutex.c Log Message: KERNEL_LOCK(9): Minor tweaks to ci->ci_biglock_wanted access. 1. Use atomic_load_relaxed to read ci->ci_biglock_wanted from another CPU, for clarity and to avoid the appearance of data races in thread sanitizers. (Reading ci->ci_biglock_wanted on the local CPU need not be atomic because no other CPU can be writing to it.) 2. Use atomic_store_relaxed to update ci->ci_biglock_wanted when we start to spin, to avoid the appearance of data races. 3. Add comments to explain what's going on and cross-reference the specific matching membars in mutex_vector_enter. related to PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.182 -r1.183 src/sys/kern/kern_lock.c cvs rdiff -u -r1.102 -r1.103 src/sys/kern/kern_mutex.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/vax/vax
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:57:09 UTC 2023 Modified Files: src/sys/arch/vax/vax: subr.S Log Message: vax: Note where cpu_switchto needs barriers. PR kern/57240 Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not even sure how to spell store-before-load barriers on VAX, so no functional change for now. To generate a diff of this commit: cvs rdiff -u -r1.41 -r1.42 src/sys/arch/vax/vax/subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/vax/vax/subr.S diff -u src/sys/arch/vax/vax/subr.S:1.41 src/sys/arch/vax/vax/subr.S:1.42 --- src/sys/arch/vax/vax/subr.S:1.41 Mon Oct 31 20:30:23 2022 +++ src/sys/arch/vax/vax/subr.S Thu Feb 23 14:57:08 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: subr.S,v 1.41 2022/10/31 20:30:23 andvar Exp $ */ +/* $NetBSD: subr.S,v 1.42 2023/02/23 14:57:08 riastradh Exp $ */ /* * Copyright (c) 1994 Ludd, University of Lule}, Sweden. @@ -315,7 +315,9 @@ softint_process: movab softint_exit,PCB_PC(%r3)/* do a quick exit */ #ifdef MULTIPROCESSOR movl L_CPU(%r6),%r8 + /* XXX store-before-store barrier -- see cpu_switchto */ movl %r6,CI_CURLWP(%r8) + /* XXX store-before-load barrier -- see cpu_switchto */ #endif mtpr PCB_PADDR(%r3),$PR_PCBB /* restore PA of interrupted pcb */ @@ -338,7 +340,9 @@ softint_common: movl %r6,PCB_R6(%r3) /* move old lwp into new pcb */ movl %r1,PCB_R7(%r3) /* move IPL into new pcb */ #ifdef MULTIPROCESSOR + /* XXX store-before-store barrier -- see cpu_switchto */ movl %r2,CI_CURLWP(%r8) /* update ci_curlwp */ + /* XXX store-before-load barrier -- see cpu_switchto */ #endif /* @@ -404,7 +408,31 @@ JSBENTRY(Swtchto) #ifdef MULTIPROCESSOR movl L_CPU(%r0), %r8 /* get cpu_info of old lwp */ movl %r8, L_CPU(%r1) /* update cpu_info of new lwp */ + /* + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. + * + * XXX I'm fuzzy on the memory model of VAX. I would guess + * it's TSO like x86 but I can't find a store-before-load + * barrier, which is the only one TSO requires explicitly. + */ + /* XXX store-before-store barrier */ movl %r1,CI_CURLWP(%r8) /* update ci_curlwp */ + /* XXX store-before-load barrier */ #endif mtpr PCB_PADDR(%r3),$PR_PCBB # set PA of new pcb
CVS commit: src/sys/arch/vax/vax
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:57:09 UTC 2023 Modified Files: src/sys/arch/vax/vax: subr.S Log Message: vax: Note where cpu_switchto needs barriers. PR kern/57240 Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not even sure how to spell store-before-load barriers on VAX, so no functional change for now. To generate a diff of this commit: cvs rdiff -u -r1.41 -r1.42 src/sys/arch/vax/vax/subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/sparc64/sparc64
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:56 UTC 2023 Modified Files: src/sys/arch/sparc64/sparc64: locore.s Log Message: sparc64: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.431 -r1.432 src/sys/arch/sparc64/sparc64/locore.s Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/sparc64/sparc64/locore.s diff -u src/sys/arch/sparc64/sparc64/locore.s:1.431 src/sys/arch/sparc64/sparc64/locore.s:1.432 --- src/sys/arch/sparc64/sparc64/locore.s:1.431 Tue Jul 5 20:15:40 2022 +++ src/sys/arch/sparc64/sparc64/locore.s Thu Feb 23 14:56:56 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.s,v 1.431 2022/07/05 20:15:40 andvar Exp $ */ +/* $NetBSD: locore.s,v 1.432 2023/02/23 14:56:56 riastradh Exp $ */ /* * Copyright (c) 2006-2010 Matthew R. Green @@ -6731,9 +6731,28 @@ ENTRY(cpu_switchto) * Load the new lwp. To load, we must change stacks and * alter cpcb and the window control registers, hence we must * keep interrupts disabled. + * + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. */ + membar #StoreStore STPTR %i1, [%l7 + %lo(CURLWP)] ! curlwp = l; + membar #StoreLoad STPTR %l1, [%l6 + %lo(CPCB)] ! cpcb = newpcb; ldx [%l1 + PCB_SP], %i6 @@ -6826,7 +6845,9 @@ ENTRY(softint_fastintr) sethi %hi(USPACE - TF_SIZE - CC64FSZ - STKB), %o3 LDPTR [%i0 + L_PCB], %l1 ! l1 = softint pcb or %o3, %lo(USPACE - TF_SIZE - CC64FSZ - STKB), %o3 + membar #StoreStore /* for mutex_enter; see cpu_switchto */ STPTR %i0, [%l7 + %lo(CURLWP)] + membar #StoreLoad /* for mutex_enter; see cpu_switchto */ add %l1, %o3, %i6 STPTR %l1, [%l6 + %lo(CPCB)] stx %i6, [%l1 + PCB_SP] @@ -6839,7 +6860,9 @@ ENTRY(softint_fastintr) /* switch back to interrupted lwp */ ldx [%l5 + PCB_SP], %i6 + membar #StoreStore /* for mutex_enter; see cpu_switchto */ STPTR %l0, [%l7 + %lo(CURLWP)] + membar #StoreLoad /* for mutex_enter; see cpu_switchto */ STPTR %l5, [%l6 + %lo(CPCB)] restore ! rewind register window
CVS commit: src/sys/arch/sparc64/sparc64
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:56 UTC 2023 Modified Files: src/sys/arch/sparc64/sparc64: locore.s Log Message: sparc64: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.431 -r1.432 src/sys/arch/sparc64/sparc64/locore.s Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/sparc/sparc
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:37 UTC 2023 Modified Files: src/sys/arch/sparc/sparc: locore.s Log Message: sparc: Add missing barriers in cpu_switchto. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.283 -r1.284 src/sys/arch/sparc/sparc/locore.s Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/sparc/sparc
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:37 UTC 2023 Modified Files: src/sys/arch/sparc/sparc: locore.s Log Message: sparc: Add missing barriers in cpu_switchto. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.283 -r1.284 src/sys/arch/sparc/sparc/locore.s Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/sparc/sparc/locore.s diff -u src/sys/arch/sparc/sparc/locore.s:1.283 src/sys/arch/sparc/sparc/locore.s:1.284 --- src/sys/arch/sparc/sparc/locore.s:1.283 Sun May 15 02:14:15 2022 +++ src/sys/arch/sparc/sparc/locore.s Thu Feb 23 14:56:37 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: locore.s,v 1.283 2022/05/15 02:14:15 mrg Exp $ */ +/* $NetBSD: locore.s,v 1.284 2023/02/23 14:56:37 riastradh Exp $ */ /* * Copyright (c) 1996 Paul Kranenburg @@ -4889,7 +4889,30 @@ Lwb1: SAVE; SAVE; SAVE; SAVE; SAVE; SAVE /* set new cpcb, and curlwp */ sethi %hi(curlwp), %l7 st %g5, [%l6 + %lo(cpcb)] ! cpcb = newpcb; + + /* + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. + */ + /* stbar -- store-before-store, not needed on TSO */ st %g3, [%l7 + %lo(curlwp)]! curlwp = l; +#ifdef MULTIPROCESSOR + ldstub [%sp - 4], %g0 /* makeshift store-before-load barrier */ +#endif /* compute new wim */ ld [%g5 + PCB_WIM], %o0
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:23 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: riscv: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/riscv/cpu_switch.S diff -u src/sys/arch/riscv/riscv/cpu_switch.S:1.2 src/sys/arch/riscv/riscv/cpu_switch.S:1.3 --- src/sys/arch/riscv/riscv/cpu_switch.S:1.2 Sun Dec 4 16:29:35 2022 +++ src/sys/arch/riscv/riscv/cpu_switch.S Thu Feb 23 14:56:23 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu_switch.S,v 1.2 2022/12/04 16:29:35 skrll Exp $ */ +/* $NetBSD: cpu_switch.S,v 1.3 2023/02/23 14:56:23 riastradh Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -62,7 +62,28 @@ ENTRY_NP(cpu_switchto) mv tp, a1 // # put the new lwp in thread pointer PTR_L t1, L_CPU(tp) // # get curcpu + + /* + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. + */ + fence w,w PTR_S tp, CI_CURLWP(t1) // # update curcpu with the new curlwp + fence w,r REG_L sp, L_MD_KTF(tp) // # load its kernel stack pointer REG_L t4, TF_SR(sp) // # fetch status register @@ -154,14 +175,18 @@ ENTRY_NP(cpu_fast_switchto) PTR_S sp, L_MD_KTF(tp) // save trapframe ptr in oldlwp mv tp, a0 // set thread pointer to newlwp + fence w,w // for mutex_enter; see cpu_switchto PTR_S tp, CI_CURLWP(t1) // update curlwp + fence w,r // for mutex_enter; see cpu_switchto PTR_L sp, L_MD_KTF(tp) // switch to its stack csrw sstatus, t0 // reenable interrupts call _C_LABEL(softint_dispatch) csrrci t0, sstatus, SR_SIE // disable interrupts PTR_L t1, L_CPU(tp) // get curcpu() again mv tp, s0 // return to pinned lwp + fence w,w // for mutex_enter; see cpu_switchto PTR_S tp, CI_CURLWP(t1) // restore curlwp + fence w,r // for mutex_enter; see cpu_switchto csrw sstatus, t0 // reenable interrupts mv sp, s1 // restore stack pointer
CVS commit: src/sys/arch/riscv/riscv
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:23 UTC 2023 Modified Files: src/sys/arch/riscv/riscv: cpu_switch.S Log Message: riscv: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/cpu_switch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/powerpc/powerpc
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:12 UTC 2023 Modified Files: src/sys/arch/powerpc/powerpc: locore_subr.S Log Message: powerpc: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.66 -r1.67 src/sys/arch/powerpc/powerpc/locore_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/powerpc/powerpc/locore_subr.S diff -u src/sys/arch/powerpc/powerpc/locore_subr.S:1.66 src/sys/arch/powerpc/powerpc/locore_subr.S:1.67 --- src/sys/arch/powerpc/powerpc/locore_subr.S:1.66 Wed Mar 16 09:48:23 2022 +++ src/sys/arch/powerpc/powerpc/locore_subr.S Thu Feb 23 14:56:11 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: locore_subr.S,v 1.66 2022/03/16 09:48:23 andvar Exp $ */ +/* $NetBSD: locore_subr.S,v 1.67 2023/02/23 14:56:11 riastradh Exp $ */ /* * Copyright (c) 2001 Wasabi Systems, Inc. @@ -215,7 +215,32 @@ ENTRY(cpu_switchto) */ GET_CPUINFO(%r7) + + /* + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. + */ +#ifdef MULTIPROCESSOR + sync /* store-before-store XXX use eieio if available -- cheaper */ +#endif stptr %r31,CI_CURLWP(%r7) +#ifdef MULTIPROCESSOR + sync /* store-before-load */ +#endif mr %r13,%r31 #ifdef PPC_BOOKE mtsprg2 %r31 /* save curlwp in sprg2 */ @@ -389,7 +414,13 @@ _ENTRY(softint_fast_dispatch) * to a kernel thread */ +#ifdef MULTIPROCESSOR + sync /* XXX eieio */ /* for mutex_enter; see cpu_switchto */ +#endif stptr %r3, CI_CURLWP(%r7) +#ifdef MULTIPROCESSOR + sync/* for mutex_enter; see cpu_switchto */ +#endif mr %r13, %r3 #ifdef PPC_BOOKE mtsprg2 %r3 @@ -423,7 +454,13 @@ _ENTRY(softint_fast_dispatch) #endif GET_CPUINFO(%r7) +#ifdef MULTIPROCESSOR + sync /* XXX eieio */ /* for mutex_enter; see cpu_switchto */ +#endif stptr %r30, CI_CURLWP(%r7) +#ifdef MULTIPROCESSOR + sync/* for mutex_enter; see cpu_switchto */ +#endif mr %r13, %r30 #ifdef PPC_BOOKE mtsprg2 %r30
CVS commit: src/sys/arch/powerpc/powerpc
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:12 UTC 2023 Modified Files: src/sys/arch/powerpc/powerpc: locore_subr.S Log Message: powerpc: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.66 -r1.67 src/sys/arch/powerpc/powerpc/locore_subr.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch
Module Name:src
Committed By: riastradh
Date: Thu Feb 23 14:56:00 UTC 2023
Modified Files:
src/sys/arch/evbmips/ingenic: cpu_startup.S
src/sys/arch/mips/include: asm.h
src/sys/arch/mips/mips: locore.S locore_mips3.S
Log Message:
mips: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/cpu_startup.S
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/mips/include/asm.h
cvs rdiff -u -r1.228 -r1.229 src/sys/arch/mips/mips/locore.S
cvs rdiff -u -r1.115 -r1.116 src/sys/arch/mips/mips/locore_mips3.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/ingenic/cpu_startup.S
diff -u src/sys/arch/evbmips/ingenic/cpu_startup.S:1.1 src/sys/arch/evbmips/ingenic/cpu_startup.S:1.2
--- src/sys/arch/evbmips/ingenic/cpu_startup.S:1.1 Fri Jan 29 01:54:14 2016
+++ src/sys/arch/evbmips/ingenic/cpu_startup.S Thu Feb 23 14:56:00 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_startup.S,v 1.1 2016/01/29 01:54:14 macallan Exp $ */
+/* $NetBSD: cpu_startup.S,v 1.2 2023/02/23 14:56:00 riastradh Exp $ */
/*-
* Copyright (c) 2015 Michael Lorenz
@@ -33,7 +33,7 @@
#include
#include
-RCSID("$NetBSD: cpu_startup.S,v 1.1 2016/01/29 01:54:14 macallan Exp $");
+RCSID("$NetBSD: cpu_startup.S,v 1.2 2023/02/23 14:56:00 riastradh Exp $");
#ifdef MULTIPROCESSOR
@@ -56,6 +56,11 @@ NESTED_NOPROFILE(ingenic_trampoline, 0,
nop
beqz MIPS_CURLWP, 1b
nop
+ /*
+ * No membar needed because we're not switching from a
+ * previous lwp, and the idle lwp we're switching to can't be
+ * holding locks already; see cpu_switchto.
+ */
PTR_S MIPS_CURLWP, CPU_INFO_CURLWP(a0)
li v0, 0
Index: src/sys/arch/mips/include/asm.h
diff -u src/sys/arch/mips/include/asm.h:1.73 src/sys/arch/mips/include/asm.h:1.74
--- src/sys/arch/mips/include/asm.h:1.73 Mon Feb 20 13:30:47 2023
+++ src/sys/arch/mips/include/asm.h Thu Feb 23 14:56:00 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.73 2023/02/20 13:30:47 riastradh Exp $ */
+/* $NetBSD: asm.h,v 1.74 2023/02/23 14:56:00 riastradh Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -633,6 +633,28 @@ _C_LABEL(x):
#define SYNC_PLUNGER /* nothing */
#endif
+/*
+ * Store-before-load barrier. Do not use this unless you know what
+ * you're doing.
+ */
+#ifdef MULTIPROCESSOR
+#define SYNC_DEKKER sync
+#else
+#define SYNC_DEKKER /* nothing */
+#endif
+
+/*
+ * Store-before-store and load-before-load barriers. These could be
+ * made weaker than release (load/store-before-store) and acquire
+ * (load-before-load/store) barriers, and newer MIPS does have
+ * instruction encodings for finer-grained barriers like this, but I
+ * dunno how to appropriately conditionalize their use or get the
+ * assembler to be happy with them, so we'll use these definitions for
+ * now.
+ */
+#define SYNC_PRODUCER SYNC_REL
+#define SYNC_CONSUMER SYNC_ACQ
+
/* CPU dependent hook for cp0 load delays */
#if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)
#define MFC0_HAZARD sll $0,$0,1 /* super scalar nop */
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.228 src/sys/arch/mips/mips/locore.S:1.229
--- src/sys/arch/mips/mips/locore.S:1.228 Sat May 29 12:35:27 2021
+++ src/sys/arch/mips/mips/locore.S Thu Feb 23 14:56:00 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.228 2021/05/29 12:35:27 simonb Exp $ */
+/* $NetBSD: locore.S,v 1.229 2023/02/23 14:56:00 riastradh Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -63,7 +63,7 @@
#include
#include
-RCSID("$NetBSD: locore.S,v 1.228 2021/05/29 12:35:27 simonb Exp $")
+RCSID("$NetBSD: locore.S,v 1.229 2023/02/23 14:56:00 riastradh Exp $")
#include "assym.h"
@@ -286,7 +286,28 @@ NESTED(cpu_switchto, CALLFRAME_SIZ, ra)
PTR_L t2, L_CPU(MIPS_CURLWP)
nop # patchable load delay slot
+
+ /*
+ * Issue barriers to coordinate mutex_exit on this CPU with
+ * mutex_vector_enter on another CPU.
+ *
+ * 1. Any prior mutex_exit by oldlwp must be visible to other
+ *CPUs before we set ci_curlwp := newlwp on this one,
+ *requiring a store-before-store barrier.
+ *
+ * 2. ci_curlwp := newlwp must be visible on all other CPUs
+ *before any subsequent mutex_exit by newlwp can even test
+ *whether there might be waiters, requiring a
+ *store-before-load barrier.
+ *
+ * See kern_mutex.c for details -- this is necessary for
+ * adaptive mutexes to detect whether the lwp is on the CPU in
+ * order to safely block without requiring atomic r/m/w in
+ * mutex_exit.
+ */
+ SYNC_PRODUCER /* XXX fixup to nop for uniprocessor boot */
PTR_S MIPS_CURLWP, CPU_INFO_CURLWP(t2)
+ SYNC_DEKKER /* XXX fixup to nop for uniprocessor boot */
/* Check for restartable atomic sequences (RAS) */
PTR_L a0, L_PROC(MIPS_CURLWP) # argument to ras_lookup
CVS commit: src/sys/arch
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:56:00 UTC 2023 Modified Files: src/sys/arch/evbmips/ingenic: cpu_startup.S src/sys/arch/mips/include: asm.h src/sys/arch/mips/mips: locore.S locore_mips3.S Log Message: mips: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/ingenic/cpu_startup.S cvs rdiff -u -r1.73 -r1.74 src/sys/arch/mips/include/asm.h cvs rdiff -u -r1.228 -r1.229 src/sys/arch/mips/mips/locore.S cvs rdiff -u -r1.115 -r1.116 src/sys/arch/mips/mips/locore_mips3.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/ia64/ia64
Module Name:src
Committed By: riastradh
Date: Thu Feb 23 14:55:47 UTC 2023
Modified Files:
src/sys/arch/ia64/ia64: machdep.c vm_machdep.c
Log Message:
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.43 -r1.44 src/sys/arch/ia64/ia64/machdep.c
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/ia64/ia64/vm_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/ia64/ia64/machdep.c
diff -u src/sys/arch/ia64/ia64/machdep.c:1.43 src/sys/arch/ia64/ia64/machdep.c:1.44
--- src/sys/arch/ia64/ia64/machdep.c:1.43 Fri Apr 19 16:28:32 2019
+++ src/sys/arch/ia64/ia64/machdep.c Thu Feb 23 14:55:47 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.43 2019/04/19 16:28:32 scole Exp $ */
+/* $NetBSD: machdep.c,v 1.44 2023/02/23 14:55:47 riastradh Exp $ */
/*-
* Copyright (c) 2003,2004 Marcel Moolenaar
@@ -638,6 +638,10 @@ ia64_init(void)
/*
* Initialise process context. XXX: This should really be in cpu_switchto
+ *
+ * No membar needed because we're not switching from a
+ * previous lwp, and the idle lwp we're switching to can't be
+ * holding locks already; see cpu_switchto.
*/
ci->ci_curlwp =
Index: src/sys/arch/ia64/ia64/vm_machdep.c
diff -u src/sys/arch/ia64/ia64/vm_machdep.c:1.17 src/sys/arch/ia64/ia64/vm_machdep.c:1.18
--- src/sys/arch/ia64/ia64/vm_machdep.c:1.17 Sat Jan 1 21:07:14 2022
+++ src/sys/arch/ia64/ia64/vm_machdep.c Thu Feb 23 14:55:47 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: vm_machdep.c,v 1.17 2022/01/01 21:07:14 andvar Exp $ */
+/* $NetBSD: vm_machdep.c,v 1.18 2023/02/23 14:55:47 riastradh Exp $ */
/*
* Copyright (c) 2006 The NetBSD Foundation, Inc.
@@ -37,6 +37,7 @@
#include
#include
#include
+#include
#include
#include
@@ -77,9 +78,29 @@ cpu_switchto(lwp_t *oldlwp, lwp_t *newlw
register uint64_t reg9 __asm("r9");
KASSERT(newlwp != NULL);
-
+
+ /*
+ * Issue barriers to coordinate mutex_exit on this CPU with
+ * mutex_vector_enter on another CPU.
+ *
+ * 1. Any prior mutex_exit by oldlwp must be visible to other
+ *CPUs before we set ci_curlwp := newlwp on this one,
+ *requiring a store-before-store barrier.
+ *
+ * 2. ci_curlwp := newlwp must be visible on all other CPUs
+ *before any subsequent mutex_exit by newlwp can even test
+ *whether there might be waiters, requiring a
+ *store-before-load barrier.
+ *
+ * See kern_mutex.c for details -- this is necessary for
+ * adaptive mutexes to detect whether the lwp is on the CPU in
+ * order to safely block without requiring atomic r/m/w in
+ * mutex_exit.
+ */
+ membar_producer(); /* store-before-store */
ci->ci_curlwp = newlwp;
-
+ membar_sync(); /* store-before-load */
+
/* required for lwp_startup, copy oldlwp into r9, "mov r9=in0" */
__asm __volatile("mov %0=%1" : "=r"(reg9) : "r"(oldlwp));
CVS commit: src/sys/arch/ia64/ia64
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:55:47 UTC 2023 Modified Files: src/sys/arch/ia64/ia64: machdep.c vm_machdep.c Log Message: ia64: Add missing barriers in cpu_switchto. (ia64 has never really worked, so no pullups needed, right?) PR kern/57240 To generate a diff of this commit: cvs rdiff -u -r1.43 -r1.44 src/sys/arch/ia64/ia64/machdep.c cvs rdiff -u -r1.17 -r1.18 src/sys/arch/ia64/ia64/vm_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/hppa/include
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:55:36 UTC 2023 Modified Files: src/sys/arch/hppa/include: cpu.h Log Message: hppa: Add missing barriers in cpu_switchto. PR kern/57240 Not sure hppa has ever had working MULTIPROCESSOR, so maybe no pullups needed? To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/hppa/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/hppa/include
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:55:36 UTC 2023 Modified Files: src/sys/arch/hppa/include: cpu.h Log Message: hppa: Add missing barriers in cpu_switchto. PR kern/57240 Not sure hppa has ever had working MULTIPROCESSOR, so maybe no pullups needed? To generate a diff of this commit: cvs rdiff -u -r1.12 -r1.13 src/sys/arch/hppa/include/cpu.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/hppa/include/cpu.h diff -u src/sys/arch/hppa/include/cpu.h:1.12 src/sys/arch/hppa/include/cpu.h:1.13 --- src/sys/arch/hppa/include/cpu.h:1.12 Tue Nov 2 11:26:04 2021 +++ src/sys/arch/hppa/include/cpu.h Thu Feb 23 14:55:36 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.12 2021/11/02 11:26:04 ryo Exp $ */ +/* $NetBSD: cpu.h,v 1.13 2023/02/23 14:55:36 riastradh Exp $ */ /* $OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $ */ @@ -200,7 +200,26 @@ extern int cpu_revision; #define GET_CURLWP(r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(r), r #define GET_CURLWP_SPACE(s, r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(s, r), r -#define SET_CURLWP(r,t) mfctl CR_CURCPU, t ! stw r, CI_CURLWP(t) +/* + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. + */ +#define SET_CURLWP(r,t) \ + sync ! mfctl CR_CURCPU, t ! stw r, CI_CURLWP(t) ! sync #else /* MULTIPROCESSOR */
CVS commit: src/sys/arch/arm
Module Name:src
Committed By: riastradh
Date: Thu Feb 23 14:55:25 UTC 2023
Modified Files:
src/sys/arch/arm/arm: armv6_start.S
src/sys/arch/arm/arm32: cpuswitch.S
Log Message:
arm32: Add missing barriers in cpu_switchto.
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/arm/armv6_start.S
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/arm/arm32/cpuswitch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/armv6_start.S
diff -u src/sys/arch/arm/arm/armv6_start.S:1.37 src/sys/arch/arm/arm/armv6_start.S:1.38
--- src/sys/arch/arm/arm/armv6_start.S:1.37 Sun Nov 14 16:56:32 2021
+++ src/sys/arch/arm/arm/armv6_start.S Thu Feb 23 14:55:24 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.37 2021/11/14 16:56:32 riastradh Exp $ */
+/* $NetBSD: armv6_start.S,v 1.38 2023/02/23 14:55:24 riastradh Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -943,6 +943,11 @@ armv7_mpcontinuation:
#else
#error either TPIDRPRW_IS_CURCPU or TPIDRPRW_IS_CURLWP must be defined
#endif
+ /*
+ * No membar needed because we're not switching from a
+ * previous lwp, and the idle lwp we're switching to can't be
+ * holding locks already; see cpu_switchto.
+ */
str r6, [r5, #CI_CURLWP] // and note we are running on it
mov r0, r5// pass cpu_info
Index: src/sys/arch/arm/arm32/cpuswitch.S
diff -u src/sys/arch/arm/arm32/cpuswitch.S:1.105 src/sys/arch/arm/arm32/cpuswitch.S:1.106
--- src/sys/arch/arm/arm32/cpuswitch.S:1.105 Sun May 30 06:53:15 2021
+++ src/sys/arch/arm/arm32/cpuswitch.S Thu Feb 23 14:55:25 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.105 2021/05/30 06:53:15 dholland Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.106 2023/02/23 14:55:25 riastradh Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -87,7 +87,7 @@
#include
#include
- RCSID("$NetBSD: cpuswitch.S,v 1.105 2021/05/30 06:53:15 dholland Exp $")
+ RCSID("$NetBSD: cpuswitch.S,v 1.106 2023/02/23 14:55:25 riastradh Exp $")
/* LINTSTUB: include */
@@ -189,11 +189,32 @@ ENTRY(cpu_switchto)
mcr p15, 0, r6, c13, c0, 4 /* set current lwp */
#endif
+ /*
+ * Issue barriers to coordinate mutex_exit on this CPU with
+ * mutex_vector_enter on another CPU.
+ *
+ * 1. Any prior mutex_exit by oldlwp must be visible to other
+ *CPUs before we set ci_curlwp := newlwp on this one,
+ *requiring a store-before-store barrier.
+ *
+ * 2. ci_curlwp := newlwp must be visible on all other CPUs
+ *before any subsequent mutex_exit by newlwp can even test
+ *whether there might be waiters, requiring a
+ *store-before-load barrier.
+ *
+ * See kern_mutex.c for details -- this is necessary for
+ * adaptive mutexes to detect whether the lwp is on the CPU in
+ * order to safely block without requiring atomic r/m/w in
+ * mutex_exit.
+ */
+
/* We have a new curlwp now so make a note of it */
+#ifdef _ARM_ARCH_7
+ dmb/* store-before-store */
+#endif
str r6, [r5, #(CI_CURLWP)]
-
#ifdef _ARM_ARCH_7
- dmb /* see comments in kern_mutex.c */
+ dmb/* store-before-load */
#endif
/* Get the new pcb */
@@ -392,9 +413,12 @@ ENTRY_NP(softint_switch)
#if defined(TPIDRPRW_IS_CURLWP)
mcr p15, 0, r5, c13, c0, 4 /* save new lwp */
#endif
+#ifdef _ARM_ARCH_7
+ dmb/* for mutex_enter; see cpu_switchto */
+#endif
str r5, [r7, #(CI_CURLWP)] /* save new lwp */
#ifdef _ARM_ARCH_7
- dmb/* see comments in kern_mutex.c */
+ dmb/* for mutex_enter; see cpu_switchto */
#endif
#ifdef KASAN
@@ -428,7 +452,13 @@ ENTRY_NP(softint_switch)
#if defined(TPIDRPRW_IS_CURLWP)
mcr p15, 0, r4, c13, c0, 4 /* restore pinned lwp */
#endif
+#ifdef _ARM_ARCH_7
+ dmb/* for mutex_enter; see cpu_switchto */
+#endif
str r4, [r7, #(CI_CURLWP)] /* restore pinned lwp */
+#ifdef _ARM_ARCH_7
+ dmb/* for mutex_enter; see cpu_switchto */
+#endif
ldr sp, [r2, #(PCB_KSP)] /* now running on the old stack. */
/* At this point we can allow IRQ's again. */
CVS commit: src/sys/arch/arm
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:55:25 UTC 2023 Modified Files: src/sys/arch/arm/arm: armv6_start.S src/sys/arch/arm/arm32: cpuswitch.S Log Message: arm32: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.37 -r1.38 src/sys/arch/arm/arm/armv6_start.S cvs rdiff -u -r1.105 -r1.106 src/sys/arch/arm/arm32/cpuswitch.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/alpha/include
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:55:10 UTC 2023 Modified Files: src/sys/arch/alpha/include: asm.h Log Message: alpha: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.44 -r1.45 src/sys/arch/alpha/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/alpha/include/asm.h diff -u src/sys/arch/alpha/include/asm.h:1.44 src/sys/arch/alpha/include/asm.h:1.45 --- src/sys/arch/alpha/include/asm.h:1.44 Fri Sep 4 03:53:12 2020 +++ src/sys/arch/alpha/include/asm.h Thu Feb 23 14:55:10 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: asm.h,v 1.44 2020/09/04 03:53:12 thorpej Exp $ */ +/* $NetBSD: asm.h,v 1.45 2023/02/23 14:55:10 riastradh Exp $ */ /* * Copyright (c) 1991,1990,1989,1994,1995,1996 Carnegie Mellon University @@ -669,10 +669,30 @@ label: ASCIZ msg; \ #define GET_CURLWP \ call_pal PAL_OSF1_rdval +/* + * Issue barriers to coordinate mutex_exit on this CPU with + * mutex_vector_enter on another CPU. + * + * 1. Any prior mutex_exit by oldlwp must be visible to other + *CPUs before we set ci_curlwp := newlwp on this one, + *requiring a store-before-store barrier. + * + * 2. ci_curlwp := newlwp must be visible on all other CPUs + *before any subsequent mutex_exit by newlwp can even test + *whether there might be waiters, requiring a + *store-before-load barrier. + * + * See kern_mutex.c for details -- this is necessary for + * adaptive mutexes to detect whether the lwp is on the CPU in + * order to safely block without requiring atomic r/m/w in + * mutex_exit. + */ #define SET_CURLWP(r) \ ldq v0, L_CPU(r) ; \ mov r, a0 ; \ + wmb /* store-before-store XXX patch out if !MP? */ ; \ stq r, CPU_INFO_CURLWP(v0); \ + mb /* store-before-load XXX patch out if !MP? */ ; \ call_pal PAL_OSF1_wrval #else /* if not MULTIPROCESSOR... */
CVS commit: src/sys/arch/alpha/include
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:55:10 UTC 2023 Modified Files: src/sys/arch/alpha/include: asm.h Log Message: alpha: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.44 -r1.45 src/sys/arch/alpha/include/asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src
Committed By: riastradh
Date: Thu Feb 23 14:54:57 UTC 2023
Modified Files:
src/sys/arch/aarch64/aarch64: cpuswitch.S locore.S
Log Message:
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/aarch64/aarch64/cpuswitch.S
cvs rdiff -u -r1.90 -r1.91 src/sys/arch/aarch64/aarch64/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpuswitch.S
diff -u src/sys/arch/aarch64/aarch64/cpuswitch.S:1.39 src/sys/arch/aarch64/aarch64/cpuswitch.S:1.40
--- src/sys/arch/aarch64/aarch64/cpuswitch.S:1.39 Mon Sep 19 17:23:14 2022
+++ src/sys/arch/aarch64/aarch64/cpuswitch.S Thu Feb 23 14:54:57 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.39 2022/09/19 17:23:14 ryo Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.40 2023/02/23 14:54:57 riastradh Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.39 2022/09/19 17:23:14 ryo Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.40 2023/02/23 14:54:57 riastradh Exp $")
ARMV8_DEFINE_OPTIONS
@@ -125,8 +125,29 @@ ENTRY_NP(cpu_switchto)
msr tpidr_el1, x1 /* switch curlwp to new lwp */
ldr x3, [x1, #L_CPU]
+
+ /*
+ * Issue barriers to coordinate mutex_exit on this CPU with
+ * mutex_vector_enter on another CPU.
+ *
+ * 1. Any prior mutex_exit by oldlwp must be visible to other
+ *CPUs before we set ci_curlwp := newlwp on this one,
+ *requiring a store-before-store barrier.
+ *
+ * 2. ci_curlwp := newlwp must be visible on all other CPUs
+ *before any subsequent mutex_exit by newlwp can even test
+ *whether there might be waiters, requiring a
+ *store-before-load barrier.
+ *
+ * See kern_mutex.c for details -- this is necessary for
+ * adaptive mutexes to detect whether the lwp is on the CPU in
+ * order to safely block without requiring atomic r/m/w in
+ * mutex_exit.
+ */
+ dmb ishst /* store-before-store */
str x1, [x3, #CI_CURLWP] /* switch curlwp to new lwp */
- dmb ishst /* see comments in kern_mutex.c */
+ dmb ish /* store-before-load */
+
ENABLE_INTERRUPT
/*
@@ -201,8 +222,9 @@ ENTRY_NP(cpu_switchto_softint)
/* onto new stack */
sub sp, x4, #TF_SIZE /* new sp := softlwp->l_md_utf - 1 */
msr tpidr_el1, x0 /* curlwp = softlwp; */
+ dmb ishst /* for mutex_enter; see cpu_switchto */
str x0, [x20, #CI_CURLWP] /* curcpu()->ci_curlwp = softlwp; */
- /* no need for memory barrier here */
+ dmb ish /* for mutex_enter; see cpu_switchto */
mov x5, #CPACR_FPEN_NONE
msr cpacr_el1, x5 /* cpacr_el1 = CPACR_FPEN_NONE */
@@ -244,8 +266,9 @@ ENTRY_NP(cpu_switchto_softint)
DISABLE_INTERRUPT
msr tpidr_el1, x19 /* curlwp = pinned_lwp */
ldr x3, [x19, #L_CPU] /* x3 = curlwp->l_cpu */
+ dmb ishst /* for mutex_enter; see cpu_switchto */
str x19, [x3, #CI_CURLWP] /* curlwp->l_cpu->ci_curlwp := x19 */
- dmb ishst /* see comments in kern_mutex.c */
+ dmb ish /* for mutex_enter; see cpu_switchto */
mov sp, x4 /* restore pinned_lwp sp */
msr cpacr_el1, x5 /* restore pinned_lwp cpacr */
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.90 src/sys/arch/aarch64/aarch64/locore.S:1.91
--- src/sys/arch/aarch64/aarch64/locore.S:1.90 Fri Feb 17 06:24:26 2023
+++ src/sys/arch/aarch64/aarch64/locore.S Thu Feb 23 14:54:57 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.90 2023/02/17 06:24:26 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.91 2023/02/23 14:54:57 riastradh Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu
@@ -38,7 +38,7 @@
#include
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.90 2023/02/17 06:24:26 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.91 2023/02/23 14:54:57 riastradh Exp $")
#ifdef AARCH64_DEVICE_MEM_NONPOSTED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -529,6 +529,11 @@ mp_vstart:
*/
ldr x1, [x0, #CI_IDLELWP] /* x0 = curcpu()->ci_idlelwp */
msr tpidr_el1, x1 /* tpidr_el1 = curlwp = x1 */
+ /*
+ * No membar needed because we're not switching from a
+ * previous lwp, and the idle lwp we're switching to can't be
+ * holding locks already; see cpu_switchto.
+ */
str x1, [x0, #CI_CURLWP] /* curlwp is idlelwp */
/* get my stack from lwp */
CVS commit: src/sys/arch/aarch64/aarch64
Module Name:src Committed By: riastradh Date: Thu Feb 23 14:54:57 UTC 2023 Modified Files: src/sys/arch/aarch64/aarch64: cpuswitch.S locore.S Log Message: aarch64: Add missing barriers in cpu_switchto. Details in comments. Note: This is a conservative change that inserts a barrier where there was a comment saying none is needed, which is probably correct. The goal of this change is to systematically add barriers to be confident in correctness; subsequent changes may remove some bariers, as an optimization, with an explanation of why each barrier is not needed. PR kern/57240 XXX pullup-9 XXX pullup-10 To generate a diff of this commit: cvs rdiff -u -r1.39 -r1.40 src/sys/arch/aarch64/aarch64/cpuswitch.S cvs rdiff -u -r1.90 -r1.91 src/sys/arch/aarch64/aarch64/locore.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-10] src/doc
Module Name:src Committed By: martin Date: Thu Feb 23 11:49:18 UTC 2023 Modified Files: src/doc [netbsd-10]: CHANGES-10.0 Log Message: Ammend ticket #91 To generate a diff of this commit: cvs rdiff -u -r1.1.2.36 -r1.1.2.37 src/doc/CHANGES-10.0 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/doc/CHANGES-10.0 diff -u src/doc/CHANGES-10.0:1.1.2.36 src/doc/CHANGES-10.0:1.1.2.37 --- src/doc/CHANGES-10.0:1.1.2.36 Wed Feb 22 19:56:27 2023 +++ src/doc/CHANGES-10.0 Thu Feb 23 11:49:18 2023 @@ -1,4 +1,4 @@ -# $NetBSD: CHANGES-10.0,v 1.1.2.36 2023/02/22 19:56:27 martin Exp $ +# $NetBSD: CHANGES-10.0,v 1.1.2.37 2023/02/23 11:49:18 martin Exp $ A complete list of changes from the initial NetBSD 10.0 branch on 2022-12-16 until the 10.0 release: @@ -1131,7 +1131,7 @@ distrib/next68k/ramdisk/list 1.1 etc/etc.next68k/MAKEDEV.conf 1.7 etc/etc.next68k/Makefile.inc 1.8 sys/arch/next68k/conf/GENERIC 1.156-1.161 -sys/arch/next68k/conf/RAMDISK 1.5 +sys/arch/next68k/conf/RAMDISK 1.5 (manually adapted) sys/arch/next68k/conf/SLAB 1.62,1.63 sys/arch/next68k/conf/majors.next68k 1.26
CVS commit: [netbsd-10] src/doc
Module Name:src Committed By: martin Date: Thu Feb 23 11:49:18 UTC 2023 Modified Files: src/doc [netbsd-10]: CHANGES-10.0 Log Message: Ammend ticket #91 To generate a diff of this commit: cvs rdiff -u -r1.1.2.36 -r1.1.2.37 src/doc/CHANGES-10.0 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: [netbsd-10] src/sys/arch/next68k/conf
Module Name:src Committed By: martin Date: Thu Feb 23 11:48:58 UTC 2023 Modified Files: src/sys/arch/next68k/conf [netbsd-10]: RAMDISK Log Message: Remove driver not yet pressent in this branch, to fix the build after ticket #91. To generate a diff of this commit: cvs rdiff -u -r1.4.96.1 -r1.4.96.2 src/sys/arch/next68k/conf/RAMDISK Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/next68k/conf/RAMDISK diff -u src/sys/arch/next68k/conf/RAMDISK:1.4.96.1 src/sys/arch/next68k/conf/RAMDISK:1.4.96.2 --- src/sys/arch/next68k/conf/RAMDISK:1.4.96.1 Wed Feb 22 12:59:17 2023 +++ src/sys/arch/next68k/conf/RAMDISK Thu Feb 23 11:48:58 2023 @@ -1,4 +1,4 @@ -# $NetBSD: RAMDISK,v 1.4.96.1 2023/02/22 12:59:17 martin Exp $ +# $NetBSD: RAMDISK,v 1.4.96.2 2023/02/23 11:48:58 martin Exp $ # # RAMDISK: Root/swap on ramdisk @@ -190,7 +190,6 @@ sd* at scsibus? target ? lun ? # SCSI di st* at scsibus? target ? lun ? # SCSI tape drives cd* at scsibus? target ? lun ? # SCSI CD-ROM drives #ch* at scsibus? target ? lun ? # SCSI autochangers -dse* at scsibus? target ? lun ? # SCSI ethernet (Dayna) se* at scsibus? target ? lun ? # SCSI ethernet #ss* at scsibus? target ? lun ? # SCSI scanners #uk* at scsibus? target ? lun ? # SCSI unknown
CVS commit: [netbsd-10] src/sys/arch/next68k/conf
Module Name:src Committed By: martin Date: Thu Feb 23 11:48:58 UTC 2023 Modified Files: src/sys/arch/next68k/conf [netbsd-10]: RAMDISK Log Message: Remove driver not yet pressent in this branch, to fix the build after ticket #91. To generate a diff of this commit: cvs rdiff -u -r1.4.96.1 -r1.4.96.2 src/sys/arch/next68k/conf/RAMDISK Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
