CVS commit: src/sys/arch/riscv/sifive
Module Name:src Committed By: skrll Date: Sun Jan 14 07:13:15 UTC 2024 Modified Files: src/sys/arch/riscv/sifive: fu540_ccache.c Log Message: risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/fu540_ccache.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/sys/arch/riscv/sifive
Module Name:src
Committed By: skrll
Date: Sun Jan 14 07:13:15 UTC 2024
Modified Files:
src/sys/arch/riscv/sifive: fu540_ccache.c
Log Message:
risc-v: the SiFive FU[57]40 cache controller is present in the JH71x0 SoCs.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/fu540_ccache.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/sifive/fu540_ccache.c
diff -u src/sys/arch/riscv/sifive/fu540_ccache.c:1.1 src/sys/arch/riscv/sifive/fu540_ccache.c:1.2
--- src/sys/arch/riscv/sifive/fu540_ccache.c:1.1 Sat Jan 13 17:01:58 2024
+++ src/sys/arch/riscv/sifive/fu540_ccache.c Sun Jan 14 07:13:15 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $ */
+/* $NetBSD: fu540_ccache.c,v 1.2 2024/01/14 07:13:15 skrll Exp $ */
/*-
* Copyright (c) 2023 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include
-__KERNEL_RCSID(0, "$NetBSD: fu540_ccache.c,v 1.1 2024/01/13 17:01:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fu540_ccache.c,v 1.2 2024/01/14 07:13:15 skrll Exp $");
#include
@@ -75,6 +75,9 @@ __KERNEL_RCSID(0, "$NetBSD: fu540_ccache
static const struct device_compatible_entry compat_data[] = {
{ .compat = "sifive,fu540-c000-ccache" },
{ .compat = "sifive,fu740-c000-ccache" },
+ { .compat = "starfive,jh7100-ccache" },
+ { .compat = "starfive,jh7110-ccache" },
+ { .compat = "starfive,ccache0" },
DEVICE_COMPAT_EOL
};
CVS commit: src/sys/arch/riscv/sifive
Module Name:src Committed By: skrll Date: Sat Dec 3 09:40:56 UTC 2022 Modified Files: src/sys/arch/riscv/sifive: files.sifive Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/files.sifive Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/riscv/sifive/files.sifive diff -u src/sys/arch/riscv/sifive/files.sifive:1.1 src/sys/arch/riscv/sifive/files.sifive:1.2 --- src/sys/arch/riscv/sifive/files.sifive:1.1 Fri Nov 25 12:35:44 2022 +++ src/sys/arch/riscv/sifive/files.sifive Sat Dec 3 09:40:56 2022 @@ -1,10 +1,10 @@ -# $NetBSD: files.sifive,v 1.1 2022/11/25 12:35:44 jmcneill Exp $ +# $NetBSD: files.sifive,v 1.2 2022/12/03 09:40:56 skrll Exp $ # # Configuration info for SiFive SoCs # # # FU540 Power Reset Clocking Interrupt (PRCI) subsystem -device prci +device prci attach prci at fdt with fu540_prci file arch/riscv/sifive/fu540_prci.c fu540_prci
CVS commit: src/sys/arch/riscv/sifive
Module Name:src Committed By: skrll Date: Sat Dec 3 09:40:56 UTC 2022 Modified Files: src/sys/arch/riscv/sifive: files.sifive Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/files.sifive Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
