CVS commit: [matt-nb5-mips64] src/gnu/dist/binutils/opcodes
Module Name:src
Committed By: matt
Date: Wed Dec 18 18:31:22 UTC 2013
Modified Files:
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: arm-dis.c
Log Message:
Decode some armv7 instructions
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 src/gnu/dist/binutils/opcodes/arm-dis.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/opcodes/arm-dis.c
diff -u src/gnu/dist/binutils/opcodes/arm-dis.c:1.1.1.3 src/gnu/dist/binutils/opcodes/arm-dis.c:1.1.1.3.32.1
--- src/gnu/dist/binutils/opcodes/arm-dis.c:1.1.1.3 Thu Feb 2 21:14:00 2006
+++ src/gnu/dist/binutils/opcodes/arm-dis.c Wed Dec 18 18:31:22 2013
@@ -80,6 +80,7 @@
%A print address for ldc/stc/ldf/stf instruction
%m print register mask for ldm/stm instruction
%C print the PSR sub type.
+ %E print the LSB and WIDTH fields of a BFI or BFC instruction.
%F print the COUNT field of a LFM/SFM instruction.
IWMMXT specific format options:
%g print as an iWMMXt 64-bit register
@@ -118,6 +119,18 @@ static const struct arm_opcode arm_opcod
{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ /* ARM V7 instructions. */
+ {ARM_EXT_V7A, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
+ {ARM_EXT_V7A, 0x07c0001f, 0x0fa0007f, "bfc%c\t%12-15R, %E"},
+ {ARM_EXT_V7A, 0x07c00010, 0x0fa00070, "bfi%c\t%12-15R, %0-3r, %E"},
+ {ARM_EXT_V7A, 0x0300, 0x0ff0, "movw%c\t%12-15r, #%16-19,0-11d"},
+ {ARM_EXT_V7A, 0xf57ff05f, 0x, "dmb"},
+ {ARM_EXT_V7A, 0xf57ff050, 0xfff0, "dmb\t#%0-3d"},
+ {ARM_EXT_V7A, 0xf57ff05f, 0x, "dsb"},
+ {ARM_EXT_V7A, 0xf57ff050, 0xfff0, "dsb\t%#0-3d"},
+ {ARM_EXT_V7A, 0xf57ff06f, 0x, "isb"},
+ {ARM_EXT_V7A, 0xf57ff060, 0xfff0, "isb\t%#0-3d"},
+
/* ARM V6Z instructions. */
{ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"},
@@ -380,7 +393,8 @@ static const struct arm_opcode arm_opcod
{ARM_EXT_V1, 0x00e0, 0x0de0, "rsc%c%20's\t%12-15r, %16-19r, %o"},
{ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
{ARM_EXT_V3, 0x010f, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
- {ARM_EXT_V1, 0x0100, 0x0de0, "tst%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x0110, 0x0df0, "tst%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x0310, 0x0df0, "tst%c%p\t%16-19r, %o"},
{ARM_EXT_V1, 0x0120, 0x0de0, "teq%c%p\t%16-19r, %o"},
{ARM_EXT_V1, 0x0140, 0x0de0, "cmp%c%p\t%16-19r, %o"},
{ARM_EXT_V1, 0x0160, 0x0de0, "cmn%c%p\t%16-19r, %o"},
@@ -1234,6 +1248,19 @@ print_insn_arm (pc, info, given)
func (stream, "c");
break;
+ case 'E':
+ {
+ long msb = (given >> 16) & 0x1f;
+ long lsb = (given >> 7) & 0x1f;
+ long width = msb - lsb + 1;
+
+ if (width > 0)
+ func(stream, "#%lu, #%lu", lsb, width);
+ else
+ func(stream, "(invalid %lu:%lu)", lsb, msb);
+ }
+ break;
+
case 'F':
switch (given & 0x00408000)
{
@@ -1307,60 +1334,59 @@ print_insn_arm (pc, info, given)
{
int bitstart = *c++ - '0';
int bitend = 0;
+ long value = 0;
+
while (*c >= '0' && *c <= '9')
bitstart = (bitstart * 10) + *c++ - '0';
switch (*c)
{
case '-':
- c++;
+ while (*c == '-')
+ {
+c++;
+bitend = 0;
+while (*c >= '0' && *c <= '9')
+ bitend = (bitend * 10) + *c++ - '0';
- while (*c >= '0' && *c <= '9')
- bitend = (bitend * 10) + *c++ - '0';
+if (!bitend)
+ abort ();
+
+if (*c == ',')
+ {
+c++;
+value <<= (bitend - bitstart + 1);
+value |= (given & ((2 << bitend) - 1)) >> bitstart;
+
+bitstart = 0;
+while (*c >= '0' && *c <= '9')
+ bitstart = (bitstart * 10) + *c++ - '0';
+ }
+ }
- if (!bitend)
- abort ();
+ value <<= (bitend - bitstart + 1);
+ value |= (given & ((2 << bitend) - 1)) >> bitstart;
switch (*c)
{
case 'r':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "%s", arm_regnames[reg]);
+ func (stream, "%s", arm_regnames[value]);
}
break;
case 'd':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "%d", reg);
+ func (stream, "%d", value);
}
break;
case 'W':
{
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- func (stream, "%d", reg + 1);
+ func (stream, "%d", value + 1);
}
break;
case 'x':
{
- long reg;
-
- reg
CVS commit: [matt-nb5-mips64] src/gnu/dist/binutils/opcodes
Module Name:src
Committed By: matt
Date: Sat Dec 24 01:17:26 UTC 2011
Modified Files:
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: mips-opc.c
Log Message:
Add pause instruction (mips32r2 - sll $0,$0,5).
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3.32.5 -r1.1.1.3.32.6 \
src/gnu/dist/binutils/opcodes/mips-opc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/opcodes/mips-opc.c
diff -u src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.5 src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.6
--- src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.5 Fri Dec 2 10:08:44 2011
+++ src/gnu/dist/binutils/opcodes/mips-opc.c Sat Dec 24 01:17:25 2011
@@ -145,6 +145,7 @@ const struct mips_opcode mips_builtin_op
{"nop", "", 0x, 0x, 0, INSN2_ALIAS, I1 }, /* sll */
{"ssnop", "", 0x0040, 0x, 0, INSN2_ALIAS, I32|N55 }, /* sll */
{"ehb", "", 0x00c0, 0x, 0, INSN2_ALIAS, I33 }, /* sll */
+{"pause", "", 0x0140, 0x, 0, INSN2_ALIAS, I33 }, /* sll */
{"li", "t,j", 0x2400, 0xffe0, WR_t, INSN2_ALIAS, I1 }, /* addiu */
{"li", "t,i", 0x3400, 0xffe0, WR_t, INSN2_ALIAS, I1 }, /* ori */
{"li", "t,I", 0,(int) M_LI, INSN_MACRO, 0, I1 },
CVS commit: [matt-nb5-mips64] src/gnu/dist/binutils/opcodes
Module Name:src
Committed By: cliff
Date: Wed Feb 17 08:41:43 UTC 2010
Modified Files:
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: mips-opc.c
Log Message:
add RMI Coprocessor 2 ops to mips_builtin_opcodes[]
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3.32.2 -r1.1.1.3.32.3 \
src/gnu/dist/binutils/opcodes/mips-opc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/opcodes/mips-opc.c
diff -u src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.2 src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.3
--- src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.2 Mon Nov 9 17:51:53 2009
+++ src/gnu/dist/binutils/opcodes/mips-opc.c Wed Feb 17 08:41:43 2010
@@ -1200,6 +1200,11 @@
{"mtc2","t,G,H", 0x4880, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
{"mthc2", "t,i", 0x48e0, 0xffe0, COD|RD_t|WR_C2|WR_CC, 0, I33 },
+/* RMI Coprocessor 2 ops */
+{"msgsnd", "t", 0x4a01, 0xffe0, COD|RD_t|WR_C2, 0, I64 },
+{"msgld", "t", 0x4a02, 0xffe0, COD|RD_t|WR_C2, 0, I64 },
+{"msgwait", "t", 0x4a03, 0xffe0, COD|RD_t|WR_C2, 0, I64 },
+
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
CVS commit: [matt-nb5-mips64] src/gnu/dist/binutils/opcodes
Module Name:src
Committed By: matt
Date: Mon Nov 9 17:51:53 UTC 2009
Modified Files:
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: mips-opc.c
Log Message:
Fix missing bits
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3.32.1 -r1.1.1.3.32.2 \
src/gnu/dist/binutils/opcodes/mips-opc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/opcodes/mips-opc.c
diff -u src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.1 src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.2
--- src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.1 Mon Nov 9 17:38:20 2009
+++ src/gnu/dist/binutils/opcodes/mips-opc.c Mon Nov 9 17:51:53 2009
@@ -802,8 +802,8 @@
/* mthc2 is at the bottom of the table. */
{"mtc3","t,G", 0x4c80, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
{"mtc3","t,G,H",0x4c80, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
-{"mfcr","t,s", 0x7018, 0xfc3f, WR_t|RD_s, 0, I64 },
-{"mtcr","t,s", 0x7019, 0xfc3f, WR_t|RD_s, 0, I64 },
+{"mfcr","t,s", 0x7018, 0xfc00, WR_t|RD_s, 0, I64 },
+{"mtcr","t,s", 0x7019, 0xfc00, WR_t|RD_s, 0, I64 },
{"mtdr","t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
{"mthi","s", 0x0011, 0xfc1f, RD_s|WR_HI, 0, I1 },
{"mtlo","s", 0x0013, 0xfc1f, RD_s|WR_LO, 0, I1 },
CVS commit: [matt-nb5-mips64] src/gnu/dist/binutils/opcodes
Module Name:src
Committed By: matt
Date: Mon Nov 9 17:38:20 UTC 2009
Modified Files:
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: mips-opc.c
Log Message:
Add RMI mtcr/mfcr instructions.
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3 -r1.1.1.3.32.1 \
src/gnu/dist/binutils/opcodes/mips-opc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/opcodes/mips-opc.c
diff -u src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3 src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.1
--- src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3 Thu Feb 2 21:16:12 2006
+++ src/gnu/dist/binutils/opcodes/mips-opc.c Mon Nov 9 17:38:20 2009
@@ -802,6 +802,8 @@
/* mthc2 is at the bottom of the table. */
{"mtc3","t,G", 0x4c80, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
{"mtc3","t,G,H",0x4c80, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
+{"mfcr","t,s", 0x7018, 0xfc3f, WR_t|RD_s, 0, I64 },
+{"mtcr","t,s", 0x7019, 0xfc3f, WR_t|RD_s, 0, I64 },
{"mtdr","t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
{"mthi","s", 0x0011, 0xfc1f, RD_s|WR_HI, 0, I1 },
{"mtlo","s", 0x0013, 0xfc1f, RD_s|WR_LO, 0, I1 },
