envy(4): *sleep(9) -> *sleep_nsec(9)

2019-11-22 Thread Scott Cheloha
ok?

Index: envy.c
===
RCS file: /cvs/src/sys/dev/pci/envy.c,v
retrieving revision 1.79
diff -u -p -r1.79 envy.c
--- envy.c  9 May 2019 05:17:45 -   1.79
+++ envy.c  23 Nov 2019 00:40:53 -
@@ -2218,7 +2218,8 @@ envy_halt_output(void *self)
mtx_enter(_lock);
sc->oactive = 0;
if (sc->obusy) {
-   err = msleep(>obusy, _lock, PWAIT, "envyobus", 4 * 
hz);
+   err = msleep_nsec(>obusy, _lock, PWAIT, "envyobus",
+   SEC_TO_NSEC(4));
if (err)
printf("%s: output DMA halt timeout\n", DEVNAME(sc));
}
@@ -2239,7 +2240,8 @@ envy_halt_input(void *self)
mtx_enter(_lock);
sc->iactive = 0;
if (sc->ibusy) {
-   err = msleep(>ibusy, _lock, PWAIT, "envyibus", 4 * 
hz); 
+   err = msleep_nsec(>ibusy, _lock, PWAIT, "envyibus",
+   SEC_TO_NSEC(4));
if (err)
printf("%s: input DMA halt timeout\n", DEVNAME(sc));
}
@@ -2488,7 +2490,7 @@ envy_midi_close(void *self)
unsigned int reg;
 
/* wait for output fifo to drain */
-   tsleep(sc, PWAIT, "envymid", hz / 10);
+   tsleep_nsec(sc, PWAIT, "envymid", MSEC_TO_NSEC(100));
 
/* disable interrupts */
reg = envy_ccs_read(sc, ENVY_CCS_INTMASK);



cardbus(4): tsleep -> tsleep_nsec(9)

2019-11-22 Thread Scott Cheloha
ok?

Index: cardbus.c
===
RCS file: /cvs/src/sys/dev/cardbus/cardbus.c,v
retrieving revision 1.51
diff -u -p -r1.51 cardbus.c
--- cardbus.c   28 Aug 2015 00:03:53 -  1.51
+++ cardbus.c   23 Nov 2019 00:31:11 -
@@ -408,8 +408,8 @@ cardbus_attach_card(struct cardbus_softc
if (cold) { /* before kernel thread invoked */
delay(100*1000);
} else {/* thread context */
-   if (tsleep((void *)sc, PCATCH, "cardbus",
-   hz/10) != EWOULDBLOCK) {
+   if (tsleep(sc, PCATCH, "cardbus",
+   MSEC_TO_NSEC(100)) != EWOULDBLOCK) {
break;
}
}



pckbc(4): tsleep -> tsleep_nsec(9)

2019-11-22 Thread Scott Cheloha
ok?

Index: pckbc.c
===
RCS file: /cvs/src/sys/dev/ic/pckbc.c,v
retrieving revision 1.52
diff -u -p -r1.52 pckbc.c
--- pckbc.c 3 Jun 2019 16:46:49 -   1.52
+++ pckbc.c 23 Nov 2019 00:27:11 -
@@ -931,7 +931,7 @@ pckbc_enqueue_cmd(pckbc_tag_t self, pckb
if (q->polling)
res = (sync ? nc->status : 0);
else if (sync) {
-   if ((res = tsleep(nc, 0, "kbccmd", 1*hz))) {
+   if ((res = tsleep_nsec(nc, 0, "kbccmd", SEC_TO_NSEC(1 {
pckbc_cleanup(t);
} else {
/*



onewire, owtemp(4): tsleep -> tsleep_nsec(9)

2019-11-22 Thread Scott Cheloha
ok?

Index: onewire.c
===
RCS file: /cvs/src/sys/dev/onewire/onewire.c,v
retrieving revision 1.17
diff -u -p -r1.17 onewire.c
--- onewire.c   3 Apr 2017 16:10:00 -   1.17
+++ onewire.c   23 Nov 2019 00:18:24 -
@@ -39,7 +39,7 @@
 #endif
 
 #define ONEWIRE_MAXDEVS16
-#define ONEWIRE_SCANTIME   3
+#define ONEWIRE_SCANTIME   SEC_TO_NSEC(3)
 
 struct onewire_softc {
struct device   sc_dev;
@@ -121,7 +121,7 @@ onewire_detach(struct device *self, int 
sc->sc_dying = 1;
if (sc->sc_thread != NULL) {
wakeup(sc->sc_thread);
-   tsleep(>sc_dying, PWAIT, "owdt", 0);
+   tsleep_nsec(>sc_dying, PWAIT, "owdt", INFSLP);
}
 
return (config_detach_children(self, flags));
@@ -326,7 +326,7 @@ onewire_search(void *arg, u_int64_t *buf
 
while (search && count < size) {
/* XXX: yield processor */
-   tsleep(sc, PWAIT, "owscan", hz / 10);
+   tsleep_nsec(sc, PWAIT, "owscan", MSEC_TO_NSEC(100));
 
/*
 * Start new search. Go through the previous path to
@@ -400,7 +400,7 @@ onewire_thread(void *arg)
onewire_scan(sc);
if (sc->sc_flags & ONEWIRE_NO_PERIODIC_SCAN)
break;
-   tsleep(sc->sc_thread, PWAIT, "owidle", ONEWIRE_SCANTIME * hz);
+   tsleep_nsec(sc->sc_thread, PWAIT, "owidle", ONEWIRE_SCANTIME);
}
 
sc->sc_thread = NULL;
Index: owtemp.c
===
RCS file: /cvs/src/sys/dev/onewire/owtemp.c,v
retrieving revision 1.16
diff -u -p -r1.16 owtemp.c
--- owtemp.c14 Sep 2014 14:17:25 -  1.16
+++ owtemp.c23 Nov 2019 00:18:24 -
@@ -158,7 +158,7 @@ owtemp_update(void *arg)
 * at least this period.
 */
onewire_write_byte(sc->sc_onewire, DS1920_CMD_CONVERT);
-   tsleep(sc, PRIBIO, "owtemp", hz);
+   tsleep_nsec(sc, PRIBIO, "owtemp", SEC_TO_NSEC(1));
 
if (onewire_reset(sc->sc_onewire) != 0)
goto done;



misc. acpi(4): *sleep -> *sleep_nsec(9)

2019-11-22 Thread Scott Cheloha
The acpi_event_wait() loop is tricky.  I'm leaving it alone for now.

Everything else here is straightforward, though.  The acpiec(4) sleep
is adjacent to a delay of 1 microsecond so I've chosen that to replace
the current duration of 1 tick.

ok?

Index: acpi.c
===
RCS file: /cvs/src/sys/dev/acpi/acpi.c,v
retrieving revision 1.374
diff -u -p -r1.374 acpi.c
--- acpi.c  7 Sep 2019 13:46:20 -   1.374
+++ acpi.c  23 Nov 2019 00:02:15 -
@@ -2866,9 +2866,7 @@ acpi_thread(void *arg)
s = spltty();
while (sc->sc_threadwaiting) {
dnprintf(10, "acpi thread going to sleep...\n");
-   rw_exit_write(>sc_lck);
-   tsleep(sc, PWAIT, "acpi0", 0);
-   rw_enter_write(>sc_lck);
+   rwsleep_nsec(sc, >sc_lck, PWAIT, "acpi0", INFSLP);
}
sc->sc_threadwaiting = 1;
splx(s);
Index: acpiec.c
===
RCS file: /cvs/src/sys/dev/acpi/acpiec.c,v
retrieving revision 1.60
diff -u -p -r1.60 acpiec.c
--- acpiec.c2 Jul 2019 21:17:24 -   1.60
+++ acpiec.c23 Nov 2019 00:02:16 -
@@ -107,8 +107,10 @@ acpiec_wait(struct acpiec_softc *sc, uin
sc->sc_gotsci = 1;
if (cold || (stat & EC_STAT_BURST))
delay(1);
-   else
-   tsleep(, PWAIT, "acpiec", 1);
+   else {
+   tsleep_nsec(, PWAIT, "acpiec",
+   USEC_TO_NSEC(1));
+   }
}
 
dnprintf(40, "%s: EC wait_ns, stat: %b\n", DEVNAME(sc), (int)stat,
Index: dsdt.c
===
RCS file: /cvs/src/sys/dev/acpi/dsdt.c,v
retrieving revision 1.249
diff -u -p -r1.249 dsdt.c
--- dsdt.c  16 Oct 2019 01:43:50 -  1.249
+++ dsdt.c  23 Nov 2019 00:02:16 -
@@ -465,15 +465,11 @@ void
 acpi_sleep(int ms, char *reason)
 {
static int acpinowait;
-   int to = ms * hz / 1000;
 
if (cold)
delay(ms * 1000);
-   else {
-   if (to <= 0)
-   to = 1;
-   tsleep(, PWAIT, reason, to);
-   }
+   else
+   tsleep_nsec(, PWAIT, reason, MSEC_TO_NSEC(ms));
 }
 
 void
Index: tipmic.c
===
RCS file: /cvs/src/sys/dev/acpi/tipmic.c,v
retrieving revision 1.4
diff -u -p -r1.4 tipmic.c
--- tipmic.c4 Apr 2019 06:33:10 -   1.4
+++ tipmic.c23 Nov 2019 00:02:16 -
@@ -333,7 +333,8 @@ tipmic_thermal_opreg_handler(void *cooki
splx(s);
 
while (sc->sc_stat_adc == 0) {
-   if (tsleep(>sc_stat_adc, PRIBIO, "tipmic", hz)) {
+   if (tsleep_nsec(>sc_stat_adc, PRIBIO, "tipmic",
+   SEC_TO_NSEC(1))) {
printf("%s: ADC timeout\n", sc->sc_dev.dv_xname);
break;
}



Re: sysupgrade: Allow to use another directory for the sets

2019-11-22 Thread Renaud Allard



On 22/11/2019 16:38, Craig Skinner wrote:

On Tue, 19 Nov 2019 10:35:56 + Stuart Henderson wrote:

We are short on partitions, there is a hard limit (14+swap), disklabel auto
defaults already use 9, and there need to be some free for typical user use
(ports, dest for "make release", people often want a separate /var/www and/or
/var/log).


Oh, I wasn't thinking of single disk desktops, but multi-drive servers
(which have plenty partition letters available to slice disks with).

Here's another idea Stuart:-

The special directory /tmp/vi.recover/ is exempt from boot & daily purging.

Could a similar /tmp/sysupgrade/ default directory suit most situations?

/tmp/ is normally mounted separately from / /home/ /var/
And probably not encrypted, nor over NFS.



Stop trying to discuss what the default should be, this has been 
discussed long enough before sysupgrade was in base. The default in 
/home/_sysupgrade is perfectly fine.


Just like sthen, I also have /tmp on MFS on multiple servers.



smime.p7s
Description: S/MIME Cryptographic Signature


Re: ix(4) need support for X553

2019-11-22 Thread Colin Hyatt Bortner
On Thu, Nov 14, 2019, at 1:06 AM, Stuart Henderson wrote:

*snip*

> 
> I have an A2SDi-2C-HLN4F that I need to put in service soon (not so
> bothered about the ix on this box, I'm using 4xSFP+ ixl, but giving it
> a spin) - applying my merged diff (https://junkpile.org/ixgbe.diff2)
> and adding PCI_PRODUCT_INTEL_X550EM_A_1G_T_L things work so far in a
> quick test.
> 
> - MACs look sane
> 
> - no problems seen in rx/tx at 1G link speed, I haven't tried other
> speeds; looking at Linux diffs it seems it may need a little change for 10M
> 
> - haven't tried jumbos yet
> 
> - seems fairly reliable so far but tx performance is a bit poor, ~500M
> max sends from tcpbench - rx speeds are fine
> 
> - NFS works
> 
> - dmesg/pcidevs below in case they're of interest
> 

*snip*

I have a Supermicro A2SDi-8C-HLN4F and my first test with the diff was also 
positive. 

I applied to 6.6-stable sources, since that's what the target machine is 
running, 
and added PCI_PRODUCT_INTEL_X550EM_A_1G_T and [...]_A_1G_T_L to if_ix.c. 

On reboot, the four onboard interfaces were picked up. Brought one interface up 
with dhclient and ssh'd in. Will do more testing in the next week or two.

My dmesg is below.


OpenBSD 6.6-stable (GENERIC.MP) #4: Fri Nov 22 17:24:44 CET 2019
coli...@x1.colinhb.com:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 17122009088 (16328MB)
avail mem = 16590336000 (15821MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.0 @ 0x7f0c3000 (35 entries)
bios0: vendor American Megatrends Inc. version "1.1c" date 06/25/2019
bios0: Supermicro A2SDi-8C-HLN4F
acpi0 at bios0: ACPI 6.1
acpi0: sleep states S0 S4 S5
acpi0: tables DSDT FACP FPDT FIDT SPMI MCFG WDAT APIC BDAT HPET UEFI SSDT DMAR 
HEST BERT ERST EINJ WSMT
acpi0: wakeup devices XHC1(S4) OBL1(S4) LAN1(S4) PEX0(S4) LAN2(S4) LAN3(S4) 
PEX1(S4) PEX6(S4) PEX7(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimcfg0 at acpi0
acpimcfg0: addr 0xe000, bus 0-255
acpimadt0 at acpi0 addr 0xfee0: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Atom(TM) CPU C3758 @ 2.20GHz, 2200.42 MHz, 06-5f-01
cpu0: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,MD_CLEAR,IBRS,IBPB,STIBP,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu0: 2MB 64b/line 16-way L2 cache
cpu0: cannot disable silicon debug
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 25MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.2, IBE
cpu1 at mainbus0: apid 4 (application processor)
cpu1: Intel(R) Atom(TM) CPU C3758 @ 2.20GHz, 2200.02 MHz, 06-5f-01
cpu1: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,MD_CLEAR,IBRS,IBPB,STIBP,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu1: 2MB 64b/line 16-way L2 cache
cpu1: cannot disable silicon debug
cpu1: smt 0, core 2, package 0
cpu2 at mainbus0: apid 8 (application processor)
cpu2: Intel(R) Atom(TM) CPU C3758 @ 2.20GHz, 2200.01 MHz, 06-5f-01
cpu2: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,MD_CLEAR,IBRS,IBPB,STIBP,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu2: 2MB 64b/line 16-way L2 cache
cpu2: cannot disable silicon debug
cpu2: smt 0, core 4, package 0
cpu3 at mainbus0: apid 12 (application processor)
cpu3: Intel(R) Atom(TM) CPU C3758 @ 2.20GHz, 2200.01 MHz, 06-5f-01
cpu3: 
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SMEP,ERMS,MPX,RDSEED,SMAP,CLFLUSHOPT,PT,SHA,MD_CLEAR,IBRS,IBPB,STIBP,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES
cpu3: 2MB 64b/line 16-way L2 cache
cpu3: cannot disable silicon debug
cpu3: smt 0, core 6, package 0
cpu4 at mainbus0: apid 16 (application processor)
cpu4: Intel(R) Atom(TM) CPU C3758 @ 2.20GHz, 2200.01 MHz, 06-5f-01
cpu4: 

Re: sysupgrade: Allow to use another directory for the sets

2019-11-22 Thread Stuart Henderson
On 2019/11/22 15:38, Craig Skinner wrote:
> Could a similar /tmp/sysupgrade/ default directory suit most situations?

My systems with MFS /tmp say no.



Re: sysupgrade: Allow to use another directory for the sets

2019-11-22 Thread Andrew Grillet
I vote for this.


On Fri, 22 Nov 2019 at 16:12, Craig Skinner  wrote:

> On Tue, 19 Nov 2019 10:35:56 + Stuart Henderson wrote:
> > We are short on partitions, there is a hard limit (14+swap), disklabel
> auto
> > defaults already use 9, and there need to be some free for typical user
> use
> > (ports, dest for "make release", people often want a separate /var/www
> and/or
> > /var/log).
>
> Oh, I wasn't thinking of single disk desktops, but multi-drive servers
> (which have plenty partition letters available to slice disks with).
>
> Here's another idea Stuart:-
>
> The special directory /tmp/vi.recover/ is exempt from boot & daily purging.
>
> Could a similar /tmp/sysupgrade/ default directory suit most situations?
>
> /tmp/ is normally mounted separately from / /home/ /var/
> And probably not encrypted, nor over NFS.
>
> Cheers,
> --
> Craig Skinner | http://linkd.in/yGqkv7
>
>


Re: sysupgrade: Allow to use another directory for the sets

2019-11-22 Thread Craig Skinner
On Tue, 19 Nov 2019 10:35:56 + Stuart Henderson wrote:
> We are short on partitions, there is a hard limit (14+swap), disklabel auto
> defaults already use 9, and there need to be some free for typical user use
> (ports, dest for "make release", people often want a separate /var/www and/or
> /var/log).

Oh, I wasn't thinking of single disk desktops, but multi-drive servers
(which have plenty partition letters available to slice disks with).

Here's another idea Stuart:-

The special directory /tmp/vi.recover/ is exempt from boot & daily purging.

Could a similar /tmp/sysupgrade/ default directory suit most situations?

/tmp/ is normally mounted separately from / /home/ /var/
And probably not encrypted, nor over NFS.

Cheers,
-- 
Craig Skinner | http://linkd.in/yGqkv7