Re: Help: USB 3.0 xHCI driver does not support non-root hub
On 10/12/14 12:34, I wrote: - 3.0 hub should work, but either HS hub or SS hub in 3.0 hub may not be recognised. It looks one of these simultaneous interrupts is lost. uhub_intr() drops latter interrupt while uhub is exploring (sc_explorepending=1) for devices of former interrupt. I tried to change root hub of xhci not to overlap SS and HS ports, and add force rescan like roothub for ehci does in uhub.c. uPD720200: xhci0: SP: 03000402 20425355 0201 xhci0: SP: 0202 20425355 0203 # usbdevs -dv -f /dev/usb5 Controller /dev/usb5: addr 0: super speed, self powered, config 1, xHCI Root Hub(0x), NetBSD(0x000 0), rev 1.00 uhub0 port 1 addr 7: super speed, self powered, config 1, USB 3.0 HUB (0x0812), VLI Labs, Inc.(0x2109), rev 85.71 uhub8 port 1 powered port 2 powered port 3 addr 8: super speed, self powered, config 1, USB3.0 Hub(0x0616), Genesy sLogic(0x05e3), rev 4.01 uhub9 port 1 powered port 2 powered port 3 powered port 4 powered port 4 powered port 2 powered port 3 addr 5: high speed, self powered, config 1, USB 2.0 HUB (0x2812), vendor 2109(0x2109), rev 85.70 uhub6 port 1 powered port 2 powered port 3 addr 6: high speed, self powered, config 1, USB2.0 Hub(0x0610), Genesys Logic(0x05e3), rev 4.01 uhub7 port 1 powered port 2 powered port 3 powered port 4 powered port 4 powered port 4 powered # BayTrail: xhci0: SP: 02000802 20425355 30100601 xhci0: SP: 03000802 20425355 1107 # usbdevs -dv Controller /dev/usb0: addr 0: super speed, self powered, config 1, xHCI Root Hub(0x), NetBSD(0x000 0), rev 1.00 uhub0 port 1 addr 3: high speed, self powered, config 1, USB 2.0 HUB (0x2812), vendor 2109(0x2109), rev 85.70 uhub3 port 1 powered port 2 powered port 3 addr 4: high speed, self powered, config 1, USB2.0 Hub(0x0610), Genesys Logic(0x05e3), rev 4.01 uhub4 port 1 powered port 2 powered port 3 powered port 4 powered port 4 powered port 2 powered port 3 powered port 4 powered port 5 powered port 6 powered port 7 addr 1: super speed, self powered, config 1, USB 3.0 HUB (0x0812), VLI Labs, Inc.(0x2109), rev 85.71 uhub1 port 1 powered port 2 powered port 3 addr 2: super speed, self powered, config 1, USB3.0 Hub(0x0616), Genesy sLogic(0x05e3), rev 4.01 uhub2 port 1 powered port 2 powered port 3 powered port 4 powered port 4 powered # -- t-hash
Re: Help: USB 3.0 xHCI driver does not support non-root hub
Hello,
I think 3.0 hub should work with this patch, but
either HS hub or SS hub in 3.0 hub may not be recognised.
still xhci is at best experimental.
Fixes:
- Fix incorrect route string was set.
Correct route string does not contain root hub port.
- Fix FS and LS devices were not recognised.
Speed values were swapped.
Known bugs:
- 3.0 hub should work, but either HS hub or SS hub in 3.0 hub
may not be recognised.
It looks one of these simultaneous interrupts is lost.
- xhci may not recognise devices at boot.
This is regression.
- Detaching hubs or devices may cause panic.
- MTT,TTT and TT* fields in slot context is not set.
- Power management is not implemented.
Misc bugs:
- Closing pipe does not work correctly,
e.g. ifconfig axen0 up - down - up won't work.
- Some of umass devices won't work due to STALL error.
They don't understand MODE_SENSE_{6,10} command but stalls.
xhci.c cannot recover stalled bulk endpoints.
- xhci.c cannot handle cross-64k transfer yet.
- Memory leaks here and there in error paths.
- Slot leaks.
Devices cannot be added more than 32 times on xhci.
- Conextant umodem is not recognised (fail with XACT/PARAMETER).
hm what is missing...
- may not work on big endian.
- Address of root hub is 0.
- needs more comments.
If your xhci fortunately recognise 3.0 hub successfully,
things will go like this:
# usbdevs -dv -f /dev/usb5
Controller /dev/usb5:
addr 0: super speed, self powered, config 1, xHCI Root Hub(0x), NetBSD(0x000
0), rev 1.00
uhub0
port 1 addr 1: super speed, self powered, config 1, USB3.0 Hub(0x0616), Genesys
Logic(0x05e3), rev 4.01
uhub6
port 1 powered
port 2 powered
port 3 addr 3: super speed, power 124 mA, config 1, AX88179(0x1790), ASIX Elec
. Corp.(0x0b95), rev 1.00, serial xx
axen0
port 4 addr 2: super speed, power 126 mA, config 1, ADATA USB Flash Drive(0x31
2b), ADATA(0x125f), rev 11.00, serial
umass0
port 2 powered
# dd if=/dev/rsd0d bs=256k count=1024 of=/dev/null msgfmt=human
1024+0 records in
1024+0 records out
268435456 bytes (256 MB) transferred in 3.614 secs (74276551 bytes/sec - 71 MB/s
ec)
#
Thanks,
--
t-hash
--- src/sys/dev/usb/uhub.c.orig 2014-08-14 07:02:24.0 +0900
+++ src/sys/dev/usb/uhub.c 2014-10-12 09:08:20.0 +0900
@@ -38,12 +38,15 @@
#include sys/cdefs.h
__KERNEL_RCSID(0, $NetBSD: uhub.c,v 1.126 2014/08/13 06:26:32 skrll Exp $);
+#include opt_usb.h
+
#include sys/param.h
#include sys/systm.h
#include sys/kernel.h
#include sys/malloc.h
#include sys/device.h
#include sys/proc.h
+#include sys/sysctl.h
#include sys/bus.h
@@ -52,14 +55,44 @@ __KERNEL_RCSID(0, $NetBSD: uhub.c,v 1.1
#include dev/usb/usbdi_util.h
#include dev/usb/usbdivar.h
-#ifdef UHUB_DEBUG
-#define DPRINTF(x) if (uhubdebug) printf x
-#define DPRINTFN(n,x) if (uhubdebug(n)) printf x
-intuhubdebug = 0;
-#else
+#ifdef USB_DEBUG
+#ifndef UHUB_DEBUG
+#define uhubdebug 0
#define DPRINTF(x)
#define DPRINTFN(n,x)
-#endif
+#else
+intuhubdebug = 0;
+#define DPRINTF(x) if (uhubdebug) printf x
+#define DPRINTFN(n,x) if (uhubdebug(n)) printf x
+
+SYSCTL_SETUP(sysctl_hw_uhub_setup, sysctl hw.uhub setup)
+{
+ int err;
+ const struct sysctlnode *rnode;
+ const struct sysctlnode *cnode;
+
+ err = sysctl_createv(clog, 0, NULL, rnode,
+ CTLFLAG_PERMANENT, CTLTYPE_NODE, uhub,
+ SYSCTL_DESCR(uhub global controls),
+ NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
+
+ if (err)
+ goto fail;
+
+ /* control debugging printfs */
+ err = sysctl_createv(clog, 0, rnode, cnode,
+ CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
+ debug, SYSCTL_DESCR(Enable debugging output),
+ NULL, 0, uhubdebug, sizeof(uhubdebug), CTL_CREATE, CTL_EOL);
+ if (err)
+ goto fail;
+
+ return;
+fail:
+ aprint_error(%s: sysctl_createv failed (err = %d)\n, __func__, err);
+}
+#endif /* UHUB_DEBUG */
+#endif /* USB_DEBUG */
struct uhub_softc {
device_tsc_dev; /* base device */
@@ -77,7 +110,12 @@ struct uhub_softc {
u_char sc_running;
};
+#if 1
+#define UHUB_IS_HIGH_SPEED(sc) \
+((sc)-sc_proto == UDPROTO_HSHUBSTT || (sc)-sc_proto == UDPROTO_HSHUBMTT)
+#else
#define UHUB_IS_HIGH_SPEED(sc) ((sc)-sc_proto != UDPROTO_FSHUB)
+#endif
#define UHUB_IS_SINGLE_TT(sc) ((sc)-sc_proto == UDPROTO_HSHUBSTT)
#define PORTSTAT_ISSET(sc, port) \
@@ -182,6 +220,47 @@ uhub_attach(device_t parent, device_t se
}
/* Get hub descriptor. */
+#if 1
+ memset(hubdesc, 0, sizeof(hubdesc));
+ if (dev-speed == USB_SPEED_SUPER dev-depth != 0) {
+ usb_hub_ss_descriptor_t hubssdesc;
+
+ /* XXX: should add member hubssdesc to usbd_hub ? */
+ memset(hubssdesc, 0, sizeof(hubssdesc));
+ req.bmRequestType = UT_READ_CLASS_DEVICE;
Re: Help: USB 3.0 xHCI driver does not support non-root hub
hi,
On 09/15/14 23:46, Ryo ONODERA wrote:
Hi,
Our xHCI USB 3.0 driver with Intel Lynx Point/Lynx Point-LP, Renesas uPD70202
and Fresco Logic 0x1b73/0x1100 xHCI chips does not support non-root hub
as following.
I believe our xHCI driver have no non-root hub support.
I have tested some USB 1.1/2.0/3.0 hubs, and gotten same results.
Address Device Command TRB execution just after Enable Slot Command TRB
execution fails with USB Transaction Error.
I got PARAMETER error when i connected usb 2.0 thumb drive to
my uPD720200 xhci via 2.0 hub.
I have spent some weeks, but I cannot find why Address Device Command fails.
(If your want to use Intel Lynx Point/Lynx Point-LP xHC, please
apply a patch in http://gnats.netbsd.org/49076.)
I think that's because incorrect route string (always 0x0) and
incorrect root hub port is set in slot context.
Anyone have a clue for xHCI's non-root hub support?
I really need any clue for non-root hub support.
Can you try this patch?
This patch tries to add route string support for hubs.
Caveats:
- SS hub is currently not supported.
SS hub will work as HS hub.
I'm not sure both of SS and HS hub in SS hub can be
attached on one roothub port.
- Detaching hub may cause panic.
xhci may try to transfer on unplugged port.
- HUB,MTT,TTT and TT* fields in slot context is not set.
--- src/sys/dev/usb/xhci.c.orig 2014-10-03 21:18:24.0 +0900
+++ src/sys/dev/usb/xhci.c 2014-10-04 08:59:16.0 +0900
@@ -615,8 +760,12 @@ xhci_init(struct xhci_softc *sc)
XHCIHIST_FUNC(); XHCIHIST_CALLED();
+#if 0
+ sc-sc_bus.usbrev = USBREV_3_0;
+#else
/* XXX Low/Full/High speeds for now */
sc-sc_bus.usbrev = USBREV_2_0;
+#endif
cap = xhci_read_4(sc, XHCI_CAPLENGTH);
caplength = XHCI_CAP_CAPLENGTH(cap);
@@ -1139,8 +1449,7 @@ xhci_open(usbd_pipe_handle pipe)
return USBD_IOERROR;
/* Root Hub */
- if (dev-depth == 0 dev-powersrc-portno == 0
- dev-speed != USB_SPEED_SUPER) {
+ if (dev-depth == 0 dev-powersrc-portno == 0) {
switch (ed-bEndpointAddress) {
case USB_CONTROL_ENDPOINT:
pipe-methods = xhci_root_ctrl_methods;
@@ -1194,13 +1631,24 @@ xhci_rhpsc(struct xhci_softc * const sc,
if (xfer == NULL)
return;
- if (!(port = sc-sc_hs_port_start
- port sc-sc_hs_port_start + sc-sc_hs_port_count))
- return;
+ xfer-pipe-device-speed =
+ XHCI_PS_SPEED_GET(xhci_op_read_4(sc, XHCI_PORTSC(port)));
- port -= sc-sc_hs_port_start;
- port += 1;
- DPRINTFN(4, hs port %u status change, port, 0, 0, 0);
+ if (port = sc-sc_hs_port_start
+ port sc-sc_hs_port_start + sc-sc_hs_port_count) {
+ port -= sc-sc_hs_port_start;
+ port += 1;
+ DPRINTFN(4, hs port %u status change, port, 0, 0, 0);
+ } else if (port = sc-sc_ss_port_start
+ port sc-sc_ss_port_start + sc-sc_ss_port_count) {
+ port -= sc-sc_ss_port_start;
+ port += 1;
+ DPRINTFN(4, ss port %u status change, port, 0, 0, 0);
+ } else {
+ /* cannot happen */
+ DPRINTFN(0, port %u out of range, port, 0, 0, 0);
+ return;
+ }
p = KERNADDR(xfer-dmabuf, 0);
memset(p, 0, xfer-length);
@@ -1468,7 +1974,7 @@ xhci_new_device(device_t parent, usbd_bu
usbd_status err;
usb_device_descriptor_t *dd;
struct usbd_device *hub;
- struct usbd_device *adev;
+ uint32_t route = 0;
int rhport = 0;
struct xhci_slot *xs;
uint32_t *cp;
@@ -1515,28 +2017,32 @@ xhci_new_device(device_t parent, usbd_bu
up-device = dev;
/* Locate root hub port */
- for (adev = dev, hub = dev;
- hub != NULL;
- adev = hub, hub = hub-myhub) {
- DPRINTFN(4, hub %p, hub, 0, 0, 0);
- }
- DPRINTFN(4, hub %p, hub, 0, 0, 0);
-
- if (hub != NULL) {
- for (int p = 0; p hub-hub-hubdesc.bNbrPorts; p++) {
- if (hub-hub-ports[p].device == adev) {
- rhport = p;
- }
- }
- } else {
- rhport = port;
+ for (hub = dev; hub != NULL; hub = hub-myhub) {
+ uint32_t dep;
+
+ DPRINTFN(4, hub %p depth %d upport %p upportno %d,
+ hub, hub-depth, hub-powersrc,
+ hub-powersrc ? hub-powersrc-portno : 0);
+
+ if (hub-powersrc == NULL)
+ continue;
+ dep = hub-depth;
+ if (dep == 0)
+ continue;
+
+ route |= hub-powersrc-portno ((dep - 1) * 4);
}
+ DPRINTFN(4, hub %p route %05x, hub, route, 0, 0);
+
if (speed == USB_SPEED_SUPER) {
- rhport += sc-sc_ss_port_start - 1
Re: Help: USB 3.0 xHCI driver does not support non-root hub
From: Jonathan A. Kollasch jakll...@kollasch.net, Date: Mon, 15 Sep 2014 10:55:54 -0500 On Mon, Sep 15, 2014 at 11:46:24PM +0900, Ryo ONODERA wrote: Hi, Our xHCI USB 3.0 driver with Intel Lynx Point/Lynx Point-LP, Renesas uPD70202 and Fresco Logic 0x1b73/0x1100 xHCI chips does not support non-root hub as following. I believe our xHCI driver have no non-root hub support. Correct, I never got around to implementing non-root hub support. Thanks for your confirmation! I am new to NetBSD kernel programming, so if you have any advice, please post it to the lists. Thank you. -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
Hi, From: Ryo ONODERA ryo...@yk.rim.or.jp, Date: Wed, 13 Aug 2014 00:57:39 +0900 (JST) From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 21:49:35 +0900 On 08/12/14 20:37, Ryo ONODERA wrote: From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 [snip] I have some questions. 1) Do you have PCI_INTR_FIXUP in your kernel config? I had no PCI_INTR_FIXUP in kernel config. I have added PCI_INTR_FIXUP to my kernel config, and no effects. hmm.. 2) Is the port enabled -- has XHCI_PS_PED in PORTSC? All PORTSC is 0x2a0. It means port is disabled? Yes, disabled. xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means XHCI_PS_CCS = 0: device is not connected XHCI_PS_PED = 0: port disabled XHCI_PS_PLS = 0x5: Link is in the RxDetect state XHCI_PS_PP = 1: not power-off state RxDetect is the state after port warm reset. In this state controller is waiting for device. - xHCI specification 1.1 http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf Hi, Thanks for your explanation. I read xhci spec already. But I cannot find missing something for Intel xhci device... I have found the missing one, and post to my PR. http://gnats.netbsd.org/49076 It works for Lynx Point xhci, but does not work fine for Lynx Point-LP xhci. If you have Lynx Point-LP machine, could you test my patch in PR kern/49076? My Lynx Point-LP machine is MacBook Air early 2014 11-inch. I would like to know the status on non-Apple Lynx Point-LP machine especially. Thank you. -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
From: Ryo ONODERA ryo...@yk.rim.or.jp, Date: Sun, 17 Aug 2014 21:52:31 +0900 (JST) Hi, From: Ryo ONODERA ryo...@yk.rim.or.jp, Date: Wed, 13 Aug 2014 00:57:39 +0900 (JST) From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 21:49:35 +0900 On 08/12/14 20:37, Ryo ONODERA wrote: From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 [snip] I have some questions. 1) Do you have PCI_INTR_FIXUP in your kernel config? I had no PCI_INTR_FIXUP in kernel config. I have added PCI_INTR_FIXUP to my kernel config, and no effects. hmm.. 2) Is the port enabled -- has XHCI_PS_PED in PORTSC? All PORTSC is 0x2a0. It means port is disabled? Yes, disabled. xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means XHCI_PS_CCS = 0: device is not connected XHCI_PS_PED = 0: port disabled XHCI_PS_PLS = 0x5: Link is in the RxDetect state XHCI_PS_PP = 1: not power-off state RxDetect is the state after port warm reset. In this state controller is waiting for device. - xHCI specification 1.1 http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf Hi, Thanks for your explanation. I read xhci spec already. But I cannot find missing something for Intel xhci device... I have found the missing one, and post to my PR. http://gnats.netbsd.org/49076 It works for Lynx Point xhci, but does not work fine for Lynx Point-LP xhci. If you have Lynx Point-LP machine, could you test my patch in PR kern/49076? My Lynx Point-LP machine is MacBook Air early 2014 11-inch. I would like to know the status on non-Apple Lynx Point-LP machine especially. Lynx Point-LP has vendor ID = 0x8086/product ID = 0x9c31. Thank you. -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
From: Takahiro HAYASHI t.hash...@gmail.com, Date: Thu, 14 Aug 2014 08:18:18 +0900 On 08/14/14 07:20, Ryo ONODERA wrote: Hi, From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 For comparison here is dmesg from my testbed: xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194 (rev. 0x04) xhci0: interrupting at ioapic0 pin 21 xhci_init xhci0: ac64 1 ctxsz 32 xhci0: xECP 500 xhci0: ECR 500: 0401 xhci0: ECR 510: 03000402 xhci0: SP: 03000402 20425355 0201 xhci0: ECR 520: 0202 xhci0: SP: 0202 20425355 0203 xhci0: PAGESIZE 0x0001 xhci0: sc_pgsz 0x1000 xhci0: sc_maxslots 0x0020 xhci0: sc_maxspbuf 0 xhci0: eventst: NORMAL_COMPLETION 02f15fc0 0x800013028fc0 1000 xhci0: dcbaa: NORMAL_COMPLETION 02f17000 0x800013029000 1000 xhci0: USBCMD 0005 usb5 at xhci0: USB revision 2.0 usb5: WARNING: power management not supported and i got: xhci0: xhci_intr1 USBSTS 0018 xhci0: xhci_intr1 USBSTS xhci0: xhci_intr1 IMAN0 0003 xhci0: xhci_intr1 IMAN0 0002 xhci0: xhci_intr1 USBSTS xhci0: port 1 status change On my machine, xhci_handle_event() is not invoked when USB memory stick is plugged. How about on your machine? It is called in my case. xhci_intr: xhci0 xhci0: xhci_intr1 USBSTS 0018 xhci0: xhci_intr1 USBSTS xhci0: xhci_intr1 IMAN0 0003 xhci0: xhci_intr1 IMAN0 0002 xhci0: xhci_intr1 USBSTS xhci_softintr: xhci0 xhci_handle_event: xhci0 xhci0: port 1 status change xhci_softintr: xhci0 ends Thank you very much. -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
From: Ryo ONODERA ryo...@yk.rim.or.jp, Date: Wed, 13 Aug 2014 00:57:39 +0900
(JST)
From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 21:49:35
+0900
On 08/12/14 20:37, Ryo ONODERA wrote:
From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014
02:14:43 +0900
[snip]
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.
xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state
RxDetect is the state after port warm reset.
In this state controller is waiting for device.
- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
Hi,
Thanks for your explanation.
I read xhci spec already.
But I cannot find missing something for Intel xhci device...
Hi,
I have found xHC halting is done before resetting, and Linux and edk2
confirm whether xHC is really halted.
I have added similar code to NetBSD's xhci.c like following.
And I have gotten
xhci0: init failed, error=5
error.
Index: xhci.c
===
RCS file: /cvsroot/src/sys/dev/usb/xhci.c,v
retrieving revision 1.26
diff -u -r1.26 xhci.c
--- xhci.c 12 Aug 2014 13:50:42 - 1.26
+++ xhci.c 13 Aug 2014 11:26:39 -
@@ -682,7 +682,14 @@
usbcmd = 0;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
- usb_delay_ms(sc-sc_bus, 1);
+ for (i = 0; i 100; i++) {
+ usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
+ if ((usbsts XHCI_STS_HCH) == 0)
+ break;
+ usb_delay_ms(sc-sc_bus, 1);
+ }
+ if (i = 100)
+ return EIO;
usbcmd = XHCI_CMD_HCRST;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
--
Ryo ONODERA // ryo...@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
From: Ryo ONODERA ryo...@yk.rim.or.jp, Date: Wed, 13 Aug 2014 20:31:31 +0900
(JST)
From: Ryo ONODERA ryo...@yk.rim.or.jp, Date: Wed, 13 Aug 2014 00:57:39
+0900 (JST)
From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014
21:49:35 +0900
On 08/12/14 20:37, Ryo ONODERA wrote:
From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014
02:14:43 +0900
[snip]
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.
xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state
RxDetect is the state after port warm reset.
In this state controller is waiting for device.
- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
Hi,
Thanks for your explanation.
I read xhci spec already.
But I cannot find missing something for Intel xhci device...
Hi,
I have found xHC halting is done before resetting, and Linux and edk2
confirm whether xHC is really halted.
I have added similar code to NetBSD's xhci.c like following.
And I have gotten
xhci0: init failed, error=5
error.
Index: xhci.c
===
RCS file: /cvsroot/src/sys/dev/usb/xhci.c,v
retrieving revision 1.26
diff -u -r1.26 xhci.c
--- xhci.c12 Aug 2014 13:50:42 - 1.26
+++ xhci.c13 Aug 2014 11:26:39 -
@@ -682,7 +682,14 @@
usbcmd = 0;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
- usb_delay_ms(sc-sc_bus, 1);
+ for (i = 0; i 100; i++) {
+ usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
+ if ((usbsts XHCI_STS_HCH) == 0)
+ break;
+ usb_delay_ms(sc-sc_bus, 1);
+ }
+ if (i = 100)
+ return EIO;
usbcmd = XHCI_CMD_HCRST;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
Oops.
(usbsts XHCI_STS_HCH) == 0 should be 1.
It is my misunderstanding.
Sorry.
--
Ryo ONODERA // ryo...@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
Hi, From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 For comparison here is dmesg from my testbed: xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194 (rev. 0x04) xhci0: interrupting at ioapic0 pin 21 xhci_init xhci0: ac64 1 ctxsz 32 xhci0: xECP 500 xhci0: ECR 500: 0401 xhci0: ECR 510: 03000402 xhci0: SP: 03000402 20425355 0201 xhci0: ECR 520: 0202 xhci0: SP: 0202 20425355 0203 xhci0: PAGESIZE 0x0001 xhci0: sc_pgsz 0x1000 xhci0: sc_maxslots 0x0020 xhci0: sc_maxspbuf 0 xhci0: eventst: NORMAL_COMPLETION 02f15fc0 0x800013028fc0 1000 xhci0: dcbaa: NORMAL_COMPLETION 02f17000 0x800013029000 1000 xhci0: USBCMD 0005 usb5 at xhci0: USB revision 2.0 usb5: WARNING: power management not supported and i got: xhci0: xhci_intr1 USBSTS 0018 xhci0: xhci_intr1 USBSTS xhci0: xhci_intr1 IMAN0 0003 xhci0: xhci_intr1 IMAN0 0002 xhci0: xhci_intr1 USBSTS xhci0: port 1 status change On my machine, xhci_handle_event() is not invoked when USB memory stick is plugged. How about on your machine? Thank you. -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
On 08/14/14 07:20, Ryo ONODERA wrote: Hi, From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 For comparison here is dmesg from my testbed: xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194 (rev. 0x04) xhci0: interrupting at ioapic0 pin 21 xhci_init xhci0: ac64 1 ctxsz 32 xhci0: xECP 500 xhci0: ECR 500: 0401 xhci0: ECR 510: 03000402 xhci0: SP: 03000402 20425355 0201 xhci0: ECR 520: 0202 xhci0: SP: 0202 20425355 0203 xhci0: PAGESIZE 0x0001 xhci0: sc_pgsz 0x1000 xhci0: sc_maxslots 0x0020 xhci0: sc_maxspbuf 0 xhci0: eventst: NORMAL_COMPLETION 02f15fc0 0x800013028fc0 1000 xhci0: dcbaa: NORMAL_COMPLETION 02f17000 0x800013029000 1000 xhci0: USBCMD 0005 usb5 at xhci0: USB revision 2.0 usb5: WARNING: power management not supported and i got: xhci0: xhci_intr1 USBSTS 0018 xhci0: xhci_intr1 USBSTS xhci0: xhci_intr1 IMAN0 0003 xhci0: xhci_intr1 IMAN0 0002 xhci0: xhci_intr1 USBSTS xhci0: port 1 status change On my machine, xhci_handle_event() is not invoked when USB memory stick is plugged. How about on your machine? It is called in my case. xhci_intr: xhci0 xhci0: xhci_intr1 USBSTS 0018 xhci0: xhci_intr1 USBSTS xhci0: xhci_intr1 IMAN0 0003 xhci0: xhci_intr1 IMAN0 0002 xhci0: xhci_intr1 USBSTS xhci_softintr: xhci0 xhci_handle_event: xhci0 xhci0: port 1 status change xhci_softintr: xhci0 ends -- t-hash
Re: USB 3.0 xhci questions
Hi, From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 Hello, On 08/11/14 21:51, Ryo ONODERA wrote: Do these xHCIs work on other OS? If yes, hardware seems good. Arch Linux (archlinux-2014.08.01.iso; Linux 3.15.7) works fine on both machines. SuperSpeed USB device is detected and attached to xhci. Hardwares have no problem. Thanks for checking. I have no good idea to explain this. It looks like xhci_intr is called even though no interrupters trigger. I have some questions. 1) Do you have PCI_INTR_FIXUP in your kernel config? I had no PCI_INTR_FIXUP in kernel config. I have added PCI_INTR_FIXUP to my kernel config, and no effects. 2) Is the port enabled -- has XHCI_PS_PED in PORTSC? All PORTSC is 0x2a0. It means port is disabled? Thank you. I think address of USBSTS is correct because xhci_init returns normally and xhci is configured. For comparison here is dmesg from my testbed: xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194 (rev. 0x04) xhci0: interrupting at ioapic0 pin 21 xhci_init xhci0: ac64 1 ctxsz 32 xhci0: xECP 500 xhci0: ECR 500: 0401 xhci0: ECR 510: 03000402 xhci0: SP: 03000402 20425355 0201 xhci0: ECR 520: 0202 xhci0: SP: 0202 20425355 0203 xhci0: PAGESIZE 0x0001 xhci0: sc_pgsz 0x1000 xhci0: sc_maxslots 0x0020 xhci0: sc_maxspbuf 0 xhci0: eventst: NORMAL_COMPLETION 02f15fc0 0x800013028fc0 1000 xhci0: dcbaa: NORMAL_COMPLETION 02f17000 0x800013029000 1000 xhci0: USBCMD 0005 usb5 at xhci0: USB revision 2.0 usb5: WARNING: power management not supported and i got: xhci0: xhci_intr1 USBSTS 0018 xhci0: xhci_intr1 USBSTS xhci0: xhci_intr1 IMAN0 0003 xhci0: xhci_intr1 IMAN0 0002 xhci0: xhci_intr1 USBSTS xhci0: port 1 status change -- t-hash -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
On 08/12/14 20:37, Ryo ONODERA wrote: From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 [snip] I have some questions. 1) Do you have PCI_INTR_FIXUP in your kernel config? I had no PCI_INTR_FIXUP in kernel config. I have added PCI_INTR_FIXUP to my kernel config, and no effects. hmm.. 2) Is the port enabled -- has XHCI_PS_PED in PORTSC? All PORTSC is 0x2a0. It means port is disabled? Yes, disabled. xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means XHCI_PS_CCS = 0: device is not connected XHCI_PS_PED = 0: port disabled XHCI_PS_PLS = 0x5: Link is in the RxDetect state XHCI_PS_PP = 1: not power-off state RxDetect is the state after port warm reset. In this state controller is waiting for device. - xHCI specification 1.1 http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf -- t-hash
Re: USB 3.0 xhci questions
Hi, From: Taylor R Campbell campbell+netbsd-tech-k...@mumble.net, Date: Sun, 10 Aug 2014 13:59:57 + Date: Sun, 10 Aug 2014 22:44:24 +0900 (JST) From: Ryo ONODERA ryo...@yk.rim.or.jp (1) The definition of XHCI_HCS2_MAXSPBUF macro. In src/sys/dev/usb/xhcireg.h, there is the following macro definition. #defineXHCI_HCS2_MAXSPBUF(x) (((x) 27) 0x7F) It seems that XHCI_HCS2_MAXSPBUF is used for reading Max Scratchpad Buffers. Max Scratchpad Buffers are in 31:27 bit of HCSPARAMS2 in capability register. 0x7F is 111(2). I feel it is too long to mask 31:27. It would be 0x1F = 1(2). Whatever the physical register specification is, please use __BITS and __SHIFTOUT to describe it -- these is much easier to work with and have fewer moving parts to get wrong than ands and shifts, and if you ever need to assemble an hcs2 from its components you can use __SHIFTIN with the same __BITS. #define XHCI_HCS2_MAXSPBUF __BITS(31,27) maxspbuf = __SHIFTOUT(hcs2, XHCI_HCS2_MAXSPBUF); hcs2 = __SHIFTIN(maxspbuf, XHCI_HCS2_MAXSPBUF) | ...; Thanks for your advice. I have created attached patch. With this patch, my machine does not work like before... -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3 Index: xhcireg.h === RCS file: /cvsroot/src/sys/dev/usb/xhcireg.h,v retrieving revision 1.1 diff -u -r1.1 xhcireg.h --- xhcireg.h 14 Sep 2013 00:40:31 - 1.1 +++ xhcireg.h 12 Aug 2014 15:53:27 - @@ -40,33 +40,33 @@ /* XHCI capability registers */ #define XHCI_CAPLENGTH 0x00 /* RO capability */ -#define XHCI_CAP_CAPLENGTH(x) ((x) 0xFF) -#define XHCI_CAP_HCIVERSION(x) (((x) 16) 0x) /* RO Interface version number */ +#define XHCI_CAP_CAPLENGTH(x) __SHIFTOUT(x, __BITS(15, 0)) +#define XHCI_CAP_HCIVERSION(x) __SHIFTOUT(x, __BITS(31, 16)) /* RO Interface version number */ #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ #define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */ -#define XHCI_HCS1_MAXSLOTS(x) ((x) 0xFF) -#define XHCI_HCS1_MAXINTRS(x) (((x) 8) 0x7FF) -#define XHCI_HCS1_MAXPORTS(x) (((x) 24) 0xFF) +#define XHCI_HCS1_MAXSLOTS(x) __SHIFTOUT(x, __BITS(7, 0)) +#define XHCI_HCS1_MAXINTRS(x) __SHIFTOUT(x, __BITS(18, 8)) +#define XHCI_HCS1_MAXPORTS(x) __SHIFTOUT(x, __BITS(31, 24)) #define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */ -#define XHCI_HCS2_IST(x) ((x) 0xF) -#define XHCI_HCS2_ERST_MAX(x) (((x) 4) 0xF) -#define XHCI_HCS2_SPR(x) (((x) 24) 0x1) -#define XHCI_HCS2_MAXSPBUF(x) (((x) 27) 0x7F) +#define XHCI_HCS2_IST(x) __SHIFTOUT(x, __BITS(3, 0)) +#define XHCI_HCS2_ERST_MAX(x) __SHIFTOUT(x, __BITS(7, 4)) +#define XHCI_HCS2_SPR(x) __SHIFTOUT(x, __BIT(26)) +#define XHCI_HCS2_MAXSPBUF(x) __SHIFTOUT(x, __BITS(31, 27)) #define XHCI_HCSPARAMS3 0x0C /* RO structual parameters 3 */ -#define XHCI_HCS3_U1_DEL(x) ((x) 0xFF) -#define XHCI_HCS3_U2_DEL(x) (((x) 16) 0x) +#define XHCI_HCS3_U1_DEL(x) __SHIFTOUT(x, __BITS(7, 0)) +#define XHCI_HCS3_U2_DEL(x) __SHIFTOUT(x, __BITS(31, 16)) #define XHCI_HCCPARAMS 0x10 /* RO capability parameters */ -#define XHCI_HCC_AC64(x) ((x) 0x1) /* 64-bit capable */ -#define XHCI_HCC_BNC(x) (((x) 1) 0x1) /* BW negotiation */ -#define XHCI_HCC_CSZ(x) (((x) 2) 0x1) /* context size */ -#define XHCI_HCC_PPC(x) (((x) 3) 0x1) /* port power control */ -#define XHCI_HCC_PIND(x) (((x) 4) 0x1) /* port indicators */ -#define XHCI_HCC_LHRC(x) (((x) 5) 0x1) /* light HC reset */ -#define XHCI_HCC_LTC(x) (((x) 6) 0x1) /* latency tolerance msg */ -#define XHCI_HCC_NSS(x) (((x) 7) 0x1) /* no secondary sid */ -#define XHCI_HCC_MAXPSASIZE(x) (((x) 12) 0xF) /* max pri. stream array size */ -#define XHCI_HCC_XECP(x) (((x) 16) 0x) /* extended capabilities pointer */ +#define XHCI_HCC_AC64(x) __SHIFTOUT(x, __BIT(0)) /* 64-bit capable */ +#define XHCI_HCC_BNC(x) __SHIFTOUT(x, __BIT(1)) /* BW negotiation */ +#define XHCI_HCC_CSZ(x) __SHIFTOUT(x, __BIT(2)) /* context size */ +#define XHCI_HCC_PPC(x) __SHIFTOUT(x, __BIT(3)) /* port power control */ +#define XHCI_HCC_PIND(x) __SHIFTOUT(x, __BIT(4)) /* port indicators */ +#define XHCI_HCC_LHRC(x) __SHIFTOUT(x, __BIT(5)) /* light HC reset */ +#define XHCI_HCC_LTC(x) __SHIFTOUT(x, __BIT(6)) /* latency tolerance msg */ +#define XHCI_HCC_NSS(x) __SHIFTOUT(x, __BIT(7)) /* no secondary sid */ +#define XHCI_HCC_MAXPSASIZE(x) __SHIFTOUT(x, __BITS(15, 12)) /* max pri. stream array size */ +#define XHCI_HCC_XECP(x) __SHIFTOUT(x, __BITS(31, 16)) /* extended capabilities pointer */ #define XHCI_DBOFF 0x14 /* RO doorbell offset */ #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ @@ -112,82 +112,82 @@ #define XHCI_CONFIG_SLOTS_MASK 0x00FF /* RW - number of device slots enabled */ /* XHCI port status registers */
Re: USB 3.0 xhci questions
From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 21:49:35 +0900 On 08/12/14 20:37, Ryo ONODERA wrote: From: Takahiro HAYASHI t.hash...@gmail.com, Date: Tue, 12 Aug 2014 02:14:43 +0900 [snip] I have some questions. 1) Do you have PCI_INTR_FIXUP in your kernel config? I had no PCI_INTR_FIXUP in kernel config. I have added PCI_INTR_FIXUP to my kernel config, and no effects. hmm.. 2) Is the port enabled -- has XHCI_PS_PED in PORTSC? All PORTSC is 0x2a0. It means port is disabled? Yes, disabled. xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means XHCI_PS_CCS = 0: device is not connected XHCI_PS_PED = 0: port disabled XHCI_PS_PLS = 0x5: Link is in the RxDetect state XHCI_PS_PP = 1: not power-off state RxDetect is the state after port warm reset. In this state controller is waiting for device. - xHCI specification 1.1 http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf Hi, Thanks for your explanation. I read xhci spec already. But I cannot find missing something for Intel xhci device... -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
Hello, On 08/10/14 22:44, Ryo ONODERA wrote: Sadly, if my guess (1) was true, my MacBook Air' and Lenovo ThinkStation E32's USB 3.0 does not work. No device is detected. Do these xHCIs work on other OS? If yes, hardware seems good. -- t-hash
Re: USB 3.0 xhci questions
Hi, From: Takahiro HAYASHI t.hash...@gmail.com, Date: Mon, 11 Aug 2014 17:58:12 +0900 Hello, On 08/10/14 22:44, Ryo ONODERA wrote: Sadly, if my guess (1) was true, my MacBook Air' and Lenovo ThinkStation E32's USB 3.0 does not work. No device is detected. Do these xHCIs work on other OS? If yes, hardware seems good. Arch Linux (archlinux-2014.08.01.iso; Linux 3.15.7) works fine on both machines. SuperSpeed USB device is detected and attached to xhci. Hardwares have no problem. -- Ryo ONODERA // ryo...@yk.rim.or.jp PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 xhci questions
Hello, On 08/11/14 21:51, Ryo ONODERA wrote: Do these xHCIs work on other OS? If yes, hardware seems good. Arch Linux (archlinux-2014.08.01.iso; Linux 3.15.7) works fine on both machines. SuperSpeed USB device is detected and attached to xhci. Hardwares have no problem. Thanks for checking. I have no good idea to explain this. It looks like xhci_intr is called even though no interrupters trigger. I have some questions. 1) Do you have PCI_INTR_FIXUP in your kernel config? 2) Is the port enabled -- has XHCI_PS_PED in PORTSC? I think address of USBSTS is correct because xhci_init returns normally and xhci is configured. For comparison here is dmesg from my testbed: xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194 (rev. 0x04) xhci0: interrupting at ioapic0 pin 21 xhci_init xhci0: ac64 1 ctxsz 32 xhci0: xECP 500 xhci0: ECR 500: 0401 xhci0: ECR 510: 03000402 xhci0: SP: 03000402 20425355 0201 xhci0: ECR 520: 0202 xhci0: SP: 0202 20425355 0203 xhci0: PAGESIZE 0x0001 xhci0: sc_pgsz 0x1000 xhci0: sc_maxslots 0x0020 xhci0: sc_maxspbuf 0 xhci0: eventst: NORMAL_COMPLETION 02f15fc0 0x800013028fc0 1000 xhci0: dcbaa: NORMAL_COMPLETION 02f17000 0x800013029000 1000 xhci0: USBCMD 0005 usb5 at xhci0: USB revision 2.0 usb5: WARNING: power management not supported and i got: xhci0: xhci_intr1 USBSTS 0018 xhci0: xhci_intr1 USBSTS xhci0: xhci_intr1 IMAN0 0003 xhci0: xhci_intr1 IMAN0 0002 xhci0: xhci_intr1 USBSTS xhci0: port 1 status change -- t-hash
USB 3.0 xhci questions
Hi,
I have read some xhci-related source code, and I have two questions.
(1) The definition of XHCI_HCS2_MAXSPBUF macro.
In src/sys/dev/usb/xhcireg.h, there is the following macro definition.
#defineXHCI_HCS2_MAXSPBUF(x) (((x) 27) 0x7F)
It seems that XHCI_HCS2_MAXSPBUF is used for reading Max Scratchpad Buffers.
Max Scratchpad Buffers are in 31:27 bit of HCSPARAMS2 in capability
register. 0x7F is 111(2). I feel it is too long to mask 31:27.
It would be 0x1F = 1(2).
(2) I may not get USB Status (USBSTS).
In src/sys/dev/usb/xhci.c's xhci_intr1() function, USBSTS is read from
operational register, but my machine returns always 0x.
The code in xhci_intr1() expects XHCI_STS_PCD flag is detcted.
The following is my modified source code snipet (enable device_printf).
I think usbsts XHCI_STS_PCD != 0 in this case, but always == 0.
PCD means Port Change Detect, and port change is not detected.
I have dumped all PORTSC value, and there is no Current Connect Status (CCS)
and Connect Status Change (CSC) bits.
I have concluded that port change is not deteced on my machine.
What may be wrong?
int
xhci_intr1(struct xhci_softc * const sc)
{
uint32_t usbsts;
uint32_t iman;
usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
device_printf(sc-sc_dev, %s USBSTS %08x\n, __func__, usbsts);
#if 0
if ((usbsts (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) {
return 0;
}
#endif
xhci_op_write_4(sc, XHCI_USBSTS,
usbsts (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */
usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
device_printf(sc-sc_dev, %s USBSTS %08x\n, __func__, usbsts);
iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
device_printf(sc-sc_dev, %s IMAN0 %08x\n, __func__, iman);
if ((iman XHCI_IMAN_INTR_PEND) == 0) {
return 0;
}
And here is a part of dmesg.
xhci0 at pci0 dev 20 function 0: vendor 0x8086 product 0x8c31 (rev. 0x04)
xhci0: interrupting at ioapic0 pin 16
xhci_init
xhci0: xHCI version 1.0
xhci0: ac64 1 ctxsz 32
xhci0: xECP 8000
xhci0: ECR 8000: 02000802
xhci0: SP: 02000802 20425355 30010f01
xhci0: ECR 8020: 03000802
xhci0: SP: 03000802 20425355 1610
xhci0: ECR 8040: 0cc1
xhci0: ECR 8070: ffc0
xhci0: ECR 846c: 0001
xhci0: PAGESIZE 0x0001
xhci0: sc_pgsz 0x1000
xhci0: sc_maxslots 0x0020
xhci0: sc_maxspbuf 16
xhci0: eventst: NORMAL_COMPLETION 00013a6cbfc0 0x80023a25cfc0 1000
xhci0: dcbaa: NORMAL_COMPLETION 00013a6cc000 0x80023a25d000 1000
xhci0: USBCMD 0005
usb0 at xhci0: USB revision 2.0
xhci1 at pci3 dev 0 function 0: vendor 0x1912 product 0x0015 (rev. 0x02)
xhci1: interrupting at ioapic0 pin 17
xhci_init
xhci1: xHCI version 1.0
xhci1: ac64 1 ctxsz 64
xhci1: xECP 500
xhci1: ECR 500: 0401
xhci1: ECR 510: 03000502
xhci1: SP: 03000502 20425355 0201
xhci1: ECR 524: 02000702
xhci1: SP: 02000702 20425355 0203
xhci1: ECR 540: 04c0
xhci1: ECR 550: 000a
xhci1: PAGESIZE 0x0001
xhci1: sc_pgsz 0x1000
xhci1: sc_maxslots 0x0020
xhci1: sc_maxspbuf 4
xhci1: eventst: NORMAL_COMPLETION 00013a6cbf40 0x80023a25cf40 1000
xhci1: dcbaa: NORMAL_COMPLETION 00013a84e000 0x80023a2e5000 1000
xhci1: USBCMD 0005
usb1 at xhci1: USB revision 2.0
(USB 3.0 memory stick is inserted)
xhci_intr: xhci0
xhci0: xhci_intr1 USBSTS
xhci0: xhci_intr1 USBSTS
xhci0: xhci_intr1 IMAN0 0002
Sadly, if my guess (1) was true, my MacBook Air' and
Lenovo ThinkStation E32's USB 3.0 does not work. No device is detected.
Thank you.
--
Ryo ONODERA // ryo...@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: USB 3.0 ?
On Thu, Mar 29, 2012 at 06:26:07PM -0700, Paul Goyette wrote: Just curious - is anyone out there working on a USB 3.0 driver for NetBSD? Not working on it yet, but I'm planing on trying someday soon. Jonathan Kollasch
USB 3.0 ?
Just curious - is anyone out there working on a USB 3.0 driver for NetBSD? - | Paul Goyette | PGP Key fingerprint: | E-mail addresses: | | Customer Service | FA29 0E3B 35AF E8AE 6651 | paul at whooppee.com| | Network Engineer | 0786 F758 55DE 53BA 7731 | pgoyette at juniper.net | | Kernel Developer | | pgoyette at netbsd.org | -
