Hi,
From: Taylor R Campbell <campbell+netbsd-tech-k...@mumble.net>, Date: Sun, 10
Aug 2014 13:59:57 +0000
> Date: Sun, 10 Aug 2014 22:44:24 +0900 (JST)
> From: Ryo ONODERA <ryo...@yk.rim.or.jp>
>
> (1) The definition of XHCI_HCS2_MAXSPBUF macro.
> In src/sys/dev/usb/xhcireg.h, there is the following macro definition.
>
> #define XHCI_HCS2_MAXSPBUF(x) (((x) >> 27) & 0x7F)
>
> It seems that XHCI_HCS2_MAXSPBUF is used for reading Max Scratchpad
> Buffers.
> Max Scratchpad Buffers are in 31:27 bit of HCSPARAMS2 in capability
> register. 0x7F is 1111111(2). I feel it is too long to mask 31:27.
> It would be 0x1F = 11111(2).
>
> Whatever the physical register specification is, please use __BITS and
> __SHIFTOUT to describe it -- these is much easier to work with and
> have fewer moving parts to get wrong than ands and shifts, and if you
> ever need to assemble an hcs2 from its components you can use
> __SHIFTIN with the same __BITS.
>
> #define XHCI_HCS2_MAXSPBUF __BITS(31,27)
>
> maxspbuf = __SHIFTOUT(hcs2, XHCI_HCS2_MAXSPBUF);
> hcs2 = __SHIFTIN(maxspbuf, XHCI_HCS2_MAXSPBUF) | ...;
Thanks for your advice.
I have created attached patch.
With this patch, my machine does not work like before...
--
Ryo ONODERA // ryo...@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Index: xhcireg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/usb/xhcireg.h,v
retrieving revision 1.1
diff -u -r1.1 xhcireg.h
--- xhcireg.h 14 Sep 2013 00:40:31 -0000 1.1
+++ xhcireg.h 12 Aug 2014 15:53:27 -0000
@@ -40,33 +40,33 @@
/* XHCI capability registers */
#define XHCI_CAPLENGTH 0x00 /* RO capability */
-#define XHCI_CAP_CAPLENGTH(x) ((x) & 0xFF)
-#define XHCI_CAP_HCIVERSION(x) (((x) >> 16) & 0xFFFF) /* RO Interface version number */
+#define XHCI_CAP_CAPLENGTH(x) __SHIFTOUT(x, __BITS(15, 0))
+#define XHCI_CAP_HCIVERSION(x) __SHIFTOUT(x, __BITS(31, 16)) /* RO Interface version number */
#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */
#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */
#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */
-#define XHCI_HCS1_MAXSLOTS(x) ((x) & 0xFF)
-#define XHCI_HCS1_MAXINTRS(x) (((x) >> 8) & 0x7FF)
-#define XHCI_HCS1_MAXPORTS(x) (((x) >> 24) & 0xFF)
+#define XHCI_HCS1_MAXSLOTS(x) __SHIFTOUT(x, __BITS(7, 0))
+#define XHCI_HCS1_MAXINTRS(x) __SHIFTOUT(x, __BITS(18, 8))
+#define XHCI_HCS1_MAXPORTS(x) __SHIFTOUT(x, __BITS(31, 24))
#define XHCI_HCSPARAMS2 0x08 /* RO structual parameters 2 */
-#define XHCI_HCS2_IST(x) ((x) & 0xF)
-#define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF)
-#define XHCI_HCS2_SPR(x) (((x) >> 24) & 0x1)
-#define XHCI_HCS2_MAXSPBUF(x) (((x) >> 27) & 0x7F)
+#define XHCI_HCS2_IST(x) __SHIFTOUT(x, __BITS(3, 0))
+#define XHCI_HCS2_ERST_MAX(x) __SHIFTOUT(x, __BITS(7, 4))
+#define XHCI_HCS2_SPR(x) __SHIFTOUT(x, __BIT(26))
+#define XHCI_HCS2_MAXSPBUF(x) __SHIFTOUT(x, __BITS(31, 27))
#define XHCI_HCSPARAMS3 0x0C /* RO structual parameters 3 */
-#define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF)
-#define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF)
+#define XHCI_HCS3_U1_DEL(x) __SHIFTOUT(x, __BITS(7, 0))
+#define XHCI_HCS3_U2_DEL(x) __SHIFTOUT(x, __BITS(31, 16))
#define XHCI_HCCPARAMS 0x10 /* RO capability parameters */
-#define XHCI_HCC_AC64(x) ((x) & 0x1) /* 64-bit capable */
-#define XHCI_HCC_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */
-#define XHCI_HCC_CSZ(x) (((x) >> 2) & 0x1) /* context size */
-#define XHCI_HCC_PPC(x) (((x) >> 3) & 0x1) /* port power control */
-#define XHCI_HCC_PIND(x) (((x) >> 4) & 0x1) /* port indicators */
-#define XHCI_HCC_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */
-#define XHCI_HCC_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */
-#define XHCI_HCC_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */
-#define XHCI_HCC_MAXPSASIZE(x) (((x) >> 12) & 0xF) /* max pri. stream array size */
-#define XHCI_HCC_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */
+#define XHCI_HCC_AC64(x) __SHIFTOUT(x, __BIT(0)) /* 64-bit capable */
+#define XHCI_HCC_BNC(x) __SHIFTOUT(x, __BIT(1)) /* BW negotiation */
+#define XHCI_HCC_CSZ(x) __SHIFTOUT(x, __BIT(2)) /* context size */
+#define XHCI_HCC_PPC(x) __SHIFTOUT(x, __BIT(3)) /* port power control */
+#define XHCI_HCC_PIND(x) __SHIFTOUT(x, __BIT(4)) /* port indicators */
+#define XHCI_HCC_LHRC(x) __SHIFTOUT(x, __BIT(5)) /* light HC reset */
+#define XHCI_HCC_LTC(x) __SHIFTOUT(x, __BIT(6)) /* latency tolerance msg */
+#define XHCI_HCC_NSS(x) __SHIFTOUT(x, __BIT(7)) /* no secondary sid */
+#define XHCI_HCC_MAXPSASIZE(x) __SHIFTOUT(x, __BITS(15, 12)) /* max pri. stream array size */
+#define XHCI_HCC_XECP(x) __SHIFTOUT(x, __BITS(31, 16)) /* extended capabilities pointer */
#define XHCI_DBOFF 0x14 /* RO doorbell offset */
#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */
@@ -112,82 +112,82 @@
#define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */
/* XHCI port status registers */
-#define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */
-#define XHCI_PS_CCS 0x00000001 /* RO - current connect status */
-#define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */
-#define XHCI_PS_OCA 0x00000008 /* RO - over current active */
-#define XHCI_PS_PR 0x00000010 /* RW - port reset */
-#define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */
-#define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */
-#define XHCI_PS_PP 0x00000200 /* RW - port power */
-#define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */
-#define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */
-#define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */
-#define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */
-#define XHCI_PS_CSC 0x00020000 /* RW - connect status change */
-#define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */
-#define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */
-#define XHCI_PS_OCC 0x00100000 /* RW - over-current change */
-#define XHCI_PS_PRC 0x00200000 /* RW - port reset change */
-#define XHCI_PS_PLC 0x00400000 /* RW - port link state change */
-#define XHCI_PS_CEC 0x00800000 /* RW - config error change */
-#define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */
-#define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */
-#define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */
-#define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */
-#define XHCI_PS_DR 0x40000000 /* RO - device removable */
-#define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */
+#define XHCI_PORTSC(n) (0x400 + 0x10 * (n - 1)) /* XHCI port status */
+#define XHCI_PS_CCS __BIT(0) /* RO - current connect status */
+#define XHCI_PS_PED __BIT(1) /* RW - port enabled / disabled */
+#define XHCI_PS_OCA __BIT(3) /* RO - over current active */
+#define XHCI_PS_PR __BIT(4) /* RW - port reset */
+#define XHCI_PS_PLS_GET(x) __SHIFTOUT(x, __BITS(8, 5)) /* RW - port link state */
+#define XHCI_PS_PLS_SET(x) __SHIFTIN(x, __BITS(8, 5)) /* RW - port link state */
+#define XHCI_PS_PP __BIT(9) /* RW - port power */
+#define XHCI_PS_SPEED_GET(x) __SHIFTOUT(x, __BITS(13, 10)) /* RO - port speed */
+#define XHCI_PS_PIC_GET(x) __SHIFTOUT(x, __BITS(15, 14)) /* RW - port indicator */
+#define XHCI_PS_PIC_SET(x) __SHIFTIN(x, __BITS(15, 14)) /* RW - port indicator */
+#define XHCI_PS_LWS __BIT(16) /* RW - port link state write strobe */
+#define XHCI_PS_CSC __BIT(17) /* RW - connect status change */
+#define XHCI_PS_PEC __BIT(18) /* RW - port enable/disable change */
+#define XHCI_PS_WRC __BIT(19) /* RW - warm port reset change */
+#define XHCI_PS_OCC __BIT(20) /* RW - over-current change */
+#define XHCI_PS_PRC __BIT(21) /* RW - port reset change */
+#define XHCI_PS_PLC __BIT(22) /* RW - port link state change */
+#define XHCI_PS_CEC __BIT(23) /* RW - config error change */
+#define XHCI_PS_CAS __BIT(24) /* RO - cold attach status */
+#define XHCI_PS_WCE __BIT(25) /* RW - wake on connect enable */
+#define XHCI_PS_WDE __BIT(26) /* RW - wake on disconnect enable */
+#define XHCI_PS_WOE __BIT(27) /* RW - wake on over-current enable */
+#define XHCI_PS_DR __BIT(30) /* RO - device removable */
+#define XHCI_PS_WPR __BIT(31) /* RW - warm port reset */
#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */
-#define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */
-#define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */
-#define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */
-#define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */
-#define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */
-#define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */
-#define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */
-#define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */
-#define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */
-#define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */
-#define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */
-#define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */
-#define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */
-#define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */
-#define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */
-#define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */
+#define XHCI_PORTPMSC(n) (0x404 + (0x10 * (n - 1))) /* XHCI status and control */
+#define XHCI_PM3_U1TO_GET(x) __SHIFTOUT(x, __BITS(7, 0)) /* RW - U1 timeout */
+#define XHCI_PM3_U1TO_SET(x) __SHIFTIN(x, __BITS(7, 0)) /* RW - U1 timeout */
+#define XHCI_PM3_U2TO_GET(x) __SHIFTOUT(x, __BITS(15, 8)) /* RW - U2 timeout */
+#define XHCI_PM3_U2TO_SET(x) __SHIFTIN(x, __BITS(15, 8)) /* RW - U2 timeout */
+#define XHCI_PM3_FLA __BIT(16) /* RW - Force Link PM Accept */
+#define XHCI_PM2_L1S_GET(x) __SHIFTOUT(x, __BITS(2, 0)) /* RO - L1 status */
+#define XHCI_PM2_RWE __BIT(3) /* RW - remote wakup enable */
+#define XHCI_PM2_HIRD_GET(x) __SHIFTOUT(x, __BITS(7, 4)) /* RW - host initiated resume duration */
+#define XHCI_PM2_HIRD_SET(x) __SHIFTIN(x, __BITS(7, 4)) /* RW - host initiated resume duration */
+#define XHCI_PM2_L1SLOT_GET(x) __SHIFTOUT(x, __BITS(15, 8)) /* RW - L1 device slot */
+#define XHCI_PM2_L1SLOT_SET(x) __SHIFTIN(x, __BITS(15, 8)) /* RW - L1 device slot */
+#define XHCI_PM2_HLE __BIT(16) /* RW - hardware LPM enable */
+#define XHCI_PORTLI(n) (0x408 + (0x10 * (n - 1)) /* XHCI port link info */
+#define XHCI_PLI3_ERR_GET(x) __SHIFTOUT(x, __BITS(15, 0)) /* RO - port link errors */
+#define XHCI_PORTRSV(n) (0x40c + (0x10 * (n - 1))) /* XHCI port reserved */
/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */
#define XHCI_MFINDEX 0x0000 /* RO - microframe index */
-#define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF)
-#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */
-#define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */
-#define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */
-#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */
-#define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */
-#define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */
-#define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */
-#define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */
+#define XHCI_MFINDEX_GET(x) __SHIFTOUT(x, __BITS(13, 0))
+#define XHCI_IMAN(n) (0x0020 + (0x20 * (32 * (n)))) /* XHCI interrupt management */
+#define XHCI_IMAN_INTR_PEND __BIT(0) /* RW - interrupt pending */
+#define XHCI_IMAN_INTR_ENA __BIT(1) /* RW - interrupt enable */
+#define XHCI_IMOD(n) (0x024 + (32 * (n))) /* XHCI interrupt moderation */
+#define XHCI_IMOD_IVAL_GET(x) __SHIFTOUT(x, __BITS(15, 0)) /* 250ns unit */
+#define XHCI_IMOD_IVAL_SET(x) __SHIFTIN(x, __BITS(15, 0)) /* 250ns unit */
+#define XHCI_IMOD_ICNT_GET(x) __SHIFTOUT(x, __BITS(31, 16)) /* 250ns unit */
+#define XHCI_IMOD_ICNT_SET(x) __SHIFTIN(x, __BITS(31, 16)) /* 250ns unit */
#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */
-#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */
-#define XHCI_ERSTS_GET(x) ((x) & 0xFFFF)
-#define XHCI_ERSTS_SET(x) ((x) & 0xFFFF)
-#define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */
-#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */
-#define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */
-#define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */
-#define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */
-#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */
+#define XHCI_ERSTSZ(n) (0x0028 + (32 * (n))) /* XHCI event ring segment table size */
+#define XHCI_ERSTS_GET(x) __SHIFTOUT(x, __BITS(15, 0))
+#define XHCI_ERSTS_SET(x) __SHIFTIN(x, __BITS(15, 0))
+#define XHCI_ERSTBA(n) (0x0030 + (32 * (n))) /* XHCI event ring segment table BA */
+#define XHCI_ERSTBA_HI(n) (0x0030 + 0x4 + (32 * (n))) /* XHCI event ring segment table BA */
+#define XHCI_ERDP(n) (0x0038 + (32 * (n))) /* XHCI event ring dequeue pointer */
+#define XHCI_ERDP_LO_SINDEX(x) __SHIFTOUT(x, __BITS(2, 0)) /* RO - dequeue segment index */
+#define XHCI_ERDP_LO_BUSY __BIT(3) /* RW - event handler busy */
+#define XHCI_ERDP_HI(n) (0x0038 + 0x4 + (32 * (n))) /* XHCI event ring dequeue pointer */
/* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */
#define XHCI_DOORBELL(n) (0x0000 + (4 * (n)))
-#define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */
-#define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */
-#define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */
-#define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */
+#define XHCI_DB_TARGET_GET(x) __SHIFTOUT(x, __BITS(7, 0)) /* RW - doorbell target */
+#define XHCI_DB_TARGET_SET(x) __SHIFTIN(x, __BITS(7, 0)) /* RW - doorbell target */
+#define XHCI_DB_SID_GET(x) __SHIFTOUT(x, __BITS(31, 16)) /* RW - doorbell stream ID */
+#define XHCI_DB_SID_SET(x) __SHIFTIN(x, __BITS(31, 16)) /* RW - doorbell stream ID */
/* XHCI legacy support */
-#define XHCI_XECP_ID(x) ((x) & 0xFF)
-#define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF)
+#define XHCI_XECP_ID(x) __SHIFTOUT(x, __BITS(7, 0))
+#define XHCI_XECP_NEXT(x) __SHIFTOUT(x, __BITS(8, 15))
#if 0
#define XHCI_XECP_BIOS_SEM 0x0002
#define XHCI_XECP_OS_SEM 0x0003
@@ -203,7 +203,7 @@
#define XHCI_PAGE_SIZE(sc) ((sc)->sc_pgsz)
-/* Chapter 6, Table 49 */
+/* Chapter 6, Table 49 (xHCI 1.1 Table 54) */
#define XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN 64
#define XHCI_DEVICE_CONTEXT_ALIGN 64
#define XHCI_INPUT_CONTROL_CONTEXT_ALIGN 64
@@ -212,7 +212,7 @@
#define XHCI_STREAM_CONTEXT_ALIGN 16
#define XHCI_STREAM_ARRAY_ALIGN 16
#define XHCI_TRANSFER_RING_SEGMENTS_ALIGN 16
-#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 16
+#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 64
#define XHCI_EVENT_RING_SEGMENTS_ALIGN 64
#define XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN 64
#define XHCI_SCRATCHPAD_BUFFER_ARRAY_ALIGN 64
@@ -224,52 +224,52 @@
struct xhci_trb {
uint64_t trb_0;
uint32_t trb_2;
-#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
-#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
-#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
-#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
-#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
-#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
-#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
-#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
-#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
-#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
-#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
-#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
+#define XHCI_TRB_2_ERROR_GET(x) __SHIFTOUT(x, __BITS(31, 24)) /* Transfer Event TRB etc. */
+#define XHCI_TRB_2_ERROR_SET(x) __SHIFTIN(x, __BITS(31, 24))
+#define XHCI_TRB_2_TDSZ_GET(x) __SHIFTOUT(x, __BITS(21, 17)) /* Normal TRB */
+#define XHCI_TRB_2_TDSZ_SET(x) __SHIFTIN(x, __BITS(21, 17))
+#define XHCI_TRB_2_REM_GET(x) __SHIFTOUT(x, __BITS(23, 0)) /* Command Completion Event TRB */
+#define XHCI_TRB_2_REM_SET(x) __SHIFTIN(x, __BITS(23, 0))
+#define XHCI_TRB_2_BYTES_GET(x) __SHIFTOUT(x, __BITS(16, 0)) /* Isoch TRB */
+#define XHCI_TRB_2_BYTES_SET(x) __SHIFTIN(x, __BITS(16, 0))
+#define XHCI_TRB_2_IRQ_GET(x) __SHIFTOUT(x, __BITS(31, 22)) /* Normal TRB, Link TRB etc. */
+#define XHCI_TRB_2_IRQ_SET(x) __SHIFTIN(x, __BITS(31, 22))
+#define XHCI_TRB_2_STREAM_GET(x) __SHIFTOUT(x, __BITS(31, 16)) /* Set TR Dequeue Pointer Command TRB */
+#define XHCI_TRB_2_STREAM_SET(x) __SHIFTIN(x, __BITS(31, 16))
uint32_t trb_3;
-#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
-#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
-#define XHCI_TRB_3_CYCLE_BIT (1U << 0)
-#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */
-#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */
-#define XHCI_TRB_3_ISP_BIT (1U << 2)
-#define XHCI_TRB_3_NSNOOP_BIT (1U << 3)
-#define XHCI_TRB_3_CHAIN_BIT (1U << 4)
-#define XHCI_TRB_3_IOC_BIT (1U << 5)
-#define XHCI_TRB_3_IDT_BIT (1U << 6)
-#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3)
-#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7)
-#define XHCI_TRB_3_BEI_BIT (1U << 9)
-#define XHCI_TRB_3_DCEP_BIT (1U << 9)
-#define XHCI_TRB_3_PRSV_BIT (1U << 9)
-#define XHCI_TRB_3_BSR_BIT (1U << 9)
-#define XHCI_TRB_3_TRT_MASK (3U << 16)
-#define XHCI_TRB_3_TRT_NONE (0U << 16)
-#define XHCI_TRB_3_TRT_OUT (2U << 16)
-#define XHCI_TRB_3_TRT_IN (3U << 16)
-#define XHCI_TRB_3_DIR_IN (1U << 16)
-#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
-#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
-#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
-#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
-#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
-#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
-#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31)
-#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23)
-#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
-#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
+#define XHCI_TRB_3_TYPE_GET(x) __SHIFTOUT(x, __BITS(15, 10)) /* Fig. 21 */
+#define XHCI_TRB_3_TYPE_SET(x) __SHIFTIN(x, __BITS(15, 10))
+#define XHCI_TRB_3_CYCLE_BIT __BIT(0)
+#define XHCI_TRB_3_TC_BIT __BIT(1) /* Link TRB */
+#define XHCI_TRB_3_ENT_BIT __BIT(1) /* transfer ring only */
+#define XHCI_TRB_3_ISP_BIT __BIT(2)
+#define XHCI_TRB_3_NSNOOP_BIT __BIT(3)
+#define XHCI_TRB_3_CHAIN_BIT __BIT(4)
+#define XHCI_TRB_3_IOC_BIT __BIT(5)
+#define XHCI_TRB_3_IDT_BIT __BIT(6)
+#define XHCI_TRB_3_TBC_GET(x) __SHIFTOUT(x, __BITS(8, 7))
+#define XHCI_TRB_3_TBC_SET(x) __SHIFTIN(x, __BITS(8, 7))
+#define XHCI_TRB_3_BEI_BIT __BIT(9) /* Normal TRB, Event Data TRB, Isoch TRB */
+#define XHCI_TRB_3_DCEP_BIT __BIT(9) /* Configure Endpoint Command TRB */
+#define XHCI_TRB_3_PRSV_BIT __BIT(9) /* Reset Endpoint Command TRB */
+#define XHCI_TRB_3_BSR_BIT __BIT(9) /* Address Device Command TRB */
+#define XHCI_TRB_3_TRT_MASK __BITS(17, 16) /* Setup Stage TRB */
+#define XHCI_TRB_3_TRT_NONE __SHIFTIN(0, __BITS(17, 16))
+#define XHCI_TRB_3_TRT_OUT __SHIFTIN(2, __BITS(17, 16))
+#define XHCI_TRB_3_TRT_IN __SHIFTIN(3, __BITS(17, 16))
+#define XHCI_TRB_3_DIR_IN __SHIFTIN(1, __BITS(17, 16)) /* Data Stage TRB, Status Stage TRB */
+#define XHCI_TRB_3_TLBPC_GET(x) __SHIFTOUT(x, __BITS(19, 16) /* Isoch TRB */
+#define XHCI_TRB_3_TLBPC_SET(x) __SHIFTIN(x, __BITS(19, 16)
+#define XHCI_TRB_3_EP_GET(x) __SHIFTOUT(x, __BITS(20, 16)) /* Transfer Event TRB */
+#define XHCI_TRB_3_EP_SET(x) __SHIFTIN(x, __BITS(20, 16))
+#define XHCI_TRB_3_FRID_GET(x) __SHIFTOUT(x, __BITS(30, 20)) /* Isoch TRB */
+#define XHCI_TRB_3_FRID_SET(x) __SHIFTIN(x, __BITS(30, 20))
+#define XHCI_TRB_3_ISO_SIA_BIT __BIT(31)
+#define XHCI_TRB_3_SUSP_EP_BIT __BIT(23) /* Stop Endpoint Command TRB */
+#define XHCI_TRB_3_SLOT_GET(x) __SHIFTOUT(x, __BITS(31, 24))
+#define XHCI_TRB_3_SLOT_SET(x) __SHIFTIN(x, __BITS(31, 24))
- /* Commands */
+ /* Commands (TRB Type; xHCI 1.1 Table 139) */
#define XHCI_TRB_TYPE_RESERVED 0x00
#define XHCI_TRB_TYPE_NORMAL 0x01
#define XHCI_TRB_TYPE_SETUP_STAGE 0x02
@@ -305,7 +305,7 @@
#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
- /* Error codes */
+ /* Error codes (xHCI 1.1 Table 138; TRB Completion Codes)*/
#define XHCI_TRB_ERROR_INVALID 0x00
#define XHCI_TRB_ERROR_SUCCESS 0x01
#define XHCI_TRB_ERROR_DATA_BUF 0x02
@@ -344,76 +344,77 @@
} __packed __aligned(XHCI_TRB_ALIGN);
#define XHCI_TRB_SIZE sizeof(struct xhci_trb)
-#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
-#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
-#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
-#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
-#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
-#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
-#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
-#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
-#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
-#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
-
-#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
-#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
-#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
-#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
-#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
-#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
-
-#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
-#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
-#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
-#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
-#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
-#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
-#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
-#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
-
-#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
-#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
-#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
-#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
-
-
-#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
-#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
-#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
-#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
-#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
-#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
-#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
-#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
-#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
-#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
-
-#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
-#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
-#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
-#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
-#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
-#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
-#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
-#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
-#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
-#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
+/* Slot Context (xHCI 1.1 Table 57) */
+#define XHCI_SCTX_0_ROUTE_SET(x) __SHIFTIN(x, __BITS(19, 0))
+#define XHCI_SCTX_0_ROUTE_GET(x) __SHIFTOUT(x, __BITS(19, 0))
+#define XHCI_SCTX_0_SPEED_SET(x) __SHIFTIN(x, __BITS(23, 20))
+#define XHCI_SCTX_0_SPEED_GET(x) __SHIFTOUT(x, __BITS(23, 20))
+#define XHCI_SCTX_0_MTT_SET(x) __SHIFTIN(x, __BIT(25))
+#define XHCI_SCTX_0_MTT_GET(x) __SHIFTOUT(x, __BIT(25))
+#define XHCI_SCTX_0_HUB_SET(x) __SHIFTIN(x, __BIT(26))
+#define XHCI_SCTX_0_HUB_GET(x) __SHIFTOUT(x, __BIT(26))
+#define XHCI_SCTX_0_CTX_NUM_SET(x) __SHIFTIN(x, __BITS(31, 27))
+#define XHCI_SCTX_0_CTX_NUM_GET(x) __SHIFTOUT(x, __BITS(31, 27))
+
+#define XHCI_SCTX_1_MAX_EL_SET(x) __SHIFTIN(x, __BITS(15, 0))
+#define XHCI_SCTX_1_MAX_EL_GET(x) __SHIFTOUT(x, __BITS(15, 0))
+#define XHCI_SCTX_1_RH_PORT_SET(x) __SHIFTIN(x, __BITS(23, 16))
+#define XHCI_SCTX_1_RH_PORT_GET(x) __SHIFTOUT(x, __BITS(23, 16))
+#define XHCI_SCTX_1_NUM_PORTS_SET(x) __SHIFTIN(x, __BITS(31, 24))
+#define XHCI_SCTX_1_NUM_PORTS_GET(x) __SHIFTOUT(x, __BITS(31, 24))
+
+#define XHCI_SCTX_2_TT_HUB_SID_SET(x) __SHIFTIN(x, __BITS(7, 0))
+#define XHCI_SCTX_2_TT_HUB_SID_GET(x) __SHIFTOUT(x, __BITS(7, 0))
+#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) __SHIFTIN(x, __BITS(15, 8))
+#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) __SHIFTOUT(x, __BITS(15, 8))
+#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) __SHIFTIN(x, __BITS(17, 16))
+#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) __SHIFTOUT(x, __BITS(17, 16))
+#define XHCI_SCTX_2_IRQ_TARGET_SET(x) __SHIFTIN(x, __BITS(31, 22))
+#define XHCI_SCTX_2_IRQ_TARGET_GET(x) __SHIFTOUT(x, __BITS(31, 22))
+
+#define XHCI_SCTX_3_DEV_ADDR_SET(x) __SHIFTIN(x, __BITS(7, 0))
+#define XHCI_SCTX_3_DEV_ADDR_GET(x) __SHIFTOUT(x, __BITS(7, 0))
+#define XHCI_SCTX_3_SLOT_STATE_SET(x) __SHIFTIN(x, __BITS(31, 27))
+#define XHCI_SCTX_3_SLOT_STATE_GET(x) __SHIFTOUT(x, __BITS(31, 27))
+
+/* Endpoint Context */
+#define XHCI_EPCTX_0_EPSTATE_SET(x) __SHIFTIN(x, __BITS(2, 0))
+#define XHCI_EPCTX_0_EPSTATE_GET(x) __SHIFTOUT(x, __BITS(2, 0))
+#define XHCI_EPCTX_0_MULT_SET(x) __SHIFTIN(x, __BITS(9, 8))
+#define XHCI_EPCTX_0_MULT_GET(x) __SHIFTOUT(x, __BITS(9, 8))
+#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) __SHIFTIN(x, __BITS(14, 10))
+#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) __SHIFTOUT(x, __BITS(14, 10))
+#define XHCI_EPCTX_0_LSA_SET(x) __SHIFTIN(x, __BIT(15))
+#define XHCI_EPCTX_0_LSA_GET(x) __SHIFTOUT(x, __BIT(15))
+#define XHCI_EPCTX_0_IVAL_SET(x) __SHIFTIN(x, __BITS(23, 16))
+#define XHCI_EPCTX_0_IVAL_GET(x) __SHIFTOUT(x, __BITS(23, 16))
+
+#define XHCI_EPCTX_1_CERR_SET(x) __SHIFTIN(x, __BITS(2, 1))
+#define XHCI_EPCTX_1_CERR_GET(x) __SHIFTOUT(x, __BITS(2, 1))
+#define XHCI_EPCTX_1_EPTYPE_SET(x) __SHIFTIN(x, __BITS(5, 3))
+#define XHCI_EPCTX_1_EPTYPE_GET(x) __SHIFTOUT(x, __BITS(5, 3))
+#define XHCI_EPCTX_1_HID_SET(x) __SHIFTIN(x, __BIT(7))
+#define XHCI_EPCTX_1_HID_GET(x) __SHIFTOUT(x, __BIT(7))
+#define XHCI_EPCTX_1_MAXB_SET(x) __SHIFTIN(x, __BITS(15, 8))
+#define XHCI_EPCTX_1_MAXB_GET(x) __SHIFTOUT(x, __BITS(15, 8))
+#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) __SHIFTIN(x, __BITS(31, 16))
+#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) __SHIFTOUT(x, __BITS(31, 16))
-#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
-#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
+#define XHCI_EPCTX_2_DCS_SET(x) __SHIFTIN(x, __BIT(0))
+#define XHCI_EPCTX_2_DCS_GET(x) __SHIFTOUT(x, __BIT(0))
#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
-#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
-#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
-#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
-#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
-
+#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) __SHIFTIN(x, __BITS(15, 0))
+#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) __SHIFTOUT(x, __BITS(15, 0))
+#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) __SHIFTIN(x, __BITS(31, 16))
+#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) __SHIFTOUT(x, __BITS(31, 16))
+/* Input Context */
#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
-#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n))
+#define XHCI_INCTX_0_DROP_MASK(n) __BIT(n)
-#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n))
+#define XHCI_INCTX_1_ADD_MASK(n) __BIT(n)
struct xhci_erste {
