Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO toadigital logic standard
From: "Bill Hawkins" <[EMAIL PROTECTED]> Subject: RE: [time-nuts] Interfacing a 8dBm sine output of an OCXO toadigital logic standard Date: Fri, 16 Sep 2005 18:42:36 -0500 Message-ID: <[EMAIL PROTECTED]> > Magnus Danielson wrote, in part, > > "I wonder if that chip isn't really a DLL after all. They usually are." > > When my brain parses DLL I get data linked library. > > Did you mean phase locked loop? No, I mean Delay Locked Loop. A Delay Locked Loop is a quite different animal than what we usually perceive as a PLL, but have similar behaviours. Wonderfull for CMOS implementation, but the drawback is the jitter. > How do you measure jitter? What instrument? I use a high BW undersampling scope with high resolution time base, such as a Tek CSA 803, CSA 8000 or Agilent 86100. You need to use a power-splitter to get a trigger signal (for all three you need a separate trigger) and the other to the sampling head but only after being delayed through a cable to compensate for the trigger delay in the scope as they are not compensated within, that is only done in real-time sampling scopes which just samples and store before the trigger kicks in. The delay-cable needs to be longer than the delay-time, so that one clearly can view the trigger point. This is necessary in order to establish the trigger jitter. Tek made a box called DL-11 which was a delay- line intended for this purpose, but I use a standard cable cut into a suitable delay. I can use the reading from the next rising edge directly, but I should really compensate it by taking the root of the squared value minus the squared trigger noise to get a more accurate measure. There are other scopes that can be used too. Notice that I use scopes to get the cycle-to-cycle jitter measure, which is not the same as a normal phase-noise analysis. You can take a phase-noise plot and convert it over, but it is so easy to measure it with a scope you have standing around in the lab anyway, so that is what I choose to use. Wouln't mine a real phase-noise system, but it really isn't needed. Cheers, Magnus ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
RE: [time-nuts] Interfacing a 8dBm sine output of an OCXO toadigital logic standard
Magnus Danielson wrote, in part, "I wonder if that chip isn't really a DLL after all. They usually are." When my brain parses DLL I get data linked library. Did you mean phase locked loop? How do you measure jitter? What instrument? Bill Hawkins ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
From: "Poul-Henning Kamp" <[EMAIL PROTECTED]> Subject: Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard Date: Fri, 16 Sep 2005 17:19:33 +0200 Message-ID: <[EMAIL PROTECTED]> > In message <[EMAIL PROTECTED]>, "Richard \(Ric > k\) Karlquist \(N6RK\)" writes: > >>http://www.icst.com/datasheets/ics2305.pdf > >> > >> ICS has many interesting clock chips which can be used for other > >> uses than what they were designed. Worth a browse. > >> -- > >> Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 > > > >This chip has 200 ps of jitter! There is no way you would > >want to use this with an OCXO. > > Be aware they don't mean the same with "jitter" as you do: they > include production tolerances, so the 200ps is the worst case jitter > measured between two output pins on a large lot of chips, not the > jitter you would measure on a single output on a single chip. No, it is the jitter of a single output, in a loaded case. It's all in the JEDEC standard. It should also be noted that it is the cycle-to-cycle jitter, so triggering at the rising edge of the 66,67 MHz clock what will the jitter of the rising edge 15 ns (one cycle away) from the trigger point be. These vendors tend to specify it as "peak-to-peak" where as I tend to use the RMS measure since if we only see Gaussian phase-noise (actually we are non-Gaussian but at tau = 15 ns the non-Gaussian noise is well suppressed) and then we can use the RMS measure, since the peak-to-peak range will expand as we measure a longer series where as the RMS value stabilizes. It is also good to see if there is any deterministic jitter component, but if it is a good design there isn't a trace of one. The hell with being able to measure jitter easilly is that you get aware just how bad stuff is all over the place! :P Cheers, Magnus ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
From: "Richard \(Rick\) Karlquist \(N6RK\)" <[EMAIL PROTECTED]> Subject: RE: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard Date: Fri, 16 Sep 2005 08:13:40 -0700 Message-ID: <[EMAIL PROTECTED]> > > http://www.icst.com/datasheets/ics2305.pdf > > > > ICS has many interesting clock chips which can be used for other > > uses than what they were designed. Worth a browse. > > -- > > Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 > > This chip has 200 ps of jitter! There is no way you would > want to use this with an OCXO. 200 ps at 66,67 MHz of jitter is bad, really bad. When I see that on oscillators I toss it unless I know it is for some quite tolerant part of the design. 2 ps RMS or less is what I usually expect to see from oscillators. I wonder if that chip isn't really a DLL after all. They usually are. Cheers, Magnus ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
Poul-Henning Kamp wrote: Just remember to stay well away from "spread spectrum" or disable it if possible. It's a 50-75 kHz FM to make the computer sneak under the EMI masks. Actually, it's a sneak to allow 15 to 20 dB greater EMI from the typical PC. The motherboard makers provide a control bit in BIOS to disable spread spectrum for normal operation, informing the user that it is to be enabled for agency testing only. The agencies should force the BIOS writers to remove that bit, since it allows the hardware to be rendered non-compliant under user control. ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
At 09:43 AM 9/16/2005 , Poul-Henning Kamp wrote: > >In modern computers the synchronous RAM requires clock signals which >have very tight specs on delay and jitter and the only way this is >possible in practice is by using 1:1 PLL's as "zero delay buffers". > >See for instance: > > http://www.icst.com/datasheets/ics2305.pdf > >ICS has many interesting clock chips which can be used for other >uses than what they were designed. Worth a browse. I used one to multiple my 10MHz OCXO reference to 80MHz. The idea was to replace the little 80MHz "clock box" oscillator in a Sun IPX with a precision clock source. Didn't work. I guess the IPX doesn't derive its 100Hz ticker from the CPU clock. -- newell N5NTL ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
In message <[EMAIL PROTECTED]>, David Kirkby writes: >Poul-Henning Kamp wrote: >> http://www.icst.com/datasheets/ics2305.pdf >> >> Be aware they don't mean the same with "jitter" as you do: they >> include production tolerances, so the 200ps is the worst case jitter >> measured between two output pins on a large lot of chips, not the >> jitter you would measure on a single output on a single chip. > >What you are describing sounds more like the 700ps "Device to Device Skew". Hmm, could be, I just picked this datasheet as an example of the concept, I didn't look at the actual numbers. Newer devices are down below 50ps jitter or rather: newer memory mandates that they be. Just remember to stay well away from "spread spectrum" or disable it if possible. It's a 50-75 kHz FM to make the computer sneak under the EMI masks. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 [EMAIL PROTECTED] | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
David Kirkby wrote: Poul-Henning Kamp wrote: In message <[EMAIL PROTECTED]>, "Richard \(Ric k\) Karlquist \(N6RK\)" writes: http://www.icst.com/datasheets/ics2305.pdf ICS has many interesting clock chips which can be used for other uses than what they were designed. Worth a browse. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 This chip has 200 ps of jitter! There is no way you would want to use this with an OCXO. Be aware they don't mean the same with "jitter" as you do: they include production tolerances, so the 200ps is the worst case jitter measured between two output pins on a large lot of chips, not the jitter you would measure on a single output on a single chip. What you are describing sounds more like the 700ps "Device to Device Skew". I used one of those chips about 5 years ago on a CPU board, and it did have about 100ps of jitter. It was horrible as a clock source. I think it was suffering a bit from being on a CPU board, though, with all the digital switching noise around it. Later versions were better, but still not very good by analog PLL standards. ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
Poul-Henning Kamp wrote: In message <[EMAIL PROTECTED]>, "Richard \(Ric k\) Karlquist \(N6RK\)" writes: http://www.icst.com/datasheets/ics2305.pdf ICS has many interesting clock chips which can be used for other uses than what they were designed. Worth a browse. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 This chip has 200 ps of jitter! There is no way you would want to use this with an OCXO. Be aware they don't mean the same with "jitter" as you do: they include production tolerances, so the 200ps is the worst case jitter measured between two output pins on a large lot of chips, not the jitter you would measure on a single output on a single chip. What you are describing sounds more like the 700ps "Device to Device Skew". -- David Kirkby, G8WRB Please check out http://www.g8wrb.org/ of if you live in Essex http://www.southminster-branch-line.org.uk/ ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
[time-nuts] Interfacing a 8 dbm sine output of an OCXO to a digital logic standard
Here is a copy of the circuit I use. I used a 74AC132, as I needed 3 sections of it for a sync circuit. So the unused gate was configured to be a gate for the input section. You can also use 74AC04 and 74AC14s. Input.pdf Description: Adobe PDF document ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
[time-nuts] Helium to cesium converter
Can anyone tell me what this item would be used for? It really started the old brain churning when one of my contacts from France sent the URL to me. I have wondered if it is labeled wrong and actually converts cesium frequency to helium frequency. Then I could see some uses for it in testing lasers and things but not if it is the other way around. I can't imagine how it got listed in the motors section on ebay. Thanks, Chuck http://cgi.ebay.com/ebaymotors/ws/eBayISAPI.dll?ViewItem&item=4575700463&sspagename=ADME%3AB%3ASS%3AFR%3A1 ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
In message <[EMAIL PROTECTED]>, "Richard \(Ric k\) Karlquist \(N6RK\)" writes: >> http://www.icst.com/datasheets/ics2305.pdf >> >> ICS has many interesting clock chips which can be used for other >> uses than what they were designed. Worth a browse. >> -- >> Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 > >This chip has 200 ps of jitter! There is no way you would >want to use this with an OCXO. Be aware they don't mean the same with "jitter" as you do: they include production tolerances, so the 200ps is the worst case jitter measured between two output pins on a large lot of chips, not the jitter you would measure on a single output on a single chip. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 [EMAIL PROTECTED] | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
RE: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigital logic standard
> http://www.icst.com/datasheets/ics2305.pdf > > ICS has many interesting clock chips which can be used for other > uses than what they were designed. Worth a browse. > -- > Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 This chip has 200 ps of jitter! There is no way you would want to use this with an OCXO. Rick Karlquist N6RK ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
RE: [time-nuts] Interfacing a 8dBm sine output of an OCXO to adigitallogic standard
> I can imagine that the sine wave must be squared off > > using a fast comparator and then fed through to a logic > > driver. Are there any integrated IC's out there that does > > this? It would be rather sad to sustain substantial phase > > noise degradation due to a floating comparator threshold and > > limited slew rate. > > > > Stephan Sandenbergh A comparator IC is the worst possible circuit you could use. Especially a fast one. Fast comparators have higher analog bandwidth, which means a greater noise bandwidth for the purpose of noise aliasing. Also, the propagation delay of comparators is very temperature and amplitude dependent (ie AM to PM noise conversion). The simplest circuit that is any good is to simply capacitively couple the sine wave into the clock input of a 74ACXX series logic gate. Use 10K resistors to ground and +5V to DC bias the input to +2.5V. Do NOT use 74HCXX logic for this. We used the 74ACXX trick in the HP/Agilent/Symmetricom 5071A cesium clock at 80 MHz, although it was not in a place that needed extremely low phase noise. The best circuits involve using bandlimited, low distortion, low phase noise amplifiers to produce a large sine wave which is then passively limited with diodes. You can also get away with driving a differential pair with a common current source for the emitters. A classic paper on zero crossing detectors by JPL's John Dick at the 1990 PTTI explains the theory behind all this. Rick Karlquist N6RK ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to a digital logic standard
In message <[EMAIL PROTECTED]>, David Forbes writes: >>My very stable OCXO output a 8dBm (50ohm) sine wave. How is this signal >>converted/interfaced to a logic standard (e.g. LVDS)? The best way to do it is actually with 1:1 PLL. In modern computers the synchronous RAM requires clock signals which have very tight specs on delay and jitter and the only way this is possible in practice is by using 1:1 PLL's as "zero delay buffers". See for instance: http://www.icst.com/datasheets/ics2305.pdf ICS has many interesting clock chips which can be used for other uses than what they were designed. Worth a browse. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 [EMAIL PROTECTED] | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to a digital logic standard
At 12:49 PM +0200 9/16/05, Stephan Sandenbergh wrote: I wondered if anyone could help me with an interfacing problem? I guess that it is a trivial question to those that know, but I am rather puzzled by it. My very stable OCXO output a 8dBm (50ohm) sine wave. How is this signal converted/interfaced to a logic standard (e.g. LVDS)? I can imagine that the sine wave must be squared off using a fast comparator and then fed through to a logic driver. Are there any integrated IC's out there that does this? It would be rather sad to sustain substantial phase noise degradation due to a floating comparator threshold and limited slew rate. Regards, Stephan Sandenbergh Stephan, Hi. I had to build such a circuit a couple years ago, and used a bit of overkill... First, I sent the 10 MHz signal through a two-section LC bandpass filter to remove any externally-generated noise. Then I detected the zero crossing with an AD8561 fast comparator chip. This circuit is tuned to 10 MHz. Schematic here: http://www.nixiebunny.com/FBEPP-A.pdf -- --David Forbes, Tucson, AZ http://www.cathodecorner.com/ ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
[time-nuts] Re: Interfacing a 8dBm sine output of an OCXO to a digital logic standard
Stephan Sandenbergh wrote: I wondered if anyone could help me with an interfacing problem? I guess that it is a trivial question to those that know, but I am rather puzzled by it. My very stable OCXO output a 8dBm (50ohm) sine wave. How is this signal converted/interfaced to a logic standard (e.g. LVDS)? I can imagine that the sine wave must be squared off using a fast comparator and then fed through to a logic driver. Are there any integrated IC's out there that does this? It would be rather sad to sustain substantial phase noise degradation due to a floating comparator threshold and limited slew rate. In my own GPSDO I have used this circuit : http://sundry.i2phd.com/squarer.gif It was taken from the book "Experimental methods in RF design" and works quite well, though no specific measurements of phase noise degradation have been made. The 10 MHz input is coming from an Isotemp OCXO, which delivers abt 3.5V pk_to_pk open circuit 73 Alberto I2PHD ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
AW: [time-nuts] Interfacing a 8dBm sine output of an OCXO to a digitallogic standard
Stephan, if you like it i can send you the manual of a Efratom LPRO rubidium standard in which several circuits for sine-to-ttl conversion are shown and discussed in terms of low phase noise. Best regards Ulrich Bangert > -Ursprüngliche Nachricht- > Von: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] Im Auftrag von Stephan Sandenbergh > Gesendet: Freitag, 16. September 2005 12:49 > An: time-nuts@febo.com > Betreff: [time-nuts] Interfacing a 8dBm sine output of an > OCXO to a digitallogic standard > > > I wondered if anyone could help me with an interfacing > problem? I guess that it is a trivial question to those that > know, but I am rather puzzled by it. > > My very stable OCXO output a 8dBm (50ohm) sine wave. How is > this signal converted/interfaced to a logic standard (e.g. > LVDS)? I can imagine that the sine wave must be squared off > using a fast comparator and then fed through to a logic > driver. Are there any integrated IC's out there that does > this? It would be rather sad to sustain substantial phase > noise degradation due to a floating comparator threshold and > limited slew rate. > > Regards, > > Stephan Sandenbergh > > > > > ___ > time-nuts mailing list > time-nuts@febo.com > https://www.febo.com/cgi-> bin/mailman/listinfo/time-nuts > ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
RE: [time-nuts] RE: HP 107BR
Thanks to the generosity of Chuck Harris in loaning me a manual, my HP 107BR is now back in service, or at least warming up back to a stable state. Shorted Zener diode (CR2 32 volt) and burned out series resistor (R1) replaced and all OK again. I have made three extra Xerox copies of the manual (2 side to 1 side, double copies of schematics), that are now available to whoever needs. Please advise. 73 Les K1YCM/3 Full Name: Lester B Veenstra Job Title: Computer Sys Des Engr Sr Stf Department: 6L01 Company:Integrated Systems & Solutions Business Address: 133 National Business Parkway Cube 224 Annapolis Junction, MD 20701 United States Business: 240/425-7335 Mobile: 240/425-7335 Pager: 240/425-7335 E-mail: [EMAIL PROTECTED] -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Veenstra, Lester Sent: Thursday, September 15, 2005 9:30 AM To: time-nuts@febo.com Subject: [time-nuts] RE: HP 107BR > I have a problem with my old faithful standard, an HP 107BR. The > regulated voltages are zero, although the raw +46 is there. Anyone > have a power supply schematic I could set a copy of? > > Well aged standard. It did better than 30 years service in our Paumalu > Hi Intelsat earth station before moving the K1YCM/3 for additional > service. > > Thanks > Les > > Full Name:Lester B Veenstra > Job Title:Computer Sys Des Engr Sr Stf > Department: 6L01 > Company: Integrated Systems & Solutions > > Business Address: 133 National Business Parkway > Cube 224 > Annapolis Junction, MD 20701 > United States > > Business: 240/425-7335 > Mobile: 240/425-7335 > Pager:240/425-7335 > > E-mail: [EMAIL PROTECTED] > > > << File: Veenstra, Lester.vcf >> ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts BEGIN:VCARD VERSION:2.1 N:Veenstra;Lester FN:Veenstra, Lester ORG:Integrated Systems & Solutions;6L01 TITLE:Computer Sys Des Engr Sr Stf TEL;WORK;VOICE:240/425-7335 TEL;CELL;VOICE:240/425-7335 TEL;PAGER;VOICE:240/425-7335 ADR;WORK;ENCODING=QUOTED-PRINTABLE:;Floor: 2 Column: 224 Room: 103 MailDrop: cube 224;133 National Business Par= kway=0D=0ALMCO IS&S Suite 200 Cube 224;Annapolis Junction;MD;20701;United St= ates LABEL;WORK;ENCODING=QUOTED-PRINTABLE:Floor: 2 Column: 224 Room: 103 MailDrop: cube 224=0D=0A133 National Business= Parkway=0D=0ALMCO IS&S Suite 200 Cube 224=0D=0AAnnapolis Junction, MD 20701= =0D=0AUnited States EMAIL;PREF;INTERNET:[EMAIL PROTECTED] REV:20050914T142238Z END:VCARD ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] Interfacing a 8dBm sine output of an OCXO to a digital logic standard
Stephan Sandenbergh wrote: I wondered if anyone could help me with an interfacing problem? I guess that it is a trivial question to those that know, but I am rather puzzled by it. My very stable OCXO output a 8dBm (50ohm) sine wave. How is this signal converted/interfaced to a logic standard (e.g. LVDS)? I can imagine that the sine wave must be squared off using a fast comparator and then fed through to a logic driver. Are there any integrated IC's out there that does this? It would be rather sad to sustain substantial phase noise degradation due to a floating comparator threshold and limited slew rate. Stephan, I don't know if this is the *best* answer, but I've stolen an idea used by Brooks Shera in his GPSDO controller. He uses the input section (only) of a 74HCT4046 PLL chip to square the OCXO signal. I implemented his idea using a 74AC4046 and it seems to work OK, though I don't know what its jitter/phase noise performance is. A schematic of my circuit is at http://www.febo.com/time-freq/gps/z3801a/mods/index.html. John ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
[time-nuts] Interfacing a 8dBm sine output of an OCXO to a digital logic standard
I wondered if anyone could help me with an interfacing problem? I guess that it is a trivial question to those that know, but I am rather puzzled by it. My very stable OCXO output a 8dBm (50ohm) sine wave. How is this signal converted/interfaced to a logic standard (e.g. LVDS)? I can imagine that the sine wave must be squared off using a fast comparator and then fed through to a logic driver. Are there any integrated IC's out there that does this? It would be rather sad to sustain substantial phase noise degradation due to a floating comparator threshold and limited slew rate. Regards, Stephan Sandenbergh ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Re: [time-nuts] FEI5680A Rubidiums On Ebay
Dear All, I just looked up the AD9832. It has no internal multiplier. Maximum reference CLK-frequency is 25 MHz. Squeezing out 10 MHz.. the wave shape will not be nice, unless extensive filtering is used. I'm not sure if this DDS is used at the end of the "chain" or is a part of the frequency controlloop? If it is at the end of the chain, one could consider disconnnecting the program-pins and program a small PIC to "program" the DDS. Or use the reference clock and connect it to a more recent type of DDS (with internal multiplier), and create a nice 10 MHz sine-wave with the external DDS. I have seen these standards on Ebay as well some time ago I expected all these kind of problems, so I decided not to buy one. However, if the price would have been lower (and if I had more time), I would have bought one. My idea was to modify the unit. Keep some of the original electronics, but redesign the synthesizer and interface part Good luck, hope you will find some way to make the oscillator usefull! Best regards & 73's Jeroen - PE1RGE Rex wrote: On Thu, 15 Sep 2005 16:21:51 +0200, Jeroen Bastemeijer <[EMAIL PROTECTED]> wrote: By the way, did someone look into the type-number of the DDS? Or is it a custom build "discrete" DDS? The FEI5680A uses an AD9832. There is also a Xilinx in it and a couple other big ICs. The output on the one I bought is 1 PPS and 10 MHz. The FEI web page specs a frequency of 1 to 20 MHz and programmable to 1 x 10^-13. FEI has not been friendly in giving any more info. The eBay seller claimed that the unit needed 15V and that info on the FEI web pages described the connector. After returning one, I did a some reverse engineering and figured out that this unit needed 15V *and 5V* to run. I think I have figured out the pins on the D connector, and it does not exactly match the info on the FEI site. Seller claims other satisfied buyers, but I can't imagine how they figured out how to use it unless they have access to some Motorola documents. (It seems it was use in Motorola equipment.) There is a MAX3232 serial chip in it that connects to the D connector. The seller claimed originally that they programmed like the 5650A, but this is not true. Nothing I ever sent to it on the serial lines ever elicited any response or reaction from the unit. Mine is not exactly on frequency (10 MHz) so it would be nice to have a way to adjust it. Here is part of a message I posted after my crusade to figure this thing out in January... --- To get to the point... by digging at circuits, I eventually figured out they needed +15 V but also +5 V on a different pin. With the two voltages, mine now came up giving 1 PPS and also 10 MHz on a different pin. I have worked out that RS232 Tx and Rx signals (from a MAX3232) come out to two pins on the external DB9 connector. I had expected it would program like the 5650 as described here: http://www.leapsecond.com/museum/fei5650a/ Thus far, I haven't seen any reply to anything I send to the unit on the RS232 pins. So, either these units are not programmable or I just don't know how to talk to them. I have not found any documentation on how to program the 5680A. Does anyone have access to any more information. Did Don Latham work out his published information about the 5650 by logic and guess work or did he have access to something more? I wanted to try all other sources of information before contacting FEI as I have heard they are not that friendly unless money is involved. If it helps, this FE 5680A rubidium was used on a Motorola SGLA4000B High Stability Oscillator (HSO) that was (I think) used in cell sights. -Rex ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts -- Ing. Jeroen Bastemeijer Delft University of Technology Department of Electrical Engineering Electronic Instrumentation Laboratory Mekelweg 4, Room 13.090 2628 CD Delft The Netherlands Phone: +31.15.27.86542 Fax: +31.15.27.85755 E-mail: [EMAIL PROTECTED] ___ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
