Re: [time-nuts] DDS'ery narrow scoped.
Hello, El 21/06/2011 02:19, Luis Cupido escribió: Imagine an FPGA and a square wave coming out. Just that. Nothing more. (That is what I had in mind when querying about the MSB usage in the first place.) My first approach was the ACC MSB (and that is working already on the bench.) I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. What it the topology you're using now? Also, I would like to know which DDS core are you using? (since I will need to use one quite soon, probably on a Cyclone IV E) Best regards, Javier ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
But I forgot to add that the resultant jitter will be also the sampling rate period (10ns at 100MHz), so I think that the output will not be too clean... so I'm afraid it will not be a great improvement over using only the MSB :) Regards, Javier El 21/06/2011 08:37, Javier Herrero escribió: I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. -- Javier HerreroEMAIL: jherr...@hvsistemas.com Chief Technology Officer HV Sistemas S.L. PHONE: +34 949 336 806 Los Charcones, 17 FAX: +34 949 336 792 19170 El Casar - Guadalajara - Spain WEB: http://www.hvsistemas.com ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern? Best regards Ulrich Bangert, DF6JB -Ursprungliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von Luis Cupido Gesendet: Dienstag, 21. Juni 2011 02:20 An: Discussion of precise time and frequency measurement Betreff: [time-nuts] DDS'ery narrow scoped. Folks, Many thanks to you all, for the info. This is indeed a great forum. My aplic. is a DDS signal that will serve as reference for a pll with a relatively narrow loop filter. As I said before. Most replies presume the analog world with DAC filters etc etc. But that I know ;-) I'm digging out the possibilities in the digital side not involving going back to analog and back to digital. this is how this started :-) Now that you all have been so kind in the great comments you gave, please let me just be very very very specific. Imagine an FPGA and a square wave coming out. Just that. Nothing more. (That is what I had in mind when querying about the MSB usage in the first place.) My first approach was the ACC MSB (and that is working already on the bench.) So I'm researching a way to have that digital output cleaner (spurs) without leaving the digital(FPGA) world sticking to the block diagram of one FPGA one digital output. Specially worried about close in spurs (the far away ones won't bother me much). That is really scenario I'm trying to picture if there is any hope to generate a cleaner digital output out of an FPGA (dds with whatever processing required to be done after and producing a square wave). Thanks for your patience. Luis Cupido. ct1dmk P.S. At the moment I'm testing on the bench with a real FPGA cyclone III with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and it is not that bad. I got better than -60dBc in the desired ranges. So not too unhappy for a start ;-) PLL cleans 99% of it... but the close in spurs are annoying. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
In the old days, HI, we used to use 6 dB/bit for SFDR for the DAC as a rule of thumb. In practice, it needed to be somewhat better. So, even with 6 dB/bit it would require a minimum of 25 bits. Good thing back then, in the early 70's I was working on ASW stuff at acoustic frequencies and some of this was doable. However, we did not require a great SFDR. More recently in the late 80's and 90's, I was concerned in getting DDSs in the 500 to 1 GHz range. Lots of RD money and lots of promises, but, no cigar for a real usable product. 73 - Mike Mike B. Feher, EOZ Inc. 89 Arnold Blvd. Howell, NJ, 07731 732-886-5960 office 908-902-3831 cell -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] On Behalf Of Ulrich Bangert Sent: Tuesday, June 21, 2011 5:03 AM To: 'Discussion of precise time and frequency measurement' Subject: Re: [time-nuts] DDS'ery John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To
Re: [time-nuts] DDS'ery
to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? It's being used as part of a digital downconverter in my case, not driving a DAC. In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. I haven't seen any unaccounted-for spurs above -130 to -140 dBc (where they could be coming from pretty much anywhere), so I've been happy with the core's real-world performance. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Hi, I'm an Altera user and would say the DDS core generator is really very good, I would expect it to be not too different from Xilinx these days. (does anyone that lives on both worlds know better ?) lc ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Hi Ulrich, Loop bandwidth could be in the KHz region or even less. I could choose more or less freely from Hz to many KHz but there are obvious tradeoffs and it is hard to decide. The phase noise of the VCO when I go too narrow versus the ammount of spurs when I go too wide. Application is the first LO for an experiment in SDR radio at VHF-SHF region,(not HF). Luis Cupido. ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern? Best regards Ulrich Bangert, DF6JB -Ursprungliche Nachricht- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
Yes that right. Is clear that I would have a 10ns jitter, So the catch would be to find a scheme to spread spurs out or to push them away from carrier. Then they would not bother me (would not pass the PLL). lc ct1dmk. On 6/21/2011 7:43 AM, Javier Herrero wrote: But I forgot to add that the resultant jitter will be also the sampling rate period (10ns at 100MHz), so I think that the output will not be too clean... so I'm afraid it will not be a great improvement over using only the MSB :) Regards, Javier El 21/06/2011 08:37, Javier Herrero escribió: I supppose that then you will need the digital version of the DDS - Filter - Comparator think, usign a FIR and outputing the sign of the resultant signal. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery narrow scoped.
I've played with the core from altera for a while, but since I was only interested in 1 bit I'm now playing with my own code. Trivial variations on the plain old clocked accumulator architecture. lc On 6/21/2011 7:37 AM, Javier Herrero wrote: What it the topology you're using now? Also, I would like to know which DDS core are you using? (since I will need to use one quite soon, probably on a Cyclone IV E) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
Hi, I live in both worlds (more or less :) ), and the tools seems somewhat similar (I suspect that when one of them includes a feature, the other tries to catch the rythm and viceversa). I've had a look to the Xilinx DDS compiler, and it is somewhat different. You can download the free version of the Xilinx ISE Design Suite and play a bit around. For the project where I will implement the DDCON I selected the Altera mainly due to similarities with other project that also uses Altera, availability of development boards around, and also because I'm more familiar with Linux on the Nios-II processor than on the Microblaze (and that for this project I prefer to be in the low end - Cyclone or Spartan - rather than in the higher end - Stratix or Virtex). Regards, Javier El 21/06/2011 12:34, Luis Cupido escribió: Hi, I'm an Altera user and would say the DDS core generator is really very good, I would expect it to be not too different from Xilinx these days. (does anyone that lives on both worlds know better ?) lc ct1dmk. On 6/21/2011 10:03 AM, Ulrich Bangert wrote: John, as usual I second your opinion and I did have already on my mind to suggest XILINX's DDS compiler to the group too. However your statement to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? Best regards Ulrich Bangert, DF6JB -Ursprüngliche Nachricht- Von: time-nuts-boun...@febo.com [mailto:time-nuts-boun...@febo.com] Im Auftrag von John Miles Gesendet: Dienstag, 21. Juni 2011 00:52 An: 'Discussion of precise time and frequency measurement' Betreff: Re: [time-nuts] DDS'ery I'm not familiar with Altera's DDS options, but I will say that Xilinx's DDS compiler is superb. It can be configured to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) As Javier hinted, the reason you can't use the MSB directly is that its transition point is not necessarily stationary between cycles of the frequency you're trying to synthesize. It will flop around all over the place. You need at least a few more bits in most applications -- remember that in an n-bit word, the magnitude represented by the n-1 LSBs is almost as much as the bit-n MSB. When DDS technology was first becoming popular in the 1980s, Qualcomm was one of the main vendors, and they required external DACs. High-speed DACs were pricy and used a lot of power, so I imagine that a great many people tried feeding the MSB directly to the filter, as I did. It could be feasible at some selected frequencies or at very high clock/output ratios, but in the general case the output signal is just comically awful. You would need a truly massive filter to provide the needed flywheel effect to make up for those missing bits. And it would need to be a BPF, not just an LPF, because not all of the artifacts associated with output quantization are above the desired carrier frequency. Sometimes the MSB's toggle period is going to be shorter than it should be, and sometimes it's going to be longer. -- john, KE5FX -Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Luis Cupido Sent: Monday, June 20, 2011 9:46 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Gracias, Javier. As you read in my previous email I'm basically worried about close-in spurs (those that will pass through the PLL loop filter). will digest that 4th section... tks. Since I'm inside an FPGA... I'm eager to get spurs down without leaving the digital world... Anyone knows any literature covering that ? Thanks. Luis cupido. ct1dmk. On 6/20/2011 4:52 PM, Javier Herrero wrote: To reduce the spurii due to quantization distortion. Here is an explanation, in Section 4 http://www.analog.com/static/imported- files/tutorials/450968421DDS_Tutorial_rev12-2-99.pdf Regards, Javier El 20/06/2011 17:39, Luis Cupido escribió: Well, if we really need to filter it out we better filter the MSB and square it again... Why having a DAC for ??? Right ? Luis Cupido. ct1dmk. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi- bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
Re: [time-nuts] DDS'ery
Clever! At least for your spectral measurements the signal never leaves the digital domain. What is the width of the multipliers involved in the mixing? Can you give me a clue, which ADCs you are working with in the front end? In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. This matches exactly my own observations in terms of ripple in the Tau-Sigma digram when i used a standard like DDS from AD for this purpose. Exactly this is why I got interested in the XILNX DDS compiler. May be the ALTERA stuff is on the same level. Have used ALTERA FPGAs and CPLDs in the past but currently I am devoted to XILINX due to the easier availability in Germany. Best regards Ulrich Bangert, DF6JB Am 21.06.2011 um 12:10 schrieb John Miles: to provide SFDR up to 150 dB (and I'd notice it if I were getting much less than that in practice.) has pushed me up! When I tell the compiler to generate me a 150 dB SFDR DDS then it produces an block with 28 (!) bits output witdh for the DAC. So, I am asking myself what wonder-chips you may be using as DAC for your DDS that features a dynamic range high enough to really measure a 150 dB SFDR? It's being used as part of a digital downconverter in my case, not driving a DAC. In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. I haven't seen any unaccounted-for spurs above -130 to -140 dBc (where they could be coming from pretty much anywhere), so I've been happy with the core's real-world performance. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. Ulrich Bangert Ortholzer Weg1 27243 Gross Ippener Deutschland Tel +49 (0)4224 95071 Fax +49 (0)4224 95072 Mob +49 (0)172 8006546 www.ulrich-bangert.de ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Replacing electrolytics - any disadvantages of high temp ones?
On 06/21/11 12:59 AM, Alan Melia wrote: David Another important factor when considering power supply caps is ripple current rating. It is generally the ripple current that makes them get warm. Yes. I must admit I did not give that any thought, which was rather stupid of me. But I did not buy cheap caps. I will check the ripple ratings, but its hard to know exactly what is needed. I think the usual thumbnail calculation still work for caps if you can reduce the temperature by 20 degrees they will last at least 4 times as long. That is an activation energy (Arrhenius eqn) of about 1ev. I also believe though I cant quote that they are best run at about 75% of their specified working voltage. I have always wonderd about this but it would seem to be a mistake to have too low a voltage on electrolytics ...maybe something to do with the strength of the instulating layer formed. Yes, I have heard this before about not using them at too low a voltage. I don't know whether its an old-wives tale, or if there is any truth to it. Alan G3NYK Thanks for your comments Alan, Dave G8WRB. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Replacing electrolytics - any disadvantages of high temp ones?
Dr. David Kirkby wrote: I think the usual thumbnail calculation still work for caps if you can reduce the temperature by 20 degrees they will last at least 4 times as long. That is an activation energy (Arrhenius eqn) of about 1ev. I also believe though I cant quote that they are best run at about 75% of their specified working voltage. I have always wonderd about this but it would seem to be a mistake to have too low a voltage on electrolytics ...maybe something to do with the strength of the instulating layer formed. Yes, I have heard this before about not using them at too low a voltage. I don't know whether its an old-wives tale, or if there is any truth to it. It is discussed in ITT's Reference Data for Radio Engineers. It certainly was true at one time not necessarily anymore, though. In the old days, the oxide layer that formed the dielectric was mostly formed in place by applying a controlled current to the capacitor at a voltage above the intended operating voltage. Now, the aluminum electrode foil is anodized before the capacitor is assembled, and the electrolytes are specifically formulated to not damage the oxide layer and yet, I find that some electrolytic capacitors that have been run at lower than normal voltage improve markedly when reformed by applying rated voltage through a 10K resistor for a couple of hours. -Chuck Harris ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
There is an excellent article about cordic on http://www.andraka.com/files/crdcsrvy.pdf There are a lot of other good publications on Ray Andraka's web site. I have published a accurate sine/cosine function on www.opencores.org underhttp://opencores.org/project,sincos It is VHDL only. The test bed is a DDS and it can write the generated waves to files for inspection with Matlab. I think I have caught all these off-by-1-LSBs by now. The sine function is ROM-based with size reduction by symmetry. Getting a cos at the same time is free wrt ROMs, just 2 adders more. Pipelining can be selected from combinatorial to 10 stages, depending on your speed requirements. Amplitude and phase resolution is automatically determined by the connected bus. feedback welcome. regards, Gerhard - Original Nachricht Von: li...@lazygranch.com An: Discussion of precise time and frequency measurement time-nuts@febo.com Datum: 20.06.2011 22:26 Betreff: Re: [time-nuts] DDS'ery With the coordic (yeah, sometimes cordic), you need to build it a few more bits wider than the DAC. Then it closely matches the lookup table. One of the best references for the coordic I found was a PhD dissertation at ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 6/21/11 6:14 AM, dk...@arcor.de wrote: There is an excellent article about cordic on http://www.andraka.com/files/crdcsrvy.pdf Yes..good explanation.. So, in the general case where you might want to rotate by an arbitrary angle at each time step, where the angle doesn't happen to be 1/2^n, you still need either multiple shift/add operations, or a multiply add. (i.e. it's no different than longhand multiplication... it takes N (optional) adds to multiply by an N bit precision number, or you cleverly parallelize/pipeline it). And, in a lot of applications, you'll need to still do a multiply by the gain (product of all those cos phi) term you factored out I can see that there could be advantages in implementation, but in the general case, is it actually that much more efficient? (in a CPU with no multiply, yes, it's a lot better, because it's essentially the same as doing long multiplication, but you get more done for the same amount of work) Maybe it's a how many gates do you need for a given precision sort of thing? Or the fact that it generates sin/cos together (which is very useful in some cases) in a random give me the cos(theta) sort of situation (e.g. a calculator), compared to computing the series expansion, clearly CORDIC is the way to go. But in a DDS, you're generating a continuous series of samples. I'll have to think about it. (and, because it's integrating a difference equation, CORDIC does have the accumulating roundoff, unless you compute each sin/cos from scratch each time) ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] cordic
Ohh.. It just came to me.. You're not using CORDIC as a replacement for both the phase accumulator and cos LUT, but JUST instead of the LUT, so you ARE doing the give me cos(theta) on every sample. So then, it's a trade between a big ROM LUT or a bunch o'gates for CORDIC. And for big N the bunch o'gates is probably going to be easier: 16 bit phase and wanting 16 bits out would be a 64kbit ROM (assuming you didn't do the usual thing of only needing 1/4 cycle).. I suppose, too, if you're building a digital up/down converter or mixer, rather than a LUT feeding a pair of multipliers for I/Q, the CORDIC scheme lets you essentially do it on the fly. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] cordic
So then, it's a trade between a big ROM LUT or a bunch o'gates for CORDIC. And for big N the bunch o'gates is probably going to be easier: 16 bit phase and wanting 16 bits out would be a 64kbit ROM (assuming you didn't do the usual thing of only needing 1/4 cycle).. There is also the Sunderland technique that can reduce the table size by a factor of 12 to 50 by splitting the table into 3 small ones and combining them with simple arith. Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] cordic
16 bits in is 64K *entries* of 16 bits each, a total of 1 megabit of ROM. The usual 90/180 degree folding could reduce that to 256 kbit. Dave On Tue, Jun 21, 2011 at 7:49 AM, Jim Lux jim...@earthlink.net wrote: So then, it's a trade between a big ROM LUT or a bunch o'gates for CORDIC. And for big N the bunch o'gates is probably going to be easier: 16 bit phase and wanting 16 bits out would be a 64kbit ROM (assuming you didn't do the usual thing of only needing 1/4 cycle).. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] DDS - Cosine v. Sine LUT
With all the discussion lately regarding DDS and CORDIC, I'm reminded of a question that came up some time ago for which I've never found an answer. Perhaps you enlightened people can enlighten me. Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835), why would one device favor a cosine LUT versus a sine LUT? On the surface, starting the roller coaster ride at the top of the hill (assuming the phase accumulator starts from zero) seems odd. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] cordic
On 6/21/11 9:38 AM, David Martindale wrote: 16 bits in is 64K *entries* of 16 bits each, a total of 1 megabit of ROM. The usual 90/180 degree folding could reduce that to 256 kbit. Dave On Tue, Jun 21, 2011 at 7:49 AM, Jim Luxjim...@earthlink.net wrote: So then, it's a trade between a big ROM LUT or a bunch o'gates for CORDIC. And for big N the bunch o'gates is probably going to be easier: 16 bit phase and wanting 16 bits out would be a 64kbit ROM (assuming you didn't do the usual thing of only needing 1/4 cycle).. Yes..mea culpa, miserere mei coffee had not been fully metabolized. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
On Tue, Jun 21, 2011 at 10:44 AM, KD0GLS kd0...@mninter.net wrote: Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835), why would one device favor a cosine LUT versus a sine LUT? Are the LUTs really different? Ages ago when I made something like this I used only 90 degrees of the table. That is all you need. The other 270 degrees can be made by flipping or inverting. I assume that what's stored is neither. It is data that needs to be interpeted based on the current quadrant. But the author might choose to call it which ever makes the most sense. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
On Jun 21, 2011, at 13:39, Chris Albertson wrote: I used only 90 degrees of the table. Yes, as did I and most implementations, but why a cosine quarter-table instead of the more common sine? A quick look at the data sheets (and the waveforms in the theory-of-op sections) for the two devices suggests they are clearly calling out one or the other, but without rationale regarding the choice. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
The cordic needs to compute both sin and cos. You are right that you just need one or the other if you have one DAC. -Original Message- From: Chris Albertson albertson.ch...@gmail.com Sender: time-nuts-boun...@febo.com Date: Tue, 21 Jun 2011 11:38:30 To: Discussion of precise time and frequency measurementtime-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS - Cosine v. Sine LUT On Tue, Jun 21, 2011 at 10:44 AM, KD0GLS kd0...@mninter.net wrote: Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835), why would one device favor a cosine LUT versus a sine LUT? Are the LUTs really different? Ages ago when I made something like this I used only 90 degrees of the table. That is all you need. The other 270 degrees can be made by flipping or inverting. I assume that what's stored is neither. It is data that needs to be interpeted based on the current quadrant. But the author might choose to call it which ever makes the most sense. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
Hi Brent, A quarter table cos is exactly the same as a quarter table sin. Only backwards, and not telling which quarter it is makes it a quarter of either sin or cos. For one single output becomes irrelevant as you only need one. So I think it is just a matter of taste the name to call it. Luis Cupido. ct1dmk. On 6/21/2011 8:03 PM, KD0GLS wrote: On Jun 21, 2011, at 13:39, Chris Albertson wrote: I used only 90 degrees of the table. Yes, as did I and most implementations, but why a cosine quarter-table instead of the more common sine? A quick look at the data sheets (and the waveforms in the theory-of-op sections) for the two devices suggests they are clearly calling out one or the other, but without rationale regarding the choice. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
On 06/21/2011 09:03 PM, KD0GLS wrote: On Jun 21, 2011, at 13:39, Chris Albertson wrote: I used only 90 degrees of the table. Yes, as did I and most implementations, but why a cosine quarter-table instead of the more common sine? A quick look at the data sheets (and the waveforms in the theory-of-op sections) for the two devices suggests they are clearly calling out one or the other, but without rationale regarding the choice. By the way, you can save two bits of the LUT table width by only storing the difference of the binary phase and the sine. Add the phase (90-degree wrapped) to the output of the LUT to get the sine. In effect the LUT can be allowed to be shifted two bits down for improved precision. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
Brent, For the specific case of generating a synchronous FSK signal with a fairly wide shift there may be a reason. Such an application presumes a high enough ratio between clock and output frequencies such that the DDS accumulator landing adequately near zero is a certainty. If the FSK frequency is changed synchronously - just after the point of DDS accumulator rollover - a sine LUT would potentially show an abrupt change in dv/dt (slew rate) with the frequency change. By using a cosine LUT the signal would be at its peak, and dv/dt would be virtually zero both before and after the frequency change. Bob LaJeunesse Ann Arbor, MI From: KD0GLS kd0...@mninter.net To: Time-Nuts time-nuts@febo.com Sent: Tue, June 21, 2011 1:44:26 PM Subject: [time-nuts] DDS - Cosine v. Sine LUT With all the discussion lately regarding DDS and CORDIC, I'm reminded of a question that came up some time ago for which I've never found an answer. Perhaps you enlightened people can enlighten me. Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835), why would one device favor a cosine LUT versus a sine LUT? On the surface, starting the roller coaster ride at the top of the hill (assuming the phase accumulator starts from zero) seems odd. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Replacing electrolytics - any disadvantages of high temp ones?
In message 4e008a73.50...@erols.com, Chuck Harris writes: and yet, I find that some electrolytic capacitors that have been run at lower than normal voltage improve markedly when reformed by applying rated voltage through a 10K resistor for a couple of hours. I noticed in a datasheet at one point, that the capacity only was warranted above a certain percentage of rated voltage. No explanation was given. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Light Squared, etc.
Light Squared backing off? http://spectrum.ieee.org/riskfactor/telecom/wireless/lightsquared-tacks-hard-in-the-face-of-opposition-says-it-has-solutions-to-gps-interference ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Light Squared, etc.
There appears to be a lot of news coverage about this. There was this article in the Register earlier today. http://www.theregister.co.uk/2011/06/21/lightsquared_gps/ All sorts of interesting information. The suggestion is that LiughtSquared will move to a lot of the Inmarsat spectrum, and go back to the original lower power levels for the L band spectrum. Not a huge set of actual technical detail, mostly an overview for those who are not radio experts in a more general technology/IT news site. -- Russell At 12:43 PM -0700 2011/06/21, Robert LaJeunesse wrote: Light Squared backing off? http://spectrum.ieee.org/riskfactor/telecom/wireless/lightsquared-tacks-hard-in-the-face-of-opposition-says-it-has-solutions-to-gps-interference ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
That's an interesting thought. The diagram of the 9835 (the one labeled as having the cosine ROM) also shows some sync logic associated with the select lines steering the FSK and PSK registers. If that logic syncs the select lines to the phase accumulator rollover, as you said, the slope of the signal would be near zero at that point, as opposed to at the zero-crossing with a sine-based device. An interesting theory at least. On Jun 21, 2011, at 14:31, Robert LaJeunesse wrote: Brent, For the specific case of generating a synchronous FSK signal with a fairly wide shift there may be a reason. Such an application presumes a high enough ratio between clock and output frequencies such that the DDS accumulator landing adequately near zero is a certainty. If the FSK frequency is changed synchronously - just after the point of DDS accumulator rollover - a sine LUT would potentially show an abrupt change in dv/dt (slew rate) with the frequency change. By using a cosine LUT the signal would be at its peak, and dv/dt would be virtually zero both before and after the frequency change. Bob LaJeunesse Ann Arbor, MI From: KD0GLS kd0...@mninter.net To: Time-Nuts time-nuts@febo.com Sent: Tue, June 21, 2011 1:44:26 PM Subject: [time-nuts] DDS - Cosine v. Sine LUT With all the discussion lately regarding DDS and CORDIC, I'm reminded of a question that came up some time ago for which I've never found an answer. Perhaps you enlightened people can enlighten me. Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835), why would one device favor a cosine LUT versus a sine LUT? On the surface, starting the roller coaster ride at the top of the hill (assuming the phase accumulator starts from zero) seems odd. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS - Cosine v. Sine LUT
Am 21.06.2011 21:03, schrieb KD0GLS: On Jun 21, 2011, at 13:39, Chris Albertson wrote: I used only 90 degrees of the table. Yes, as did I and most implementations, but why a cosine quarter-table instead of the more common sine? A quick look at the data sheets (and the waveforms in the theory-of-op sections) for the two devices suggests they are clearly calling out one or the other, but without rationale regarding the choice. It can be the same table, and if it delivers sine or cosine is determined only whether you start indexing from the highest or lowest address . (if you store only 1/4 wave) When you split the ROM into 2 smaller ones, you can get sin and cos at the same time, there will never be an address clash. One ROM for 0...44.9 deg and one for 45...89.999° . Just a MUX to select the appropriate ROM for each output and a little bit of address massage. Big cost saver for complex converters. Gerhard, dk4xp ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
-Original Message- From: time-nuts-boun...@febo.com [mailto:time-nuts- boun...@febo.com] On Behalf Of Ulrich Bangert Sent: Tuesday, June 21, 2011 4:37 AM To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] DDS'ery Clever! At least for your spectral measurements the signal never leaves the digital domain. What is the width of the multipliers involved in the mixing? Can you give me a clue, which ADCs you are working with in the front end? I was using AD9446s for a long time, but I'm going with LTC2216s for the final design. They're a lot pricier but they have better S/H front ends. That goes unnoticed in many cases but can be pretty important in others. The current implementation multiplies 26 bits from the DDS by 16 bits from the ADCs and keeps the top 28 bits of the baseband product. The noise floor does go up noticeably if you throw away too many bits. In this application, DDS artifacts would ultimately show up as spurs on phase noise plots or as ripple in ADEV plots. This matches exactly my own observations in terms of ripple in the Tau- Sigma digram when i used a standard like DDS from AD for this purpose. Exactly this is why I got interested in the XILNX DDS compiler. May be the ALTERA stuff is on the same level. Have used ALTERA FPGAs and CPLDs in the past but currently I am devoted to XILINX due to the easier availability in Germany. I think they've both got some really solid parts. I usually end up reading the app notes and core user manuals from both manufacturers, since (IMHO) Altera does a better job with their docs in some cases. -- john, KE5FX ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] DDS'ery
On 06/21/2011 04:29 PM, Jim Lux wrote: On 6/21/11 6:14 AM, dk...@arcor.de wrote: There is an excellent article about cordic on http://www.andraka.com/files/crdcsrvy.pdf Yes..good explanation.. So, in the general case where you might want to rotate by an arbitrary angle at each time step, where the angle doesn't happen to be 1/2^n, you still need either multiple shift/add operations, or a multiply add. (i.e. it's no different than longhand multiplication... it takes N (optional) adds to multiply by an N bit precision number, or you cleverly parallelize/pipeline it). And, in a lot of applications, you'll need to still do a multiply by the gain (product of all those cos phi) term you factored out I can see that there could be advantages in implementation, but in the general case, is it actually that much more efficient? (in a CPU with no multiply, yes, it's a lot better, because it's essentially the same as doing long multiplication, but you get more done for the same amount of work) Maybe it's a how many gates do you need for a given precision sort of thing? Or the fact that it generates sin/cos together (which is very useful in some cases) in a random give me the cos(theta) sort of situation (e.g. a calculator), compared to computing the series expansion, clearly CORDIC is the way to go. But in a DDS, you're generating a continuous series of samples. I'll have to think about it. (and, because it's integrating a difference equation, CORDIC does have the accumulating roundoff, unless you compute each sin/cos from scratch each time) You do calculate the sin/cos from scratch on each sample. The CORDIC add/sub strategy allows for pipe-line processing at sample rate and will take less real estate than equivalent LUT. Do read the article that Bruce referenced. You could also play a little with integrators and stuff to let the dynamics grow up if you can allow some upper frequency limitation. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Replacing electrolytics - any disadvantages of high temp ones?
Group, During my days of interest in antique radios, I learned that the dielectric between aluminum plates was formed by passing current in one direction to build up an oxide coating on the plates, which became the dielectric. The thickness is directly proportional to working voltage and inversely proportional to capacitance. As we learned from reforming old caps, the oxide thins when there is no voltage on the cap, but can be restored by passing several milliamps through the cap. Applying rated voltage before it was formed would destroy the cap by welding spots of the plates together. I'm not sure that this applies to modern caps. As to the temperature rating, a high temp cap run in a cool environment will be as unhappy as someone transplanted from Miami to Minneapolis in the winter. It may work, but it will be very unhappy - so it depends on your empathy for the cap. There ought to be a way to work precision time into this thread, but I can't think of one. Bill Hawkins -Original Message- From: Poul-Henning Kamp Sent: Tuesday, June 21, 2011 2:40 PM In message 4e008a73.50...@erols.com, Chuck Harris writes: and yet, I find that some electrolytic capacitors that have been run at lower than normal voltage improve markedly when reformed by applying rated voltage through a 10K resistor for a couple of hours. I noticed in a datasheet at one point, that the capacity only was warranted above a certain percentage of rated voltage. No explanation was given. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Light Squared
http://www.technewsworld.com/story/72712.html Hardy - Original Message - From: time-nuts-requ...@febo.com To: time-nuts@febo.com Sent: Tuesday, June 21, 2011 10:09 PM Subject: time-nuts Digest, Vol 83, Issue 72 Send time-nuts mailing list submissions to time-nuts@febo.com To subscribe or unsubscribe via the World Wide Web, visit https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts or, via email, send a message with subject or body 'help' to time-nuts-requ...@febo.com You can reach the person managing the list at time-nuts-ow...@febo.com When replying, please edit your Subject line so it is more specific than Re: Contents of time-nuts digest... Today's Topics: 1. Re: DDS - Cosine v. Sine LUT (KD0GLS) 2. Re: DDS - Cosine v. Sine LUT (li...@lazygranch.com) 3. Re: DDS - Cosine v. Sine LUT (Luis Cupido) 4. Re: DDS - Cosine v. Sine LUT (Magnus Danielson) 5. Re: DDS - Cosine v. Sine LUT (Robert LaJeunesse) 6. Re: Replacing electrolytics - any disadvantages of high temp ones? (Poul-Henning Kamp) 7. Re: Light Squared, etc. (Robert LaJeunesse) 8. Re: Light Squared, etc. (Russell Rezaian) 9. Re: DDS - Cosine v. Sine LUT (KD0GLS) -- Message: 1 Date: Tue, 21 Jun 2011 14:03:49 -0500 (CDT) From: KD0GLS kd0...@mninter.net To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS - Cosine v. Sine LUT Message-ID: f72d67e5-5f4b-4d22-abd5-66930d060...@mninter.net Content-Type: text/plain; charset=us-ascii On Jun 21, 2011, at 13:39, Chris Albertson wrote: I used only 90 degrees of the table. Yes, as did I and most implementations, but why a cosine quarter-table instead of the more common sine? A quick look at the data sheets (and the waveforms in the theory-of-op sections) for the two devices suggests they are clearly calling out one or the other, but without rationale regarding the choice. .73, Brent, KD0GLS, Minneapolis -- Message: 2 Date: Tue, 21 Jun 2011 19:11:18 + From: li...@lazygranch.com To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS - Cosine v. Sine LUT Message-ID: 948099068-1308683479-cardhu_decombobulator_blackberry.rim.net-1357307805-@b12.c1.bise6.blackberry Content-Type: text/plain The cordic needs to compute both sin and cos. You are right that you just need one or the other if you have one DAC. -Original Message- From: Chris Albertson albertson.ch...@gmail.com Sender: time-nuts-boun...@febo.com Date: Tue, 21 Jun 2011 11:38:30 To: Discussion of precise time and frequency measurementtime-nuts@febo.com Reply-To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS - Cosine v. Sine LUT On Tue, Jun 21, 2011 at 10:44 AM, KD0GLS kd0...@mninter.net wrote: Given a complete DDS chip with a single output channel (e.g. AD9834, AD9835), why would one device favor a cosine LUT versus a sine LUT? Are the LUTs really different? Ages ago when I made something like this I used only 90 degrees of the table. That is all you need. The other 270 degrees can be made by flipping or inverting. I assume that what's stored is neither. It is data that needs to be interpeted based on the current quadrant. But the author might choose to call it which ever makes the most sense. -- Chris Albertson Redondo Beach, California ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. -- Message: 3 Date: Tue, 21 Jun 2011 20:18:19 +0100 From: Luis Cupido cup...@mail.ua.pt To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] DDS - Cosine v. Sine LUT Message-ID: 4e00ee7b.4020...@mail.ua.pt Content-Type: text/plain; charset=ISO-8859-1; format=flowed Hi Brent, A quarter table cos is exactly the same as a quarter table sin. Only backwards, and not telling which quarter it is makes it a quarter of either sin or cos. For one single output becomes irrelevant as you only need one. So I think it is just a matter of taste the name to call it. Luis Cupido. ct1dmk. On 6/21/2011 8:03 PM, KD0GLS wrote: On Jun 21, 2011, at 13:39, Chris Albertson wrote: I used only 90 degrees of the table. Yes, as did I and most implementations, but why a cosine quarter-table instead of the more common sine? A quick look at the data sheets (and the waveforms in the theory-of-op sections) for the two devices suggests they are clearly calling out one or the other, but without rationale regarding the choice. .73, Brent, KD0GLS, Minneapolis ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
Re: [time-nuts] Replacing electrolytics - any disadvantages of high temp ones?
Hi Bill, I agree with your forming information, as applied to older caps, but not your temperature information. The 105C high temp caps are just as happy, or unhappy really, with low temperatures as the 85C caps. Basically the difference between the two is water. The 85C caps have an electrolyte with a significant amount of water, that boils dry at high temperatures. The 105C caps don't. Kind of like the difference between an antifreeze and water solution, and straight antifreeze. Both seriously run out of capacitance when they get below freezing. The loss of capacitance can really bite you when you use integrated low overhead voltage regulators in automotive temperature ranges. The regulators will oscillate if they don't have enough capacitance on their input terminals... which can happen if you specify an electrolytic capacitor that is right around the 100uf needed. When it gets to 0C, and becomes a 10uf capacitor, the regulator takes off and burns up your load. -Chuck Harris Bill Hawkins wrote: Group, During my days of interest in antique radios, I learned that the dielectric between aluminum plates was formed by passing current in one direction to build up an oxide coating on the plates, which became the dielectric. The thickness is directly proportional to working voltage and inversely proportional to capacitance. As we learned from reforming old caps, the oxide thins when there is no voltage on the cap, but can be restored by passing several milliamps through the cap. Applying rated voltage before it was formed would destroy the cap by welding spots of the plates together. I'm not sure that this applies to modern caps. As to the temperature rating, a high temp cap run in a cool environment will be as unhappy as someone transplanted from Miami to Minneapolis in the winter. It may work, but it will be very unhappy - so it depends on your empathy for the cap. There ought to be a way to work precision time into this thread, but I can't think of one. Bill Hawkins -Original Message- From: Poul-Henning Kamp Sent: Tuesday, June 21, 2011 2:40 PM In message4e008a73.50...@erols.com, Chuck Harris writes: and yet, I find that some electrolytic capacitors that have been run at lower than normal voltage improve markedly when reformed by applying rated voltage through a 10K resistor for a couple of hours. I noticed in a datasheet at one point, that the capacity only was warranted above a certain percentage of rated voltage. No explanation was given. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
