Luis, the information that you are concerned about close carrier spurs that will pass through the PLL's low pass filter is not precise enough: are you talking about a few Hz, a few ten Hz, a few 100 Hz away from the carrier or are you going to build a device for precise timing applications where also spurs far below (perhaps orders of magnitude below) 1 Hz may be of concern?
Best regards Ulrich Bangert, DF6JB > -----Ursprungliche Nachricht----- > Von: time-nuts-boun...@febo.com > [mailto:time-nuts-boun...@febo.com] Im Auftrag von Luis Cupido > Gesendet: Dienstag, 21. Juni 2011 02:20 > An: Discussion of precise time and frequency measurement > Betreff: [time-nuts] DDS'ery narrow scoped. > > > Folks, > > Many thanks to you all, for the info. > This is indeed a great forum. > > My aplic. is a DDS signal that > will serve as reference for a pll with a relatively > narrow loop filter. As I said before. > > Most replies presume the analog world with DAC > filters etc etc. But that I know ;-) > I'm digging out the possibilities in the digital side > not involving going back to analog and back to digital. > this is how this started :-) > > > Now that you all have been so kind in the great comments > you gave, please let me just be > very very very specific. > > > Imagine an FPGA and a square wave coming out. > Just that. Nothing more. > > (That is what I had in mind when querying about the MSB usage > in the first place.) > > > My first approach was the ACC MSB > (and that is working already on the bench.) > > So I'm researching a way to have that digital output cleaner (spurs) > without leaving the digital(FPGA) world sticking to the block > diagram of one FPGA one digital output. Specially worried > about close in spurs > (the far away ones won't bother me much). > > That is really scenario I'm trying to picture if there is any > hope to generate a cleaner digital output out of an FPGA (dds > with whatever > processing required to be done after and producing a square wave). > > Thanks for your patience. > > Luis Cupido. > ct1dmk > > > P.S. At the moment I'm testing on the bench with a real FPGA > cyclone III with a 48bit dds at 100MHz fclock and at circa 6 > and 18MHz output and it > is not that bad. I got better than -60dBc in the desired > ranges. So not too unhappy for a start ;-) PLL cleans 99% of > it... but the close in spurs are annoying. > > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.