from:"Dr Bruce Griffiths"

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Ulrich Bangert wrote:
 Richard,

 metastability is an effect that happens when the setup times of an
 d-flipflop are not met. This can happen (with a certain statistical
 likelyhood) when the sources of the data input and the clock input of an
 d-flipflop are not synchronized. The important thing to know about
 metastability is that the likelyhood of its appearance might be directly
 computed from the setup time and the frequency of the d- and
 clock-signal as described in

 http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=sSeco
 ndaryNavPick=category=iLanguageID=1multPartNum=1sTechX_ID=pa_metasta
 bility

 Peter Alfke is THE expert in metastability at XILINX! I guess if you
 apply the data presented here to your case you will find that the
 probabilty of metastability in your case may be neclected. Roumors are
 that 99% of all assumed cases of metastability are due to other design
 flaws. 

 However I would like to draw your attention to an second point. From
 your posting it gets clear that you are not the pure user of the Shera
 design but have otherwise put a lot of brains into the question of how
 to improve it. 

 First, forget about the Shera design for a moment and consider the case
 that you have two 1pps sources and want to compare them by means of an
 REAL tic as the HP5370 or the SR620. Question: Since you are comparing
 TWO oscillators by means of an THIRD oscillator (the tic's time base),
 does the tic's time base stability influence your measurement results or
 not?

 Clearly so, if you think about it for a while. With this arrangement it
 is not possible to decide whether 1pps a or 1pps b or the tic's time
 base are responsible if you notice statistical fluctuations in the
 measurement results. The measured results will be an statistical average
 (not an simple arithmetic one but an more complicated one, but basically
 you can imagine it as an average) of ALL source's fluctuations. The
 situation changes if you have more sources and/or more tics available
 because there are statistical methods available to allocate which source
 and which tic is responsible for what but in the simple case of only
 three sources these rules cannot be applied. 

 Now that you aware of the fact that the tic's timebase has an impact on
 measurements made with the tic what would you do about it? In the real
 world you would synchronize the tic's time base to the best reference
 available, for example to the cesium in the backyard or the H2 maser in
 the kitchen. But what if you lack equipment like that and have only this
 one rubidium oscillator and this gps receiver? Clearly the second best
 choice is to use the rubidium also as the timebase for the tic EVEN if
 it IS the source that you want to discipline, just because you reduce
 the complexity of the problem back to TWO sources of fluctuations.

 Now let us come back to the Shera circuit. The question that must be put
 forward at this point is: If we have just recognized that the tic's
 timebase has pretty much the same influence on our mesurements as the
 duts itself, how can the Shera design work with an timebase consisting
 of a garden variety canned oscillator of the lowest class of stability?
 If the above explained claims are true and the measurement results are
 the statistical average over ALL sources then in your case this cheesy
 little timebase is by some orders of magnitude worse in terms of
 stability compared to the rubidium and the gps and what we measure
 should in theory be dominated by the bad time base and not by the duts.
 So, how can the circuit work at all ??? 

 At this point we come to one of the big but not commonly well understood
 tricks of the Shera design. The cheap canned timebase IS indeed the
 biggest source of fluctuations in the design. However the design
 includes precautions so that these fluctuation are hindered to show up.
 Howzat?

 Consider two 1pps signals. They can be as close as 0 s or they can be
 apart as much as 500 ms. Consider they are 500 ms apart and you have an
 timebase of 24.576 MHz to measure how far they are apart. With 500 ms
 your tic will reach something like 12288000 counts in that time. Among
 other environmental depencencies the coefficent of temperature will be
 the most prominent one with simple xtal oscillators being in the order
 of 1E-6/Kelvin. With 10 Kelvin temperature variation this will give you
 an change of app. 123 counts in the count result for the SAME 500 ms
 just due to temperature. This is an noticeable effect! Even the 10th
 part of it, 12 counts would be an noticeable effect. But now comes the
 clue: Both effects are noticeable because and ONLY because we made an
 HIGH RESOLUTION MEASUREMENT. With 12288000 counts 1 count equals less
 then 1E-7 of the result, so we made an measurement with better than 1E-7
 resolution. Now consider the case when we limit the measurement range of
 the phase

Re: [time-nuts] Metastability in a 100 MHz TIC

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Tom
Tom Van Baak wrote:
 Bruce,

 I like your point about the random quantization error in the
 sawtooth. Yes, that would help the noise by a few dB.

 On the other hand it would also seem the 10 ns resolution
 of the TIC is the limiting factor (by an order of magnitude)
 over the 1 ns resolution limit of the sawtooth corrections,
 so improving the quality of the sawtooth corrections has
 limited gain.

 Now, I'd still like to pursue the issue of noise in the 100 MHz
 oscillator. Do we agree one doesn't need a cesium for this?
 Or even an XO?

   
As long as one keeps track of the frequency drift of the timebase 
oscillator this is true.
 True, you want some accuracy in the 100 MHz. But the counts
 are only integers from 0 to 160 so the accuracy requirement
 is just 3 digits, 0.1% (so cheap quartz, at 1e-6, or cesium, at
 1e-13, is extreme overkill). I mean, almost anything wiggling at
 100.0 MHz will serve as an adequate timebase.

 Also, as you point out, instability or jitter is your friend, not
 your enemy in this case. Would it be possible to introduce
 the +/- 5 ns jitter deliberately in the 1pps trigger level instead
 of in the timebase? I.e., slow down the rising edge enough
 so that you get jitter for free?
   
Yes adding stochastic jitter to the leading edge of the PPS signal is a 
good way of injecting the required noise into the measurement.
The most predictable way is to slow down the PPS edge (a simple RC 
filter should be more than adequate ) and feed it into one input of a 
comparator whilst the other input is connected to a noise source.
 Another solution might be to deliberately choose an inaccurate
 and unstable oscillator; use the 1pps to count oscillator cycles
 per second, as well as to count the time interval. The larger
 count can be used to calibrate the smaller count on every count.
 This gives all the jitter you need and avoids any injection issues.

   
Yes a suitably noisy LC oscillator should work, will probably need to 
reduce the tank Q somewhat to achieve sufficient noise/jitter.
Deliberately using resistors to introduce predictable noise may be a 
useful technique.

Attenuating the sinusiodal ouput of an oscillator that is too stable 
using a resistive attenuator with a high output resistance may also be a 
viable technique for producing a sufficiently noisy clock.
 While you're at it, how about N of these oscillators, each making
 its own out of phase measurement of the same OCXO-GPS 1pps.
 Another couple of dB of resolution...

 /tvb
   
This is getting way to complicated, surely the method of using the 
inherent noise in the hardware corrected PPS signal in conjunction with 
a D flip flop acting as a simple precedence detector (as proposed 
several weeks ago) is easier, cheaper and simpler, it also has more 
resolution than almost any other method one can devise. It can easily be 
elaborated slightly to allow detection and rejection of phase error 
measurement outliers.

Clock the D flip flop with the hardware corrected PPS signal, connect 
the divided down OCXO (or other standard) being disciplined to the D 
input. Interrupt the microprocessor on the trailing edge of the PPS 
signal, read the Q output of the D flip flop (the 200 milliseconds PPS 
width of the PPS signal from an M12M or similar GPS timing  receiver is 
more than adequate to allow the D flipflop to settle with an extremely 
low probability of being in a metastable state- even a few microseconds 
is probably more than sufficient) and add 1 to the phase count whenever 
D is 1 subtract 1 whenever D is 0. The EFC voltage is then adjusted to 
keep the phase error at zero (corresponds to a 50% probability of the D 
flipflop output being 1 when read by the micro). This simplistic 
algorithm can be replaced by a more optimum algorithm as required.

This can all be built with a few DIP ICs to ease assembly, however a 
well designed 2 layer PCB with a ground plane is probably advisable. 
Other than a programmable delay line and a high resolution DAC no 
unusual parts are required.

Instead of using one microprocessor to do everything several of simpler 
processors each dedicated to a particular function may be better.
One processor could be dedicated to hardware correction of the PPS 
signal, whilst another can implement the phase error measurement and the 
OCXO control loop.

Bruce

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Re: [time-nuts] Sawtooth correction with a slower TIC

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Richard H McCorkle wrote:
 Gentlemen,
 I would like to pose a theory question and see if my thinking is
 faulty. My original design used a 50 MHz TIC clock and the TMR0
 prescaler as the phase counter giving 20ns single sample resolution
 in the prototype system. A synchronizer is used to insure only
 whole clock pulses are counted. If a 1-second sawtooth correction
 having a 1ns sample resolution is divided by 20 with the low bits
 retained and added to the 20ns single sample phase count, does this
 result in a resolution of 1ns per sample when the corrected samples
 are averaged? Does a faster TIC clock with an external high-speed
 counter really result in better sample resolution as long as the
 TIC clock granularity is within the sawtooth correction limits with
 the TIC giving the the MSB's of the sample and the sawtooth
 correction providing the LSB's of the sample?

 Just Wondering?
 Richard
   
Richard

You are confusing resolution with noise, they are not the same.

Since the quantisation error of the TIC measurements are statistically 
independent of the sawtooth correction, one cannot achieve a measurement 
noise of 1ns using this technique. The TIC noise contribution will be 
20/SQRT(12) ns rms (assuming a uniform error distribution) per 
measurement whereas the sawtooth quantisation error will be around 
1/SQRT(12) ns rms, and the receiver noise will also contribute a noise 
of several ns rms. The resultant noise in the measurement is calculated 
by squaring all the noise terms, adding them together and taking the 
square root (assuming these errors are uncorrelated ie statistically 
independent). Averaging reduces the noise by a factor equal of 1/SQRT(N) 
where N is the number of samples averaged.

Bruce

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Re: [time-nuts] Metastability in a 100 MHz TIC

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Alan Melia wrote:
 Bruce I find this an interesting thread...one maybe naive thought..
 it would be nice to have atoo-good stability on the 100MHz TIC but
 detracts from the averaging (My interpretation), this almost suggests to me
 that a small amount of noise modulation which of course would be random,
 controlled,  and not biassed in a way to affect the accuacy of the driving,
 should be added to the 100MHz TIC OCXO. Would that counter the problems on
 uncharacterised drifting and still allow long averaging.?? Maybe even a slow
 unsynchonised low frequeny sine wave FM would achieve the same effect. It
 would seem this would be better than relying on processes which are unknown
 and not controlled to provide the effect.It is counter intuitive to
 intentionally degrade a standard in some respects but has been shown to
 work in some cases.

 Alan G3NYK
   
Alan

Using a slow unsynchronised sinewave is not the way to go a noise source 
is better and is easily implemented.
Essentially the technique used by HP in one of their counters would 
suffice, phase modulate say a 10MHz signal by a few degrees and then 
multiply the output by 10
to produce a 100MHz signal with 10x the phase modulation. This 
simplifies the design and construction of the phase modulator. A diode 
double balanced mixer can be used to phase modulate a signal by the 
required amount. Feed the LO port of the mixer with the signal to be 
modulated apply the modulation signal to the IF port and add the output 
of the RF port in phase quadrature with the original signal.

The drawback is the complexity and the fact that the resolution is still 
inadequate to achieve the maximum performance from the better GPS timing 
receivers with a good antenna and site. The simpler and cheaper D 
flipflop precedence detector used together with hardware sawtooth 
correction has far higher resolution. It also has the advantage of not 
requiring any high frequency clocks.

Bruce

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Re: [time-nuts] Metastability in a 100 MHz TIC


Tom Van Baak wrote:
The simpler and cheaper D 
flipflop precedence detector used together with hardware sawtooth 
correction has far higher resolution. It also has the advantage of not 
requiring any high frequency clocks.


Bruce



Since Rick  Dr TAC brought it up some months ago, does
anyone have measurements for this approach yet?

Also what is its equivalent resolution; i.e., what resolution
would a conventional TIC need to be to match the behavior
of the D-flipflop approach, all other factors equal?

/tvb
  

Tom

With say a 2ns rms noise on the corrected PPS output, a TIC would need 
an rms quantisation noise less than 1/3 of this to avoid significantly 
degrading the measurement noise.
The corresponding TIC resolution would be about 7ns (140MHz). However to 
achieve accurate averaging the required rms jitter at the TIC input is 
around 1 clock period which implies that a TIC clock period of around 
2ns (500MHz) is required. If the receiver timing noise is greater then a 
lower frequency clock can be used. The D flipflop approach produces a 
degradation of less than 2dB with respect to an ideal TIC with infinite 
resolution. The other advantage is that such a 1 bit TIC automatically 
adapts to the timing noise that is present.


The most cost effective way of achieving perhaps a dB or so improvement 
is to use an ADC as a TIC, sampling an input sinewave produced by 
dividing down and low pass filtering the output of the OCXO on the 
leading edge of the PPS signal. A resolution equivalent to using a 1GHz 
or faster clock is easily achieved. The cost of suitable ADCs is 
relatively low.


Neither of these solutions requires using clocks faster than 10MHz or 
so. Nor are particularly esoteric high speed logic devices required. 
Although ACMOS devices are desirable, even HCMOS devices should be 
satisfactory, particularly if given 200 millisec to resolve any 
metastable state.


The circuit schematic attached also provides 100ns (with a 10MHz clock) 
guardbands either side of the edge that is locked to the hardware 
corrected PPS signal.
For example U103 3Q, 4Q, 5Q are used as precedence detectors the PPS 
being locked to  U102 Q4 with  Q3 and Q5 acting as guardbands 
transitions to allow detection of when the PPS leading edge is 100ns or 
more away from  the transition on U102  Q4. This allows rejection of 
outliers.


Bruce


1 bit TIC phase detector.pdf
Description: Adobe PDF document
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Re: [time-nuts] Oncore VP problem

2007-07-19 Thread Dr Bruce Griffiths

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[EMAIL PROTECTED] wrote:
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 Errors-To: [EMAIL PROTECTED]

  
 In a message dated 19/07/2007 02:44:42 GMT Daylight Time,  [EMAIL PROTECTED] 
 writes:

 My  suggestion is that you pick up a free evaluation copy of Rick
 Hambly's  TAC32 software at http://cnssys.com/cnsclock/Tac32Software.html
 . TAC32  knows all the quirks  options that ever existed in a  Motorola
 receiver, going all the way back to the Rev.3 PVT6. Then if you  find it
 useful, a legal copy can be purchased from Rick, or at members  discount
 from TAPR  (http://www.tapr.org/gps_tac32.html).



 ---
  
 Hi Tom
  
 Many thanks for the suggestion.
  
 You may have seen my subsequent post in which I commented that I had tried  
 TAC32 without solving my problem, only to find the kit was working ok but  
 with 
 an incorrectly labelled connector.
  
 TAC32 does look useful though so I'll check it over more thoroughly  later.
  
 One interesting side effect..
  
 Some time after shutting down TAC32 last night, but with the Oncore still  
 connected to the serial port and outputting data, my PS2 connected mouse 
 started 
  misbehaving, with the pointer jumping all over the place then settling down 
 for  a while before repeating the performance.
 It didn't occur to me at first that the incoming serial data might have  
 anything to do with it until it started again this morning and I eventually  
 stopped it by disconnecting the serial lead from the receiver.
  
 Whilst I can't say for sure that running TAC32 was what caused it, it's not  
 something I've ever seen in the past nor previously this past few  days after 
 running WinOncore.
  
 I'll check later to see if the port shut down properly and also take a look  
 at the Oncore message stream, perhaps TAC32 may have changed something  there 
 as part of its auto setup routine?
  
 regards
  
 Nigel
 GM8PZR
  
Nigel

This is a well known quirk/feature of Windows itself.
There is a way of curing it (other than using a better OS) but I cant 
recall the details at the moment.

Bruce

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Re: [time-nuts] Metastability in a 100 MHz TIC

2007-07-19 Thread Dr Bruce Griffiths

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Richard H McCorkle wrote:

With the discussions here on metastable states in TIC
 counters, I am asking the experts on the list for their
 opinion if the performance of this design would improve
 by adding a shift register synchronizer between the phase
 detector output and the count enable input of the 74F163A
 TIC to reduce metastable states. The 74F series has the
 best reliability figures from metastable effects of all
 the TTL logic families according to the data I have read.
 Each D F/F counter cell in the 74F163A has the clock applied
 directly to the F/F, so no clock gating occurs. Instead the
 input data is gated by count enable signals for each cell and
 either the cell output is sent to the D input if the count
 enable is low, or the previous cell output is gated into the
 D input on carry if the count enable is high with D latched
 into all F/Fs on each clock rising edge. While I see the need
 for a synchronizing shift register in a gated clock design
 like the original Shera controller, is it necessary for best
 performance in a GPSDRO application with a 74F163A 100 MHz TIC?

   


It is always advisable to use a synchroniser to substantially reduce any 
bias in the averaged phase due to metastability.
However unless there is very high isolation between the 100MHz XO and 
the LPRO output as well as the 100MHz XO the divided down output of the 
LPRO injection locking of the 100MHz oscillator may be a more 
significant source of bias in the averaged phase. If the PPS signal from 
the GPS timing receiver has sufficient random noise (~10ns) then this 
should not be an issue.

When designing a synchroniser it is useful to have a quntitative model 
of the metastability characteristics of the devices used so that a 
reasonably accurate estimate of its output metastability rate can be 
calculated.


Bruce

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Re: [time-nuts] Cs stability

2007-07-16 Thread Dr Bruce Griffiths

Pablo Alvarez Sanchez wrote:
 ); SAEximRunCond expanded to false
 Errors-To: [EMAIL PROTECTED]

 Hi, 

 I am curious about the total stability of Cs clocks. Normally producers give 
 you an initial accuracy after 30 minutes of power on and a table with the 
 Allan deviation for different measurement intervals. 

 After that they give you the environmental and physical specifications. For 
 the hp5071 you have:

 General environment
 Temperature
 Operating 0°C to 55°C
 Non-operating -40°C to 70°C
 Humidity 0 to 95%RH (45C max)
 Magnetic field dc, 55, 60Hz 0 to 2 gauss peak - any orientation Atmospheric 
 pressure £1E-13 change in frequency for pressure down to 19kPa (equivalent to 
 an altitude of 12.2km) Shock and vibration Mil-T-28800D, Type III, class 5 
 Hammer Blow Shock Test, Mil-S-901C, Grade A, Class 1, Type A Mile-STD, 167-1 
 (phase noise)
 EMI: Conducted and radiated emissions per CISPR 11/EN 55011, Group 1, Class A
 EMC: per MIL-STD-461C, Part 7, Class B dc magnetic field up to 7.8 Gauss



 My questions are:

 Are the Allan deviation specs also valid for all the environmental range, 
 including shock and vibration, or only for lab conditions?

 In the article OBSERVATIONS ON STABILITY MEASUREMENTS OF COMMERCIAL ATOMIC 
 CLOCKS, Pekka Eskelinen claims to have measured a phase temperature 
 coefficient of 100ns/degree for commercial Cs clocks in 1999.

 http://ieeexplore.ieee.org/iel5/6762/18075/00840739.pdf (If you cannot read 
 it I can try to send you a copy by email)

 Has any of you ever measured such a coefficient?

 Cheers

 Pablo 
   
Pablo

A Cs clock uses a frequency lock loop to control the frequency of the 
local crystal oscillator, the crystal oscillator phase is arbitrary. The 
phase of the output with respect to the crystal depends on the 
propagation delay of any intervening electronics including amplifier and 
filter phase shifts. The phase shift of tuned circuits and other narrow 
bandwidth filters has a relatively high temperature coefficient and this 
is perhaps what has been measured. Modern isolation amplifier designs 
eschew the use of tuned circuits and other narrow bandwidth filters and 
consequently have much lower phase shift temperature coefficients 
(typically a few picosec/C).

Bruce

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Re: [time-nuts] Cs stability

2007-07-16 Thread Dr Bruce Griffiths

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Tom Van Baak wrote:
 The given specs are conservative (in typical HP style) but
 I would guess the best ADEV numbers are only for laboratory
 conditions. Someone from Agilent/Symmetricom might want
 to comment on this.

   
 In the article OBSERVATIONS ON STABILITY MEASUREMENTS
 OF COMMERCIAL ATOMIC CLOCKS, Pekka Eskelinen claims to
 have measured a phase temperature coefficient of 100ns/degree
 for commercial Cs clocks in 1999.
 

 I'll comment after I read it. But the 100ns/degree value doesn't
 make sense because that's phase instead of frequency units.

 Did he mean 100 ns per day per degree? Or per 200 hours,
 or 2000 hours, etc. If the latter, that represents a per-degree
 frequency shift of 100 ns / 2000 h = 1.3e-14 which sounds
 about right to me for a cesium tempco. It also depends on the
 model: the tempco of a vintage hp 5060A or hp 5061A is likely
 worse than a modern 5071A, for example.
   
Tom

Yes it can make sense.
Place one Cs clock in a chamber where the ambient temperature can be 
adjusted to various fixed temperatures. Compare the phase of its 
5/10MHz  and/or PPS outputs with respect to those of another Cs standard 
held at constant temperature. The observed phase shift sequence may then 
be fitted to both frequency shift and a fixed (for a given temperature) 
phase shift components. Repeat for a range of temperatures and plot the 
(temperature dependent) fixed phase shift component as a function of 
temperature.

Bruce

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Re: [time-nuts] HP 5370B jitter

2007-07-14 Thread Dr Bruce Griffiths

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Hej Magnus
Magnus Danielson wrote:
 Further investigations have now shown that the 10811 output is clean, just a
 little 3rd harmonic but nothing to worry about. The INT test point is also
 clean. I suspect the output drive part, as other outputs to various parts are
 also free of the 5 MHz. The 10 MHz present detector circuit is currently my
 main suspect. It consists of a one-shot multi-vibrator triggered by the 10 
 MHz
 signal. Having a RC time-constant of 100 ns makes it a suspect indeed. 
 Probing
 it (pin 11 on A8U1) clearly shows a waveform wich looks like a 25% 5 MHz with
 a short spike on it. This little culprit of a detector is infact a wideband
 comb-generator which contributes its 5 MHz as sidebands to the output 10 MHz.
 It's only purpose in life is to light a LED only visible to the servicing
 engineer (me in this case). Thus, making a small modification to disable it
 during normal operation would improve the quality of the 10 MHz output
 considerably if I am right. Since I don't do ECL design on a daily basis, I
 will have to ponder a bit in order to come up with a good method of acheiving
 this.

   
Try shorting AU8U1 Pins 6 and 7 to ground.
This turns of the npn output emitter followers driving the longtailed 
pair which drives the LED.
This is permitted and nothing will be destroyed or degraded even if the 
shorts are permanent.
 Cheers,
 Magnus
   
Bruce


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Re: [time-nuts] NIST frequency doubler

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Peter Vince wrote:
 Hi Bruce,

   With a quick search of the NIST site, I couldn't find any 
 mention of this, and the circuit diagram in your GIF was a little 
 small and fuzzy: is that a crystal on the centre-tap of the secondary 
 of the first transformer?  Would it be tuned to the input or output 
 frequency? And would you know the values of the components?

   Thanks,

   Peter

   
Peter

It just an RF bypass capacitor to ground.
This circuit was embedded in a very small section of a much larger 
paper, so its difficult to find.
You may even have read the paper and not have noticed  the mixer circuit.
The resistor from the centre tap to ground is selected so that the peak 
drain current is around 28mA or so when the RF is applied

RF input ~ 13dBm.
Input transformer 1:4 turns ratio (or thereabouts) centre tapped secondary.
Output transformer 2:1 turns ratio (or thereabouts).
RF bypass capacitor depends on input frequency typically 100nF or so.

Bruce

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Re: [time-nuts] NIST frequency doubler

); SAEximRunCond expanded to false
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[EMAIL PROTECTED] wrote:
Hi Bruce,

nice circuit. Many questions:

I wonder how well it works to get a 5MHz source up to 10MHz?

Also, would you have recommendations on the transformer part numbers?
(MiniCircuits, MaCom, etc)? I think the transformers are probably key to
getting
good phase noise (preventing them from saturating, crosstalk, etc).

Do you have a suggestion on who makes the best (lowest-noise) JFets?

Where could we find the original paper's PDF?

Lastly, how much fundamental attenuation would you expect from such a
circuit?

Thanks!
Said

Said

Embedded in:

1992 IEEE FREQUENCY CONTROL SYMPOSIUM
ULTRA-HIGH STABILITY SYNTHESIZER FOR DIODE LASER PUMPED RUBIDIUM
John P. Lowe, F. L. Walls, and R. E. Drullinger
Time and Frequency Division
National Institute of Standards and Technology
325 Broadway
Boulder, CO 80303

There is little more than the image I extracted.
This circuit had been developed somewhat earlier and as far as I have
been able to tell hasn't appeared anywhere else.

It has also been used for a 5MHz to 10MHz doubler. (Wenzels 5- 20MHz
JFET doublers are supposed to be derivatives of a NIST design)
There is no fundamental reason that it cant be used at even lower
frequencies, provided suitable transformers can be built/obtained.

The real question is perhaps who make JFETS (especially matched ones)
anymore.
JFET matched pairs:
Interfet
http://www.interfet.com/
Linear systems
http://www.linearsystems.com

Other JFETs:
Vishay/Siliconix
http://www.vishay.com/fets-small-signal/SSFsgnchjampP/
Onsemiconductor:
http://www.onsemi.com/PowerSolutions/parametrics.do?id=806
Fairchild semiconductor
http://www.fairchildsemi.com/sitesearch/fsc.jsp?command=eqattr1=AAAFamilyattr2=Junction+FET+%28JFET%29

http://www.fairchildsemi.com/sitesearch/fsc.jsp?command=eqattr1=AAAFamilyattr2=Junction+FET+%28JFET%29

Various other suppliers
Hitachi
Sony
etc.

Noise specifications are similar for all manufacturers, however to
achieve the stated phase noise performance testing and selection of
JFETS may be required.
At lower frequencies higher capacitance JFETS should be usable.
a pair of J310s can be substituted for the U431 but some matching of the
JFETS is desirable
The fundamental attenuation depends on the matching of the 2 FETs and
the input transformer.
I would expect 20dB suppression of the fundamental to be easy and
perhaps 40dB if the circuit is modified slightly to allow compensation
for residual JFET mismatch.

Transformers:
There should not be any great problem with input transformer saturation
as the dc current flowing in the secondary due to FET mismatch will be
small.
The output transformer has dc current flowing in the primary (~20mA for
28mA peak JFET currents) this doesn't appear to exceed the specified
limits for most Minicircuits transformers, however these limits aren't
well specified in the datasheets (it does make a difference if it is
flowing in the secondary or primary of a transformer with a turns ratio
of other than 1:1, Minicircuits do not specify which winding the dc
limit refers to). NIST regularly drive the primary of Minicircuits 2:1
stepdown (200:50 ohm) transformers without difficulties due to
transformer saturation.

The best turns ratio for the input transformer is best determined by a
combination of simulation and testing to achieve the desired JFET peak
drain currents.

Bruce

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Re: [time-nuts] NIST frequency doubler

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

Said
To give some idea of the transformer ratios required a simulation using 
pSpice shows that:

When using 2 x 2N4393's connected in parallel (limited choice of JFETs 
available) for each JFET in the NIST circuit, an  input transformer with 
a 1:2 turns ratio with centre-tapped secondary and an output with a 2:1 
turns ratio is about optimum. Input is fed from a 5MHz  2Vrms source 
with a 50 ohm source impedance (develops 1V rms in a 50 ohm load) source 
resistor is 100 ohms. Input transformer primary magnetising inductance 
was 50uH. Output transformer secondary magnetising inductance was 50uH.
Output is 1V rms into a 50 ohm load. Output transformer primary dc 
current is ~ 20mA.
 
To allow adjustment for individual FET characteristics the input 
transformer secondary centre tap can be grounded and a capacitively 
bypassed resistor connected in series with the source of each JFET. The 
resistor values are then selected/adjusted to achieve the desired output 
and minimise the fundamental component in the output. Trimpots can be 
used, initially adjust the trimpots to the required value whilst the 
specified input is applied, then measure each trimpot's resistance 
setting and replace it with a fixed resistor.

Since JFETS have a relatively large spread in characteristics individual 
adjustments are required.

Bruce

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Re: [time-nuts] NIST frequency doubler


[EMAIL PROTECTED] wrote


Thanks for the info Bruce, Magnus,
 
I will be reading the Felton paper to get more info.
 
With a bit of trickery, I bet this circuit can be used with Bipolar  
transistors.
 
bye,

Said

  

Said

You mean like the circuit in the attached file?
Input transformer configuration is the only way I can simulate a 
centre-tapped transformer.
1 ohm resistors are merely present to keep the simulator happy with 
transformer primaries connected in parallel.


The circuit is far more predictable than the JFET version, however there 
is no data on the close in phase noise performance.
Whilst this circuit will work with the 2N3904's shown, with higher ft 
transistors the emitter base reverse voltage ratings may be exceeded.


At least with JFETS the gate source reverse breakdown voltage is 
relatively high.


Bruce



BJTCommonBaseFrequencyDoubler.pdf
Description: Adobe PDF document
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Re: [time-nuts] NIST frequency doubler

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

[EMAIL PROTECTED] wrote:
 ); SAEximRunCond expanded to false
 Errors-To: [EMAIL PROTECTED]

  
 In a message dated 7/9/2007 18:34:30 Pacific Daylight Time,  
 [EMAIL PROTECTED] writes:

   
 Since JFETS have a relatively large spread in characteristics  individual 
 adjustments are  required.
 

   
 Bruce
 



 Thanks again Bruce,
  
 I am not a big fan of Jfets... Prefer Mosfets or Bipolars..
  
 There are some ultra-low-noise Audio Jfets such as the dual LSK389:
  
 _http://www.linearsystems.com/products.html#GlossD_ 
 (http://www.linearsystems.com/products.html#GlossD) 
  
 I wonder if these work well at 5/10MHz...
  
 bye,
 Said


   
Said

Probably not as they tend to have relatively large gate source 
capacitances especially the lower noise ones.
MOSFETS tend to have excessive flicker noise for this application.

Bruce


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[time-nuts] NIST frequency doubler

2007-07-07 Thread Dr Bruce Griffiths

The schematic for a NIST developed, low phase noise frequency doubler is 
attached.
This device appears to perform significantly better than the Wenzel FET 
doubler specifications at least in the flicker noise region.
With suitable modifications to allow individual adjustement/selection of 
the bias for each JFET a pair of the more readily obtainable J310's can 
be substituted for the U431.


Bruce
inline: NISTFreqDoubler.gif___
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Re: [time-nuts] NIST frequency doubler

2007-07-07 Thread Dr Bruce Griffiths

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

Mike Feher wrote:
 Interesting. Diode doublers of this configuration have been around for about
 40 years, and of course so have their FET counterparts. While I never did an
 investigation on any additive residual noise, since typically the 6 dB was
 enough to mask it, how is this better than the plain jane full wave diode
 doubler? 73 - Mike

  
  
 Mike B. Feher, N4FS
 89 Arnold Blvd.
 Howell, NJ, 07731
 732-886-5960
   
It has lower phase noise especially at lower frequency offsets.
About 10-12dB lower (@75Hz offset, 10MHz input) than a typical frequency 
multiplier according to NIST.

Bruce


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Re: [time-nuts] NIST frequency doubler

2007-07-07 Thread Dr Bruce Griffiths

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

Mike Feher wrote:
 Well, I guess that is according to NIST. I do not see how an active doubler
 can have lower noise than a passive one, especially when the original signal
 has already been degraded by 20log2, or 6 dB so the contribution of the
 doubler would not even be noticed unless the source was so much better.
 Regardless, an interesting observation, but I am skeptical. I have seen
 other stupid measurement procedures come out of these high ranking so called
 official institutions over the past 40 years. There are a couple I am
 fighting right now, one regarding measurement of AM/PM conversion and the
 other basing oscillator long time ageing on short term measurements. Regards
 - Mike 

  
  
 Mike B. Feher, N4FS
 89 Arnold Blvd.
 Howell, NJ, 07731
 732-886-5960
  
   
However, it apparently makes a detectable (10x) improvement to the short 
term stability of an atomic frequency standard.
Diode frequency doublers do need an amplifier to produce a doubled 
frequency output at the same level as a JFET frequency doubler.

Bruce


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Re: [time-nuts] Troubleshooting SR DG435 Four Channel Digital Delay/Pulse Gen

2007-07-02 Thread Dr Bruce Griffiths

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

Brooke Clarke wrote:
 Hi Bruce:

 The common pin has a 100 ns period wave at + and - 500 mv.
 One of the center pins on the INT/EX switch had + and - 1 volt at 100 ns 
 period.
 Have Fun,

 Brooke Clarke
 http://www.PRC68.com
 http://www.precisionclock.com
   
Brooke

The 10MHz level translator for the MC12040 probably looks something like 
the posted schematic, basically a longtailed pnp pair that translates a 
sinwave (or TTL) input to differential ECL levels.
The base of Q2 may be biased at 1,4V or so to translate TTL level from 
the on board oscillator or GND for a sinewave input. Supply voltages may 
vary but essentially the collectors should produce complementary ELC 
level signals one of which is used to drive the MC12040. Details may 
differ but essentially one collector will produce an ECL output to drive 
the MC12040.
Check the voltage waveforms on the MC12040 pins 6 and 9.

Bruce

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Re: [time-nuts] May I ask for your advice on a faulty 5370B?

2007-07-02 Thread Dr Bruce Griffiths

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

S McNamara wrote:
 G'Day All,
 I just purchased a 2nd hand HP5370B counter.
 It was last calibrated in 2002 but fails the operators checks.
 I have run tests 1-21 and only a few fail.
 In step 13 the display indicates 90.9*ns
 In step 15 the std dev is 20.* to 16.*ns with a min of 90.9*ns and a max 
 of 91.*ns
 In step 17 the stop period is 91.*ns and the start period is 8.91ns
 I have measured its ref output with another counter and it seems stable 
 and 10MHz.
 So I am seeking ideas on where to start to fault find, any guidance 
 would be much appreciated.
 Regards Scott

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Check the frequency multiplier chain alignment.

Bruce

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Re: [time-nuts] ? phase comparison or other device

Bob Paddock wrote:
 On Saturday 30 June 2007 10:15, Dr Bruce Griffiths wrote:

   
 Not true, there's nothing magic about amplifier saturation, any means 
 that limits the amplifier output whilst dropping the small signal gain 
 to a low value will have exactly the same effect.
 

 The AD8036 and AD8037, from Analog Devices, are wide bandwidth, low 
 distortion clamping amplifiers. 
 The AD8036 is unity gain stable. The AD8037 is stable at a gain of two or 
 greater. 
 These devices allow the designer to specify a high (VCH) and low (VCL) output 
 clamp voltage.
 The output signal will clamp at these specified levels.

 http://www.analog.com/en/prodDesc/0,2895,AD8036%255F0,00.html

 AN-402: Replacing Output Clamping Op Amps with Input Clamping Amps (pdf, 
 57,313 bytes)

 http://www.analog.com/UploadedFiles/Application_Notes/374941256AN-402.pdf

 So far most clamping amplifiers have relied upon an output clamping 
 architecture and are called output clamp amps (OCAs). 
 A new architecture called an input clamp amp (ICA) offers superior clamping 
 accuracy and lower distortion.

   
 A diode clamp in the feedback path will cut the noise gain to 1 when 
 either diode turns on. The following diode clamp across the filter 
 capacitor will reduce the noise gain to a very small value when it turns on.
 Both diode clamps and internal saturation will still produce some output 
 noise although not from the amplifier input stages.
 

 Improperly done diode clamps can significantly increase harmonics.


   
Bob

These devices are a little noisy below 100Hz.
Also any noise at the input clamp level inputs appears at the output.
Since these devices actually set the maximum input voltage before 
clamping occurs they are unsuitable when the gain is high.

The distortion produced by a diode clamp is immaterial when one is only 
interested in the zero crossing time.

Bruce


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Re: [time-nuts] ? phase comparison or other device

Bob Paddock wrote:
 These devices are a little noisy below 100Hz.
 

 Rather than constantly battle the there is to much noise, what are
 your thoughts on deliberately injecting out-of-band noise?

 As an example:
 http://www.analog.com/UploadedFiles/Application_Notes/319765654AN-410.pdf
 Overcoming Converter Nonlinearities with Dither

   
 The distortion produced by a diode clamp is immaterial when one is only 
 interested in the zero crossing time.
 

 It depends on where the harmonics fall.


   
Bob

What is the application for which you want to use injected out of band 
noise?
Since the performance of a well designed zero-crossing detector is 
equivalent to a 25 bit ADC when locating the zero-crossing, it will be 
difficult to replicate this performance using a lower resolution ADC 
even combined with out of band dithering.

In practice, diode clamp circuit distortion in a zero-crossing detector 
isn't an issue.

Bruce

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Re: [time-nuts] ? phase comparison or other device

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

Bob Paddock wrote:
 The AD8036 and AD8037, from Analog Devices, are wide bandwidth, low 
 distortion clamping amplifiers. 
 The AD8036 is unity gain stable. The AD8037 is stable at a gain of two or 
 greater. 
 These devices allow the designer to specify a high (VCH) and low (VCL) output 
 clamp voltage.
 The output signal will clamp at these specified levels.

 http://www.analog.com/en/prodDesc/0,2895,AD8036%255F0,00.html

 AN-402: Replacing Output Clamping Op Amps with Input Clamping Amps (pdf, 
 57,313 bytes)

 http://www.analog.com/UploadedFiles/Application_Notes/374941256AN-402.pdf

 So far most clamping amplifiers have relied upon an output clamping 
 architecture and are called output clamp amps (OCAs). 
 A new architecture called an input clamp amp (ICA) offers superior clamping 
 accuracy and lower distortion.
   
Bob

A significant issue with these clamping amplifiers is that although when 
the clamp is active the signal gain is near very low, the amplifier 
noise gain is the same as when the clamp isn't active.
In contrast with a simple diode clamp, the signal gain is low when the 
clamp is conducting and the amplifier noise gain is at worst unity.
Surely this characteristic of a simple diode clamp reduces the noise 
associated with the amplifier accumulated on the low pass filter 
capacitor in a zero-crossing detector over the amplifier noise 
contribution from an equivalent zero-crossing detector using such input 
clamping amplifiers?

Bruce

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Re: [time-nuts] Troubleshooting SR DG435 Four Channel Digital Delay/Pulse Gen

); SAEximRunCond expanded to false
Errors-To: [EMAIL PROTECTED]

Brooke Clarke wrote:
 Hi:

 The DG535 Four Channel Digital Delay/Pulse Generator shows
 Ext Clk Error on power up.
 The obvious thing to do is turn the rear panel switch to INT, but after 
 powering up with the switch in either position the same error message appears.

 Connecting an external 10 MHz to the clock input and with the INT/EX switch 
 in 
 either position the same error is there.

 The on line manual does not have schematics.  Any thoughts?

   
Brooke

Is the longtailed pair Q502+ Q503 producing a 10MHz ECL level output signal?

Bruce

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Re: [time-nuts] ? phase comparison or other device

2007-06-26 Thread Dr Bruce Griffiths

Pete wrote:
 Bruce,

 A few final thoughts.

 1. Thanks for the critical view; it does help.

 2. Like many time-nuts I have a reasonably good 10MHz source 
 sometimes need to check out a newly acquired OXCO to ensure
 it can muster 1E9 or 1E10 performance (with 10x headroom).
 An SR620 would be ideal, but it's just too many $$ ;even used.
 I expect casual participants of time-nuts already have a basic,
 decent counter e.g. HP5335A  a basic decent synthesizer
 e.g. PTS040, Fluke6060(?), HP3335x or 6x. Also, I assumed a
 coaxial level 7 mixer  suitable lowpass filter would be available.

 3. I read the JPL paper (more than once)  developed the first three
 stages (modified for 1KHz bandpass) per their process. At that point
 the measured jitter was well under 1ns rms; which was enough to enable
 1E12 resolution for 10MHz sources. I deliberately choose the ADA4899-1
 opamp since it's characterized for 5V operation, low noise, fast  cheap
 enough ($4.30/ea). It was apparent that even with 2 stages the ZCD
 was still under 1ns jitter; the risetime wasn't blazing, but it was 
 obviously
 good enough.

 4. Without PCB capability (at home  now retired) even this simple
 circuit is tough to build; each part adds significantly to the effort 
 when
 doing 1-up. So I examined the need for every part in an effort to
 minimize parts count, but retain jitter performance. I found that the
 opamp overload recovery was more than fast enough to discard the
 limiting without measurable deterioration in jitter. Lots of parts went
 away; construction became easy.

 5. I went TOO FAR. The opamps I had exhibited such low offset that I
 DC coupled without thinking about it. WRONG answer (as you noted),
 Rookie mistake. I have shown the AC coupling  2nd stage feedback
 resistor in the revised circuit.

 6. The ZCD costs $20 for parts  about 2 hours to build/check out.
 It performs well enough to look at stable sources to 2 parts in 1E12
 in 50 to 100 seconds and be confident in the data. The noise floor is
 easy to measure  verifies functionality.

 Is it well designed ? NO. Could it be (much) better? Certainly.
 Does it work well for it's intended purpose? Yes.

 My assumptions about equipment may be out of line. In my case, eBay
 supplied everything, except the mixer, filter  ADA4899-1s, so this
 effort didn't require much in the way of extra $$. It does what I wanted.

 As previously observed, the mixer should have a diplexer between it and
 the filter for the mixer higher order products to be terminated properly.
 I examined the filter input Z, as terminated, and found it to be from 150
 ohms inductive to 1200 ohms inductive from 10 to 30 MHz. This suggests
 the use of a feedthrough termination of around 100 ohms as a first order
 fix. Using a 93 ohm feedthrough, no improvement, or degradation in 
 results
 was noted. This could use more study.

 From your earlier response, I suspect you have a cheaper, better method
 in mind to achieve the same results. Would you detail it?

 Regards,
 Pete Rawson
 

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Pete

Try connecting the input stage inductor and capacitor in parallel with 
the 6190 ohm feedback resistor, but before you do this replace the first 
opamp with a lower gain bandwidth (audio??) device that is unity gain 
stable. This will produce a first gain stage that amplifies the signal 
of interest as well as the noise within the tuned circuit bandwidth 
without unduly amplifying the noise not within the tuned circuit bandpass.
The other thing you could do since you've chosen a 1kHz beat frequency 
is to use an audio transformer to step up the output of the mixer before 
amplifying it. NB dont forget to connect the transformer to ground 
through a capacitor that has a low impedance at 1kHz (this ensures that 
the dc load current at the mixer IF port is low)..

The mixer IF port should be terminated with a 10nF capacitor and a 
simple low pass filter consisting of say a 100uH inductor and a 1nF 
capacitor substituted for the 1.9MHz bandpass filter.
This, as shown by the NIST paper alluded to by Magnus, will increase the 
mixer sensitivity considerably. You should also run the mixer with both 
the RF and LO ports saturated ie more than 7dBm for both of these ports.

The mixer output noise at the 1KHz beat frequency will be somewhere in 
the vicinity of 100nV/rtHz, so if you have say a 1V peak output then the 
inherent jitter due to mixer noise will be around 160ps rms for a tuned 
circuit noise bandwidth of 100Hz. With a suitable amplifier choice you 
shouldn't degrade this by more than 5% or so. Achieving a resolution of 
better than 1E-13 in 1 second with a 10MHz input and a suitable counter 
is easy, provided you dont rely on the counters input circuitry to 
trigger on the amplified mixer output you

Re: [time-nuts] ? phase comparison or other device

2007-06-25 Thread Dr Bruce Griffiths

Ulrich Bangert wrote:
 Pete,

   
  5. Mini-circuits BLP-1.9 low pass filter.
 

 terminating the mixer if output with an lowpass/bandpass filter and NOT
 with an diplexer is not so good an idea. Where does the rf go?

 Best regards
 Ulrich Bangert

   
Ulrich

This depends on whether the low pass filter has a shunt capacitor at its 
input or a series inductor.
With the shunt capacitor the RF is shunted to ground through this capacitor.
With a series inductor the RF sees a relatively high input impedance and 
the mixer will not perform well.

Bruce

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Re: [time-nuts] ? phase comparison or other device

2007-06-24 Thread Dr Bruce Griffiths

Pete wrote:
 Bruce,

 This idea is NOT intended to rival the JPL results. Instead,
 it's intended to be cheap, easy to replicate  allow rather
 low cost instruments to be used to compare good sources
 to parts in 1E12, quickly. The 1KHz heterodyne frequency
 makes life much easier than 1Hz. Noisy components 
 ground loops are still of concern, but not so hard to fix.

 ADA4899-1 overload recovery is 50ns (per data sheet).

 I've attached a rather poor schematic which doesn't show
 power supply decoupling or the need to pull the disable pin high. The 
 ADA4899-1 uses 14mA per part, but it's
 quiet  fast. Metal film resistors are fine for this low
 noise application  all are low values to keep noise down.

 The inductors are easy to wind, but I found materials other
 than moly permalloy powder to be too noisy. Even with
 MPP material, cores with u200 are prone to field induced
 shifts which are unacceptable.

 Regards,
 Pete Rawson
 

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Pete

Even so, it pays to use a well designed circuit instead of something 
thrown together with little understanding of what you are doing.
The JPL design is not expensive and doesn't require particularly exotic 
wideband components or high resolution counters.
There is still a noise advantage in using a 1Hz beat frequency, suitable 
opamps are readily available.

Magnetic shielding of the inductors and/or the entire circuit is 
probably advisable for the best performance.

The circuit diagram is sufficient to confirm my suspicions.

The input stage noise gain will be high at frequencies away from the 
1kHz frequency of interest.
This is a very poor design.
It is very easy to do much better with the same components.
A 50ns overload recovery will be somewhat problematic when you are 
attempting 1ns or less timing jitter.
A well designed and simple feedback bound circuit will be much faster.
Using an inverting amplifier input stage is not optimum for noise.

In fact the input stage doesn't need to use such a wideband opamp, a low 
noise opamp with a more modest gain bandwidth configured as a non 
inverting stage with gain followed by a bandpass filter will have far 
better performance.
Only the final limiting stage needs to be fast.

Also since you are using a 1kHz offset frequency it may be advantageous 
to use a transformer to couple the mixer output to the input stage, a 
stepup transformer will improve the equivalent input noise significantly 
even when using a somewhat noisier slower and cheaper opamp for the 
input stage.

A low pass filter with a lower cutoff frequency than  the several  MHz  
of the  BLP 1.9 is desirable between the mixer and the input amplifier, 
a tuned bandpass filter would be optimum but don't forget to terminate 
the mixer IF port in a suitable impedance at frequencies other than the 
beat frequency. It should be possible to combine the tuned bandpass 
filter and the stepup transformer.

Try reading the JPL article to gain an understanding of how to do it 
properly.
Although their design uses cascaded low pass filtered amplifiers with 
feedback bound circuits, the same technique can be used with bandpss 
filters.
Since you use a 1kHz beat frequency it is advantageous to AC couple the 
various stages to reduce the effective output dc offset.
Low frequency earth loops will limit the performance unless a different 
mixer with dc isolated RF. LO and IF outputs is used.
Suitable mixers are available.

Your claimed performance is comparable with that which can be achieved 
using a linear phase comparator which neither requires a mixer (other 
than the implicit mixer built into the phase comparator) nor a high 
resolution counter.

Bruce

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Re: [time-nuts] ? phase comparison or other device

2007-06-24 Thread Dr Bruce Griffiths

WB6BNQ wrote:
 Bruce,

 Can you provide a link to the JPL system you reference above ?

 Thank you,

 BillWB6BNQ

   
Bill

http://ntrs.nasa.gov/index.jsp?method=orderoaiID=19910016462 
http://ntrs.nasa.gov/index.jsp?method=orderoaiID=19910016462

There is also, or was, a free to download source for this paper 
somewhere, which I cant recall.

Bruce

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Re: [time-nuts] ? phase comparison or other device

2007-06-23 Thread Dr Bruce Griffiths

Pete wrote:
 Here is a scheme that seems to work well for comparing stable frequency
 sources in the range of 10 to 100 second measurement intervals.

 Objective - Measure frequency to +/-2E-12 in less than 1 minute.

 Method - Heterodyne DUT output to 1KHz with a master reference source +
 mixer feeding a tuned zero crossing detector + counter.

 Equipment - 1. Master reference source at 5 or 10 MHz, e.g. mature OXCO or
GPSDO.
 2. Synthesizer set to DUT - 1KHz, locked to reference
source. The synthesizer averaged output must settle 
 to
 10uHz in 10 seconds, e.g. HP 3335A or 3336C.
 PTS 040 should work fine, also.
 3. 9 digit/s counter, locked to reference source with
 selectable gate time. An input LPF (100KHz) helps,
 e.g. HP 5335A.
 4. Mini-circuits ZRPD-1 mixer. Other level 7 mixers
  should work, but haven't been tested.
 5. Mini-circuits BLP-1.9 low pass filter. Other filters
 should work, but haven't been tested.
 6. Tuned zero crossing detector, accepts 0 to 5dBm 1KHz
 sinewave input  outputs 1KHz squarewave to counter
 with less than 1nS rms jitter.

 Setup - DUT set to +7dBm connects to mixer LO port. Synthesizer set to DUT -
 1KHz at +4dBm connects to mixer RF port. BLP-1.9 connects to
  mixer IF port. ZCD input connects to BLP-1.9. Counter connects 
 to ZCD
  output  set for 5 to 10 second gate time. The DUT frequency =
  synthesizer setting + counter frequency;
  10uHz digit = 1E-12 for 10MHz DUT.

 The ZCD - Made from 2 Analog devices ADA4899-1, inverting configuration,
   cascaded, using +/- 2.5 volt power supplies. Both amps 
 have their
   non-inverting pins connected (only) to a 100 ohm resistor 
 to ground.
   Both amps have 5uF//5mH to ground on their inverting 
 inputs. The
   input amp has Rin = 422 ohms and Rf = 6190 ohms. The 
 output amp
   has Rin = 562 ohms and Rf = open. The output amp output 
 pin has
   2ea 100 ohm resistors in series to ground. The counter is 
 connected
   to the common point of the 100 ohm resistors. Nominal 
 supply bypassing
   is required. Battery supplies at +/- 3 volts help isolate 
 noise sources.

 Only 2 ZCD parts aren't junk box items. The Analog Devices ADA4899-1 are in
 distributor stock as SMT parts only. The 5mH inductors are hand wound on MPP
 toroid cores. 133 turns on a 55438 core or 114 turns on 2 stacked 55521 
 cores
 using 22 or 24 AWG wire work fine. Other MPP cores will work, but limit Bmax
 to 50mT at 1KHz  0.5V rms. Gapped ferrites are too noisy. The 5uF caps are
 polypropylene or mylar film types.

 Noise floor measurements using HP5335A opt 010 as reference source  1KHz
 counter + HP3336C synthesizer yielded Favg = 10,000,000.000 001 5 Hz and
 Fdev = 4.3 uHz for 36 samples at 5.7 second gate time per sample. 10 sample
 groups are within +/- 2E-12.

 Pete Rawson

   
I am confused the opamp circuitry as described seems to be almost 
exactly the inverse of what is required.
Please send a schematic so I can check.

Are the MPP cores powdered iron or ferrite?
The phase stability of the bandpass filters is critical as is any phase 
instability like that exhibited by ferrite cores.

The overdrive recovery characteristics of the ADA4889-1 are not 
specified, how fast does it actually recover from overdrive?

One can do considerably better than this (JPL have a system with a 
resolution of around 1E-15/Tau 1Hz offset, 100MHz input) with lower 
offset frequencies and a well designed amplifier and cascaded limiters, 
however low frequency ground loops are problematic.
Optical isolation is almost mandatory.

Bruce

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Re: [time-nuts] another Ebay mixup, 5370

2007-06-10 Thread Dr Bruce Griffiths

Tom

Tom Van Baak wrote:
 In the case of the 5370, page 3-12 of the manual is where it came from (15.
 Press STD DEV and +/- TI switch.  Display should read less than 100 ps (this
 reading is the instrument's jitter).)
 

 I'm wondering if it would be more informative to make three
 runs: one with A and B uncorrelated to ref; one with A=ref
 and one with B=ref.

   
 At some point between my original 2316 edition and the 2904 edition scanned
 by David Kirkby, they apparently changed this step to call for pressing the
 +TI switch, unless the +/- symbol failed to scan properly.  I get about
 10-15 ps more jitter in +TI ONLY mode for whatever reason.
 

 Agreed, that's odd. Bruce, any ideas on this one?
   
Whenever one uses an asynchronous input frequency, the start and stop 
interpolators are used over their full range (or a substantial part 
thereof) so that the variations in the difference in differential 
nonlinearities of the 2 interpolators is combined with the intrinsic 
jitter when calculating the jitter from the series of period measurements.
When using +TI only the START event precedes the STOP event and the 
period of the input waveform is measured (the differential delay of the 
START and STOP channels as well as the effect of any START and STOP 
trigger mismatch affect the measurement).

When using +-TI then the START and STOP events occur on the same edge of 
the input waveform so that the measured time interval is nominally zero.
When the START and STOP events are separated by 1 period of the input 
signal (100ns for a 10MHz input) the difference in the differential non 
linearities of the START and STOP interpolators are not as well matched 
than when the the START and STOP events are nominally coincident. Thus 
the calculated jitter will be larger for the +TI only setting.

The jitter measurement with an asynchronous input signal is more 
representative of the result when measuring signals that are not 
coherent with the internal timebase.
When using the internal timebase as the input signal the START and STOP 
events will tend to exercise the same narrow region of the interpolators 
so that the calculated jitter will be dominated by noise rather than the 
interpolators differential non linearity characteristics.
   
 The last time I studied the manual, I remember being convinced that the 5370
 would be relatively immune to clock-correlation effects if the interpolators
 were set up properly.
 

   
Wishful thinking, the designers don't believe this so why should we?

I have a copy of a letter from David Chu detailing the then known 
sources of differential nonlinearity in the 5370A.
These causes are principally crosstalk between the START and STOP 
channels, and interaction between the mixers and the phase locked 
oscillators.
 Right, but that's a big if, especially if the unit is surplus. So it's
 best to assume the interpolators aren't perfectly tuned which is
 why keeping ref away from the A or B inputs is important.

 /tvb
   
Bruce

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Re: [time-nuts] another Ebay mixup, 5370

2007-06-10 Thread Dr Bruce Griffiths

[EMAIL PROTECTED] wrote:
  Hi Bruce,
  
 sounds like I can probably do the 200MHz multiplier board adjustment. I  
 wonder how much improvement that by itself, with the hardware mods will give? 
  I'm 
 just afraid to make things worse.
  
 I used to work with TV's, and it took me years to learn how to adjust a  
 good-old picture tube correctly. It's more an art than science. By giving the 
  
 service manual a quick glance, I fear this is similar.
  
 bye,
 Said
   
Said

Its probably still worth looking at all the test points on this board 
and seeing if the spectral content is what it should be.
If it is don't make any adjustments, otherwise adjustment should be 
relatively trivial as the procedure is relatively straightforward.
However there are some capacitively (critically?) tuned resonant 
circuits which will need some care to adjust correctly.

Bruce



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Re: [time-nuts] another Ebay mixup, 5370

[EMAIL PROTECTED] wrote:
 Hi Tom,
  
 this was the recommended setup (by HP) for checking the internal  noise. Feed 
 the 10MHz output back to the input using a short cable, and set the  unit for 
 COMMON input, setting 50 Ohm impedance etc.
  
 In the meantime I did some more tests, and found the following:
  
1) The sine-wave output is crappy. The sine wave has some sort  of 
 Class-B cross-over distortion, and it measures a whooping 200ps RMS jitter  
 on my 
 Wavecrest jitter analyzer (400ps pk-pk). Compare that to 2.7ps RMS  jitter I 
 measure on our Fury 10MHz output. Definitely the crystal got damaged,  or 
 something else.
  
 The unit has about 2x better jitter performance (around 50ps RMS) if I feed  
 a clean Fury 10MHz into it. I think the 10811 OCXO or the internal driver  
 circuit may have gotten damaged.
  
  
 thanks,
 bye,
 Said
   
Said

Can you send an image of the rear panel sinewave output waveform?

Bruce

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Re: [time-nuts] another Ebay mixup, 5370

[EMAIL PROTECTED] wrote:
 Hi Bruce,
  
 just found out that the 10MHz output looks very much like the  picture in the 
 5370B service manual.
  
 I am not impressed. HP could have done a better job on that output :( Maybe  
 my unit isn't broken after all, maybe the 200ps RMS jitter is normal?
  
 I attached some pics of the 5370B 10MHz output here.
  
 Will send plots of the Fury sine output in separate email, then plots of  
 both Fury and 5370B 10MHz outputs on the spectrum analyzer.

 The 5370B is quite noisy, energy up to 700MHz. That's also clearly  visible 
 in the sine wave.
  
 Of course the 200ps RMS jitter is not visible in these pics.
  
 bye,
 Said
   
The HP5370 external output isnt taken directly from the internal xtal 
oscillator, but is squared up using a sting of ECL line receivers and 
then its fed to a longtailed pair which produces a squarewave collector 
current. An LC tank in the collector filters out the 10MHz component.
The simple output filter will off course not attenuate the higher 
harmonics as much as you may like.
However as long as the amplitude and phase of each harmonic is stable 
they will have little effect on the jitter.

A 200ps jitter from the EXT 10MHz output isnt normal.
Even the low cost oscillator option is far better than this.

Remove the 10811 and power it up externally and then check its output 
jitter.
It can drive a 50 ohm load directly.
Its output waveform should be much cleaner than that of the 10MHz output.

Bruce

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Re: [time-nuts] another Ebay mixup, 5370

John Miles wrote:
 Pretty similar results here, taken from the 5370B's rear-panel output while
 running on the internal 10811B (attached).  Indicated jitter with this setup
 is about the same as it was on the ext ref via the 5087A (10-12 ps).

 I've seen this counter return self-test jitter results in the 15-25 ps range
 before.  Not sure why it's in such a good mood today.

 At any rate, it doesn't appear that the wave shape is a problem... but of
 course, you will usually get better jitter readings with a fast edge than
 with a sine wave.

 -- john, KE5FX
   
John

Internal crosstalk can cause the 5370 to appear to be much better than 
specified.
The jitter will vary as you vary the length of the cable connecting the 
external 10MHz output to the input.
If the input is attenuated (inadvertently by internal fault or 
otherwise) the jitter will increase considerably with a sine wave input.

It would be nice to have a look at the jitter spectrum (of Said's 5370 
), to see if there are any line frequency related components.
After 20 years or less some of the power supply electros may be suspect.


Bruce


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Re: [time-nuts] another Ebay mixup, 5370

John Miles wrote:
 Pretty similar results here, taken from the 5370B's rear-panel output while
 running on the internal 10811B (attached).  Indicated jitter with this setup
 is about the same as it was on the ext ref via the 5087A (10-12 ps).

 I've seen this counter return self-test jitter results in the 15-25 ps range
 before.  Not sure why it's in such a good mood today.

 At any rate, it doesn't appear that the wave shape is a problem... but of
 course, you will usually get better jitter readings with a fast edge than
 with a sine wave.

 -- john, KE5FX

   
John

My 5370A currently has the following characteristics:
With the EXT 10MHz connected to the input jitter is 15ps.
With an FTS1200 5MHz input signal jitter is 46ps.
With an external GPS locked 10MHz input signal jitter is 45ps.

This illustrates the danger in believing the jitter measured with a 
coherent input signal.

Bruce

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Re: [time-nuts] Pendulums and Atomic Clocks and Gravity :probably more than you want to know...

2007-06-01 Thread Dr Bruce Griffiths

Bill Beam wrote:
 Mike,

 I was afraid someone would say 'Riemann tensor'
 The problem with the Riemann tensor is that I don't
 think that anyone here can write in down in detail
 for this problem (let alone solve it).  I surely can not.

 I also don't think that anyone here is ready for the
 idea that there is no such thing as gravitational force,
 and that in the absence of any other force everything
 is in free fall.  World lines and geodesics, oh my!
 (inside joke).

   
Surely its not necessary to write down the detailed Riemann Tensor for 
this simple case?
Surely the Schwarzchild metric is a good approximation to situation of a 
test mass orbiting the Earth?
If so, then perhaps the methods espoused by Wheeler can be used to 
derive the orbits?

Bruce

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Re: [time-nuts] Sensing pendulum position, speed, or height

2007-05-31 Thread Dr Bruce Griffiths

Tom Van Baak wrote:
 A Measurement of the Period Stability of a Free Pendulum
 http://www.leapsecond.com/history/1996-DeMarchi-Pendulum-Stability.pdf

 Clever solution. His optical gap is something like 5 microns.

 /tvb

   
An additional issue is the pointing instability of the laser used.

A position sensitive detector (lateral-effect photodiode sensor) for 
which the output is independent of the beam flux could be used however 
the noise and drift (typically =1um/C) may be an issue.

Bruce


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Re: [time-nuts] PRS-10 findings

2007-05-30 Thread Dr Bruce Griffiths

Poul-Henning Kamp wrote:
 In message [EMAIL PROTECTED], Peter Vince writes:

   
  I have seen something similar with my 53132A.  I was checking 
 on the delay variation of an amplifier distributing 10 MHz, and 
 noticed a regular sinusoidal pattern, about a third of a nanosecond 
 peak-to-peak, with a period of about 70 seconds.
 

   
A manifestation of the effects of slowly sweeping through a range of 
start and stop interpolator values so that the interpolator integral and 
and differential non linearities become apparent?
Strictly the difference between the nonlinearities of the start and stop 
interpolators becomes visible.
The resultant variation of around 300ps pp are well within the 
specifications for the counter.
 Almost any kind of interference will cause such anomalies and the
 closer the frequencies are to a multiple of each other, the longer
 the period will be.

 It is quite common for the frequency difference between the counters
 internal X-tal and the measued frequency to show up like that once
 you start to measure down in the nanosecond end of things.

 The HP5370 has a rather heavyhanded piece of electronics that
 eliminate this effect with a jitter based approach and as far as I
 have been able to measure, it works.

   
Not quite true the HP5370 has a whole host of anomalies like 
differential linearity errors of 100psec or more for certain time 
interval ranges, at least according to its designers.
The identified causes are:
Crosstalk between microstriplines used for each channel (effective only 
when the affected signals are simultaneously active near a trigger 
point) and modulation of the internal 200MHz reference by the mixer 
outputs (always present with a quasi period of ~5.02ns).

 normal counters don't have this, as they are not designed to measure
 in that domain of disturbances.

 The easiest way to determine if this is indeed the problem, is to
 feed the counter an external frequency which can be varied a bit
 up and down.  If the period of the artifact changes accordingly: QED.
   
Bruce


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Re: [time-nuts] FW: Pendulums Atomic Clocks Gravity

2007-05-30 Thread Dr Bruce Griffiths

Bill Beam wrote:
 Assume satellite in circular orbit.  (Not really necessary.)
 Assume test mass's released at rest wrt satellite center of mass.
 Inner test mass released closer to Earth and outer released farther
   
 from Earth.  Also assume no air currents, no relativity, no luminiferous
 
 ether, no static, no s- -t.
   

   
 It helps if this problem is solved in a proper (Earth based) inertial frame
 and to consider the total energy (kinetic plus potential) of the test 
 masses.
   
   
 But there are no strictly inertial frames based on the Earth.
 The earth rotates around its axis (neglecting precession, nutation etc), 
 it also orbits the sun which in turn ...
 An actual test of these predictions would be somewhat expensive to carry 
 out.
 The damping due to the air in the shuttle or ISS (as well as a host of 
 other small effects) would tend to damp out such motion.
 The question is how quickly?
 

 This contradicts the last assumption stated above.
   
Yes, but if one wishes to experimentally test the predictions it is not 
always practical to use an SV with an internal vacuum.
The question is really could this be done on the ISS or shuttle or would 
the effects of the internal atmosphere disturb/damp the motion too quickly?
In other words what would actually happen to 2 such test masses within 
the space shuttle, for example?
The other question is how large would the interior of the SV have to be 
to avoid the test masses colliding with internal surfaces?

The other point that in practice the frames in which virtually all 
measurements are made are non inertial.
Sure one can correct the results to an Inertial frame if one can 
find/identify one that is inertial to a sufficient approximation.
However this is an elusive target which keeps shifting around as the 
precision of measurement increases.
General relativity surely indicates that the concept of an Inertial 
frame has a strictly local existence/validity?
 Bill Beam
 NL7F
   



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Re: [time-nuts] HP E1938 oscillator

2007-05-29 Thread Dr Bruce Griffiths

Robert Atkinson wrote:
 Hi,
 I'd have to agree with Said,
 FEI got hit with fines for shipping 1000B OCXO's that were diverted to a
 proscribed country. Most major countries that are allies of the USA
 should be OK though. 
 It's surprising what is controlled, very high speed 'scopes, low
 inductance high energy capacitors, quite a lot of fibre optic and laser
 stuff too.

 Robert.

   
Robert

That would have been under the old COCOM rules and cooresponding lists 
of controlled export items.
The actual controlled export items in the new lists were revised 
recently and such crystal oscillators no longer appear to be a 
controlled item.
Makes sense, since the Russia and China and other countries have have 
made equivalent performance oscillators for years.
Similarly rules on exporting some lasers have also been relaxed.

Bruce

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Re: [time-nuts] HP E1938 oscillator

2007-05-29 Thread Dr Bruce Griffiths

Poul-Henning Kamp wrote:
 In message [EMAIL PROTECTED], Dr Bruce Griffiths writes:
   
 Robert Atkinson wrote:
 

   
 The actual controlled export items in the new lists were revised 
 recently and such crystal oscillators no longer appear to be a 
 controlled item.
 

 But interestingly enough, nobody has bothered remove analogue
 computers from the list last I looked :-)

   
Poul-Henning

Well spotted.
To this you can add
Machetes (Post Rwanda item??).
Horses (by sea for slaughter).

The most amusing part is that the list of components proscribed by non 
nuclear proliferation requirements creates a handy shopping list of all 
you need to acquire for Uranium enrichment either via centrifuge or 
gaseous diffusion as well as a set of specifications for these and bomb 
triggering components.

Bruce

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Re: [time-nuts] FW: Pendulums Atomic Clocks Gravity

2007-05-29 Thread Dr Bruce Griffiths

Bill
Bill Beam wrote:
 On Tue, 29 May 2007 16:31:40 +1200, Dr Bruce Griffiths wrote:

   
 Ulrich, Didier

 Talking about forces, gravitational fields etc makes no physical sense 
 if the observer's reference frame isn't specified.
 For an observer in/on a satellite orbiting about the Earth with their 
 reference frame fixed with respect to the satellite.
 There is no gravitational field, whatever methods chosen to measure a 
 gravitational field (within the satellite) will always produce a null 
 result.
 

 Not true.
 Very simple experiments will show occupants of the satellite that they
 are in a non-inertial reference frame.  (Release a few test masses
 about the cabin and you will observe that they move/accelerate for no
 apparent reason, unless the satellite is in free fall which you'll know soon
 enough,)  The experimenter must conclude that the satellite is undergoing
 acceleration due to the influence of an attractive (gravitational) field.

 Just because NASA calls it 'microgravity' doesn't make it true.  It means
 NASA is wrong.  Weightlessness is not the same as zero-g.

   
Only, if you insist on sticking to Newtonian physics with all its 
attendant problems.

 Pendulum clocks fail to work, given an initial push they will just 
 rotate around the pivot, provided the pivot suitably constrains the 
 motion of the pendulum (ie a shaft running in a set of ball or roller 
 bearings or similar and not a knife edge pivot).

 If, however the satellite acts as a rigid body and has a large enough 
 diameter then it would be possible for an observer on the satellite to 
 detect a gravitational field gradient.
 

 Therefore, you must conclude that somewhere inside the satellite g is not 
 zero.

   
A finite gradient doesn't imply that the field itself is nonzero, except 
of course towards the extremeities of the satellite.

 Regards,
 Bill Beam (PhD, physics 1966, past tenured Associate Professor of Physics)


 Bill Beam
 NL7F


   
Bruce


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Re: [time-nuts] FW: Pendulums Atomic Clocks Gravity

2007-05-28 Thread Dr Bruce Griffiths

Ulrich, Didier

Talking about forces, gravitational fields etc makes no physical sense 
if the observer's reference frame isn't specified.
For an observer in/on a satellite orbiting about the Earth with their 
reference frame fixed with respect to the satellite.
There is no gravitational field, whatever methods chosen to measure a 
gravitational field (within the satellite) will always produce a null 
result.
Pendulum clocks fail to work, given an initial push they will just 
rotate around the pivot, provided the pivot suitably constrains the 
motion of the pendulum (ie a shaft running in a set of ball or roller 
bearings or similar and not a knife edge pivot).

If, however the satellite acts as a rigid body and has a large enough 
diameter then it would be possible for an observer on the satellite to 
detect a gravitational field gradient.
If the satellite is large enough and orbits close enough to the Earth, 
this gravitational field gradient would tear the satellite apart.

For an observer located on the Earth however the motion of the satellite 
can be accurately described by Newtonian mechanics where the centripetal 
pull of gravity acts on the satellite causing it to have a centripetal 
(radial) acceleration as it orbits the Earth.


Bruce

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Re: [time-nuts] FW: Pendulums Atomic Clocks Gravity

2007-05-28 Thread Dr Bruce Griffiths

Neville Michie wrote:
 Hi All,
 
 I am still having difficulty getting my head around the gravity point.
 Now I accept, in principle, that due to relativity  an intense  
 gravity field will slow a clock.
 My problem is visualising where you will find this field.
 At the centre of this planet gravity (from the planet) is zero. This  
 comes about by an elegant piece of
 calculus that shows that everywhere inside a hollow sphere the  
 gravity is zero. So a clock in the centre of Earth
 runs at the same rate as one on the surface? or does it run faster  
 because the one on the surface has the planetary gravity acting on it?
 I think that the one inside the Earth runs faster.
 But when you are between the Earth and Moon at a point where gravity  
 forces are neutral we should have the same rate as centre of planet?
 Now the way to measure gravity is to measure the force on a test  
 mass. If there is zero force there is zero gravity, except when you  
 are in orbit.
 This can be tested with 3 crossed gyroscopes that show your angular  
 velocity. If your angular velocity is negligible then the magnitude  
 of the gravity field is proportional to the force on a test mass.
 Unless you are in free fall accelerating towards a mass.
 I guess my question really is can you know that you are in a zero  
 gravity field so your clock is running at the fastest rate?
 Or is relativity relative. Does relativity only show up when there  
 are two frames of reference being compared, so there is no ultimate  
 reference frame with the fastest clock? Or can any clock have a  
 single relativity correction applied to it? How do you measure the  
 gravitational potential at any site? (ie the scalar quantity that  
 would be used to correct your clock).
 Has anyone got a clear answer?
 cheers, neville Michie
   
Neville

You are somewhat astray its not the gravitational field but the change 
in gravitational potential that red or blue shifts an atomic clock as it 
is moved from one location to another.
The same gravitational potential difference can result for a small 
change in altitude in a strong gravitational field as a larger change in 
altitude in a smaller gravitational field.

Also the gravitational field within a spherical shell is only zero when 
the density distribution on the shell is spherically symmetric.
This is important in determining the gravitational field at the centre 
of a body that has mascons of different density to their surrounding 
matter they are embedded within.

A clock doesn't necessarily run fastest when the gravitational field is 
zero, it runs fastest when the gravitational potential is highest.
Locations of zero gravity and maximum gravitational potential do not 
necessarily coincide.

For example an atomic clock located at the centre of the Earth runs 
slower than one located on the surface (ignoring the effects of rotation).
However the gravitational field at the centre of the Earth is near zero 
whilst on the surface it is non zero.

Bruce

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Re: [time-nuts] Pendulums Atomic Clocks Gravity

2007-05-27 Thread Dr Bruce Griffiths

Rex wrote:
 On Sat, 26 May 2007 19:54:21 -0700, Tom Van Baak [EMAIL PROTECTED]
 wrote:

   
 Even fused silica is unstable (see attachment).
 Single crystal materials should be significantly better.
 Ageing Invar doesn't do much for its dimensional instability.

 Bruce
   
 Nice plot. Thanks Bruce. Where'd you find it? Someday
 I want to visit your library! You are just amazing.
 

 I don't know what most of those materials are, but looking at the plots,
 seems Super Invar and Zerodur tags both point to the same line. The line
 just above is unlabeled. I wonder which should be assigned to this line.


 ___
   
Rex

Dont even think about super Invar.
It was only this stable at a particular temperature.
When measured at a different temperature it proved no more stable than 
invar.

Bruce

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Re: [time-nuts] HP E1938 oscillator

2007-05-27 Thread Dr Bruce Griffiths

Said

Part of the confusion probably stems from such gems as:

Technical Notes:
1.
A resolution of n bit corresponds to a quantization of 2n levels.

Random snippet from Supplement No1 to Part 774.

Bruce

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Re: [time-nuts] HP E1938 oscillator

2007-05-27 Thread Dr Bruce Griffiths

[EMAIL PROTECTED] wrote:
  
 In a message dated 5/27/2007 16:10:46 Pacific Daylight Time,  
 [EMAIL PROTECTED] writes:

   
 Technical Notes:
 1.
 A resolution of n bit corresponds  to a quantization of 2n levels.
 

   
 Random snippet from Supplement No1  to Part 774.
 

   
 Bruce
 


 Hi Bruce,
  
 I have yet to figure it out too. That's why we have all these lawyers here  
 in the US. What's even worse: if you give (well meant) advice, and the person 
  
 get's into trouble, they can come after you  :(
  
 But I think in spirit the export controls mean: anything that is  of 
 technical value, especially if it can be used militarily, needs to be under  
 very 
 close control of the government.
  
 Then again most Western Countries are free of most export  restrictions.
  
 bye,
 Said
   
Said

As far as I have been able to ascertain the list of export controlled 
items is virtually identical for most western countries and Russia.
There are some slight variations (mainly additions) between countries.
No doubt (for Russia at least) the country list classifications differ.

I stumbled over the local NZ list of export controlled items, as usual 
purely by accident, when searching for something somewhat unrelated 
(External cavity diode lasers).

As far as I can tell by perusing the complete CCL list (US version) 
neither the E1938A nor any of its component parts is a controlled item.
It would take a creative interpretation by an incompetent lawyer to 
apply the section on Atomic frequency standards to the E1938A which is 
not by any stretch of the imagination an Atomic frequency standard. It 
is not capable of being space qualified without substantial redesign nor 
is it capable by design of achieving a drift of 1E-11 or less per month.

Since the US has no jurisdiction here I can give well intentioned advice 
without worrying about prosecution (as long as I don't visit the US at 
least).

Bruce


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Re: [time-nuts] Pendulums Atomic Clocks Gravity

2007-05-26 Thread Dr Bruce Griffiths

Brooke Clarke wrote:
 Hi Mike:

 Back in the 1800s clock makers found ways to temperature compensate the 
 pendulum such as putting a Mercury thermometer at the bottom, using metals 
 with 
 dissimilar expansion coefficients (Harrison used steel and bronze (no zinc 
 then)) or materials with almost zero COE like Invar.

 The Dent clock at Greenwich in 1885 had an arenoid type compensator to remove 
 barometric pressure effects, later clocks were run in vacuum.

 Have Fun,

 Brooke Clarke
 http://www.PRC68.com
 http://www.precisionclock.com
   
Brooke

Invar and super Invar sound OK except that they are notoriously unstable 
with the dimensions changing slowly over time even at constant temperature.

Bruce

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Re: [time-nuts] Pendulums Atomic Clocks Gravity

2007-05-26 Thread Dr Bruce Griffiths


Tom Van Baak wrote:

Depends on what you mean by real clocks. The best pendulum
clocks, made in the early 1900's, solved almost all the normal
sources of error and instability. That left gravitational tides as
the one of the few remaining sources of error, down well below
the 1 ppm level. I say error in quotes because if you call them
gravimeters instead of clocks, they we're just doing their job
and did it well. These were real clocks; most of the pendulum
clocks, vintage or modern, that you see are toys.

Specifically, these used aged invar rods, at very low amplitude,
running in partial vacuum inside brass chambers. That helped
reduce buoyancy, humidity, and barometric pressure issues.
They were also either well temperature compensated and were
operated deep in constant-temperature basements.

Some modern attempts at world-class pendulum clocks have
tried fused quartz instead of invar to avoid the reputation that
fresh invar has for long-term instability. A great example is:
http://www.precisionclocks.com/
You should know Bill had hp cesium clocks in his home clock
collection long before I did.

Those of you really interested in the history, art, and science
of pendulum clocks should see the following six books:

Accurate Clock Pendulums by Robert J. Matthys
Precision Pendulum Clocks, A Trilogy of Books by Derek Roberts
My Own Right Time, by Philip Woodward
The Science of Clocks  Watches, by Arthur L. Rawlings

/tvb
http://www.LeapSecond.com
  

Tom

Even fused silica is unstable (see attachment).
Single crystal materials should be significantly better.
Ageing Invar doesn't do much for its dimensional instability.

Bruce
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Re: [time-nuts] Pendulums Atomic Clocks Gravity

2007-05-26 Thread Dr Bruce Griffiths

Tom Van Baak wrote:
Even fused silica is unstable (see attachment).
Single crystal materials should be significantly better.
Ageing Invar doesn't do much for its dimensional instability.

Bruce

Tom
Nice plot. Thanks Bruce. Where'd you find it? Someday
I want to visit your library! You are just amazing.

I scanned it from a text on Opto-Mechanical design.
Original data taken from Berthod, J.W., Jacobs, S.F., and Norton M.A.,
Dimensional stability of fused silica, Invar and several ultralow
thermal expansion materials,
Appl. Opt. 15, 1898, 1976.

A more comprehensive study with greater sensitivity using the material
under test as spacers in Fabry Perot resonators:
Dimensional stability of Materials Useful in Optical Engineering,
S.F Jacobs Applied Optics and Optical Engineering Vol X pp71-107.
Edited by Shannon and Wyant. Academic Press, 1987, ISBN 0-12-408610-1
This study also examines thermal expansivity gradients within a sample.
Yes, I presume everything is unstable, depending on how
close you look, or how long you watch. This is true for
quartz crystals, pendulum rods, rubidium vapor cells, or
hydrogen masers. The art of making high-end, low-drift
frequency standards is to create (through sound engineering),
or to batch select (through dumb luck), those ingredients
with the least instability. Try to order a hydrogen maser or
a BVA oscillator and you'll see what I mean.

I have heard, but can't provide reference, that some of the
US or UK invar made in the early 1900's (think Shortt), or
the Russian invar made in the 1950's (think Fedchenko) is
far superior to the commercial invar made today. Makes me
wonder if it's like famous violins: they don't (or can't) make
'em like they used to.

Modern super Invar is quite a complex alloy of Iron, Nickel, Cobalt,
Carbon, Silicon and Manganese and these are just the intentional
constituents.
LR35 invar is principally 35% Nickel with 65% iron.
Less complex alloys with lower impurity content may be more stable.

It shouldn't be too difficult to repeat the Fabry Perot resonator tests
using ancient invar samples if you can obtain them.
Back to the plot. Unlike the electronic frequency standards
that we time-nuts play with, the timescale real men use for
pendulum clocks is years, not days. Too bad the plot doesn't
show how super invar, zerodur, and fused silica do over N
years instead of N days. Do you know if zerodur is available
in long rods (as in pendulums), or just blocks (telescopes)?

I guess that DARPA didn't want to fund a study of dimensional
instability that might span several decades.
Zerodur is available in rod form (4m length) from Schott:
http://www.us.schott.com/optics_devices/english/products/zerodur/index.html?highlighted_text=zerodur
You can even order it online. However it is relatively expensive as is
most optical quality glass in these days of Lead, Arsenic, and Thorium
free varieties.
However It comes in several varieties some of which are more stable than
others.
It is best at constant temperature or at least stay below 130C for the
standard variety.
It makes nice ring laser gyros - widely used, at least before the advent
of fibre ring laser gyros.
I know zerodur was mentioned by some of the pendulum
guys at the latest NAWCC pendulum clock conference. On
the other hand, the best modern pendulum clock to date
was made by Hall, and he used a vintage invar rod, I think.

/tvb

Bruce
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Re: [time-nuts] New Trimble timing products

2007-05-21 Thread Dr Bruce Griffiths

Didier Juges wrote:
 Sorry, it's not 15nS rms, it's 15nS at 1 sigma.

 Didier KO4BB
   
Didier

Surely the standard deviation (1 sigma) and the rms values are identical?
Specifying 1 sigma is perhaps intended to signify that the timing error 
is stochastic.

Bruce


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Re: [time-nuts] New Trimble timing products

2007-05-21 Thread Dr Bruce Griffiths

Didier Juges wrote:
 Dr Bruce Griffiths wrote:
   
 Didier Juges wrote:
   
 
 Sorry, it's not 15nS rms, it's 15nS at 1 sigma.

 Didier KO4BB
   
 
   
 Didier

 Surely the standard deviation (1 sigma) and the rms values are identical?
 Specifying 1 sigma is perhaps intended to signify that the timing error 
 is stochastic.

 Bruce
   
 
 Bruce,

 Not knowing how it is measured and the nature of the noise, I realized I 
 had *assumed* rms and 1 sigma to be the same, but in fact I was not sure.
 The data sheet does say at 1 sigma, so I wanted to be accurate and not 
 make assumptions, this is time-nuts after all :-)

 Let's be honest, if I had not corrected myself, you would probably have 
 commented, and rightfully so, that the data sheet actually said at 1 
 sigma :-)

 I am trying to learn, I am just a little slow...

 Didier
   
Didier

Oops, if however the error has a non zero mean then the rms and 1 sigma 
values are not identical.
Such a systematic offset can arise from antenna, receiver and cable delay

Bruce


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Re: [time-nuts] Metastability?

2007-05-20 Thread Dr Bruce Griffiths

Hal Murray wrote:
 You need to have a two stage register, allowing one clock period for
 the first stage to come out of metastability.  This of course delays
 the signal to be synchronized by a clock period.
 

 Yup.  The delay is unavoidable.  The only thing you can do is trade off delay 
 vs MTBF.


   
 In an attempt to get around this delay, you sometimes see a series of
 registers in cascade clocked at slightly different times in an attempt
 to solve metastability w/o giving up a clock period.  This is unlikely
 to work well.  You need one long settling period, not a bunch of short
 ones.
 

 That's an example of the sort of bogus kludge I mentioned.

 Consider a chain of 3 FFs where the clock for the middle one is in between 
 the other two clocks.  Compare that to the same setup without the middle FF.

 In the first case, you have clock-out, setup, clock-out, and setup that gets 
 subtracted off from the settling time.  In the second case, you have 
 clock-out and setup that gets subtracted.  The extra setup/clock-out from the 
 middle FF is reducing the settling time.  Settling time is an exponential.  
 It's almost always wrong put anything in that path.

 It's not the number of FFs, it's the settling time that's important, or sum 
 of settling times.

   
Hal

Except that in synchronous systems where the the clock frequency is 
close to the worst case limit of the technology employed, it isn't 
always convenient or practical to wait longer than 1 clock period for 
the second flipflop to settle. In this case cascading chain of flipflops 
can be useful to reduce the probability of metastability at the output.
It would be better to use a slower synchroniser clock produced by 
dividing down the system clock for the synchroniser, but this may unduly 
constrain the maximum clock frequency when the delay between system 
clock transitions and the divided down clock transitions is considered, 
unless of course the divided down clock transitions are aligned with the 
system clock transitions.

With low frequency clocks (eg sampling/clocking with the leading edge of 
a PPS pulse) using a delay before sampling the output of the flipflop 
can be convenient in that it can be considerably shorter than the clock 
period whilst maintaining an acceptable MTBF.

If one connects the asynchronous signal to the inputs of a pair of 
synchronisers one of which is clocked by the rising edge of a clock and 
and the other by the falling edge of the same clock clock (~50% duty 
cycle), then one synchroniser will meet it setup and hold times 
(provided the clock frequency isn't too high) whilst the other may not. 
If the position of the asynchronous signal transition within the clock 
cycle were known then it would be possible to select the output from the 
synchroniser for which the input flipflop setup and hold times are met.  
Measuring the position of the asynchronous signal transition within the 
clock cycle introduces its own problems and the added complexity and 
cost isn't warranted except when one needs to timestamp the asynchronous 
signal transition with a resolution better than 1 clock cycle.

When using the traditional set of equations to calculate the MTBF of a 
synchroniser one has to be careful that the assumptions made in deriving 
these equations are valid for the particular case of interest.
An example of a synchroniser where these assumptions are violated is the 
case where a feedback loop is employed to lock the input signal 
transition so that  the output of the synchroniser has equal probability 
of being 1 or 0 when sampling this transition. In this case instead of 
having a uniform probability distribution of the location of the input 
signal transition within clock cycle, the location of such transitions 
has a narrow distribution about the sampling clock active transition. 
The width of the distribution being determined by the signal (or 
clock) jitter.

An example of this is when a D flipflop is used to lock an OCXO to the 
sawtooth corrected leading edge of the PPS pulse from a timing receiver.
The jitter on the sawtooth corrected PPS transition may then only be a 
few nanoseconds rms constraining that the PPS transition has a high 
probability of always being within a few nanoseconds of the OCXO derived 
clock transition. Thus although the sampling rate is very low it is 
essential to use a fast flipflop and/or wait long enough before sampling 
its output to achieve an adequately low synchroniser failure rate.

Bruce


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Re: [time-nuts] Z3801A with other GPS receiver

Jason Rabel wrote:
 I thought you had to use a VP in 6 channel mode for it to work on the
 Z3801A?

 Jason 

   
 If it uses the Motorola propietary commands, a M12 should be quite 
 compatible. I think a have somewhere some older documentation about the 
 @@ commands used in the 8-channel GPSs, but I think that they are quite 
 the same for all Motorola GPSs.

 Regards,
 Javier, EA1CRB
 
Jason

If one reads the M12 user manual, it states that there were some changes 
in the commands and messages from those used by older receivers.
All the required data is available perhaps in a different message.
Thus as Tom indicated a processor would be needed to translate between 
the two different dialects.

Bruce

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Re: [time-nuts] Trimble's Mini-T

michael taylor wrote:
 I was wondering if anyone knows any details, or has evaluated the
 Trimble Mini-T, a cost effective GPSDO in a small board form factor.

 http://www.trimble.com/minit.shtml
 http://trl.trimble.com/dscgi/ds.py/Get/File-361589/022542-007_Mini-T_DS_0207_lr.pdf

 The datasheet quotes: 1 PPS Accuracy. . GPS 15 nanoseconds (one
 sigma, without SA)

 There is a whitepaper from Trimble which I believe describes the
 Mini-T's design as a Third-Generation GPS Clock at
 http://trl.trimble.com/docushare/dsweb/Get/Document-8439/ (In Sync
 with GPS: GPS Clocks for the Wireless Infrastructure).

 If anyone knows the cost of board and/or starter kit, I wonder
 interested in knowing.

 Thanks,
 Michael

   
Michael

The datasheet is distinguished by its lack of information on the 
stability of the reference when locked to the GPS signals.
Either its so poor that its embarrassing, or they just haven't got 
around to measuring ADEV etc.
The phase noise figures quoted re only useful for estimating ADEV etc 
for (tau  0.1 sec) when this is largely determined by the OCXO itself.

Bruce

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Re: [time-nuts] Z3801A with other GPS receiver

Didier Juges wrote:
 That would be fine if I were dealing with a Z3801, but at the moment, I 
 am looking at that Z3801 main board someone has been trying to sell on 
 eBay for the best part of a year and I was wondering if something could 
 be done with it. It has no GPS and no OCXO.

 I have a spare 10811 and lots of GPS receivers (4 different types at 
 last count, excluding the Thunderbolt), but no Oncore or M12.

 I have several uC dev boards for my favorite chips, and some have dual 
 serial ports, so a converter would be quite feasible (assuming the 
 system software can deal with the delay in translating the command, 
 resending the command, getting the response, translating the response 
 and resending the response.)

 I am not sure I want to do that for one piece though, I simply can't 
 justify the time. If there was a market however, it would be different.

 Didier KO4BB

   
Didier

It would probably be more productive/profitable to develop one of the 
inexpensive high resolution GPS disciplining techniques recently discussed.
performance is likely to be better and could be used to discipline most 
commonly available OCXOs using any GPS receiver that has sawtooth 
correction data available.

Bruce

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Re: [time-nuts] Z3801A with other GPS receiver

Didier
Didier Juges wrote:
 Bruce,

 Not knowing exactly what that entails, in spite of the volume of useful 
 information you and others have dispensed on this list on that subject, 
 but always the hopeful engineer that I am :-), I wholeheartedly agree 
 with you.

 Another approach I am interested in pursuing is the Thunderbolt 
 approach, where the 10 MHz is used (directly or via PLL or multiplier) 
 as the processor clock. That eliminates the sawtooth issue entirely, but 
 would limit the GPS engine to one that can be operated that way (with 
 the right clock frequency).

   
If the GPS receiver uses the OCXO as its local oscillator reference, 
then this is what the carrier phase (with code phase assistance) 
disciplining technique does.
No additional phase detector, no sawtooth, only a DAC or a DDS is 
required to adjust the OCXO frequency.
Using older (well aged) OCXOs that have drifted so much (0.5-1ppm or so) 
that they cannot be adjusted back to their nominal frequency is also 
possible.
In effect a  small additional doppler shift from the frequency offset 
is of little consequence.
The new Trimble GPSDOCXO probably incorporates some elements of this 
scheme, however the data sheet specs give no frequency stability data.
 Either way, it sounds more fun than a serial converter.

 However, it would be a fairly long term project for me, and for the 
 foreseeable future, I probably won't be able to dedicate enough time to 
 get such an ambitious project going.

 Oh well, there is always retirement...

 Didier

   

Bruce

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Re: [time-nuts] antenna length

2007-05-17 Thread Dr Bruce Griffiths

jmfranke wrote:
 Nope.

 John  WA4WDL

 - Original Message - 
 From: Howard W. Ashcraft [EMAIL PROTECTED]
 To: time-nuts@febo.com
 Sent: Thursday, May 17, 2007 5:44 PM
 Subject: [time-nuts] antenna length

 Simple question.

 I have a stock trimble thunderbolt that I am currently running with a 
 generic active gps antenna.  I know that you should offset for the time 
 delay of your antenna feed line.  However, it would think that the timing 
 offset is important for determining the actual time, but not necessary if 
 you are only wanting a stable 10 mhz output.  Is there a consideration 
 that I am overlooking?

 HOWARD W. ASHCRAFT, Jr.
 Direct Dial: (415) 995-5073
 [EMAIL PROTECTED]
 HANSON 425 Market Street, 26th Floor
 BRIDGETT San Francisco, CA 94105-2173
 MARCUS  Direct: (415) 995-5073
 VLAHOS Main: (415) 777-3200
 RUDY, LLP Fax: (415) 995-3460

Not quite correct.
If the antenna cable is long enough the diurnal variations in its delay 
will be noticeable.

However with a Thunderbolt the cable will need to be kilometers in 
length for this to become significant.
The diurnal variation in the delay of the various amplifiers required 
with such cable lengths is even more significant.
With short cable lengths the diurnal variation of the antenna and/or 
receiver delay is more significant.

With a more accurate timing receiver and/or wider diurnal temperature 
swings the effect may be noticeable with shorter cable lengths.

With GPS carrier phase measurements the diurnal delay variation of a 
cable as short as 20m should make a good thermometer.
However the antenna and/or receiver delay will be more significant.

Bruce

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[time-nuts] Low cost high resolution software sawtooth error correction

2007-05-17 Thread Dr Bruce Griffiths

Software correction of the sawtooth timing error of a GPS timing 
receiver can be used to discipline an OCXO at a similar parts cost and 
performance to the hardware sawtooth correction method.
The OCXO sinewave output is sampled by the leading edge of the PPS 
signal and corrected for the sawtooth error in software. The LTC1412 is 
a suitable ADC (~$US12 (1-99) from Linear technology).
The ADC output is 12 bit parallel (for those who want a serial output 
just add a couple of parallel input serial output shift registers) and 
it is best to use a differential input signal (use an RF transformer).
The input sinewave amplitude only has to be known to within a few (5%) 
percent to keep the effective sawtooth correction error due to the phase 
detector gain uncertainty under 1ns.
In principle the ADC can be used to measure the amplitude of its input 
sinewave, such calibration conversions being interleaved between 
successive PPS pulses.
If the OCXO has a wider EFC range than 1E-7 for a 10MHz OCXO then the 
frequency can be divided down to say 1MHz and low pass filtered before 
being used as the analog input to the ADC. The phase detector resolution 
is still less than 1ns.

Alternatively if one has an older OCXO which has drifted so that it can 
no longer be adjusted to its nominal frequency, then using the OCXO 
output frequency as the ADC input frequency can be useful in that the 
OCXO can then be locked to a multiple of 1Hz. Such a OCXO frequency is 
still very useful, however you need to know which multiple of 1Hz the 
OCXO has locked to. Once the OCXO has locked  it is easy to measure the 
frequency using either an external counter or one built into the 
GPSDOCXO control circuitry.

If one wants to produce an exact 10MHz output when the OCXO has locked 
to a different multiple of 1Hz, then an offset generator using a DDS can 
be employed.

The hardware sawtooth can also be used to lock an OCXO to a multiple of 
1Hz if the frequency of the D flipflop input is equal to the OCXO frequency.

Bruce

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Re: [time-nuts] Low cost high resolution software sawtooth error correction

2007-05-17 Thread Dr Bruce Griffiths

A small correction/clarification to the paragraph on the effect phase 
detector gain error.

The input sinewave amplitude only has to be known to within a few (5%) 
percent to keep the effective sawtooth correction error due to the phase 
detector gain uncertainty under 1ns when using an M12+T or M12M GPS timing 
receiver.In principle the ADC can be used to measure the amplitude of its 
input sinewave, such calibration conversions being interleaved between 
successive PPS pulses.

Bruce


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Re: [time-nuts] NTP problem on Windows

2007-05-16 Thread Dr Bruce Griffiths

Joseph Gray wrote:
 I am running the Meinberg NTP software on two PCs. Both PCs are running 
 WinXP w/SP2, both are on the same network and both are syncing to servers at 
 pool.ntp.org. In the past, both clocks have shown that the two PCs had the 
 same time. Today, I just noticed that one of the PCs is running about 9 
 seconds fast, compared to my Casio WWVB watch.

 As far as I know, nothing has changed to account for the difference. The PC 
 that is fast has been running without a reboot for three months. Does anyone 
 have any ideas?


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Joseph

Are both machines syncing to the same ntp erver?
One or both of them of them hasn't synced to 127.127.1.0 by any chance?

Bruce

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Re: [time-nuts] NTP problem on Windows

2007-05-16 Thread Dr Bruce Griffiths

Joseph Gray wrote:
 Are both machines syncing to the same ntp erver?
 One or both of them of them hasn't synced to 127.127.1.0 by any chance?

 Bruce
 

 Although they are both using the pool at ntp.org, they are currently syncing 
 to different servers. They both are syncing to stratum 2 servers. Neither is 
 syncing to 127.127.1.0.


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Joseph

What are the actual IP addresses of the servers they are syncing to?

Bruce

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Re: [time-nuts] NTP problem on Windows

2007-05-16 Thread Dr Bruce Griffiths

Tim Shoppa wrote:
 Joseph Gray [EMAIL PROTECTED] wrote:
   
 What are the actual IP addresses of the servers they are syncing to?

 Bruce
   
 The one with the correct time:
 Sync to: 64.5.1.130 Offset: 38.346ms Stratum: 3

 The one with the wrong time:
 Sync to: 24.123.66.139 Offset: -1.074ms Stratum: 3
 

 At my QTH both of those servers are Stratum 2 and within a few hundredths
 of a second of the Right Time.

   
Same here some 10,000+ km away

Bruce
 Odd that you see them as Stratum 3, maybe you've got a firewall pulling
 tricks on you :-).

 The best way to configure a NTP client is with multiple (preferably
 3 or 4) servers, ideally nearby network-wise and diverse time-source
 wise. It's pretty sad how almost all stratum 1's are locked to GPS
 these days. If your NTP software doesn't support multiple servers,
 it is REALLY REALLY a good idea to move to something that does...
 hint: check out http://www.ntp.org/

 Tim.

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Re: [time-nuts] Software Sawtooth correction prerequisites?

Tom Van Baak wrote:
 Define cheap.
 You can already get essentially single chip TICs with a resolution (and 
 accuracy) better than 100ps for around 100 Euros or so.
 

 Has anyone in the group tried one of these? I would very
 much like to see the results.
   

All except Xavier seem to have shied away from obtaining these on cost 
grounds and the need to layout a 4 layer PCB.
Although the vendor does offer an evaluation system (External box plus 
card plugs into PC with fat multiconductor SCSI type (but not SCSI 
signalling)cable connecting the two), too expensive for general use but 
perhaps useful for performance evaluation.
The above price was for an earlier version the later reduced cost higher 
resolution version (range 5 nanosec - 4millisec) should be cheaper.
The range can easily be extended to years if required (using CPLD 
counters (or even a PIC with built in counters - eg PIC18F4550) + 
software+ 74AC164).
 However the optimal solution doesn't use a TIC at all, just use a good 
 GPS receiver that makes the carrier phase observables available.
 Quite a few of the older receivers used to make the carrier phase data 
 available.
 

 Many of the Oncore VP's did this, but I don't know of
 anyone, amateur or commercial, that built a GPSDO
 using that feature. That makes me wonder if carrier
 phase observables alone is not enough.
   
You also need code phase measurements as a sanity check, to determine 
the ionospheric delay, and to initialise the control loop.
To obtain maximum performance you also need to know the GPS antenna 
location accurately.
This may take several days to establish using code phase SV transit data.
 The catch is that the GPS receiver local oscillator must be phase locked 
 to the OCXO.
 Some receivers use a 10MHz crystal oscillator in which case this can be 
 removed and replaced with an external 10MHz signal derived from the OCXO 
 being disciplined.
 

 Right, this is the key. Do you know any OEM receivers that
 allow an external 5/10/20 MHz? I know my Z12T does (but that
 is far from an OEM receiver).

   
The Novatel SuperstarII receivers use an on board Rakon 10MHz TCXO (made 
a little (120km) to the North of me) local oscillator which can be 
disconnected with relatively little surgery and replaced with a piece of 
thin coax and a connector. However the required amplitude is relatively 
small - easily fixed with a pair of resistors - typically the output 
from the onboard TCXO itself has to be attenuated.
Magnus acquired some of these cheaply, however even the new price isn't 
too steep. UNSW has used these receivers in geodetic survey/monitoring 
applications. The code phase field data from some of these exhibits 
encouraging stability (about 5 -10x better than the oscillator specs) 
when averaged over a few seconds even with the standard TCXO.

If you want to roll your own GPS receiver the MITEL/ZARLINK chipsets use 
a 10MHz reference.
 Unfortunately there are as yet no relatively inexpensive off the shelf 
 implementations of the GPS carrier phase discipling technique available.
 The calculations involved for maximum performance are somewhat complex, 
 however not too much computing horsepower should be required.
 

 The QL carrier phase GPSDO is unique and probably not
 cost-effective. Sounds like it's a custom single-channel GPS
 receiver designed from the ground up. If there were an easier
 way surely someone would have done it in the past ten years.

   
Yes $30,000 Euros or so is a little steep.
Depends what you mean by easy.
Vested interest in an existing receiver can lead to inertia.
The other players seem wedded to using PPS disciplining, possibly 
because of all the existing equipment using it.
Investigations into using multichannel carrier phase disciplining have 
been somewhat sporadic.
Although single channel receivers employing carrier phase measurement 
have been successfully deployed in geodetic arrays for monitoring 
applications.
 Magnus hopes to remedy this lack of suitable software and hardware 
 sometime in the future.
 

 That would be very nice. Will it be L1 only or L1/L2?
   
Only L1 as that's all the Superstar receivers provide.
However combining carrier and code phase measurements allows correction 
for the ionospheric delay.
 /tvb
   
Bruce



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Re: [time-nuts] Software Sawtooth correction prerequisites?

Tom Clark, K3IO wrote:
 Bruce Griffiths wrote:

   
 The Dallas delay lines aren't all that accurate, you need to calibrate
 them to acheive 1ns accuracy (read the specs) and then you have to
 worry about temperature variations.
 To use them you need to decode the sawtooth correction message from
 the GPS timing receiver.
 If you've decoded this message then you have all the information
 needed to make a software correction to the measured phase error.
 
 I need to correct some impressions that seem to have gone astray. To
 help me, I refer you to a PowerPoint presentation that I gave to the
 technicians and operators at the world's VLBI (Very Long Baseline
 Interferometry) sites. The presentation is available at
 http://gpstime.com as the 2007 version of  Timing for VLBI.

 [Aside -- If you are interested in learning about some of VLBI's
 buzz-words, I also gave a tutorial What's all this VLBI stuff, anyway?
 that was intended as a view of the Physics and Radio Astronomy of making
 VLBI measurements. Some people find my de-mystifying of Heisenberg's
 Uncertainty Principle interesting -- especially the Schroedinger quotes
 at #21. This plays best if you view it as a PPT presentation.]

 Starting on Slide #20, I describe the reason that the Motorola receivers
 have the sawtooth dither. Basically clock edges of the receiver's 1PPS
 pulse are locked to a crystal oscillator in the receiver and that
 oscillator is on a frequency that is not neatly commensurate with the
 true second marks. As has been pointed out in these discussions,
 Motorola reports an estimate of the error on the NEXT 1PPS tick. Slides
 21 and 22 show some of the pathological example we have seen on typical
 receivers. AFAIK, all the bizarre behavior has been traced to firmware
 problems.

 The reason for making sawtooth corrections (and not simply averaging
 multiple samples) can be seen in the hanging bridges (22:34 to 22:36
 on #22, 01:04:30 to 01:05:30 on #23) when the 1PPS signal went thru a
 zero-beat. For these 1-2 minute windows, all statistical averaging
 breaks down and typical GPSDO's perform badly. However, when the
 sawtooth is corrected in software (blue line on #23) the resulting
 paper clock is well behaved (at ~1.5 nsec RMS level).

 Slides #24  #25 describe an annoying problem in VLBI -- we want to be
 able to blindly trust ANY 1PPS pulse whenever (rarely) we need to reset
 the working VLBI clock. Slide #26 is the block diagram of the circuit
 that Rick has implemented in his newest clock. Slide #29 shows a (more
 noisy than normal) comparison between the hardware ans software
 correction performance with only 0.3 nsec RMS noise between the two.

 Bruce noted a misconception that may have come from our earlier
 implementation of the correction algorithm. What we found was that EVERY
 sample of the 1 nsec step Dallas/Maxim delay line showed considerably
 more scatter.What we found, on closer examination, was that it seems
 that the DSI delay line chip defines one nsec about 10% differently
 than Motorola's one nsec. After correcting for this definition
 problem, as you see in #30, the hardware  and software correction are in
 agreement with an observed regression coefficient of 0.9962 (on this
 sample, which shows correlation coefficient  0.999) and good tracking
 between samples.

 Bruce also made some disparaging comments on the stability of the delay
 lone. I can say that we have not seen any stability problems at all.
 This is quite logical when you carefully reverse engineer the DSI chip
 based on its data sheets. The delay inside the chip is really an analog
 delay. The 8-bit number you sent to the chip programs a D/A converter to
 produce a (256 step) constant current source. When the input pulse is
 applied to the DSI delay line, the constant current charges an on-chip
 capacitor. When the resulting ramp matches the level defined by a
 comparator, the output is changed. The comparator level and capacitor
 value are temperature compensated by a second, fixed rate ramp. This is
 pretty much the same thing that you all have been described here.

   
I know exactly how these delay devices work, the problem is that using 
them in this way relies on a one time calibration of the device delays, 
it would be far better if delay calibration cycles could be interspersed 
between PPS transitions. This would technique would cope with any ageing 
or temperature drifts. The variable slope technique (see Dallas 
application note AN107) for setting the delays used in these devices 
means that the delay jitter increases faster with increasing delay than 
in the equivalent fixed slope variable threshold ramp timed delay 
technique. The DS1020 -15-datasheet specifies a 4ns max deviation from 
the programmed delay. There is no statement on the datasheet as to if 
this error is due to scale factor error, offset error or integral 
linearity error or differential linearity error. If one doesn't 
calibrate each individual chip how can

Re: [time-nuts] Software Sawtooth correction prerequisites?

Tom

Tom Clark, K3IO wrote:

 Why add the cost of a programmable delay line when the additional cost
 of correction is a few lines of code?
 They also don't remove the requirement for subnanosecond phase
 measurement resolution and accuracy.
 
 But the receiver itself has intrinsic noise at the nsec level. You are
 better off by averaging sawtooth corrected (either hardware or software)
 measurements to achieve sub-nsec precision; IMHO, sub-nsec individual
 measurements aren't needed. Surely you don't plan to tweak a GPSDO every
 second! A good xtal is much better than ANY GPS rcvr on times of 1-100 sec.
   
 Whilst an analog phase lock loop can have the necessary resolution
 they are somewhat impractical for the relatively long averaging times
 required when optimally disciplining a good OCXO.

 The computational load isnt that severe as you only make one phase
 measurement per second.

 One of the simplest ways of achieving subnanosecond phase measurement
 resolution is to feed a quadrature phase 10MHz sinewave into a pair of
 simultaneous sampling ADCs (MAXIM have suitable devices prices seem
 reasonable). The sinewaves are sampled at the leading edge of the GPS
 receiver PPS signal.
 The ADC outputs can then be used to determine where in the cycle the
 PPS edge occurred. This in effect is a subnanosecond resolution phase
 detector with a range of 100nsec. The range can easily be extended by
 using a small CPLD which incorporates a couple of synchronisers (one
 clocked by the positive slope transition of the 10MHz signal and the
 other clocked by the negative slope xero crossing transition of the
 10MHz signal) The output of both synchronisers samples the value of a
 synchronous counter which is clocked by the positive slope zero
 crossing of the 10MHz sinewave. Software then sorts out which latched
 count is most reliable (the synchroniser whose clock edge is furthest
 from the PPS transition). This sounds complex but it isnt, especially
 if you select the right PIC (or other micro) with built in counters
 (PIC18F4550?) that can be sampled by an external transition (output of
 a synchroniser). The counter need only be an 8 bits counter.
 
 This sure sounds like a more complicated measurement than is necessary
 to me. If you have a 10 MHz oscillator, simply feed it into the D
 input into a latch clocked by the de-sawtoothed GPS 1PPS. The output of
 the latch is a 0 or 1 depending on the precise phase of the oscillator.
 You want this latched 0/1 measurement to average to ½ over a long term
 (seconds). As the statistics deviate from a 50/50 split, you tweak the
 oscillator. The ~1 nsec of residual noise from the sawtooth corrected
 GPS rcvr acts a natural dither. No counters, no ramps, no big A/D
 converter -- it couldn't be simpler! And if the 10MHz (= 100 nsec phase
 ambiguity) is too fine for your oscillator, then divide it to 5 MHz
 (=200 nsec) or 1 MHz (= 1µsec). This should be good enough to pull in
 a xtal that is off by 1:10e6.
   
Very nice technique, much better to make use of the receiver noise if 
you can.
In this case hardware correction of the PPS error is of course essential.
In essence this technique implements a servo with a narrow proportional 
band of a few nanoseconds the width of the proportional band being 
determined by the corrected PPS signal noise characteristics.
Outside the proportional band the servo saturates but retains the sign 
of the phase error.
As the noise of the receiver increases so does the width of the 
proportional band.
How then does one then actually measure the receiver timing noise, if 
one wishes to detect when it deteriorates to a point where it is prudent 
to go into holdover mode?

Perhaps a chain of (3) flipflops whose D inputs are driven by the OCXO 
derived (10MHz, IMHz, etc) frequency and the clock inputs of which are 
driven by successively delayed (stable delay) versions of the PPS edge. 
For example the first flipflop is clocked by the PPS edge, the second 
fliflop is clocked by the PPS edge delayed by say T ns, and the third 
flipflop is clocked by PPS delayed by 2T ns.
Follow these flipflops by a set of synchronisers. Lock the OCXO so that 
the 2nd Flipflop has 50% probability of being either 1 or 0.  The 
probability of occurrence of say a logic 1 at the outputs of the other 
first and third flipflops can then be used to monitor the receiver 
timing noise level. Alternatively the D inputs to the flipflops could be 
successively delayeed by T ns whilst all flipflops are clocked by the 
PPS signal.

Surely it would be better to use a synchroniser and/or a flipflop/latch 
with extremely short regeneration time constant to ensure that the 
probability of metastable states is insignificant.
In this case subsequent stages of the synchroniser could be clocked by 
delayed (fixed non critical delay) versions of the PPS transition as 
waiting several seconds for a particular decision to propagate to the 
output of the synchroniser if each

Re: [time-nuts] Software Sawtooth correction prerequisites?

Lester

I have no idea you'll need to contact Acam direct.
http://www.acam.de

Bruce
Lester Veenstra M0YCM K1YCM wrote:
 What is the cost of the two channel pci system, if you happen to have the
 price in hand. If not, I will ask direct.

 Full Name:  Lester B Veenstra 
 Job Title:  Communication Sys Des Engr Sr Stf 
 Department: 6L01 Site Operations Collaboration  and Reach-Back (SOCAR) 
 Company:Integrated Systems  Solutions 

 Business Address:   

 Lockheed Martin ISS 
 PSC 45 Box 781
 APO AE 09468 

 Home Address Address:   

 Dawn Cottage 
 Norwood, Harrogate
 HG3, 1SD  UK 

 Telephones:  

 Office 940-6456

 Office +44-(0)1423-846-385

 Home:   +44-(0)1943-880-963  

 UK Cell  +44-(0)7716-298-224 

 US Cell  +1-240-425-7335

 Jamaica+1-876-352-7504


 -Original Message-
 From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On
 Behalf Of Dr Bruce Griffiths
 Sent: Saturday, May 12, 2007 7:00 AM
 To: Tom Van Baak; Discussion of precise time and frequency measurement
 Subject: Re: [time-nuts] Software Sawtooth correction prerequisites?

 Tom Van Baak wrote:
   
 Define cheap.
 You can already get essentially single chip TICs with a resolution (and 
 accuracy) better than 100ps for around 100 Euros or so.
 
   
 Has anyone in the group tried one of these? I would very
 much like to see the results.
   
 

 All except Xavier seem to have shied away from obtaining these on cost 
 grounds and the need to layout a 4 layer PCB.
 Although the vendor does offer an evaluation system (External box plus 
 card plugs into PC with fat multiconductor SCSI type (but not SCSI 
 signalling)cable connecting the two), too expensive for general use but 
 perhaps useful for performance evaluation.
 The above price was for an earlier version the later reduced cost higher 
 resolution version (range 5 nanosec - 4millisec) should be cheaper.
 The range can easily be extended to years if required (using CPLD 
 counters (or even a PIC with built in counters - eg PIC18F4550) + 
 software+ 74AC164).
   
 Bruce
   


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Re: [time-nuts] Software Sawtooth correction prerequisites?

Tom Clark, K3IO wrote:
 If you have a 10 MHz oscillator, simply feed it into the D
 input into a latch clocked by the de-sawtoothed GPS 1PPS. The output of
 the latch is a 0 or 1 depending on the precise phase of the oscillator.
 You want this latched 0/1 measurement to average to ½ over a long term
 (seconds). As the statistics deviate from a 50/50 split, you tweak the
 oscillator. The ~1 nsec of residual noise from the sawtooth corrected
 GPS rcvr acts a natural dither. No counters, no ramps, no big A/D
 converter -- it couldn't be simpler! And if the 10MHz (= 100 nsec phase
 ambiguity) is too fine for your oscillator, then divide it to 5 MHz
 (=200 nsec) or 1 MHz (= 1µsec). This should be good enough to pull in
 a xtal that is off by 1:10e6.
   
Tom

How does one do robust statistical filtering of outliers when one uses 
this technique??

Bruce
 I hope these comments helped a bit -- 73, Tom
   



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Re: [time-nuts] Software Sawtooth correction prerequisites?

Jim Miller wrote:
 My first post...newbie...be gentle...

 I spent the last several evenings reading the archives and saw mention of 
 sawtooth error correction in software. Since the corrections to be applied 
 are on the order of 1e-9 seconds it would seem that the phase detector 
 outputs to which these are applied must be similar in resolution.

 That would seem to require a pretty hefty phase detector and a pretty 
 substantial computing resource. Doesn't sound inexpensive. Is there a way 
 around this?

 OTOH, the Dallas Semi delay line pushes the computation out into the input 
 of the phase detector at the cost of a $17 chip (1k qty) which in small 
 quantities is likely $50 or so. This would seem to allow for a wider variety 
 of phase measurement techniques.

 Do I have this right?

 tnx

 jim miller
 ab3cv 


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Jim

DS1021-15 (SOIC package) price is about $31 (1 off) from the 
Maxim-Dallas on line shop

Bruce

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Re: [time-nuts] Software Sawtooth correction prerequisites?

The statement that Dallas' version of the nanosecond differs by 10% from 
Motorola's is somewhat disconcerting until one analyses how the delay 
generator works.

Simplified description

Aside from the contribution from internal logic propagation delays

Delay = Constant*RC,
Where R is the value of a resistor that determines the current used to 
charge a capacitor and the constant is determined by resistor ratios.


Thus a naive implementation may use 256 equal resistors (r) connected in 
series with a set of switches used to select the the required  
resistance value (Nr)  in 256 nominally equal steps.

The delay would then be proportional to N.
Unfortunately the ramp slope would vary over a range of 256 to 1 as 
would the current. The current mirror used in the actual circuit may 
have some dificulty in operating accurately over a current range of 
256:1. Also the power dissipation in some of the resistors in the string 
would vary over a large range. The large range (256:1) in the ramp slew 
rate seen by the comparator would lead to significant variations in the 
comparator delay. Fortunately if the effective value of the resistor 
corresponding to N=0 is made somewhat larger (=Ro) than r then although 
the N=0 delay will increased, the range of currents seen by the current 
mirror and the corresponding slew rates seen by the comparator can be 
reduced significantly improving the performance and reducing the 
variation in resistor dissipation. This implementation should be 
inherently monotonic despite variations in r and Ro. The effective RC 
product and the corresponding delay can be designed to have a low 
temperature coefficient. The RC product will vary from lot to lot and 
this variation can be compensated by resistor trimming. There are other 
schemes other than a series resistor string that can be used, however 
most of these are not inherently monotonic and resistor trimming to 
correct this error as well as the scale error may be necessary.


The attached plot of the error of a typical DS1020-15 illustrates that 
the integral non linearity of the delay may amount to several 
nanoseconds worst case.
This indicates that if one uses say 30ns of the range to correct for the 
sawtooth error of an M12M or equivalent GPS timing receiver, that a 
typical correction error due to the intergral non linearity of the 
DS1020-15 may be as large as 1ns. However this can be reduced 
significantly by calibration or perhaps by just calibrating the gain. 
However unless an actual calibration or parameter fitting to a more 
elaborate model for the INL other than just a change of scale factor the 
specified data sheet maximum value for the delay it is unlikely that a 
mere adjustment of the scale factor will ensure that the delay error of 
every DS1021-15 that meets its datasheet specification will be less than 
1 nanosecond. The optimum scale factor may also vary from wafer to wafer 
as well as within the wafer.


Thus whilst it is highly likely that calibrating the delay and using a 
lookup table or a model for the INL using several adjustable parameters 
will allow a programmed delay error of under 1ns, it is unlikely that 
merely adjusting the gain will reduce the programmed delay error to 
under 1ns for all DS1021-15s ever produced that meet the datasheet 
specifications.


More detailed
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Re: [time-nuts] Software Sawtooth correction prerequisites?

Tom Van Baak wrote:
 This sure sounds like a more complicated measurement than is necessary
 to me. If you have a 10 MHz oscillator, simply feed it into the D
 input into a latch clocked by the de-sawtoothed GPS 1PPS. The output of
 the latch is a 0 or 1 depending on the precise phase of the oscillator.
 You want this latched 0/1 measurement to average to ½ over a long term
 (seconds). As the statistics deviate from a 50/50 split, you tweak the
 oscillator. The ~1 nsec of residual noise from the sawtooth corrected
 GPS rcvr acts a natural dither. No counters, no ramps, no big A/D
 converter -- it couldn't be simpler! And if the 10MHz (= 100 nsec phase
 ambiguity) is too fine for your oscillator, then divide it to 5 MHz
 (=200 nsec) or 1 MHz (= 1µsec). This should be good enough to pull in
 a xtal that is off by 1:10e6.
 

 This sounds really simple and irresistible. Have you or Rick
 tried it out? I see instead of a TIC (Time Interval Counter)
 you have a TAC (Time Average Controller ;-)

 Not just GPS 1PPS noise but any oscillator noise (jitter), if
 large enough, is also a source of natural dither. Sounds like
 this design would be especially ideal for a low-end GPSDO;
 i.e., one that only needs to be accurate to 10^-9 or 10^-10.

 Did you envision that the OCXO EFC would be driven by a
 statistics-collecting microprocessor and a high-resolution
 DAC? Or is there some clever way to tie statistical results
 of the D-latch to the EFC and avoid the DAC too?

 /tvb 



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Tom

A D flipflop is a better choice than a transparent latch.

If the PPS signal also interrupts the micro, the built in interrupt 
synchroniser will ensure sufficient delay that when the output of the D 
flipflop is sampled the probability of its output being in a metastable 
state will be extremely low particularly if a 74AC74 or faster flipflop 
is employed.

Bruce

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Re: [time-nuts] Software Sawtooth correction prerequisites?

Jim Miller wrote:
 My first post...newbie...be gentle...

 I spent the last several evenings reading the archives and saw mention of 
 sawtooth error correction in software. Since the corrections to be applied 
 are on the order of 1e-9 seconds it would seem that the phase detector 
 outputs to which these are applied must be similar in resolution.

 That would seem to require a pretty hefty phase detector and a pretty 
 substantial computing resource. Doesn't sound inexpensive. Is there a way 
 around this?

 OTOH, the Dallas Semi delay line pushes the computation out into the input 
 of the phase detector at the cost of a $17 chip (1k qty) which in small 
 quantities is likely $50 or so. This would seem to allow for a wider variety 
 of phase measurement techniques.

 Do I have this right?

 tnx

 jim miller
 ab3cv 
   
Jim

Your conclusions are somewhat astray.



The Dallas delay lines aren't all that accurate, you need to calibrate 
them to acheive 1ns accuracy (read the specs) and then you have to worry 
about temperature variations.
To use them you need to decode the sawtooth correction message from the 
GPS timing receiver.
If you've decoded this message then you have all the information needed 
to make a software correction to the measured phase error.
Why add the cost of a programmable delay line when the additional cost 
of correction is a few lines of code?
They also don't remove the requirement for subnanosecond phase 
measurement resolution and accuracy.
Whilst an analog phase lock loop can have the necessary resolution they 
are somewhat impractical for the relatively long averaging times 
required when optimally disciplining a good OCXO.

The computational load isnt that severe as you only make one phase 
measurement per second.

One of the simplest ways of achieving subnanosecond phase measurement 
resolution is to feed a quadrature phase 10MHz sinewave into a pair of 
simultaneous sampling ADCs (MAXIM have suitable devices prices seem 
reasonable). The sinewaves are sampled at the leading edge of the GPS 
receiver PPS signal.
The ADC outputs can then be used to determine where in the cycle the PPS 
edge occurred. This in effect is a subnanosecond resolution phase 
detector with a range of 100nsec. The range can easily be extended by 
using a small CPLD which incorporates a couple of synchronisers (one 
clocked by the positive slope transition of the 10MHz signal and the 
other clocked by the negative slope xero crossing transition of the 
10MHz signal) The output of both synchronisers samples the value of a 
synchronous counter which is clocked by the positive slope zero crossing 
of the 10MHz sinewave. Software then sorts out which latched count is 
most reliable (the synchroniser whose clock edge is furthest from the 
PPS transition). This sounds complex but it isnt, especially if you 
select the right PIC (or other micro) with built in counters 
(PIC18F4550?) that can be sampled by an external transition (output of a 
synchroniser). The counter need only be an 8 bits counter.

Another technique is to start a ramp on the leading edge of the PPS 
signal from the GPS receiver and stop it at the corresponding output 
transition of a synchroniser (clocked at 10MHz) whose output samples an 
(8bit) counter (also clocked at 10MHz - your local OCXO standards 
frequency). The final value of the ramp is sampled by an ADC and 
combined with the sampled count to resolve the 1 count ambiguity at the 
synchroniser output. The ramp is then reset for the next PPS pulse. 
Calibration of the ramp generator is required but calibration cycles are 
easily interleaved between PPS pulses.
Although it may seem that a fast opamp is required for the ramp 
generator, this isnt so as you can wait for any opamp (and/or ADC input) 
to settle to before sampling the ramp output.
With careful design curvature correction isn't required (don't slavishly 
copy the Linear technology Application note, you can do better with 
less). The ramp generator needs a range of  300ns or greater with a  
10MHz synchroniser clock. A 10-12 bit ADC will provide subnanosecond 
resolution. The ADC need not be fast (10us per conversion is adequate), 
however a sigma delta ADC is unsuitable.

Synchronisers can easily be built from shift registers.



Bruce

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Re: [time-nuts] Software Sawtooth correction prerequisites?


Javier wrote:

Tom Van Baak escribió:
  

When someone finds a cheap single-shot 1 ns TIC-on-a-chip
please let me know.

  


www.acam.de

Not very expensive although not cheap. I've some samples... but not yet 
time to experiment with them.


Regards,

Javier, EA1CRB
  

Javier

You still need some additional hardware like a synchroniser (shift 
register).
However this is indeed about as close as you will get to a single chip 
solution.


For an analog style TAC see attached schematic.
The required level shifting has been omitted for clarity.
NB current mode logic is employed where either P1 or P2 collector 
current is equal to alpha times P3's collector current.

Similarly for N1, N2, N3.
During reset both N2 and P2 are ON.
Diodes D1 and D2 conduct equal currents.
The collector current of N3 is 2x the collector current of P3.
The START input turns off N2 so that P2 charges C1.
The STOP input turns off P2 leaving the ramp voltage corresponding to 
the time between the START and STOP transitions stored on C1.
The opamp is then takes a few microsec to settle at which point its 
output can be sampled by an ADC.
When START and STOP both go to zero the capacitor voltage ramps down 
until it is clamped at 0V by D1 and D2.



Bruce
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Re: [time-nuts] Software Sawtooth correction prerequisites?


Javier

Corrected Analog TAC schematic attached.

The number of extra chips required depends on if one uses a CPLD or SSI 
logic (eg 74HC/74AHC parts) and if your selected micro has a suitable 
internal ADC and or a counter that can be sampled by an external signal 
transition.


Bruce
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Re: [time-nuts] Software Sawtooth correction prerequisites?

Hal Murray wrote:
 Synchronisers can easily be built from shift registers.
 

 What do you mean by synchronizer?

 Are you talking about a delay so the times line up correctly or a 
 circuit to avoid metastability?


   
Hal

Usually just a fast shift register with the number of stages selected to 
achieve a suitably low rate of metastable states at the output.
Its usually easy to ensure that the failure rate is less than once in a 
few terayears.
The PPS signal will not be synchronous with the local OCXO due to noise 
and sawtooth error so that metastable states are possible when the PPS 
is connected to the D input of a flipflop clocked by the OCXO.

Bruce

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Re: [time-nuts] ? phase comparison or other device

2007-05-09 Thread Dr Bruce Griffiths

Bill Janssen wrote:
 I thought that someone was designing a circuit that could be used to compare
 two oscillators.

 What happened to that project?  I now have a HP 5370A so I have 
 something, but
 I would like to make simultaneous measurements on three or four precision
 clocks.I am not qualified to design a state of the art device, so I am 
 looking for others
 to do that.

 Thanks
 Bill K7NOM


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Bill

Ulrich and I have designed and Ulrich is currently testing a CPLD 
implementation of the improved version of the HP K34-5991A linear phase 
detector.
It includes programmable prescalers (1-256) so that frequency like 10MHz 
and 5MHz for example can be compared. The maximum input frequency is 
about 50MHz.
It has 2 quadrature phase outputs. The prescalers also allow the phase 
detector gain to be adjusted. The phase detector has a triangular wave 
characteristic with a period of 4 cycles of the input frequency to the 
phase detector (ie at the built in prescaler output).

Preliminary results using a very crude kitchen table breadboard 
indicate that instabilities of a few parts in 1E12 are easily seen 
within an hour or so.
Sensitivity is likely to be much better than this but a 10X prescaler 
was used on each 10MHz input.

Comparing 3 or 4 standards requires using a set of distribution 
amplifiers plus a set of linear phase comparators to achieve the desired 
configuration.
This is more flexible than trying to anticipate exactly how many 
channels a user may want, it also has less crosstalk than an 
implementation with more than 2 input frequencies to a single board or CPLD.

With external prescalers the maximum input frequency can be extended to 
100MHz or more.

Bruce

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Re: [time-nuts] Z3815A - what? -who? -where?

2007-05-07 Thread Dr Bruce Griffiths

Murray Greenman wrote:
 TFers,

 Further to Kit's post a week or two back, we've started to make some
 ground regarding understanding and using these excellent little GPSDO
 units. I have working DOS software, and they also work OK with SATSTAT.
 I have also sussed the GPS module comms and written a display
 application for that as well.

 I'm surprised that there have been no comments or expressions of
 interest in these units - are there really no other HP/Agilent Z3815A
 units anywhere else in the world?

 Many of these units have the HP E1938A 'hockey puck' oscillator. We'd
 really LOVE to find a manual and a schematic for these units, plus some
 setup info.

 If you twist my arm enough, I'll reveal where you can find photographs
 and info about these nice little units.

 73,
 Murray ZL1BPU

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Murray

I'd be interested in viewing some images.

Bruce

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Re: [time-nuts] 5087A Distribution Amplifier

2007-05-02 Thread Dr Bruce Griffiths

Brian Kirby wrote:
 Your a life saver.  Can you confirm the pass transistor part number and 
 the regulator IC, looks like the 723 ?

   
Brian

Regulator is a 723, Transistor Q1 is a 2N3054.

Bruce

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Re: [time-nuts] Fury Realhamradio listing

[EMAIL PROTECTED] wrote:
 In a message dated 4/29/2007 04:13:30 Pacific Daylight Time, 
 [EMAIL PROTECTED] writes:

 Indeed. Three-four transistors and a handfull of caps and
 resistors. The
 Z3801A uses the 10 MHz clock and thus require a x1000
 interpolation, which is
 easy enought to acheive. Look at the HP5335A service manual for
 further
 details. What you do is that you stretch the error-pulse (1-2
 cycles) by
 charging a cap with one current and discharging it with another,
 the output is
 then run into a comparator for the sake of gain. This stretched
 pulse is then
 measured with the coarse clock and voila!

 Hi Magnus,
  
 I respectfully disagree, if it was that easy to get 100ps _accuracy_ 
 and resolution, then the 53132A would have it and not 150ps I would 
 think.
  

 bye,
 Said
Said

Try studying a little history, its been possible to achieve 25 
picosecond accuracy and resolution for over 30 years.
Such resolution is routine in Nuclear instrumentation. State of the art 
nuclear instrumentation strives for subpicosecond resolution and accuracy.

The reason that the 53132A doesn't have resolution and accuracy better 
resolution than 150ps, is that a design choice was made to implement it 
all (counters plus interpolators) in a CMOS chip using the delay of a 
CMOS inverter to set the resolution. This reduces the cost and 
complexity significantly and allows faster cycling of the interpolator 
facilitating continuous operation with zero deadtime between 
measurements. The drawback is reduced resolution and the requirement for 
frequent calibration or the use of a delay lock loop to correct the for 
the CMOS inverter delay tempco.

Bruce

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Re: [time-nuts] retry: PRS10 has spurious frequencies

Henk ten Pierick wrote:
 On Apr 25, 2007, at 23:38, Dave Brown wrote:

   
 Henk
 Do any of the spurious signals show on the SA with a search antenna
 (located in your lab environment)connected instead of the PRS10?
 DaveB
 


 No, they are not. I can see spurious if and only if the PRS10 is  
 powered. When I open the PRS10 and search with a loop antenna, then I  
 see the whole spectrum up to 600MHz. Most of the power comes from the  
 board with the micro which runs at 10MHz. I expect that there is a  
 parasitic coupling of this micro 10MHz to the PRS10 output.  This can  
 explain why the spurious level increases with frequency to higher  
 than the spectrum analyzer noise level at say 500MHz. The micro slew  
 rate can explain why it decreases again into the noise above 700MHz.  
 The spurious is only there if the micro runs. It is not clear to me  
 why I can see this spurious and other PRS10 owners can not. May be a  
 different run or version of the PRS10. My PRS10 has serial 5099.

 Henk

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Henk

If indeed the micro is the source of the spurious frequencies that other 
PRS10's do not exhibit, then either you've got an unusually fast micro 
or there is something wrong/different in the micro supply decoupling 
and/or EMI filtering. The PCB layout could differ or different or even 
extra components may have been used in the other PRS10's.

Bruce

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Re: [time-nuts] Fury Realhamradio listing

[EMAIL PROTECTED] wrote:
  
 Also, the PRS10 Stanford Rubiudium would have better than 1ns 
 resolution for time-tagging. I think they actually do resolve better 
 than 1ns, but don't use it.
  
  
 bye,
 Said
Said

The interpolator circuit resolution in the PRS10 time tagging circuitry 
is about 200 picosec.

Bruce

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Re: [time-nuts] Fury Realhamradio listing

[EMAIL PROTECTED] wrote:
 Hi Bruce,
  
 never doubted that it was technically possible to get this type of  
 resolution/accuracy. I myself mentioned the 15 year old Wavecrest units 
 achieve  800 
 femtoseconds resolution, single shot.
  
 The point was
  
 A) that type of resolution is not needed in a TI unit where the intrinsic  pk 
 to pk noise on the TI intervall is 100ns (more than three orders of  
 magnitude above 100ps).
  
 B) that implementing it with that kind of resolution and getting a  
 meaningful accuracy (say 250ps 6-sigma accuracy) is not easy while at the 
 same  time 
 keeping the cost to Three-four transistors and a handfull of caps and  
 resistors. In mass production a handfull of caps and transistors/resistors 
 cost  less 
 than $0.20.
  
 Again if it was that easy and cheap, HP would have done it in their 5334A's  
 or even the 5335A for example which have 1 or 2ns resolution I  believe
  
 SRS would have given us 100ps resolution on their PRS10 time-stamping input  
 - what better place to do it than in a highly-accurate frequency  reference.
  
   
Said

Actually the interpolator in the PRS10 has 200 picosec resolution.
However they have not provide a means of accurate autocalibration of the 
interpolator offset and gain.

 The reason that the 53132A doesn't have resolution and accuracy better  
 resolution than 150ps, is that a design choice was made to implement it  
 all (counters plus interpolators) in a CMOS chip using the delay of a  
 CMOS inverter to set the resolution. This reduces the cost  and 
 complexity significantly and allows faster cycling of  the interpolator 
 

 Bingo. QED.
  
 People choose not to do 100ps resolution in their  products because of cost 
 and complexity, even in $3K products such as the  53132A - let alone in $750 
 products.
  
   
Not exactly the point, the entire counter complexity and PCB area was 
reduced by using a single chip for the counters etc., and it was easy to 
incorporate an interpolator with sufficient resolution for the target 
market. One doesn't usually add a synchroniser with more than the 
required resolution even if it only costs a few dollars, if a device 
with adequate resolution can be obtained at very little added cost when 
its incorporated within the counter chip itself. Having decided to 
implement the counter in a CMOS chip, the  jitter due to internal cross 
coupling and noise within the chip would have  made it difficult to 
achieve a usable resolution much better than the 150ps actually achieved 
even if a cheap high resolution external interpolator were used.
 C) I don't believe the Z3801A has 100ps single shot resolution and accuracy  
 (for resolution doesn't do anything without accuracy) until someone will  
 prove it to me. And even then it would be wasted resolution since the GPS 
 1PPS  
 source noise will totally swamp out any benefit a 100ps resolution would  
 give.
  
 On top of that, all GPSDO's do heavy averaging of this time intervall, with  
 a PRS10 typically doing 7 hours or more of averaging. 100ps per-second  
 resolution in that kind of averaging window is meaningless, since the OCXO  
 cannot 
 perform that well - it would require 4E-015 stability in a 7 hour window.  
 Not 
 possible without a high-end Cs/Rb/H source. Certainly not possible with  the 
 10811 that's inside a Z3801A.
  
 Still hoping someone knows the TI hardware used in the Z3801A's...
  
 bye,
 Said
   
Bruce

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Re: [time-nuts] Fury Realhamradio listing