Re: [time-nuts] Divider circuit for Rubidium Standard
Hi Rick, On Sat, 9 Jan 2016 14:45:43 -0800 "Richard (Rick) Karlquist"wrote: > This circuit is very similar to one that was championed by Tom > Faulker of HP/Agilent at the now closed Spokane site. Tom > measured the circuit at about -171 dBc/Hz. He was very knowledgeable > about this topic, so we can believe the number. Is this documented anywhere publicly? I would be very interested to read this. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Moin Bruce, On Sat, 9 Jan 2016 21:36:35 + (UTC) Bruce Griffithswrote: > Splitting the resistor in 2 and ac coupling the emitters together > reduces the effects of Vbe and/or base biasing mismatch allowing a more > symmetric output and/or operation at lower input signal levels.The inductor > reduces the high frequency variations in the total emitter current. It also > reduces the tail current noise at high frequencies. Thanks for the explanation! One additional question: Why is the bias voltage for the two transistors derived independently? In my naivite i would have used a single resistive devider, buffered it with a large enough C and then split that bias voltage off with a 3.3k resistor each. This would get rid off the bias mismatch. (though not of the mismatch of the transistors) Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
No, it was just word of mouth within the company. Somewhere I have a piece of notebook paper on which Tom drew the circuit. We did have internal forums where papers where presented, but this was never even published internally. As with all forums, a lot of stuff happens outside the official forums in the hallways, or over lunch, etc. Ya gotta network. There was probably a great sigh of relief when I retired, and wouldn't be annoying coworkers with endless questions any more. Tom's contribution wasn't the circuit per se. I used this same basic circuit at Zeta Labs 40 years ago. I ever remember the PNP transistors we used: the Fairchild 2N5771. Those were the days... Tom's contribution was pointing out the fact that it was better than the other circuits out there, and the fact that he gave a number. It has been a never ending battle to disabuse low information designers of line receivers, comparators, and other low performance solutions. If you want to do some reading, I vaguely remember that NIST published some papers on sine to square at UFFC or PTTI. Start with Fred Walls for your search. Also remember that this circuit, as good as it is, is a poor mans substitute for the multistage zero crossing detectors discussed on this forum many times. Rick On 1/10/2016 2:24 AM, Attila Kinali wrote: Hi Rick, On Sat, 9 Jan 2016 14:45:43 -0800 "Richard (Rick) Karlquist"wrote: This circuit is very similar to one that was championed by Tom Faulker of HP/Agilent at the now closed Spokane site. Tom measured the circuit at about -171 dBc/Hz. He was very knowledgeable about this topic, so we can believe the number. Is this documented anywhere publicly? I would be very interested to read this. Attila Kinali ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Anything like the pnp + diode circuit shown in HP application note 301-1? Bruce On Monday, 11 January 2016 8:00 AM, Richard (Rick) Karlquistwrote: No, it was just word of mouth within the company. Somewhere I have a piece of notebook paper on which Tom drew the circuit. We did have internal forums where papers where presented, but this was never even published internally. As with all forums, a lot of stuff happens outside the official forums in the hallways, or over lunch, etc. Ya gotta network. There was probably a great sigh of relief when I retired, and wouldn't be annoying coworkers with endless questions any more. Tom's contribution wasn't the circuit per se. I used this same basic circuit at Zeta Labs 40 years ago. I ever remember the PNP transistors we used: the Fairchild 2N5771. Those were the days... Tom's contribution was pointing out the fact that it was better than the other circuits out there, and the fact that he gave a number. It has been a never ending battle to disabuse low information designers of line receivers, comparators, and other low performance solutions. If you want to do some reading, I vaguely remember that NIST published some papers on sine to square at UFFC or PTTI. Start with Fred Walls for your search. Also remember that this circuit, as good as it is, is a poor mans substitute for the multistage zero crossing detectors discussed on this forum many times. Rick On 1/10/2016 2:24 AM, Attila Kinali wrote: > Hi Rick, > > On Sat, 9 Jan 2016 14:45:43 -0800 > "Richard (Rick) Karlquist" wrote: > >> This circuit is very similar to one that was championed by Tom >> Faulker of HP/Agilent at the now closed Spokane site. Tom >> measured the circuit at about -171 dBc/Hz. He was very knowledgeable >> about this topic, so we can believe the number. > > Is this documented anywhere publicly? I would be very interested > to read this. > > Attila Kinali > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Moin John, Yes, I know I am comming back to an "old" discussion, but I have questions that need to be answered! :-) On Wed, 06 May 2015 08:56:10 -0400 John Ackermann N8URwrote: > Wenzel has published the schematic of an excellent squaring circuit. I > don't have the URL for their version handy, but I used it (with a couple > of mods) in the TADD-2 and TADD-2 Mini designs. You can see the > schematic in the T2-Mini users guide at > http://www.tapr.org/~n8ur/T2_Mini_Manual.pdf. The manual says: ---schnipp--- The purpose of the input circuit is to convert the RF input signal into a low-jitter square wave that can drive the PIC clock input. The circuit is closely based on the one published by Wenzel at http://www.wenzel.com/documents/waveform.html, with modifications suggested by Bruce Griffiths and Ulrich Bangert. The revised circuit works with inputs as low as -20dBm. ---schnapp--- The modification I can see is that the "current source" part of the differential pair changed from being a single, shared resistor of 100R to an inductor of 100uH, then splits up into two resistors of 220R, which are bridged by a 100nF capacitor. The inductor results in a reactance between 62R (100kHz) and 12k (20MHz) for the input range. Can you shed a bit of light on why you did those modifications and what the intended effect is? Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Splitting the resistor in 2 and ac coupling the emitters together reduces the effects of Vbe and/or base biasing mismatch allowing a more symmetric output and/or operation at lower input signal levels.The inductor reduces the high frequency variations in the total emitter current. It also reduces the tail current noise at high frequencies. Bruce On Sunday, 10 January 2016 10:05 AM, Attila Kinaliwrote: Moin John, Yes, I know I am comming back to an "old" discussion, but I have questions that need to be answered! :-) On Wed, 06 May 2015 08:56:10 -0400 John Ackermann N8UR wrote: > Wenzel has published the schematic of an excellent squaring circuit. I > don't have the URL for their version handy, but I used it (with a couple > of mods) in the TADD-2 and TADD-2 Mini designs. You can see the > schematic in the T2-Mini users guide at > http://www.tapr.org/~n8ur/T2_Mini_Manual.pdf. The manual says: ---schnipp--- The purpose of the input circuit is to convert the RF input signal into a low-jitter square wave that can drive the PIC clock input. The circuit is closely based on the one published by Wenzel at http://www.wenzel.com/documents/waveform.html, with modifications suggested by Bruce Griffiths and Ulrich Bangert. The revised circuit works with inputs as low as -20dBm. ---schnapp--- The modification I can see is that the "current source" part of the differential pair changed from being a single, shared resistor of 100R to an inductor of 100uH, then splits up into two resistors of 220R, which are bridged by a 100nF capacitor. The inductor results in a reactance between 62R (100kHz) and 12k (20MHz) for the input range. Can you shed a bit of light on why you did those modifications and what the intended effect is? Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On 1/9/2016 12:44 PM, Attila Kinali wrote: The purpose of the input circuit is to convert the RF input signal into a low-jitter square wave that can drive the PIC clock input. The circuit is closely based on the one published by Wenzel at http://www.wenzel.com/documents/waveform.html, with modifications suggested by Bruce Griffiths and Ulrich Bangert. The revised circuit works with inputs as low as -20dBm. This circuit is very similar to one that was championed by Tom Faulker of HP/Agilent at the now closed Spokane site. Tom measured the circuit at about -171 dBc/Hz. He was very knowledgeable about this topic, so we can believe the number. This is good, because the cited Wenzel document would give me no confidence whatsoever if that was all I had to go on. It reads like it was written by some marketing guy (as opposed to R) who knows just enough to be dangerous. Other than the circuit in question, the rest of the document is full of unreliable information. Such as how line receivers make great sine wave to square wave converters. They are terribly noisy. IE, the document contains a kernel of truth. It also has no quantitative information about the circuit in question or any other ones discussed. It's disappointing to see this published by an otherwise excellent outfit like Wenzel. The modifications make sense IMHO. I suspect that the 2N3906's are good for two reasons: the low f-t reduces noise bandwidth and the high current gain reduces noise current. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Bob wrote: The simple answer is that a biased fast CMOS gate will do a better job ADEV wise than your signal sources will. Maybe or maybe not, at tau ~1 second. Trouble is, as tau gets larger, the gate performs *worse*. The switching threshold of all MOSFET logic devices varies all over the place with temperature and supply voltage as well as random drift. At tau 10 or 100 seconds, these effects become more and more pronounced and xDEV gets worse, even if you take pains to keep the circuitry out of drafts. Gates are not a good way to square sine waves if you care about stability at longer tau. Most of what has been said against comparators on this thread are indictments of mistakes made in applying them, NOT deficiencies of comparators per se. I don't have the time nor energy to go into it in any depth right now, but: Properly applied, comparators can work better than pretty much anything else when the job is squaring a 1 to 100 MHz sine wave. A few Do's and Do not's: Do use a comparator with split supplies for the input section, so you can use actual ground as the reference voltage. Do not use inputs biased to mid-supply. Most especially, do not use separate voltage dividers to bias the two inputs, because the divider noise is uncorrelated and adds. If you must use inputs biased to mid-supply, use one good, low-noise voltage reference (LM329 or LM399) to bias both inputs so the bias noise is low and is common-mode (make sure to keep the time constants equal at the two inputs). But just don't use inputs biased to mid-supply in the first place. Do use a comparator with properly-designed internal hysteresis of a few mV (e.g., LT1719). Do use a good, modern comparator (again, e.g., LT1719) that was designed since chip-level thermal flow analysis became standard practice, to avoid the mysterious drift, instabilities, and metastabilities that comparators from the bad old days (mid-'90s and earlier) were famous for. Do not rely on a comparator to work with inputs from mV to 10s of volts. You wouldn't expect that with a logic gate, why in the world would you expect it with a comparator? Adjust the input level with amplifiers or attenuators to the optimum value for the comparator you are using at the frequency you are operating. A 5 or 10Vp-p sine wave at 10MHz slews fast enough at zero-cross not to need bandwidth-limited clipping amplifiers (a la Dick and Collins). Those techniques were designed for squaring audio-frequency sine waves, such as the mixer output(s) of a single- or double-mixer system. If you feel the need, you can increase the zero-crossing slope of the input signal by starting with a larger input signal than is optimum for the comparator in use and using diode clamps to limit the peak amplitude. There are many other best practices, but the ones above are enough to avoid the major application mistakes and have a reasonable chance of designing something that works to a high standard. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi On May 23, 2015, at 12:37 AM, Charles Steinmetz csteinm...@yandex.com wrote: Bob wrote: The simple answer is that a biased fast CMOS gate will do a better job ADEV wise than your signal sources will. Maybe or maybe not, at tau ~1 second. Trouble is, as tau gets larger, the gate performs *worse*. The switching threshold of all MOSFET logic devices varies all over the place with temperature and supply voltage as well as random drift. At tau 10 or 100 seconds, these effects become more and more pronounced and xDEV gets worse, even if you take pains to keep the circuitry out of drafts. Gates are not a good way to square sine waves if you care about stability at longer tau. Yes indeed, if you have a clock that goes below 1x10^-15 at 1 second and drops linearly with tau from there, you will have issues. If you do not have such a clock. The gate probably will do just fine. The delta on the gate turns out to be a delta time (as in delta ns / ps / fs). As you go out in tau, the impact (parts in 10^whatever) of that time delta drops linearly with tau. So: what sort of clock (that you have) are you proposing to look at? Bob Most of what has been said against comparators on this thread are indictments of mistakes made in applying them, NOT deficiencies of comparators per se. I don't have the time nor energy to go into it in any depth right now, but: Properly applied, comparators can work better than pretty much anything else when the job is squaring a 1 to 100 MHz sine wave. A few Do's and Do not's: Do use a comparator with split supplies for the input section, so you can use actual ground as the reference voltage. Do not use inputs biased to mid-supply. Most especially, do not use separate voltage dividers to bias the two inputs, because the divider noise is uncorrelated and adds. If you must use inputs biased to mid-supply, use one good, low-noise voltage reference (LM329 or LM399) to bias both inputs so the bias noise is low and is common-mode (make sure to keep the time constants equal at the two inputs). But just don't use inputs biased to mid-supply in the first place. Do use a comparator with properly-designed internal hysteresis of a few mV (e.g., LT1719). Do use a good, modern comparator (again, e.g., LT1719) that was designed since chip-level thermal flow analysis became standard practice, to avoid the mysterious drift, instabilities, and metastabilities that comparators from the bad old days (mid-'90s and earlier) were famous for. Do not rely on a comparator to work with inputs from mV to 10s of volts. You wouldn't expect that with a logic gate, why in the world would you expect it with a comparator? Adjust the input level with amplifiers or attenuators to the optimum value for the comparator you are using at the frequency you are operating. A 5 or 10Vp-p sine wave at 10MHz slews fast enough at zero-cross not to need bandwidth-limited clipping amplifiers (a la Dick and Collins). Those techniques were designed for squaring audio-frequency sine waves, such as the mixer output(s) of a single- or double-mixer system. If you feel the need, you can increase the zero-crossing slope of the input signal by starting with a larger input signal than is optimum for the comparator in use and using diode clamps to limit the peak amplitude. There are many other best practices, but the ones above are enough to avoid the major application mistakes and have a reasonable chance of designing something that works to a high standard. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
I was the OP and the reason for the whole exercise is to take a Rubidium standard that only outputs 1pps and modify for use as 10MHz. With some research there is a 20Mhz source onboard, issue is the sine is not very clean at 20MHz (60MHZ as well, much cleaner and may be worth inputting straight to logic). Thus the need for a divider circuit to divide down to 10Mhz. The purpose is to create a bench standard for hobby use and a external 10MHz reference for a HP 53131A Pics of the waveforms (not my pics but my results are the same) http://1drv.ms/1HB0Nwn -=Bryan=- From: kb...@n1k.org Date: Fri, 22 May 2015 17:31:47 -0400 To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard Hi What is your objective? Put another way: 1) How clean is your sine wave source? 2) What frequency (or range) are you trying to convert? 3) What level range are you trying to work with? 4) What is it going into (how clean is the next stage)? If you have an optical fountain that is good to 1x10^-15 at 1 second, and you are trying to map Pluto with a radar in your back yard, the answer will be a bit different than if you are starting with a surplus OCXO and trying to drive a 5334 :) Bob On May 22, 2015, at 4:27 PM, xaos x...@darksmile.net wrote: After reading the posts on this subject I have a question. First, in my experience I used a rather simple circuit made from diodes used as limiters and a transistor feeding a logic inverter. No AGC. So here is my question. What is the proper circuit to use? I'd like to do a PSPICE and check things out followed by a prototype. I got that a comparator is out, etc. Cheers, George H. N2FGX On 04/26/2015 06:51 AM, Bryan _ wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
After reading the posts on this subject I have a question. First, in my experience I used a rather simple circuit made from diodes used as limiters and a transistor feeding a logic inverter. No AGC. So here is my question. What is the proper circuit to use? I'd like to do a PSPICE and check things out followed by a prototype. I got that a comparator is out, etc. Cheers, George H. N2FGX On 04/26/2015 06:51 AM, Bryan _ wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi What is your objective? Put another way: 1) How clean is your sine wave source? 2) What frequency (or range) are you trying to convert? 3) What level range are you trying to work with? 4) What is it going into (how clean is the next stage)? If you have an optical fountain that is good to 1x10^-15 at 1 second, and you are trying to map Pluto with a radar in your back yard, the answer will be a bit different than if you are starting with a surplus OCXO and trying to drive a 5334 :) Bob On May 22, 2015, at 4:27 PM, xaos x...@darksmile.net wrote: After reading the posts on this subject I have a question. First, in my experience I used a rather simple circuit made from diodes used as limiters and a transistor feeding a logic inverter. No AGC. So here is my question. What is the proper circuit to use? I'd like to do a PSPICE and check things out followed by a prototype. I got that a comparator is out, etc. Cheers, George H. N2FGX On 04/26/2015 06:51 AM, Bryan _ wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On Friday, May 22, 2015 10:48:16 AM Gerhard Hoffmann wrote: Am 21.05.2015 um 23:32 schrieb Magnus Danielson: On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote: The counter front ends seem to be modeled after scope front ends and scope triggering circuits, where you can adjust the triggering level. Any jitter in the triggering would normally only affect the interpolator. The interpolators in general were no great shakes, so the triggering wasn't the limiting factor. Depends on the signal. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. Magnus ___ ECL is bad because the voltage swing is low; because as you say, a lot of the circuitry is in the active region all the time, and because the current source in the emitters generates a lot of noise. Yes, it is bound to have 1/f noise with it's 50 Ohm current load. I was thinking about the continuous current, as I do know of the gating effect. Today there is other interface standards having lower swings than ECL. In the early 1990's, I thought I had proved that the high ECL noise was mostly common mode and that you could reduce it 20 dB by using a transformer to couple the output. Alternately, a good differential amplifier with high CMRR would do the trick. I had actual measurements to back up this theory. Subsequently, other people tried to reproduce this and could not. By that time, I had moved on and didn't have the bandwidth to continue to own the problem. It would make a nice project for some time-nut to prove or disprove my hypothesis regarding ECL. ECL line receivers as squarers are not as bad as comparators, but are much noisier than 74AC. Interesting. Don't have a lot of ECL lying around, but some toys that might measure things. Could we agree on a test procedure? A friend of mine did some tests for synthesizers in mil. avionics and he told me that Motorola's MOSAIC3 process was the worst thing that has hit the planet wrt phase noise. That was used for a lot of fast ECL. (Some years have passed since he made the test.) Comparators have their advantages, too. At least, someone has been thinking about dispersion, constant flowthrough time against frequency and overdrive; there are even specs that include overdrive. Just that comparators can switch cleanly at mV levels does not mean that they are to be used that way. More gain may mean more noise voltage, but it also means less time spent in the transition region. Once the decision has been made the noise is squelched anyway. And I prefer setting the bandwidth with thin film Rs and np0 capacitors, not with oversized junctions. The fairest shootout between the logic families that we have is the LTC6957. http://cds.linear.com/docs/en/datasheet/6957f.pdf Probably just bondout options of the same chip. The PECL version wins hands-down, LVDS is worst and CMOS is in-between. Especially at low offsets PECL is best, that clearly contradicts the above-assumed 1/f problem and the lower swing standard of today comes out worst. regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. The LT6957 dtasheet PN curves differ from what I measured with a 10-MHz input in that when shielded from air currents the flicker noise corner is much lower than 100Hz offr a 100MHz input. I have only tested the LTC6957-4 evaluation board. Bruce set shown fo ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi The simple answer is that a biased fast CMOS gate will do a better job ADEV wise than your signal sources will. If you want that to also hold for phase noise, run the gate on 5.5V and get the input signal as close to that (5.5V p-p) as you can. Bob On May 22, 2015, at 6:29 PM, xaos x...@darksmile.net wrote: Bob, This are all great questions. 1. Let's assume that it varies from a HP Signal generator to a home built device. However, If I was to build it I would expect to pay more and get better specs. I have a few HP 3325B's and a few 8660C. I would probably use those as inputs but not always. 2. Let's stick with the basics: 5-10Mhz. 3. Again, basics: 1-7V peak to Peak. 4. Ok, this is the real important question. The answer is, an amplifier of some sort. And that amp will probably feed something like a Test Instrument or some circuit I am building. What are my options? For now, I'd like to simulate some of my simple designs as well as some designs suggested here. Then, see where it goes. George On 05/22/2015 05:31 PM, Bob Camp wrote: Hi What is your objective? Put another way: 1) How clean is your sine wave source? 2) What frequency (or range) are you trying to convert? 3) What level range are you trying to work with? 4) What is it going into (how clean is the next stage)? If you have an optical fountain that is good to 1x10^-15 at 1 second, and you are trying to map Pluto with a radar in your back yard, the answer will be a bit different than if you are starting with a surplus OCXO and trying to drive a 5334 :) Bob On May 22, 2015, at 4:27 PM, xaos x...@darksmile.net wrote: After reading the posts on this subject I have a question. First, in my experience I used a rather simple circuit made from diodes used as limiters and a transistor feeding a logic inverter. No AGC. So here is my question. What is the proper circuit to use? I'd like to do a PSPICE and check things out followed by a prototype. I got that a comparator is out, etc. Cheers, George H. N2FGX On 04/26/2015 06:51 AM, Bryan _ wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Bob, This are all great questions. 1. Let's assume that it varies from a HP Signal generator to a home built device. However, If I was to build it I would expect to pay more and get better specs. I have a few HP 3325B's and a few 8660C. I would probably use those as inputs but not always. 2. Let's stick with the basics: 5-10Mhz. 3. Again, basics: 1-7V peak to Peak. 4. Ok, this is the real important question. The answer is, an amplifier of some sort. And that amp will probably feed something like a Test Instrument or some circuit I am building. What are my options? For now, I'd like to simulate some of my simple designs as well as some designs suggested here. Then, see where it goes. George On 05/22/2015 05:31 PM, Bob Camp wrote: Hi What is your objective? Put another way: 1) How clean is your sine wave source? 2) What frequency (or range) are you trying to convert? 3) What level range are you trying to work with? 4) What is it going into (how clean is the next stage)? If you have an optical fountain that is good to 1x10^-15 at 1 second, and you are trying to map Pluto with a radar in your back yard, the answer will be a bit different than if you are starting with a surplus OCXO and trying to drive a 5334 :) Bob On May 22, 2015, at 4:27 PM, xaos x...@darksmile.net wrote: After reading the posts on this subject I have a question. First, in my experience I used a rather simple circuit made from diodes used as limiters and a transistor feeding a logic inverter. No AGC. So here is my question. What is the proper circuit to use? I'd like to do a PSPICE and check things out followed by a prototype. I got that a comparator is out, etc. Cheers, George H. N2FGX On 04/26/2015 06:51 AM, Bryan _ wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi To answer the next part of the question - simulation: Noise wise, Spice is fundamentally a linear analysis program. Logic gates mostly operate in a non-linear fashion (full on / full off). The noise models that are commonly used (when you can even find them) apply to fairly limited “active region” conditions. In this case, you have noise in the “DC” region and at audio modulating your signal. It’s very much a non-linear case. A conventional Spice analysis will quickly lead you astray. You *can* make it work after the fact by plugging this and that in here and there. To do that, you need to measure some parts and then back fit the dummy elements in the model to your results. To predictively accurately model noise in a gate as it switches you need: 1) A program that handles non-linear models properly 2) The basic device models for the devices in your IC 3) The non-linear noise add-on for your analysis program 4) The generalized non-linear noise models (DC to GHz) to add onto your device data 5) A way to convert the result into something meaningful (ADEV , phase noise) Last time I looked, 1 + 3 ran above $125K for something that *might* be accurate. The models for the IC process devices (2 above) were “sort of” included in that price. Adding 4 to the mix was a “cost plus” sort of thing. Obviously number 5 is a “do it your self” task. Far cheaper (at least 10X) to just build one and buy all the brand new gear needed to test it. We’re not talking about big buckets of noise, this stuff is all mighty far down. 1x10^-14 is a long long ways. A simple term like “accurate” gets a major workout in this case. If once you have your data, you want to back fit a dummy model - go for it. Bob On May 22, 2015, at 6:29 PM, xaos x...@darksmile.net wrote: Bob, This are all great questions. 1. Let's assume that it varies from a HP Signal generator to a home built device. However, If I was to build it I would expect to pay more and get better specs. I have a few HP 3325B's and a few 8660C. I would probably use those as inputs but not always. 2. Let's stick with the basics: 5-10Mhz. 3. Again, basics: 1-7V peak to Peak. 4. Ok, this is the real important question. The answer is, an amplifier of some sort. And that amp will probably feed something like a Test Instrument or some circuit I am building. What are my options? For now, I'd like to simulate some of my simple designs as well as some designs suggested here. Then, see where it goes. George On 05/22/2015 05:31 PM, Bob Camp wrote: Hi What is your objective? Put another way: 1) How clean is your sine wave source? 2) What frequency (or range) are you trying to convert? 3) What level range are you trying to work with? 4) What is it going into (how clean is the next stage)? If you have an optical fountain that is good to 1x10^-15 at 1 second, and you are trying to map Pluto with a radar in your back yard, the answer will be a bit different than if you are starting with a surplus OCXO and trying to drive a 5334 :) Bob On May 22, 2015, at 4:27 PM, xaos x...@darksmile.net wrote: After reading the posts on this subject I have a question. First, in my experience I used a rather simple circuit made from diodes used as limiters and a transistor feeding a logic inverter. No AGC. So here is my question. What is the proper circuit to use? I'd like to do a PSPICE and check things out followed by a prototype. I got that a comparator is out, etc. Cheers, George H. N2FGX On 04/26/2015 06:51 AM, Bryan _ wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions
Re: [time-nuts] Divider circuit for Rubidium Standard
Am 21.05.2015 um 23:32 schrieb Magnus Danielson: On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote: The counter front ends seem to be modeled after scope front ends and scope triggering circuits, where you can adjust the triggering level. Any jitter in the triggering would normally only affect the interpolator. The interpolators in general were no great shakes, so the triggering wasn't the limiting factor. Depends on the signal. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. Magnus ___ ECL is bad because the voltage swing is low; because as you say, a lot of the circuitry is in the active region all the time, and because the current source in the emitters generates a lot of noise. Yes, it is bound to have 1/f noise with it's 50 Ohm current load. I was thinking about the continuous current, as I do know of the gating effect. Today there is other interface standards having lower swings than ECL. In the early 1990's, I thought I had proved that the high ECL noise was mostly common mode and that you could reduce it 20 dB by using a transformer to couple the output. Alternately, a good differential amplifier with high CMRR would do the trick. I had actual measurements to back up this theory. Subsequently, other people tried to reproduce this and could not. By that time, I had moved on and didn't have the bandwidth to continue to own the problem. It would make a nice project for some time-nut to prove or disprove my hypothesis regarding ECL. ECL line receivers as squarers are not as bad as comparators, but are much noisier than 74AC. Interesting. Don't have a lot of ECL lying around, but some toys that might measure things. Could we agree on a test procedure? A friend of mine did some tests for synthesizers in mil. avionics and he told me that Motorola's MOSAIC3 process was the worst thing that has hit the planet wrt phase noise. That was used for a lot of fast ECL. (Some years have passed since he made the test.) Comparators have their advantages, too. At least, someone has been thinking about dispersion, constant flowthrough time against frequency and overdrive; there are even specs that include overdrive. Just that comparators can switch cleanly at mV levels does not mean that they are to be used that way. More gain may mean more noise voltage, but it also means less time spent in the transition region. Once the decision has been made the noise is squelched anyway. And I prefer setting the bandwidth with thin film Rs and np0 capacitors, not with oversized junctions. The fairest shootout between the logic families that we have is the LTC6957. http://cds.linear.com/docs/en/datasheet/6957f.pdf Probably just bondout options of the same chip. The PECL version wins hands-down, LVDS is worst and CMOS is in-between. Especially at low offsets PECL is best, that clearly contradicts the above-assumed 1/f problem and the lower swing standard of today comes out worst. regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi On May 22, 2015, at 4:48 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 21.05.2015 um 23:32 schrieb Magnus Danielson: On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote: The counter front ends seem to be modeled after scope front ends and scope triggering circuits, where you can adjust the triggering level. Any jitter in the triggering would normally only affect the interpolator. The interpolators in general were no great shakes, so the triggering wasn't the limiting factor. Depends on the signal. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. Magnus ___ ECL is bad because the voltage swing is low; because as you say, a lot of the circuitry is in the active region all the time, and because the current source in the emitters generates a lot of noise. Yes, it is bound to have 1/f noise with it's 50 Ohm current load. I was thinking about the continuous current, as I do know of the gating effect. Today there is other interface standards having lower swings than ECL. In the early 1990's, I thought I had proved that the high ECL noise was mostly common mode and that you could reduce it 20 dB by using a transformer to couple the output. Alternately, a good differential amplifier with high CMRR would do the trick. I had actual measurements to back up this theory. Subsequently, other people tried to reproduce this and could not. By that time, I had moved on and didn't have the bandwidth to continue to own the problem. It would make a nice project for some time-nut to prove or disprove my hypothesis regarding ECL. ECL line receivers as squarers are not as bad as comparators, but are much noisier than 74AC. Interesting. Don't have a lot of ECL lying around, but some toys that might measure things. Could we agree on a test procedure? A friend of mine did some tests for synthesizers in mil. avionics and he told me that Motorola's MOSAIC3 process was the worst thing that has hit the planet wrt phase noise. That was used for a lot of fast ECL. (Some years have passed since he made the test.) Comparators have their advantages, too. At least, someone has been thinking about dispersion, constant flowthrough time against frequency and overdrive; there are even specs that include overdrive. Just that comparators can switch cleanly at mV levels does not mean that they are to be used that way. More gain may mean more noise voltage, but it also means less time spent in the transition region. Once the decision has been made the noise is squelched anyway. And I prefer setting the bandwidth with thin film Rs and np0 capacitors, not with oversized junctions. The fairest shootout between the logic families that we have is the LTC6957. http://cds.linear.com/docs/en/datasheet/6957f.pdf Probably just bondout options of the same chip. The PECL version wins hands-down, LVDS is worst and CMOS is in-between. Especially at low offsets PECL is best, that clearly contradicts the above-assumed 1/f problem and the lower swing standard of today comes out worst. regards, Gerhard The way I’ve tested most of this is with a TimePod or something similar. You start with a power splitter of some sort (active or passive) and feed one input to the tester off of one port. The DUT connects to the other port. Once the signal has flowed through what ever circuits you have, it’s output goes to the other input of the tester. In the “good old days” the test had to be done with two pieces of gear. You ran one set of tests with a short term stability box. You ran another set of tests with a phase noise analyzer. The nice thing about the more modern gear is that you can run both tests at once. That’s nice when you consider that the tests run for 10 hours in many cases. If you want to go *really* old school, you can run a single mixer setup for the phase noise and a DMTD for the short term. That approach works (been there done that). You do need to start by testing some amplifiers. I’ve found that the results make more sense if you use a good signal source for the testing. An OCXO is generally a good idea. If you have a source with a lot of AM noise, you will spend time learning about AM to PM conversion … What to expect: Phase noise @ 100KHz can / might get down below -190 dbc Hz. Short term can / might hit 1x10^-14 at 1 second. You will need some pretty good setups to get that data. The bad news is that those numbers are not the bottom of the range :) You probably will spend some time checking things like square to sine converters. In some cases they will be pretty easy in others they will turn out to tell you a lot about how your HVAC system is running overnight. Bob ___ time-nuts mailing list
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi On May 20, 2015, at 11:27 PM, Alex Pummer a...@pcscons.com wrote: once upon the time at Gigatronics we compared logic devices noise and found that TTL were the quietest 73 KJ6UHN Alex Before the 74AC stuff came along, some flavor of TTL was the best bet. With TTL you needed to be a bit carefull about just what family (and in some cases manufacturer) you used. All that picky stuff has pretty much gone away with fast silicon CMOS, at least among the major outfits. Bob On 5/20/2015 3:15 PM, Richard (Rick) Karlquist wrote: On 5/20/2015 11:22 AM, Magnus Danielson wrote: The older HP counter manuals explained it very nicely too, as they illustrated the slew-rate amplitude noise to time-noise conversion. What do amazes me is the fact that I've yet to see a counter input channel which takes care to square up the signal properly, they rather provide the comparator after the obvious damping and AC-blocking conditioning. I can't even recall that there where much such shaping as a side-product. The counter front ends seem to be modeled after scope front ends and scope triggering circuits, where you can adjust the triggering level. Any jitter in the triggering would normally only affect the interpolator. The interpolators in general were no great shakes, so the triggering wasn't the limiting factor. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. Magnus ___ ECL is bad because the voltage swing is low; because as you say, a lot of the circuitry is in the active region all the time, and because the current source in the emitters generates a lot of noise. In the early 1990's, I thought I had proved that the high ECL noise was mostly common mode and that you could reduce it 20 dB by using a transformer to couple the output. Alternately, a good differential amplifier with high CMRR would do the trick. I had actual measurements to back up this theory. Subsequently, other people tried to reproduce this and could not. By that time, I had moved on and didn't have the bandwidth to continue to own the problem. It would make a nice project for some time-nut to prove or disprove my hypothesis regarding ECL. ECL line receivers as squarers are not as bad as comparators, but are much noisier than 74AC. Rick Karlquist N6RK Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote: On 5/20/2015 11:22 AM, Magnus Danielson wrote: The older HP counter manuals explained it very nicely too, as they illustrated the slew-rate amplitude noise to time-noise conversion. What do amazes me is the fact that I've yet to see a counter input channel which takes care to square up the signal properly, they rather provide the comparator after the obvious damping and AC-blocking conditioning. I can't even recall that there where much such shaping as a side-product. The counter front ends seem to be modeled after scope front ends and scope triggering circuits, where you can adjust the triggering level. Any jitter in the triggering would normally only affect the interpolator. The interpolators in general were no great shakes, so the triggering wasn't the limiting factor. Depends on the signal. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. Magnus ___ ECL is bad because the voltage swing is low; because as you say, a lot of the circuitry is in the active region all the time, and because the current source in the emitters generates a lot of noise. Yes, it is bound to have 1/f noise with it's 50 Ohm current load. I was thinking about the continuous current, as I do know of the gating effect. Today there is other interface standards having lower swings than ECL. In the early 1990's, I thought I had proved that the high ECL noise was mostly common mode and that you could reduce it 20 dB by using a transformer to couple the output. Alternately, a good differential amplifier with high CMRR would do the trick. I had actual measurements to back up this theory. Subsequently, other people tried to reproduce this and could not. By that time, I had moved on and didn't have the bandwidth to continue to own the problem. It would make a nice project for some time-nut to prove or disprove my hypothesis regarding ECL. ECL line receivers as squarers are not as bad as comparators, but are much noisier than 74AC. Interesting. Don't have a lot of ECL lying around, but some toys that might measure things. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi On May 19, 2015, at 7:10 PM, Richard (Rick) Karlquist rich...@karlquist.com wrote: On 5/8/2015 2:19 PM, Bob Camp wrote: On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote: On Wed, 06 May 2015 18:09:03 -0700 Richard (Rick) Karlquist rich...@karlquist.com wrote: A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Logic gate, yes. Comparator, no. This reminds me a lot of a similar discussion a couple of weeks ago. (where the issue boiled down to noise bandwidth) What is the problem with a comparator vs a logic gate? What makes the logic gate supperior? Attila Kinali The comparator as a squarer circuit is folklore that unsophisticated users want to believe in, because it is seemingly the easiest way to get the job done. Wouldn't it be wonderful to be able to put in any signal from -30 dBm to +15 dBm and get a perfect square wave out with no effort? Unfortunately, what a comparator looks like is a very high gain differential amplifier that is slew rate limited. The threshold voltage input must be extremely low noise or it will introduce jitter. Even if the input pin is clean, there is internal noise. Driving it will a low level signal will produce a jittery output for obvious reasons. The trouble is that if you drive it with a high level signal, the jitter doesn't go away because the input stage is already in saturation. Also, the effective noise figure of the comparator is usually high. Making the comparator faster exacerbates the problem. Read papers on zero crossing detectors such as John Dick's 1990 paper in PTTI and you will see that a comparator is the exact opposite architecture from the optimum one. I hope that clears up the question. Regarding logic gates: it is not so much that there is something magic about gates; actually ECL gates are lousy. It is just that comparators are so bad that almost anything else is better. The only gates that seem to do very well are high speed (as in 74AC or faster) silicon CMOS. You need to run them with a fairly clean supply and feed them with a p-p input that matches the supply voltage. Other than that, not a lot of magic. Are they ideal - surely not. Will they hit 2x10^-13 ADEV at 1 second and drop from there as tau increases - yes they will. Bob Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Rick, On 05/20/2015 01:10 AM, Richard (Rick) Karlquist wrote: On 5/8/2015 2:19 PM, Bob Camp wrote: On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote: On Wed, 06 May 2015 18:09:03 -0700 Richard (Rick) Karlquist rich...@karlquist.com wrote: A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Logic gate, yes. Comparator, no. This reminds me a lot of a similar discussion a couple of weeks ago. (where the issue boiled down to noise bandwidth) What is the problem with a comparator vs a logic gate? What makes the logic gate supperior? Attila Kinali The comparator as a squarer circuit is folklore that unsophisticated users want to believe in, because it is seemingly the easiest way to get the job done. Wouldn't it be wonderful to be able to put in any signal from -30 dBm to +15 dBm and get a perfect square wave out with no effort? Unfortunately, what a comparator looks like is a very high gain differential amplifier that is slew rate limited. The threshold voltage input must be extremely low noise or it will introduce jitter. Even if the input pin is clean, there is internal noise. Driving it will a low level signal will produce a jittery output for obvious reasons. The trouble is that if you drive it with a high level signal, the jitter doesn't go away because the input stage is already in saturation. Also, the effective noise figure of the comparator is usually high. Making the comparator faster exacerbates the problem. Read papers on zero crossing detectors such as John Dick's 1990 paper in PTTI and you will see that a comparator is the exact opposite architecture from the optimum one. I hope that clears up the question. The older HP counter manuals explained it very nicely too, as they illustrated the slew-rate amplitude noise to time-noise conversion. What do amazes me is the fact that I've yet to see a counter input channel which takes care to square up the signal properly, they rather provide the comparator after the obvious damping and AC-blocking conditioning. I can't even recall that there where much such shaping as a side-product. Regarding logic gates: it is not so much that there is something magic about gates; actually ECL gates are lousy. It is just that comparators are so bad that almost anything else is better. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. PS. Sniffed the heat from a 1979 ECL based PM6674 counter as I was doing some checkout before put it in the hands of a friend. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
The only gates that seem to do very well are high speed (as in 74AC or faster) silicon CMOS. You need to run them with a fairly clean supply and feed them with a p-p input that matches the supply voltage. Other than that, not a lot of magic. Are they ideal - surely not. Will they hit 2x10^-13 ADEV at 1 second and drop from there as tau increases - yes they will. Bob Interesting. Back in the stone age in 1990, 74AC was state of the art. As soon as it came out, I used it exclusively for everything that didn't require ECL, for which I used ECLinPS exclusively. In the 5071A, we used one to square up 80 MHz for the DDS board. You are exactly right: put in a huge sinewave obtained by good old fashioned analog anplifiers and let the 74AC do its thing. 80 MHz is pretty much flat out for a 74AC series. The 80 MHz came from a 10 to 80 MHz multiplier running from the 10811. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On 5/20/2015 11:22 AM, Magnus Danielson wrote: The older HP counter manuals explained it very nicely too, as they illustrated the slew-rate amplitude noise to time-noise conversion. What do amazes me is the fact that I've yet to see a counter input channel which takes care to square up the signal properly, they rather provide the comparator after the obvious damping and AC-blocking conditioning. I can't even recall that there where much such shaping as a side-product. The counter front ends seem to be modeled after scope front ends and scope triggering circuits, where you can adjust the triggering level. Any jitter in the triggering would normally only affect the interpolator. The interpolators in general were no great shakes, so the triggering wasn't the limiting factor. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. Magnus ___ ECL is bad because the voltage swing is low; because as you say, a lot of the circuitry is in the active region all the time, and because the current source in the emitters generates a lot of noise. In the early 1990's, I thought I had proved that the high ECL noise was mostly common mode and that you could reduce it 20 dB by using a transformer to couple the output. Alternately, a good differential amplifier with high CMRR would do the trick. I had actual measurements to back up this theory. Subsequently, other people tried to reproduce this and could not. By that time, I had moved on and didn't have the bandwidth to continue to own the problem. It would make a nice project for some time-nut to prove or disprove my hypothesis regarding ECL. ECL line receivers as squarers are not as bad as comparators, but are much noisier than 74AC. Rick Karlquist N6RK Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
HI On May 20, 2015, at 11:55 AM, Richard (Rick) Karlquist rich...@karlquist.com wrote: The only gates that seem to do very well are high speed (as in 74AC or faster) silicon CMOS. You need to run them with a fairly clean supply and feed them with a p-p input that matches the supply voltage. Other than that, not a lot of magic. Are they ideal - surely not. Will they hit 2x10^-13 ADEV at 1 second and drop from there as tau increases - yes they will. Bob Interesting. Back in the stone age in 1990, 74AC was state of the art. As soon as it came out, I used it exclusively for everything that didn't require ECL, for which I used ECLinPS exclusively. In the 5071A, we used one to square up 80 MHz for the DDS board. You are exactly right: put in a huge sinewave obtained by good old fashioned analog anplifiers and let the 74AC do its thing. … you actually can do a pretty good job with just a terminated L network feeding the input to the gate. It’s a high input impedance so driving it from 200 to 1K ohms isn’t all that different than 50 ohms. Again - not ideal, but it saves a few parts and some current. Bob 80 MHz is pretty much flat out for a 74AC series. The 80 MHz came from a 10 to 80 MHz multiplier running from the 10811. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
once upon the time at Gigatronics we compared logic devices noise and found that TTL were the quietest 73 KJ6UHN Alex On 5/20/2015 3:15 PM, Richard (Rick) Karlquist wrote: On 5/20/2015 11:22 AM, Magnus Danielson wrote: The older HP counter manuals explained it very nicely too, as they illustrated the slew-rate amplitude noise to time-noise conversion. What do amazes me is the fact that I've yet to see a counter input channel which takes care to square up the signal properly, they rather provide the comparator after the obvious damping and AC-blocking conditioning. I can't even recall that there where much such shaping as a side-product. The counter front ends seem to be modeled after scope front ends and scope triggering circuits, where you can adjust the triggering level. Any jitter in the triggering would normally only affect the interpolator. The interpolators in general were no great shakes, so the triggering wasn't the limiting factor. Now, remind me why ECL is lousy, I can't recall there being very high gain in them, but fairly high bandwidth and they stay in the linear operation region. Magnus ___ ECL is bad because the voltage swing is low; because as you say, a lot of the circuitry is in the active region all the time, and because the current source in the emitters generates a lot of noise. In the early 1990's, I thought I had proved that the high ECL noise was mostly common mode and that you could reduce it 20 dB by using a transformer to couple the output. Alternately, a good differential amplifier with high CMRR would do the trick. I had actual measurements to back up this theory. Subsequently, other people tried to reproduce this and could not. By that time, I had moved on and didn't have the bandwidth to continue to own the problem. It would make a nice project for some time-nut to prove or disprove my hypothesis regarding ECL. ECL line receivers as squarers are not as bad as comparators, but are much noisier than 74AC. Rick Karlquist N6RK Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On 5/8/2015 2:19 PM, Bob Camp wrote: On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote: On Wed, 06 May 2015 18:09:03 -0700 Richard (Rick) Karlquist rich...@karlquist.com wrote: A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Logic gate, yes. Comparator, no. This reminds me a lot of a similar discussion a couple of weeks ago. (where the issue boiled down to noise bandwidth) What is the problem with a comparator vs a logic gate? What makes the logic gate supperior? Attila Kinali The comparator as a squarer circuit is folklore that unsophisticated users want to believe in, because it is seemingly the easiest way to get the job done. Wouldn't it be wonderful to be able to put in any signal from -30 dBm to +15 dBm and get a perfect square wave out with no effort? Unfortunately, what a comparator looks like is a very high gain differential amplifier that is slew rate limited. The threshold voltage input must be extremely low noise or it will introduce jitter. Even if the input pin is clean, there is internal noise. Driving it will a low level signal will produce a jittery output for obvious reasons. The trouble is that if you drive it with a high level signal, the jitter doesn't go away because the input stage is already in saturation. Also, the effective noise figure of the comparator is usually high. Making the comparator faster exacerbates the problem. Read papers on zero crossing detectors such as John Dick's 1990 paper in PTTI and you will see that a comparator is the exact opposite architecture from the optimum one. I hope that clears up the question. Regarding logic gates: it is not so much that there is something magic about gates; actually ECL gates are lousy. It is just that comparators are so bad that almost anything else is better. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi Bob: i assume when you are referring to the comparator you are referencing the ADCMP600 or MAX999 that is used to clock shape the input for the logic dividers etc and the 74AC541 bus drivers. Could one modify the circuit to use a low noise LTC6957 to clock shape and then divide down using the existing circuitry. I would assume this would offer a greater improvement in phase noise? Cheers -=Bryan=- From: kb...@n1k.org Date: Fri, 8 May 2015 17:19:59 -0400 To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard Hi I guess the simple answer is “when you measure them that’s the result”. The slightly more complex answer is “fast silicon CMOS is indeed good, other types may require further analysis”. In general the faster stuff is better than the slower CMOS. Deeper into it you get to the fact that the gate is optimized for one input swing range, speed and consistent (short) delay. The amount of time that anything in a CMOS gate spends in-between “on” and “off” if very short. If you look at the time it’s hooked to a rail as noiseless (= quiet supplies), then the time noise can get into the output is quite short. Short time = little noise. You could go further with fancy tools. Bob On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote: On Wed, 06 May 2015 18:09:03 -0700 Richard (Rick) Karlquist rich...@karlquist.com wrote: A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Logic gate, yes. Comparator, no. This reminds me a lot of a similar discussion a couple of weeks ago. (where the issue boiled down to noise bandwidth) What is the problem with a comparator vs a logic gate? What makes the logic gate supperior? Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi The simple answer is that pumping the sine wave into a biased logic gate works down to at least the 2x10^-13 (at 1 second tau) level. Why spend more than 10 cents when you don’t have to ? Bob On May 18, 2015, at 6:19 AM, Bryan _ bpl...@outlook.com wrote: Hi Bob: i assume when you are referring to the comparator you are referencing the ADCMP600 or MAX999 that is used to clock shape the input for the logic dividers etc and the 74AC541 bus drivers. Could one modify the circuit to use a low noise LTC6957 to clock shape and then divide down using the existing circuitry. I would assume this would offer a greater improvement in phase noise? Cheers -=Bryan=- From: kb...@n1k.org Date: Fri, 8 May 2015 17:19:59 -0400 To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard Hi I guess the simple answer is “when you measure them that’s the result”. The slightly more complex answer is “fast silicon CMOS is indeed good, other types may require further analysis”. In general the faster stuff is better than the slower CMOS. Deeper into it you get to the fact that the gate is optimized for one input swing range, speed and consistent (short) delay. The amount of time that anything in a CMOS gate spends in-between “on” and “off” if very short. If you look at the time it’s hooked to a rail as noiseless (= quiet supplies), then the time noise can get into the output is quite short. Short time = little noise. You could go further with fancy tools. Bob On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote: On Wed, 06 May 2015 18:09:03 -0700 Richard (Rick) Karlquist rich...@karlquist.com wrote: A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Logic gate, yes. Comparator, no. This reminds me a lot of a similar discussion a couple of weeks ago. (where the issue boiled down to noise bandwidth) What is the problem with a comparator vs a logic gate? What makes the logic gate supperior? Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On Wed, 06 May 2015 18:09:03 -0700 Richard (Rick) Karlquist rich...@karlquist.com wrote: A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Logic gate, yes. Comparator, no. This reminds me a lot of a similar discussion a couple of weeks ago. (where the issue boiled down to noise bandwidth) What is the problem with a comparator vs a logic gate? What makes the logic gate supperior? Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi I guess the simple answer is “when you measure them that’s the result”. The slightly more complex answer is “fast silicon CMOS is indeed good, other types may require further analysis”. In general the faster stuff is better than the slower CMOS. Deeper into it you get to the fact that the gate is optimized for one input swing range, speed and consistent (short) delay. The amount of time that anything in a CMOS gate spends in-between “on” and “off” if very short. If you look at the time it’s hooked to a rail as noiseless (= quiet supplies), then the time noise can get into the output is quite short. Short time = little noise. You could go further with fancy tools. Bob On May 7, 2015, at 11:09 AM, Attila Kinali att...@kinali.ch wrote: On Wed, 06 May 2015 18:09:03 -0700 Richard (Rick) Karlquist rich...@karlquist.com wrote: A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Logic gate, yes. Comparator, no. This reminds me a lot of a similar discussion a couple of weeks ago. (where the issue boiled down to noise bandwidth) What is the problem with a comparator vs a logic gate? What makes the logic gate supperior? Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On 5/6/2015 3:24 PM, Bob Camp wrote: Hi A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Bob Logic gate, yes. Comparator, no. Rick ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi Rick: Any suggestions for a circuit with better performance. Purpose will be a external standard for a frequency counter. -=Bryan=- Date: Mon, 4 May 2015 21:09:51 -0700 From: rich...@karlquist.com To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard On 4/26/2015 3:51 AM, Bryan _ wrote: All: P I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html -=Bryan=- ___ This is a comparator based circuit. This will give you worse performance than just about anything else, but it may be good enough anyway. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
That's one of the reasons I was considering a re-spin of the board using a better ZCD solution. Dave -Original Message- From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Richard (Rick) Karlquist Sent: 05 May 2015 05:10 To: Discussion of precise time and frequency measurement Subject: Re: [time-nuts] Divider circuit for Rubidium Standard This is a comparator based circuit. This will give you worse performance than just about anything else, but it may be good enough anyway. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
The Phase noise floor (~-143dBc/Hz @ 1kHz) of the 10MHz output of that divider is about 17dBc/Hz higher than either the LTC6957-4 (demo board) or the Holzworth HX2410 (both ~ -160dBc/Hz @ 1kHz).All measured with a 10MHz +14dBm input signal.For offsets below a few Hz shielding of the circuitry from air currents and reducing temperature fluctuations experienced by the circuitry is essential for accurate phase noise measurements. Bruce On Wednesday, 6 May 2015 2:36 PM, Richard (Rick) Karlquist rich...@karlquist.com wrote: On 4/26/2015 3:51 AM, Bryan _ wrote: All: P I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html -=Bryan=- ___ This is a comparator based circuit. This will give you worse performance than just about anything else, but it may be good enough anyway. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Wenzel has published the schematic of an excellent squaring circuit. I don't have the URL for their version handy, but I used it (with a couple of mods) in the TADD-2 and TADD-2 Mini designs. You can see the schematic in the T2-Mini users guide at http://www.tapr.org/~n8ur/T2_Mini_Manual.pdf. It will square up signals as low as -20dBm with very low jitter, and provides a TTL-compatible output. John On 5/6/2015 2:52 AM, Bryan _ wrote: Hi Rick: Any suggestions for a circuit with better performance. Purpose will be a external standard for a frequency counter. -=Bryan=- Date: Mon, 4 May 2015 21:09:51 -0700 From: rich...@karlquist.com To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard On 4/26/2015 3:51 AM, Bryan _ wrote: All: P I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html -=Bryan=- ___ This is a comparator based circuit. This will give you worse performance than just about anything else, but it may be good enough anyway. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi A standard input on a frequency counter is not a very demanding thing in the hierarchy of TimeNut signals. You can drive any of them with some pretty simple logic gate based circuits. No need to spend a lot of money. Bob On May 6, 2015, at 2:52 AM, Bryan _ bpl...@outlook.com wrote: Hi Rick: Any suggestions for a circuit with better performance. Purpose will be a external standard for a frequency counter. -=Bryan=- Date: Mon, 4 May 2015 21:09:51 -0700 From: rich...@karlquist.com To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard On 4/26/2015 3:51 AM, Bryan _ wrote: All: P I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html -=Bryan=- ___ This is a comparator based circuit. This will give you worse performance than just about anything else, but it may be good enough anyway. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
On 4/26/2015 3:51 AM, Bryan _ wrote: All: P I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html -=Bryan=- ___ This is a comparator based circuit. This will give you worse performance than just about anything else, but it may be good enough anyway. Rick Karlquist N6RK ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Bob: The output of the 60 and 20 MHz are sine waves. The 60MHz is very clean whereas the 20Mhz is not. The ebay link has picture of the outputs and they mirror my results. Thanks for the tip on the LT1763, probably better to use a modified schematic of the one I posted and modify the circuit as I don't need all the dividers, but it has the circuitry for the amplifiers and buffers as well wave shaping the input. Cheers -=Bryan=- From: kb...@n1k.org Date: Sun, 26 Apr 2015 09:56:17 -0400 To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard Hi I would *assume* that either the 20 or 60 MHz is already a square wave. If they both are, use the 20, if not use which ever one is a square wave already. Past that it is just a divide by 2 or a divide by 3 followed by a divide by 2. You want the last stage to be divide by 2 so the output is symmetrical. One of a multitude of possible divide by 3 circuits: http://www.indiabix.com/electronics-circuits/divide-by-3/ The divide by 2 would just be a D F-F with the inverted output tied to the D input. I would build it out of whatever fast modern logic is available. My preference would be for a +5 supply coming off of something like an LT1763 linear regulator. Buffers up the outputs with several inverters in parallel. Yes it’s not the ultimate super duper circuit. Done properly it will be about 100X lower noise than your Rb at Tau = 10 seconds. Bob On Apr 26, 2015, at 6:51 AM, Bryan _ bpl...@outlook.com wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi Take a look at how the 60 MHz is generated. I believe that you will find that you have a sine wave that has come out of a logic gate via a low pass filter or that they square it up on the board already. My *guess* is that you could fit a little board with a divide by 6 into the Rb and run it off of the device’s internal supplies. You would then have a 10 MHz unit. Bob On Apr 27, 2015, at 5:34 AM, Bryan _ bpl...@outlook.com wrote: Bob: The output of the 60 and 20 MHz are sine waves. The 60MHz is very clean whereas the 20Mhz is not. The ebay link has picture of the outputs and they mirror my results. Thanks for the tip on the LT1763, probably better to use a modified schematic of the one I posted and modify the circuit as I don't need all the dividers, but it has the circuitry for the amplifiers and buffers as well wave shaping the input. Cheers -=Bryan=- From: kb...@n1k.org Date: Sun, 26 Apr 2015 09:56:17 -0400 To: time-nuts@febo.com Subject: Re: [time-nuts] Divider circuit for Rubidium Standard Hi I would *assume* that either the 20 or 60 MHz is already a square wave. If they both are, use the 20, if not use which ever one is a square wave already. Past that it is just a divide by 2 or a divide by 3 followed by a divide by 2. You want the last stage to be divide by 2 so the output is symmetrical. One of a multitude of possible divide by 3 circuits: http://www.indiabix.com/electronics-circuits/divide-by-3/ The divide by 2 would just be a D F-F with the inverted output tied to the D input. I would build it out of whatever fast modern logic is available. My preference would be for a +5 supply coming off of something like an LT1763 linear regulator. Buffers up the outputs with several inverters in parallel. Yes it’s not the ultimate super duper circuit. Done properly it will be about 100X lower noise than your Rb at Tau = 10 seconds. Bob On Apr 26, 2015, at 6:51 AM, Bryan _ bpl...@outlook.com wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Divider circuit for Rubidium Standard
Hi I would *assume* that either the 20 or 60 MHz is already a square wave. If they both are, use the 20, if not use which ever one is a square wave already. Past that it is just a divide by 2 or a divide by 3 followed by a divide by 2. You want the last stage to be divide by 2 so the output is symmetrical. One of a multitude of possible divide by 3 circuits: http://www.indiabix.com/electronics-circuits/divide-by-3/ The divide by 2 would just be a D F-F with the inverted output tied to the D input. I would build it out of whatever fast modern logic is available. My preference would be for a +5 supply coming off of something like an LT1763 linear regulator. Buffers up the outputs with several inverters in parallel. Yes it’s not the ultimate super duper circuit. Done properly it will be about 100X lower noise than your Rb at Tau = 10 seconds. Bob On Apr 26, 2015, at 6:51 AM, Bryan _ bpl...@outlook.com wrote: All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Divider circuit for Rubidium Standard
All: Picked up a FE 5680B from Ebay awhile back. Appears to work fine, but is limited to a 1pps output. However there is a point on the PCB that's documented that has a 20Mhz output. There is actually a clean 60Mhz output as well. http://www.ebay.com/itm/FEI-fe-5680b-rubidium-oscillator-With-1pps-20mhz-output-ONLY-10mhz-NEED-to-MOD-/291419889143?pt=LH_DefaultDomain_0hash=item43d9fa9df7 I would like to tap this 20mhz output and feed it to a divider/buffer circuit for a 10Mhz output at 50ohm. Can anyone recommend a good schematic for such a purpose. I was looking at the project from David partridges web site http://www.perdrix.co.uk/FrequencyDivider/index.html Cheers and thanks in advance. -=Bryan=- ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.