Re: [time-nuts] PICDIV build

[Bruce Griffiths]

The CLKIN input is compatible with STTL logic levels so driving the CLKIN from 
3.3V CMOS levels from the LTC6957 output whilst operating the PIC at 5V Vcc 
will work well. 

The LTC6957 evaluation board outputs are AC coupled and drive a 100 ohm + 100 
ohm attenuator to produce a 50 ohm output impedance reduce the pulse currents 
from the LTC6957 to 8.25mA peak from either the NMOS or PMOS output devices 
when driving a high impedance load. The output deice peak currents increase to 
12mA with a 50 ohm load well within  the maximum specified. A buffer is 
advisable when driving a grounded 50 ohm load either with or without a series 
50 ohm resistor.

Bruce
 

On Sunday, 17 April 2016 10:10 AM, Bruce Griffiths 
 wrote:
 

 The PN floor of the 10MHz output from the LTC6957 is very high, much higher 
than I measured the PN contribution of the LTC6957 itself using an evaluation 
board.
Are you sure that this isn't due to the source itself?
What did you use for the reference source for the 3120A?What is its PN?Have you 
tried driving the LTC6957 input from a clean low  PN source that is also used 
as the reference for the 3120A?

Bruce 

    On Sunday, 17 April 2016 2:01 AM, Bob Camp  wrote:
 

 Hi

Just about any of the modern ‘125 or ‘126 buffer gates will do a pretty good 
job 
of generating a logic output:

https://www.fairchildsemi.com/datasheets/NC/NC7SZ125.pdf
https://www.fairchildsemi.com/datasheets/NC/NC7SZ126.pdf
http://www.nxp.com/products/discretes-and-logic/logic/quad-buffer-3-state:74ABT125
http://www.nxp.com/products/discretes-and-logic/logic/quad-buffer-3-state:74ABT126
http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf
http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf

The typical ’04 inverters also will do the job:

http://cache.nxp.com/documents/data_sheet/74AHC_AHCT1G04_Q100.pdf?pspll=1
http://www.ti.com/product/sn74ahc1g04
http://www.ti.com/product/sn74ahc1g125

The list could go on for several pages….

3.3V into 50 ohms is 66 ma. Close to the rail most gates will only put out 
around 
10 ma. If you want to drive close to the 3.3V level, you will need to parallel 
up about 
6 to 8 gates. It’s probably best to drive them all from a single high speed 
gate output. 
If you are picky about the levels, twice that number of gates may be needed... 
Since you 
are driving out of an “un-terminated source”, you can expect a bit of ring on 
your cable. 

If you want to deliver 3.3V into a 50 ohm load out of a 50 ohm source, you will 
need 
a circuit that will handle a 6.6V supply. You *might* be able to select gates 
that won’t 
blow up at that voltage. The current will be 2X higher so you will need a few 
gates. In
this case, each one gets a series resistor in it’s output to make up the 50 ohm 
total. 

Bob  


> On Apr 16, 2016, at 2:29 AM, Anders Wallin  
> wrote:
> 
> hi all, I wrote down some notes on a recent PICDIV build and measurements:
> http://www.anderswallin.net/2016/04/picdiv-frequency-divider/
> 
> If/when I make v2 of this board:
> - any suggestions for boosting the output amplitude of both 1PPS and 10MHz
> CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?
> - any obvious mistakes that cause the phase-noise observed? Mostly I think
> 50/100Hz and harmonics would be nice to suppress..
> 
> thanks!
> Anders
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Re: [time-nuts] PICDIV build

[Bruce Griffiths]

The PN floor of the 10MHz output from the LTC6957 is very high, much higher 
than I measured the PN contribution of the LTC6957 itself using an evaluation 
board.
Are you sure that this isn't due to the source itself?
What did you use for the reference source for the 3120A?What is its PN?Have you 
tried driving the LTC6957 input from a clean low  PN source that is also used 
as the reference for the 3120A?

Bruce 

On Sunday, 17 April 2016 2:01 AM, Bob Camp  wrote:
 

 Hi

Just about any of the modern ‘125 or ‘126 buffer gates will do a pretty good 
job 
of generating a logic output:

https://www.fairchildsemi.com/datasheets/NC/NC7SZ125.pdf
https://www.fairchildsemi.com/datasheets/NC/NC7SZ126.pdf
http://www.nxp.com/products/discretes-and-logic/logic/quad-buffer-3-state:74ABT125
http://www.nxp.com/products/discretes-and-logic/logic/quad-buffer-3-state:74ABT126
http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf
http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf

The typical ’04 inverters also will do the job:

http://cache.nxp.com/documents/data_sheet/74AHC_AHCT1G04_Q100.pdf?pspll=1
http://www.ti.com/product/sn74ahc1g04
http://www.ti.com/product/sn74ahc1g125

The list could go on for several pages….

3.3V into 50 ohms is 66 ma. Close to the rail most gates will only put out 
around 
10 ma. If you want to drive close to the 3.3V level, you will need to parallel 
up about 
6 to 8 gates. It’s probably best to drive them all from a single high speed 
gate output. 
If you are picky about the levels, twice that number of gates may be needed.. 
Since you 
are driving out of an “un-terminated source”, you can expect a bit of ring on 
your cable. 

If you want to deliver 3.3V into a 50 ohm load out of a 50 ohm source, you will 
need 
a circuit that will handle a 6.6V supply. You *might* be able to select gates 
that won’t 
blow up at that voltage. The current will be 2X higher so you will need a few 
gates. In
this case, each one gets a series resistor in it’s output to make up the 50 ohm 
total. 

Bob  


> On Apr 16, 2016, at 2:29 AM, Anders Wallin  
> wrote:
> 
> hi all, I wrote down some notes on a recent PICDIV build and measurements:
> http://www.anderswallin.net/2016/04/picdiv-frequency-divider/
> 
> If/when I make v2 of this board:
> - any suggestions for boosting the output amplitude of both 1PPS and 10MHz
> CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?
> - any obvious mistakes that cause the phase-noise observed? Mostly I think
> 50/100Hz and harmonics would be nice to suppress..
> 
> thanks!
> Anders
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.

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Re: [time-nuts] PICDIV build

[Bob Camp]

Hi

Just about any of the modern ‘125 or ‘126 buffer gates will do a pretty good 
job 
of generating a logic output:

https://www.fairchildsemi.com/datasheets/NC/NC7SZ125.pdf
https://www.fairchildsemi.com/datasheets/NC/NC7SZ126.pdf
http://www.nxp.com/products/discretes-and-logic/logic/quad-buffer-3-state:74ABT125
http://www.nxp.com/products/discretes-and-logic/logic/quad-buffer-3-state:74ABT126
http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf
http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf

The typical ’04 inverters also will do the job:

http://cache.nxp.com/documents/data_sheet/74AHC_AHCT1G04_Q100.pdf?pspll=1
http://www.ti.com/product/sn74ahc1g04
http://www.ti.com/product/sn74ahc1g125

The list could go on for several pages….

3.3V into 50 ohms is 66 ma. Close to the rail most gates will only put out 
around 
10 ma. If you want to drive close to the 3.3V level, you will need to parallel 
up about 
6 to 8 gates. It’s probably best to drive them all from a single high speed 
gate output. 
If you are picky about the levels, twice that number of gates may be needed. 
Since you 
are driving out of an “un-terminated source”, you can expect a bit of ring on 
your cable. 

If you want to deliver 3.3V into a 50 ohm load out of a 50 ohm source, you will 
need 
a circuit that will handle a 6.6V supply. You *might* be able to select gates 
that won’t 
blow up at that voltage. The current will be 2X higher so you will need a few 
gates. In
this case, each one gets a series resistor in it’s output to make up the 50 ohm 
total. 

Bob  


> On Apr 16, 2016, at 2:29 AM, Anders Wallin  
> wrote:
> 
> hi all, I wrote down some notes on a recent PICDIV build and measurements:
> http://www.anderswallin.net/2016/04/picdiv-frequency-divider/
> 
> If/when I make v2 of this board:
> - any suggestions for boosting the output amplitude of both 1PPS and 10MHz
> CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?
> - any obvious mistakes that cause the phase-noise observed? Mostly I think
> 50/100Hz and harmonics would be nice to suppress..
> 
> thanks!
> Anders
> ___
> time-nuts mailing list -- time-nuts@febo.com
> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.

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Re: [time-nuts] PICDIV build

[Magnus Danielson]

Hej igen Anders,

On 04/16/2016 08:29 AM, Anders Wallin wrote:

hi all, I wrote down some notes on a recent PICDIV build and measurements:
http://www.anderswallin.net/2016/04/picdiv-frequency-divider/

If/when I make v2 of this board:
- any suggestions for boosting the output amplitude of both 1PPS and 10MHz
CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?


No or very little output resistance from a number of CMOS drivers get 
you close. Output impedance will be far from 50 Ohm thought, which may 
or may not be an issue. Otherwise, you need higher voltage. Often "TTL 
level" meaning 2,5 Vp is being used.



- any obvious mistakes that cause the phase-noise observed? Mostly I think
50/100Hz and harmonics would be nice to suppress..


OK. Bond the shields to the front-plate properly. Preferably bond your 
10 MHz source and your measurement kit with a high conductance path, and 
also any power-supply. In general, make the PCB board shunted for ground 
potential differences, as those will easily be amplified as they go 
through the board. Tie things together away from the board and whatever 
current needs to go via the module, make sure it finds a better path 
than through the PCB ground traces. There is also layout tricks to make 
all the internal circuit only tie to the outside ground currents but 
tying to them voltage wise by using a star ground from the ground point.


Cheers,
Magnus
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Re: [time-nuts] PICDIV build

[Magnus Danielson]

Hej Anders,

On 04/16/2016 08:29 AM, Anders Wallin wrote:

hi all, I wrote down some notes on a recent PICDIV build and measurements:
http://www.anderswallin.net/2016/04/picdiv-frequency-divider/

If/when I make v2 of this board:
- any suggestions for boosting the output amplitude of both 1PPS and 10MHz
CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?
- any obvious mistakes that cause the phase-noise observed? Mostly I think
50/100Hz and harmonics would be nice to suppress..


I can't seem to get a full size of the plots or schematics. It's just 
very hard to read and interpret.


MVH
Magnus
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Re: [time-nuts] PICDIV build

[Tom Van Baak]

Anders,

Nice work.

Your output level is low because the 3.3 V output of the PIC gets cut in half 
by the series 50R on your board and the 50R termination. But 700 mV into 50R 
seems way too low. Something's not right.

FYI: see how John handles input and output in the TADD-2-mini:

https://www.tapr.org/kits_t2-mini.html
http://www.tapr.org/~n8ur/T2_Mini_Manual.pdf

That board ships with PD17 [1] and most of the dividers I design to be pin 
compatible with his PCB. For example, the 10 MHz to 32 kHz divider [2] that we 
were talking about a few weeks ago can be used with the TADD-2-mini.

You can use the same trick he did to parallel multiple outputs to gain higher 
output levels. The comments [3] in PD09 chip say that you can use pin3 and pin6 
in addition to pin7 for output. So combine each pin through its own 50R to a 
common output BNC. It also helps that he runs the board at 5 V and not 3.3 V.

/tvb

[1] http://leapsecond.com/pic/src/pd17.asm
[2] http://leapsecond.com/pic/src/pd30.asm
[3] http://leapsecond.com/pic/src/pd09.asm

- Original Message - 
From: "Anders Wallin" <anders.e.e.wal...@gmail.com>
To: "Discussion" <time-nuts@febo.com>
Sent: Friday, April 15, 2016 11:29 PM
Subject: [time-nuts] PICDIV build


> hi all, I wrote down some notes on a recent PICDIV build and measurements:
> http://www.anderswallin.net/2016/04/picdiv-frequency-divider/
> 
> If/when I make v2 of this board:
> - any suggestions for boosting the output amplitude of both 1PPS and 10MHz
> CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?
> - any obvious mistakes that cause the phase-noise observed? Mostly I think
> 50/100Hz and harmonics would be nice to suppress..
> 
> thanks!
> Anders

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[time-nuts] PICDIV build

[Anders Wallin]

hi all, I wrote down some notes on a recent PICDIV build and measurements:
http://www.anderswallin.net/2016/04/picdiv-frequency-divider/

If/when I make v2 of this board:
- any suggestions for boosting the output amplitude of both 1PPS and 10MHz
CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?
- any obvious mistakes that cause the phase-noise observed? Mostly I think
50/100Hz and harmonics would be nice to suppress..

thanks!
Anders
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