Re: [time-nuts] Single ended or differential input to TDC chip
Moin, I do understand the advantages of having differential input. But my problem is that we are really sensitive to delay differences between channels. And I mean _really_ sensitive. The TDCs will have a total usefull range of about 100-200ps. The input pulses will arrive within this time frame. There is some provision in there to calibrate delay differnces between different paths, but it's not much. If there is an electronic component in the path, that has a delay variation between different devices of 1ns (like the ADN4661 that Bruce recommended), this would mean we would need somehow extend our measurement range to at least 2ns to be able to compensate for this delay variations. This >10 fold increase in measurement range means that we need more circuitry after the TDC, ie the digital circuitry would increase by more than a factor of 40 (grows with approximately n+n*log(n)) and that will cause us all kinds of other headaches. This sensitivity to delay variations also means that we have to minimize the number of components in the signal path. Hence things like having the option of selecting single-ended or differential is would degrade our signal path too much. The multiplexer alone would add too much delay variation. As the signal is distributed to multiple boards and the number of connections we need for that is already large enough, i want to keep the signal going between the boards single-ended. This also makes it easier for us to find cables that are withing a few ps (a non-representative sampling of cables of same type i had at hand gave me <30ps variation between cables) On Tue, 28 Mar 2017 02:00:11 +0200 Gerhard Hoffmann wrote: > Somewhere you'll have to produce sharp differential edges and this > semi-analogue stuff is probably hard on a chip shared with thousands of > other gates and a digital process. Going differentially into the chip will > reduce the effects of ground bounce etc a lot. It's a full custom ASIC, with only the circuitry to support the TDC around it. The digital logic after the TDC are only there to convert the thermometer code we get from the TDC into binary. There is also a bit of arming logic and various other small bits, but nothing substantial. We are also going to split the power supplies on the chip for the TDC and the digital part, to isolate them even further from eachother. > This is what you can expect from an ADCMP580 on a homebrew > board and soldered-in semi rigid cable: I was actually thinking about the ADCMP572. The datasheet unfortunately does not specify a variation of delay between devices, not even a maximum propagation delay. Guessing from the typical propagation delay of 150ps, the 35ps rise/fall time and the 10ps deterministic jitter, it is probably safe to assume that the device to device variation is in the order of 20 to 100ps. This means, in best case this device will work, in worst case we would need to enlarge our measurement range to at least 400ps. I am now trying to figure out whether we have any other posibilites to get path delay variations down. > Some will cry: eeek - a comparator, and an ECL or CML one at that, but > in the end > it is just a differential amplifier like that Wenzel design, made by > people who > know their SiGe process. I've seen worse :-) We are currently designing CML in a pure digital, Si 65nm process (nothing fancy, not even SOI). So, having a CML chip as input source isn't going to kill us, quite to the contrary. > If you have a slowly rising source, you'll need multi-stage slope > amplification > and low pass filtering in Collins style anyway which will be safer to do > off-chip. Slope is reasonably fast. I was thinking about using an LMK00101 into an 50R load (~10cm of coax). This should provide us with <500ps of rise/fall time. > If you can specify the interface, go for something speedy, then > the guys who do the the signal source have the hard time and > can be pointed at. :-)) The "guys who do the signal source", that's me :-) As I am the only one in the group with significant experience in both analog and digital electronics, I have to not only come up with a feasible overall design, but also figure out solution for all these pesky details. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Single ended or differential input to TDC chip
On Mon, 27 Mar 2017 18:05:13 +0200, you wrote: >... > >* Single-ended input in a chip might lead to shifting ground potential > on the chip and thus to measurment jitter. > >... This is a major problem I have run across before. Various single ended logic families have great noise immunity as far as proper functioning but their limited PSRR (power supply rejection ratio) becomes vary apparent when power supply noise shifts their logic thresholds resulting in additional jitter. Depending on the logic family, single ended inputs may be referenced to one or the other supply or to both. For this reason alone I would use differential inputs which can always be driven single ended in less demanding applications. Some ECL parts include a "reference" input/output for their logic inputs and might also be suitable. Powering critical logic with a reference grade supply voltage and avoiding ground loops helps mitigate the effects of poor PSRR. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Single ended or differential input to TDC chip
Hi Eventually you will want multiple inputs to any chip like this. The more I/o the more crosstalk. Properly done, differential inputs will reduce your crosstalk quite a bit. You might as well debug that part of it now. Bob > On Mar 27, 2017, at 9:05 AM, Attila Kinali wrote: > > Hi, > > We (the group I am with and a group at TU Vienna) are currently designing > an ASIC (digital 65nm process) that will contain a TDC part. The TDC will > be a simple delay line TDC design using differential buffers, which we > expect to give us something in the order of 20ps of resolution (hopefully > better, but we will not know until we get post-layout simulation data). > We are loosely following the design CERN came up with for their new TDC > chip[1]. > > > Now, the TDC expects a differential input, but the system gets single-ended > pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not > fixed yet, ie can be freely choosen). I can either convert these single-ended > signals into differential off-chip or on-chip. Unfortunately, I lack knowledge > and experience to judge either approach. The issues I see are: > > * Single-ended input in a chip might lead to shifting ground potential > on the chip and thus to measurment jitter. > * There are different architectures to preform the single-ended to > differential > conversion on-chip, but I have no clue which one to choose or even how > to judge them without extensive simulations for which we do not have the > time, know-how and probably not even the tools. > * Conversion to differential off-chip means another component off-chip > that might introduce additional delay uncertainty (our application is > very sensitive to that) and an unknown amount of jitter. > > My google foo has been so far not strong enough to find answers to these > questions. > > I would appreciate if someone could give me some hints in this matter > or tell me where I could find appropriate literature and maybe even > tell me whether I am missing anything. > > Thanks in advance > > Attila Kinali > > [1] > https://indico.cern.ch/event/228972/contributions/1539621/attachments/378552/526492/TDC_TWEPP_2013.pdf > > -- > It is upon moral qualities that a society is ultimately founded. All > the prosperity and technological sophistication in the world is of no > use without that foundation. > -- Miss Matheson, The Diamond Age, Neil Stephenson > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Single ended or differential input to TDC chip
Hi, Attila! Somewhere you'll have to produce sharp differential edges and this semi-analogue stuff is probably hard on a chip shared with thousands of other gates and a digital process. Going differentially into the chip will reduce the effects of ground bounce etc a lot. This is what you can expect from an ADCMP580 on a homebrew board and soldered-in semi rigid cable: < https://www.flickr.com/photos/137684711@N07/33305853110/in/album-72157662535945536/ > Some will cry: eeek - a comparator, and an ECL or CML one at that, but in the end it is just a differential amplifier like that Wenzel design, made by people who know their SiGe process. If you have a slowly rising source, you'll need multi-stage slope amplification and low pass filtering in Collins style anyway which will be safer to do off-chip. If you can specify the interface, go for something speedy, then the guys who do the the signal source have the hard time and can be pointed at. :-)) regards, Gerhard Am 27.03.2017 um 18:05 schrieb Attila Kinali: Hi, We (the group I am with and a group at TU Vienna) are currently designing an ASIC (digital 65nm process) that will contain a TDC part. The TDC will be a simple delay line TDC design using differential buffers, which we expect to give us something in the order of 20ps of resolution (hopefully better, but we will not know until we get post-layout simulation data). We are loosely following the design CERN came up with for their new TDC chip[1]. Now, the TDC expects a differential input, but the system gets single-ended pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not fixed yet, ie can be freely choosen). I can either convert these single-ended signals into differential off-chip or on-chip. Unfortunately, I lack knowledge and experience to judge either approach. The issues I see are: * Single-ended input in a chip might lead to shifting ground potential on the chip and thus to measurment jitter. * There are different architectures to preform the single-ended to differential conversion on-chip, but I have no clue which one to choose or even how to judge them without extensive simulations for which we do not have the time, know-how and probably not even the tools. * Conversion to differential off-chip means another component off-chip that might introduce additional delay uncertainty (our application is very sensitive to that) and an unknown amount of jitter. My google foo has been so far not strong enough to find answers to these questions. I would appreciate if someone could give me some hints in this matter or tell me where I could find appropriate literature and maybe even tell me whether I am missing anything. Thanks in advance Attila Kinali [1] https://indico.cern.ch/event/228972/contributions/1539621/attachments/378552/526492/TDC_TWEPP_2013.pdf ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Single ended or differential input to TDC chip
Hi, On 03/27/2017 06:05 PM, Attila Kinali wrote: Hi, We (the group I am with and a group at TU Vienna) are currently designing an ASIC (digital 65nm process) that will contain a TDC part. The TDC will be a simple delay line TDC design using differential buffers, which we expect to give us something in the order of 20ps of resolution (hopefully better, but we will not know until we get post-layout simulation data). We are loosely following the design CERN came up with for their new TDC chip[1]. Now, the TDC expects a differential input, but the system gets single-ended pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not fixed yet, ie can be freely choosen). I can either convert these single-ended signals into differential off-chip or on-chip. Unfortunately, I lack knowledge and experience to judge either approach. The issues I see are: * Single-ended input in a chip might lead to shifting ground potential on the chip and thus to measurment jitter. * There are different architectures to preform the single-ended to differential conversion on-chip, but I have no clue which one to choose or even how to judge them without extensive simulations for which we do not have the time, know-how and probably not even the tools. * Conversion to differential off-chip means another component off-chip that might introduce additional delay uncertainty (our application is very sensitive to that) and an unknown amount of jitter. My google foo has been so far not strong enough to find answers to these questions. I would appreciate if someone could give me some hints in this matter or tell me where I could find appropriate literature and maybe even tell me whether I am missing anything. There is benefit of going diffrential over the chip border, and there is plenty of examples where it has been used for great benefit. Make sure to keep ground attached to neighbor pins/balls. When we run 10 Gb/s with low jitter (7 ps RMS max), then we need and use differential signals. Single-mode to differential mode conversion can be done off-chip if needed, and it may suffice with very simple setups, allowing for passive components. What you might want to look at iis if you have a good CMRR of your differential input or if you should have a inputstage to get better margin. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Single ended or differential input to TDC chip
In message <20170327180513.307125ed395c80e4e6490...@kinali.ch>, Attila Kinali w rites: >Now, the TDC expects a differential input, but the system gets single-ended >pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not >fixed yet, ie can be freely choosen). I can either convert these single-ended >signals into differential off-chip or on-chip. Unfortunately, I lack knowledge >and experience to judge either approach. The issues I see are: I would give the chip differential inputs, because that way it can also be used, without loss of performance, on future differential signals. -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 p...@freebsd.org | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Single ended or differential input to TDC chip
Attila Differential inputs, either LVDS or PECL compatible, together with a fast single supply comparator for the CMOS to PECL to LVDS/differential PECL would be the conservative approach. Ultra fast comparators with aaa delay belo 2ns are readilyy available. Alternatively a CMOS to LVDS converter like: http://www.analog.com/media/en/technical-documentation/data-sheets/ADN4661.pdf could be used. There are commercial TDCs that claim similar resolution that use CMOS inputs. One could provide both CMOS and differential inputs so that if the CMOS inputs prove problematic one could just use the differential inputs. Bruce > > On 28 March 2017 at 05:05 Attila Kinali wrote: > > Hi, > > We (the group I am with and a group at TU Vienna) are currently designing > an ASIC (digital 65nm process) that will contain a TDC part. The TDC will > be a simple delay line TDC design using differential buffers, which we > expect to give us something in the order of 20ps of resolution (hopefully > better, but we will not know until we get post-layout simulation data). > We are loosely following the design CERN came up with for their new TDC > chip[1]. > > Now, the TDC expects a differential input, but the system gets > single-ended > pulses as input (50R coax input, level likely to be CMOS 3.3V, but level > not > fixed yet, ie can be freely choosen). I can either convert these > single-ended > signals into differential off-chip or on-chip. Unfortunately, I lack > knowledge > and experience to judge either approach. The issues I see are: > > * Single-ended input in a chip might lead to shifting ground potential > on the chip and thus to measurment jitter. > * There are different architectures to preform the single-ended to > differential > conversion on-chip, but I have no clue which one to choose or even > how > to judge them without extensive simulations for which we do not > have the > time, know-how and probably not even the tools. > * Conversion to differential off-chip means another component off-chip > that might introduce additional delay uncertainty (our application > is > very sensitive to that) and an unknown amount of jitter. > > My google foo has been so far not strong enough to find answers to these > questions. > > I would appreciate if someone could give me some hints in this matter > or tell me where I could find appropriate literature and maybe even > tell me whether I am missing anything. > > Thanks in advance > > Attila Kinali > > [1] > https://indico.cern.ch/event/228972/contributions/1539621/attachments/378552/526492/TDC_TWEPP_2013.pdf > -- > It is upon moral qualities that a society is ultimately founded. All > the prosperity and technological sophistication in the world is of no > use without that foundation. > -- Miss Matheson, The Diamond Age, Neil Stephenson > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Single ended or differential input to TDC chip
Hi, We (the group I am with and a group at TU Vienna) are currently designing an ASIC (digital 65nm process) that will contain a TDC part. The TDC will be a simple delay line TDC design using differential buffers, which we expect to give us something in the order of 20ps of resolution (hopefully better, but we will not know until we get post-layout simulation data). We are loosely following the design CERN came up with for their new TDC chip[1]. Now, the TDC expects a differential input, but the system gets single-ended pulses as input (50R coax input, level likely to be CMOS 3.3V, but level not fixed yet, ie can be freely choosen). I can either convert these single-ended signals into differential off-chip or on-chip. Unfortunately, I lack knowledge and experience to judge either approach. The issues I see are: * Single-ended input in a chip might lead to shifting ground potential on the chip and thus to measurment jitter. * There are different architectures to preform the single-ended to differential conversion on-chip, but I have no clue which one to choose or even how to judge them without extensive simulations for which we do not have the time, know-how and probably not even the tools. * Conversion to differential off-chip means another component off-chip that might introduce additional delay uncertainty (our application is very sensitive to that) and an unknown amount of jitter. My google foo has been so far not strong enough to find answers to these questions. I would appreciate if someone could give me some hints in this matter or tell me where I could find appropriate literature and maybe even tell me whether I am missing anything. Thanks in advance Attila Kinali [1] https://indico.cern.ch/event/228972/contributions/1539621/attachments/378552/526492/TDC_TWEPP_2013.pdf -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
