Re: [time-nuts] homebrew counter new board test result
Tom, On 02/28/2015 06:10 PM, Tom Van Baak wrote: A good paper to read about the trouble when DUT is close (or equal to REF) is: http://literature.cdn.keysight.com/litweb/pdf/5990-9189EN.pdf Isolating Frequency Measurement Error and Sourcing Frequency Error near the Reference Frequency Harmonics Nice reading and illustration of the problem. It does not go into explain where these errors come from. I especially like that he worked on an offset frequency to handle source issues and that he elaborates with both time-base time and frequency offset, as well as average and peak-to-peak values. Have you seen any papers going into depth about that? The Robert Leiby (5990-9189EN) paper was a real find. Agilent sent it to me after I ran tests of their new 53230A counter. I had two of them on loan (TCXO and OCXO) and the closer I looked the less I was impressed. The one feature that was a show-stopper for me was that the TCXO version would not outperform the OCXO version even if you gave it a BVA or maser as external reference to the counter. That means in order to get decent performance out of the 53230A you must buy the overpriced OCXO version of the counter. I wonder if anyone else has run into this? Maybe my eval units were out of spec. Or, I wonder if anyone has opened their 53230A and hacked the timebase PLL to overcome this problem? Anyway, that led to me checking out a pile of 53132A counters to see how well they performed. Yes, it makes good sense to follow up with those. The paper is indeed a good find. In these tests I like to use slightly drifting, ultrastable, independent inputs instead of the old BNC tee trick where CH1=CH2 or CH1=CH2=REF. What you want is to see is not only the RMS noise in a measurement, but also how consistent the TI measurements are across the entire fundamental period of the inputs or timebase. Indeed. The time error over the time-base period is relevant to measure, but also you have cross-talk from time-base into channels as well as cross-talk between channels. For the frequency case, you might not expect there to be cross-talk, but there will be if the frequency measure uses the start and stop channels. For my test I used two ultrastable sources with 1e-12 or 1e-11 frequency offset. At 1e-11 you can scan an entire 100 ns period in 10,000 seconds (under 3 hours). I'd have to look at my notes to see what I did with the REF input. I think I tried REF=CH1 and REF=CH2 and REF=3rd independent source. But the main goal was to see the interaction between CH1 and CH2 because that's the mode used by any TI measurement. Indeed. It can be hard to separate the non-linearity of a channel (over the time-base period) from the cross-talk from reference to channel. The non-linearity usually has a periodicity over the time-base reference due to the use of a coarse counter frequency (such as 90, 100, 200 and 500 MHz) where as some (HP5335A, HP5334A/B) uses the time-base directly as coarse counters. Enrico have been looking at post-processing filtering, and it's effects. I just haven't seen any paper giving much about how cross-talk and such affects non-linearity and post-processing such as frequency reading and ADEV. I have my own model from experience and various sources, but not seen anything comprehensive. Cheers, Magnus Right, there's no paper that I could find yet. Instead I was planning on taking several models of popular high-end TI counters (SR620, HP5370, CNT-91, 53132A, 53230A) and run them all through the same offset/linearity test to investigate the fine structure of their measurement errors, as was done in the Leiby paper. If you have some measurement setup suggestions beyond what I already did with the 53132 counters, let me know. Leiby's paper is focused on the frequency measurement and in particular the non-linearities of the hardware in relation to frequency measurements. The underlying model is time errors and considering that the frequency estimate f = events/(t_stop - t_start) the non-linearities in the time estimations t_stop and t_start will be subtracted from each other. As the number of complete cycles of error increases with tau, the remaining time error within such a period will be divided by a tau. Consider the period formula t_period = (t_stop - t_start)/events Consider that events = tau*f_1, t_start = 0 + te_start, t_stop = tau + te_stop (approximation for understanding) we get t_period = 1/f_1 + (te_stop - te_start)/(tau*f_1) No wonder that the period (and thus frequency) measure errors varies with tau and measured frequency. Rather than measuring with free-floating oscillators, I have been considering using frequency syntesizers as in Leiby's article and programmable delays. That way I can stay at a particular delay and bang the same point and get statistics. The histogram will give me information about the offset and coupling properties. I think this could be an interesting paper maybe.
Re: [time-nuts] homebrew counter new board test result
Tom, On 02/27/2015 01:18 PM, Tom Van Baak wrote: 2) Does any one have the test data of 12 digit/s counter when DUT=REF? I want to know the gap between mine and a commercial counter. Thanks Li Ang I did a lot of testing of 53132A counters a while back to research how well the interpolators worked and to measure the interference when CH1 gets too close to CH2. There was some discussion on the list about this at the time. For the context, see: https://www.febo.com/pipermail/time-nuts/2014-April/084670.html For the plots, see: http://leapsecond.com/pages/53132/ A good paper to read about the trouble when DUT is close (or equal to REF) is: http://literature.cdn.keysight.com/litweb/pdf/5990-9189EN.pdf Isolating Frequency Measurement Error and Sourcing Frequency Error near the Reference Frequency Harmonics Nice reading and illustration of the problem. It does not go into explain where these errors come from. I especially like that he worked on an offset frequency to handle source issues and that he elaborates with both time-base time and frequency offset, as well as average and peak-to-peak values. Have you seen any papers going into depth about that? Enrico have been looking at post-processing filtering, and it's effects. I just haven't seen any paper giving much about how cross-talk and such affects non-linearity and post-processing such as frequency reading and ADEV. I have my own model from experience and various sources, but not seen anything comprehensive. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
A good paper to read about the trouble when DUT is close (or equal to REF) is: http://literature.cdn.keysight.com/litweb/pdf/5990-9189EN.pdf Isolating Frequency Measurement Error and Sourcing Frequency Error near the Reference Frequency Harmonics Nice reading and illustration of the problem. It does not go into explain where these errors come from. I especially like that he worked on an offset frequency to handle source issues and that he elaborates with both time-base time and frequency offset, as well as average and peak-to-peak values. Have you seen any papers going into depth about that? The Robert Leiby (5990-9189EN) paper was a real find. Agilent sent it to me after I ran tests of their new 53230A counter. I had two of them on loan (TCXO and OCXO) and the closer I looked the less I was impressed. The one feature that was a show-stopper for me was that the TCXO version would not outperform the OCXO version even if you gave it a BVA or maser as external reference to the counter. That means in order to get decent performance out of the 53230A you must buy the overpriced OCXO version of the counter. I wonder if anyone else has run into this? Maybe my eval units were out of spec. Or, I wonder if anyone has opened their 53230A and hacked the timebase PLL to overcome this problem? Anyway, that led to me checking out a pile of 53132A counters to see how well they performed. In these tests I like to use slightly drifting, ultrastable, independent inputs instead of the old BNC tee trick where CH1=CH2 or CH1=CH2=REF. What you want is to see is not only the RMS noise in a measurement, but also how consistent the TI measurements are across the entire fundamental period of the inputs or timebase. For my test I used two ultrastable sources with 1e-12 or 1e-11 frequency offset. At 1e-11 you can scan an entire 100 ns period in 10,000 seconds (under 3 hours). I'd have to look at my notes to see what I did with the REF input. I think I tried REF=CH1 and REF=CH2 and REF=3rd independent source. But the main goal was to see the interaction between CH1 and CH2 because that's the mode used by any TI measurement. Enrico have been looking at post-processing filtering, and it's effects. I just haven't seen any paper giving much about how cross-talk and such affects non-linearity and post-processing such as frequency reading and ADEV. I have my own model from experience and various sources, but not seen anything comprehensive. Cheers, Magnus Right, there's no paper that I could find yet. Instead I was planning on taking several models of popular high-end TI counters (SR620, HP5370, CNT-91, 53132A, 53230A) and run them all through the same offset/linearity test to investigate the fine structure of their measurement errors, as was done in the Leiby paper. If you have some measurement setup suggestions beyond what I already did with the 53132 counters, let me know. Thanks, /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
2) Does any one have the test data of 12 digit/s counter when DUT=REF? I want to know the gap between mine and a commercial counter. Thanks Li Ang I did a lot of testing of 53132A counters a while back to research how well the interpolators worked and to measure the interference when CH1 gets too close to CH2. There was some discussion on the list about this at the time. For the context, see: https://www.febo.com/pipermail/time-nuts/2014-April/084670.html For the plots, see: http://leapsecond.com/pages/53132/ A good paper to read about the trouble when DUT is close (or equal to REF) is: http://literature.cdn.keysight.com/litweb/pdf/5990-9189EN.pdf Isolating Frequency Measurement Error and Sourcing Frequency Error near the Reference Frequency Harmonics See also: https://www.febo.com/pipermail/time-nuts/2012-October/070737.html /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
Hi Thanks about the explanation on hysteresis and comparator. The PM6685(http://assets.fluke.com/manuals/PM6685__smeng.pdf ) is using 74ALS176 as the frontend for REF channel. So I tried that on the previous board. The performance is better with 74ALS176+74LVC2G14 than MC100LVELT22 at the sin wave input condition. Since the stdev has reached the spec of TDC chip, I need to do some more experiments with these chips next. There are some questions I want to ask: 1) Does the trigger interval need to be very accurate? Now I am using software scheduler to generate the interval, it might vary few ms. 2) Does any one have the test data of 12 digit/s counter when DUT=REF? I want to know the gap between mine and a commercial counter. Thanks Li Ang 2015-02-27 4:30 GMT+08:00 Charles Steinmetz csteinm...@yandex.com: Magnus wrote: A bit of hysteresis can help to avoid flipping back, but considering the type of signal, it passes the mid-point (0 V) at highest slew-rate, so there is very little risk of flipping back and fourth in the first place, so hysteresis may not even be needed. A 1 Vrms, 10MHz sine wave has a zero-cross slew rate of 88v/uS (88mV/nS). One would think that would be enough to avoid indecision in a comparator with 5-10nS of propagation delay. However, the LT1016 (10nS) is prone to jitter problems when operating as a ZCD with such a signal, and external hysteresis does not help much because it is delayed by 10nS. (The problem appears to be that the front end has some indecision at this input slew rate that happens faster than the propagation delay to the output -- but this is just an inference because the internal nodes are not accessible for measurement.) For this application, the small amount of internal hysteresis of the LT1719 and LT1720 is very beneficial. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
On Wed, 25 Feb 2015 01:44:40 -0800 Hal Murray hmur...@megapathdsl.net wrote: The Schmitt trigger mostly avoids glitches on the output. Does it do anything to reduce timing noise if the input signal is clean enough that it doesn't make any glitches? A Schmitt Trigger avoids glitches at the input, not the output. It does prevent the input circuitry in the gate to switch back and forth between 0 and 1, or, even worse, from going metastable. This by itself might improve timing, if you have problems due to low slew rate. But as Magnus wrote, in general does not improve things. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
Hi Charles, On 02/26/2015 02:46 AM, Charles Steinmetz wrote: The Schmitt trigger mostly avoids glitches on the output. Does it do anything to reduce timing noise if the input signal is clean enough that it doesn't make any glitches? No, it just avoids flipping state at the transition point(s). Note also that the hysteresis of logic gates with Schmitt inputs is WAY too much to be optimal for squaring sine waves (300mV minimum, typically 400 to 450mV, for the 74LVC14). Fast comparators with internal hysteresis are optimized for that sort of thing (the LT1719 and LT1720 have a few mV of hysteresis). Indeed. If you think about what large hysteresis does on a sine, it moves the trigger points further up and down on the sine from the mid-point, which moves them into lower slew-rate areas. If you are picky, amplitude variations will then also move the phase more than mid-point triggers. A bit of hysteresis can help to avoid flipping back, but considering the type of signal, it passes the mid-point (0 V) at highest slew-rate, so there is very little risk of flipping back and fourth in the first place, so hysteresis may not even be needed. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
Magnus wrote: A bit of hysteresis can help to avoid flipping back, but considering the type of signal, it passes the mid-point (0 V) at highest slew-rate, so there is very little risk of flipping back and fourth in the first place, so hysteresis may not even be needed. A 1 Vrms, 10MHz sine wave has a zero-cross slew rate of 88v/uS (88mV/nS). One would think that would be enough to avoid indecision in a comparator with 5-10nS of propagation delay. However, the LT1016 (10nS) is prone to jitter problems when operating as a ZCD with such a signal, and external hysteresis does not help much because it is delayed by 10nS. (The problem appears to be that the front end has some indecision at this input slew rate that happens faster than the propagation delay to the output -- but this is just an inference because the internal nodes are not accessible for measurement.) For this application, the small amount of internal hysteresis of the LT1719 and LT1720 is very beneficial. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
att...@kinali.ch said: Yes. You should not use a logic gates with analog input signals. Using a 74LVC14 helps due to its Schmitt-Trigger input. I think the proper solution here would be to use a high speed comparator instead (with hysteresis). The Schmitt trigger mostly avoids glitches on the output. Does it do anything to reduce timing noise if the input signal is clean enough that it doesn't make any glitches? -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
Hi Attila Thanks for the history about 74 series. BTW, The result.gif is a TDEV chart. I only know that different K means different kinds of noise. I don't know what it means if the turnning corner comes earlier or latter. Hi Charles Thanks for the circuit. I have some LT1016 in hand, I will evaluate with it. 2015-02-25 0:02 GMT+08:00 Attila Kinali att...@kinali.ch: On Tue, 24 Feb 2015 14:43:10 +0800 Li Ang lll...@gmail.com wrote: I saw people talking about using 74AC to square the signal, what's the difference between 74LVC and 74AC? 74AC is not easy to get. These are different families of chip production. You can see the 74HCxx as the grandfather, 74ACxx as the father and the 74LVCxx as the son. IIRC the AC (Advanced CMOS) was introduced in the 80s. The process which they were produced got superseeded and also the voltage levels went down. The LVC (Low Voltage CMOS) and LVX families are the current choice for logic gates. The main difference is that the node size (those nm measures people boast with, when they talk about chips these days) went down and with that the threshold voltage of the FETs and the maximum voltage the chips can withstand. Of course there are differences in the timing specs as well. TI's Logic Guide[1] and their Logic Migration Guide[2] contain additional information. Attila Kinali [1] http://www.ti.com/lit/sg/sdyu001aa/sdyu001aa.pdf [2] http://www.ti.com/lit/ml/scyb032/scyb032.pdf -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
You might wish to look at the LTC6957 as your input shaper device. I think you'll find it far superior to either 74xx logic or fast comparator such as the LT1016. Cheers, Dave ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
Li Ang wrote: I have some LT1016 in hand, I will evaluate with it. I know it is tempting to use what is in hand rather than source new parts, but for squaring 10MHz the LT1719 and LT1720 are much better suited than the LT1016. They have internal hysteresis, which makes them much easier to apply, and they are more than twice as fast as the 1016 (4 to 4.5nS vs. 10nS), which is a real consideration at 10MHz (50nS half-period). The 1016 is quite fussy -- even with good construction techniques and bypassing, they tend to oscillate and exhibit other funny behaviors. I think you will find that using the LT1719 or LT1720 gives much better results. Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
The Schmitt trigger mostly avoids glitches on the output. Does it do anything to reduce timing noise if the input signal is clean enough that it doesn't make any glitches? No, it just avoids flipping state at the transition point(s). Note also that the hysteresis of logic gates with Schmitt inputs is WAY too much to be optimal for squaring sine waves (300mV minimum, typically 400 to 450mV, for the 74LVC14). Fast comparators with internal hysteresis are optimized for that sort of thing (the LT1719 and LT1720 have a few mV of hysteresis). Best regards, Charles ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
Hi Hal, On 02/25/2015 10:44 AM, Hal Murray wrote: att...@kinali.ch said: Yes. You should not use a logic gates with analog input signals. Using a 74LVC14 helps due to its Schmitt-Trigger input. I think the proper solution here would be to use a high speed comparator instead (with hysteresis). The Schmitt trigger mostly avoids glitches on the output. Does it do anything to reduce timing noise if the input signal is clean enough that it doesn't make any glitches? No, it just avoids flipping state at the transition point(s). The trigger jitter problem remains the same, regardless if it is at one voltage (comparator with no hysteresis) or two voltages (comparator with hysteresis aka Schmitt trigger), the slew-rate at the comparator voltage and the noise will interact to create trigger jitter. If you want to improve on that the main solution is to improve slew rate, but naturally careful filtering can help. It is all to often that I have encountered people to confuse the Schmitt-trigger for improving the timing jitter. It's movement in two different domains, voltage (schmitt trigger) and time (trigger jitter). Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
Hi Magnus, The C channel is the SMA on the back of the PCB. The input of 74LVC2G14 is set to 0.5vcc with 1k resistor and AC coupled with 100nF. Today I compared the performance 74LVC2G04, 74LVC2G17, 74LVC2G14. http://www.qsl.net/b/bi7lnq//freqcntv4.1/test/20150224/ . I saw people talking about using 74AC to square the signal, what's the difference between 74LVC and 74AC? 74AC is not easy to get. Thanks Li Ang 2015-02-24 5:36 GMT+08:00 Magnus Danielson mag...@rubidium.dyndns.org: Dear Li Ang, Nice to have you back reporting on your progress! Now, you have some pretty impressive performance going on there. Looks like a nice little unit too. Is the C-channel the SMA on the back of the PCB? How did you wire up the 74LVC2G14? While it is tempting to use both channels in it, don't if you want to keep cross-talk between channels low. Cheers, Magnus On 02/23/2015 02:10 PM, Li Ang wrote: Hi, I'm back. I have been testing my new borad for days. Compared to previous version, this board makes the PCB track of signals far from each other and replaces LDO for TDC with LP5907. CH_A: simple resistor bias and ac couple front end, CH_B: CH_A+MC100LVELT22 LVPECL , CH_C: CH_A+74LVC2G14 . At first, the result is worse than previous board. Using CH_B as the REF and DUT source, the stdev of the phase measurement is about 160ps. The old board can reach about 70ps. CH_A and CH_C are way much better than CH_B. That bothers me for days. Today, I use the 74LVC2G14 to square the signal from MV89A, and do the same test. For all three channel, the stdevs are about 37ps. The spec of TDC_GP22 is 35ps. And now the performance looks a little bit better than the previous board. It looks like that the jitter of MC100LVELT22 is much bigger at slow slew rate. It seems that next step is to play with the front end. The raw data is uploaded to http://www.qsl.net/b/bi7lnq/ freqcntv4.1/test/20150222/ The pic of this version is uploaded to http://www.qsl.net/b/bi7lnq/ freqcntv4.1/pic/ Regards Li Ang ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/ mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] homebrew counter new board test result
On Mon, 23 Feb 2015 21:10:30 +0800 Li Ang 379...@qq.com wrote: Thanks for the update! It looks like that the jitter of MC100LVELT22 is much bigger at slow slew rate. Yes. You should not use a logic gates with analog input signals. Using a 74LVC14 helps due to its Schmitt-Trigger input. I think the proper solution here would be to use a high speed comparator instead (with hysteresis). Do you have an Idea why the ADEV diverges between 10s and 100s? Are those temperature effects on the different input configurations? Or is it an artefact of the measurement? Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] homebrew counter new board test result
Hi, I'm back. I have been testing my new borad for days. Compared to previous version, this board makes the PCB track of signals far from each other and replaces LDO for TDC with LP5907. CH_A: simple resistor bias and ac couple front end, CH_B: CH_A+MC100LVELT22 LVPECL , CH_C: CH_A+74LVC2G14 . At first, the result is worse than previous board. Using CH_B as the REF and DUT source, the stdev of the phase measurement is about 160ps. The old board can reach about 70ps. CH_A and CH_C are way much better than CH_B. That bothers me for days. Today, I use the 74LVC2G14 to square the signal from MV89A, and do the same test. For all three channel, the stdevs are about 37ps. The spec of TDC_GP22 is 35ps. And now the performance looks a little bit better than the previous board. It looks like that the jitter of MC100LVELT22 is much bigger at slow slew rate. It seems that next step is to play with the front end. The raw data is uploaded to http://www.qsl.net/b/bi7lnq/freqcntv4.1/test/20150222/ The pic of this version is uploaded to http://www.qsl.net/b/bi7lnq/freqcntv4.1/pic/ Regards Li Angattachment: results.gif ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
