Re: [time-nuts] low noise multiplication to 100 MHz

[Chuck Harris]

Back years ago I was a dealer for Aoyue rework stations,
so I use one of those.  They are all knockoff's of Hakko
stations, and frankly any that has a servo'd heat source
would do nicely.  What I sold had a digital temperature
control, and a flow meter to show how fast the air was
flowing kind of important to know, but you can wing
it easily enough.

There are scads of special tips available for all sorts
of different package types.  For small stuff, I use the
smallest round air nozzle... which is about 1/8 inch.  If
I am doing a large QPF package, I will often take the time
to put the right manifold/nozzle on the unit.  It depends
a lot on whether I am just scrapping parts off of a board,
or am trying to save the part/board.

Under board heating is very important to your success.

Back when I sold Aoyue, they were going for about $230,
which was pretty reasonable.  You can get them direct from
China cheaper than that... which is why I don't sell them
anymore.

-Chuck Harris

Bryan _ wrote:

Chuck, what do you use for a hot air source. The good ones are very expensive.
Wonder if there is something for the hobbyist. Have seen a few repair videos 
where
they used just used a hot air stripper. I had to yank a couple SMD resistors 
off a
board the other day and had to use two soldering irons at each end of the 
resistor
. If they are small enough you can add a glob of solder to the whole 
resistor,
so both ends will melt. Cheers

-=Bryan=-

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Re: [time-nuts] low noise multiplication to 100 MHz

[Herbert Poetzl]

On Tue, Jan 26, 2016 at 06:57:54AM +, Mark Sims wrote:
> Actually not hard to do... lay out circuit board (free version
> of Eagle), have boards fab'd at Oshpark.com or your favorite
> Chinese proto shop (I like gojgo.com). Have solder paste
> stencil made at oshstencils.com. Squeege solder paste down with
> a credit card. Place components by hand. Reflow board with a
> modified toaster oven, electric skillet, hot air tool, etc.

Because I build and solder SMD boards on a regular basis,
I would like to add a few hints and tricks here which can 
simplify the task significantly:

For one-sided designs, the skillet method is really simple
and if the temperature is right, gives excellent results.

There are a bunch of ceramic heater elements (PTC) on eBay
and they often provide the perfect temperature stability
without the need for actual regulation (i.e. connect them
to a current limited power supply and it will reach a 
specific temperature at a given current).

As they are small, they work perfectly under a microscope
and you can not only watch the solder reflow, you can also
move the parts around in the liquid solder.

Most SMD components can also be soldered by hand with a
soldering iron, which doesn't even have to have a delicate
tip because there is an easy way with the help of (usually
red) thixotropic glue.

You first place a little dot or line of glue where the SMD
component will go (obviously not on the pads but between :) 
and then you place the component (down to 0201 imperial) 
with tweezers or a vacuum pick-up tool (doesn't need to be
extremely precise at this point) and now you can move the 
part into its final position with the help of an acupuncture 
needle.

Once all the components have been placed (the glue stays
liquid for several hours, probably days) and oriented/aligned
perfectly, you heat up the entire board to 120-160°C for
about 10 minutes which polymerizes the glue and thus fixes 
the parts in place.

You can then apply a good amount of solder on all the tiny 
pads to make sure that they are well connected. Heating the
entire PCB to around 150-180°C will help a lot and usually
doesn't harm the board or components (iron temperature can
be as low as 280°C which reduces the danger of overheating
dramatically). Do not worry about accidential bridges and
excessive solder, this will be fixed in the next step.

Once the parts have been soldered in place, you get a solder
wick (I prefer to use one of those highly flexible silicone
wires with hundreds of tiny conductors - you need to strip
it down to the copper wires first) and some flux to remove 
excessive solder from the joints.

After that, clean up the board (i.e. remove flux and other
stuff) with a flux remover or alcohol (isopropanol).

Here a few examples what can be done without hot air gun or 
reflow oven:

http://vserver.13thfloor.at/Stuff/AXIOM/pmod_assembled_top_600dpi.png
http://vserver.13thfloor.at/Stuff/AXIOM/pmod_assembled_bottom_600dpi.png
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/pmod_clock_nosma.png
https://wiki.apertus.org/images/4/42/Axiom_Beta_Plugin_Module_1x_HDMI_v0.4_BOT.jpg
https://wiki.apertus.org/images/c/c0/BetaSensorBoardZIF_0.18_2.jpg
https://wiki.apertus.org/images/d/da/BetaMainboard_0.32_BOTTOM.jpg
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/axiom_beta_power_board_v0.18_r1.0_fix01.jpg
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/axiom_beta_power_board_v0.18_r1.0_fix02.jpg

And some links to the mentioned helpers:

http://www.ebay.com/itm/PTC-heating-element-100W-AC-DC-12V-constant-temperature-60-21mm-/151727264825
www.ebay.com/itm/AC-DC-12V-40W-PTC-Heater-Element-Thermostat-Heating-Plate-for-Warmer-Hot-Melter-/252212420224
www.ebay.com/itm/1Pc-40g-30mL-SMD-SMT-PCB-BGA-IC-Stencil-Paste-Dispenser-Red-Glue-Effective-Work-/321845571034
http://uk.farnell.com/multi-contact/60-7180-21/litze-blank-hochflex-0-5qmm-tpe/dp/135276
http://www.ebay.com/itm/5pcs-BGA-SMD-Soldering-Paste-Flux-Grease-Volume-10cc-RMA-223-/281358896876
http://uk.farnell.com/pro-power/ppc120/propower-flussmittelentfernerspray/dp/1736213

If you have any problems or general questions, do not
hesitate to email me.

Best,
Herbert

> If you want to get anywhere in electronics these days, you
> really need to get set up to do simple SMD work. It's not hard
> or expensive. The days of point to point wiring of vacuum
> tubes to terminal strips be looong gone. Through-hole and DIP
> packages are not far behind.
> 
> ---
> > There are other neat parts out there but again who is able to 
> solder  them.   
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[time-nuts] low noise multiplication to 100 MHz

[Mark Sims]

Actually not hard to do...  lay out circuit board (free version of Eagle),  
have boards fab'd at Oshpark.com or your favorite Chinese proto shop (I like 
gojgo.com).   Have solder paste stencil made at oshstencils.com.  Squeege 
solder paste down with a credit card.  Place components by hand.  Reflow board 
with a modified toaster oven,  electric skillet,  hot air tool, etc.

If you want to get anywhere in electronics these days,  you really need to get 
set up to do simple SMD work.  It's not hard or expensive.   The days of point 
to point wiring of vacuum tubes to terminal strips be looong gone.  
Through-hole and DIP packages are not far behind.

---
> There are other neat parts out there but again who is able to 
solder  them. 
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Re: [time-nuts] low noise multiplication to 100 MHz

[Bob Camp]

Hi



> On Jan 25, 2016, at 8:36 PM, Gerhard Hoffmann  wrote:
> 
> Am 25.01.2016 um 18:20 schrieb Graham / KE9H:
>> There are clock distribution parts designed to do this low noise frequency
>> conversion and distribution.
>> 
>> Consider TI  LMK04100
>> 
>> 
>> 150 fs class jitter.
>> 
> But only if you integrate the noise only from 12 kHz offset to 20 MHz.
> It is a telecom spec.

You take the phase noise over that range and calculate the jitter from the 
phase noise. 
There is no “phase” (as in audio phase) information in the phase noise 
information you collect. There is just 
amplitude. Since you do not have angle information, you have to make some 
assumptions
about how the noise in each region sums up. 

How much of a difference can that be? Take a look at how the Fourier components 
of an impulse
add up. The angle of the components can matter quite a bit. Keep the same 
amplitudes, but fiddle
the angles between the components — you get a very different waveform. 

The calculation has the nice property that you *can* do the math with normal 
data. Run on 
broadband noise it works pretty well. When you get into noise regions that 
*may* have 
correlated noise (say from a modulation process). 

So, yes, there are a number of questions you need to ask when you see a jitter 
spec. A
number done by the formula will be very different 12 KHz to 20 MHz compared to 
1 Hz to 
100 KHz. The directly measured noise may be different from either number.

Bob 


> 
> regards, Gerhard
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Re: [time-nuts] low noise multiplication to 100 MHz

[Chuck Harris]

Hi Bert,

I have noticed that if I have the right magnification,
I can do amazing things.  Even the tiny age related
tremors that naturally occur in my hands reduce with
magnification.  The brain is a marvelous  servo mechanism.

Get a good 40x-80x zoom stereo microscope meant for
dissection, the type mounted on a boom, and I would bet
you too could deal with the small surface mount parts.

When I build with SMD, I always put all of the parts on
the top side, and use solder paste.  I used to put lots
of tiny dots out with a syringe that works a lot like a
caulking gun... only smaller.  But I found that simply
drawing a thin stripe of paste across the SMD pads
on the board, and then setting the part on the paste,
works just fine.  The solder draws towards the pads, and
leaves the space between the pins clear.  Occasionally
there will be some tiny balls sitting between the pins,
but they clean up when I clean the board with alcohol
and a brush...not that they hurt anything anyway.

The chips self center while they are floating on the
molten solder.  No need to touch them with a soldering
iron, or anything else.

I use a lab grade hot plate to bring the board up to reflow
temperature.  And I am off to the races.

For disassembly, I use an IR underboard heater, and a
hot air source... about 1/8 inch diameter, and move it
around the pin area until it melts, and then lift the
part free.

To put parts on an already populated board, I pre heat
the underside of the board to about 1/2-2/3 the way to
the solder melting temperature, and use a little gentle
hot air source to head the pads the rest of the way to
molten.  No need for soldering irons.

Practice on junk boards until it becomes natural.

-Chuck Harris

Bert Kehren via time-nuts wrote:

We have looked at the LMK devices but with my 74 years would not try to
solder it. There are other neat parts out there but again who is able to
solder  them.
Bert Kehren

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Re: [time-nuts] low noise multiplication to 100 MHz

[Bert Kehren via time-nuts]

Chuck
Thank you for your advice, I will print it out and when needed experiment.  
We use SMD.s and two of our tem members are very good at it, I do limited 
stuff  and have some tools but also a macular hole in one eye. In designs I 
try to stay  with solder able SMD's and we have projects like the AD9913 
which gets to the  limit what I will consider. I did not do the soldering.
Bert
 
 
In a message dated 1/26/2016 10:00:51 A.M. Eastern Standard Time,  
cfhar...@erols.com writes:

Hi  Bert,

I have noticed that if I have the right magnification,
I can  do amazing things.  Even the tiny age related
tremors that naturally  occur in my hands reduce with
magnification.  The brain is a  marvelous  servo mechanism.

Get a good 40x-80x zoom stereo  microscope meant for
dissection, the type mounted on a boom, and I would  bet
you too could deal with the small surface mount parts.

When I  build with SMD, I always put all of the parts on
the top side, and use  solder paste.  I used to put lots
of tiny dots out with a syringe that  works a lot like a
caulking gun... only smaller.  But I found that  simply
drawing a thin stripe of paste across the SMD pads
on the board,  and then setting the part on the paste,
works just fine.  The solder  draws towards the pads, and
leaves the space between the pins clear.   Occasionally
there will be some tiny balls sitting between the pins,
but  they clean up when I clean the board with alcohol
and a brush...not that  they hurt anything anyway.

The chips self center while they are  floating on the
molten solder.  No need to touch them with a  soldering
iron, or anything else.

I use a lab grade hot plate to  bring the board up to reflow
temperature.  And I am off to the  races.

For disassembly, I use an IR underboard heater, and a
hot air  source... about 1/8 inch diameter, and move it
around the pin area until it  melts, and then lift the
part free.

To put parts on an already  populated board, I pre heat
the underside of the board to about 1/2-2/3 the  way to
the solder melting temperature, and use a little gentle
hot air  source to head the pads the rest of the way to
molten.  No need for  soldering irons.

Practice on junk boards until it becomes  natural.

-Chuck Harris

Bert Kehren via time-nuts wrote:
>  We have looked at the LMK devices but with my 74 years would not try  to
> solder it. There are other neat parts out there but again who is  able to
> solder  them.
> Bert  Kehren
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Re: [time-nuts] low noise multiplication to 100 MHz

[Chuck Harris]

One last post on this off topic subject: Eyes.

The younger folk will think eye problems amount to near
or farsightedness... maybe a little astigmatism.  The
slightly older folk (37+) will know about presbyopia...
the loss of your close working focus... your arms get
shorter.

Then there are the 60+ folks who know about a whole new
spectrum of problems.  For you the macular degeneration,
for me the detached vitreous humor from my retina.

These result in holes in the vision, or ghosts and shadows
that float into and out of view.  Fun!

Microscopes cause problems with the 60+ kinds of vision
problems because they hold the eyes steady, and accentuate
the floaters and holes.  You can't just shift your eyes
and look around them because the scope needs each eye to
be accurately fixed on axis with the optical path for it
to work.

Fortunately there is a way out of this problem, and it is
a pretty cheap one too.  The little CCD or CMOS video camera,
and an LCD monitor.  This allows your eyes to look up, down
and around on the screen, and you get the needed
magnification, but because of the way your brain works, you
won't notice the floaters, and macular holes...  You just
look around them, and your brain fills in the gaps.  You do
lose your stereo optic distance clues, but there are more
expensive ways of correcting that too.

The more expensive solution is the Mantis, a large flat
screened stereo optic microscope that is supposed to help
provide the distance clues.  I haven't used one, but I have
heard good things from those that have.  Not exactly cheap,
but getting old has its costs.

You can work in SMD electronics when you get old.

-Chuck Harris

Bert Kehren via time-nuts wrote:

Chuck
Thank you for your advice, I will print it out and when needed experiment.
We use SMD.s and two of our tem members are very good at it, I do limited
stuff  and have some tools but also a macular hole in one eye. In designs I
try to stay  with solder able SMD's and we have projects like the AD9913
which gets to the  limit what I will consider. I did not do the soldering.
Bert

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Re: [time-nuts] low noise multiplication to 100 MHz

[Garry Thorp]

Jim,

3) Input and output level (?)
the oscillator is a HCMOS output, so figure swinging about 3.5V


Any multiplier configuration will produce lots of different harmonics, and will 
need fairly serious filtering after it if you want a clean 100MHz.

If you have a 20MHz oscillator with CMOS output, it should produce a healthy 
component at 100MHz provided its output is reasonably symmetrical, say ~55:45 
or better. The easiest (and probably lowest noise) approach might be to extract 
the 100MHz component directly. A common-base circuit such as the attached 
sketch would probably work OK.

Rin is needed to avoid overloading the CMOS output. The input tuned circuit Q 
could be made quite high, as its ESR can be incorporated into Rin. As this 
would take very little signal current from the oscillator at 20MHz or 60MHz, 
most of the CMOS output current capability would be available at 100MHz.

A common-emitter amplifier with a tuned emitter load would take less current 
from the oscillator, but probably isn't practical if you only have 5V regulated 
supply available.

Garry


CMOS oscillator x5.pdf
Description: CMOS oscillator x5.pdf
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Re: [time-nuts] low noise multiplication to 100 MHz

[Bryan _]

Chuck, what do you use for a hot air source. The good ones are very expensive. 
Wonder if there is something for the hobbyist. Have seen a few repair videos 
where they used just used a hot air stripper.
I had to yank a couple SMD resistors off a board the other day and had to use 
two soldering irons at each end of the resistor . If they are small enough 
you can add a glob of solder to the whole resistor, so both ends will melt.
Cheers

-=Bryan=-

> To: time-nuts@febo.com
> From: cfhar...@erols.com
> Date: Tue, 26 Jan 2016 01:50:47 -0500
> Subject: Re: [time-nuts] low noise multiplication to 100 MHz
> 
> Hi Bert,
> 
> I have noticed that if I have the right magnification,
> I can do amazing things.  Even the tiny age related
> tremors that naturally occur in my hands reduce with
> magnification.  The brain is a marvelous  servo mechanism.
> 
> Get a good 40x-80x zoom stereo microscope meant for
> dissection, the type mounted on a boom, and I would bet
> you too could deal with the small surface mount parts.
> 
> When I build with SMD, I always put all of the parts on
> the top side, and use solder paste.  I used to put lots
> of tiny dots out with a syringe that works a lot like a
> caulking gun... only smaller.  But I found that simply
> drawing a thin stripe of paste across the SMD pads
> on the board, and then setting the part on the paste,
> works just fine.  The solder draws towards the pads, and
> leaves the space between the pins clear.  Occasionally
> there will be some tiny balls sitting between the pins,
> but they clean up when I clean the board with alcohol
> and a brush...not that they hurt anything anyway.
> 
> The chips self center while they are floating on the
> molten solder.  No need to touch them with a soldering
> iron, or anything else.
> 
> I use a lab grade hot plate to bring the board up to reflow
> temperature.  And I am off to the races.
> 
> For disassembly, I use an IR underboard heater, and a
> hot air source... about 1/8 inch diameter, and move it
> around the pin area until it melts, and then lift the
> part free.
> 
> To put parts on an already populated board, I pre heat
> the underside of the board to about 1/2-2/3 the way to
> the solder melting temperature, and use a little gentle
> hot air source to head the pads the rest of the way to
> molten.  No need for soldering irons.
> 
> Practice on junk boards until it becomes natural.
> 
> -Chuck Harris
> 
> Bert Kehren via time-nuts wrote:
> > We have looked at the LMK devices but with my 74 years would not try to
> > solder it. There are other neat parts out there but again who is able to
> > solder  them.
> > Bert Kehren
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Re: [time-nuts] low noise multiplication to 100 MHz

[Cash Olsen]

About 10 years ago I demonstrated a Hot Air Reflow method that is simple
and needs no exotic tools and no heroic skills to solder surface mount
devices. I also supply the solder paste in a syringe with a modified
needle. The paste is Kester Easy Profile 256.

You can see my method at:
http://kd5ssj.com/solderpaste/smt-tools-and-process

You can order paste at: http://kd5ssj.com/solderpaste/smd-soldering

BTW the cost of the solder paste has been constant for ten years but the
cost of shipping is up more than 5x, the USPS just raised the cost of
shipping a padded envelope by about 25%.

--
S. Cash Olsen KD5SSJ
ARRL Technical Specialist

Message: 15
Date: Tue, 26 Jan 2016 01:50:47 -0500
From: Chuck Harris <cfhar...@erols.com>
To: Discussion of precise time and frequency measurement
<time-nuts@febo.com>
Subject: Re: [time-nuts] low noise multiplication to 100 MHz
Message-ID: <56a71747.8040...@erols.com>
Content-Type: text/plain; charset=UTF-8; format=flowed

Hi Bert,

I have noticed that if I have the right magnification,
I can do amazing things.  Even the tiny age related
tremors that naturally occur in my hands reduce with
magnification.  The brain is a marvelous  servo mechanism.

Get a good 40x-80x zoom stereo microscope meant for
dissection, the type mounted on a boom, and I would bet
you too could deal with the small surface mount parts.

When I build with SMD, I always put all of the parts on
the top side, and use solder paste.  I used to put lots
of tiny dots out with a syringe that works a lot like a
caulking gun... only smaller.  But I found that simply
drawing a thin stripe of paste across the SMD pads
on the board, and then setting the part on the paste,
works just fine.  The solder draws towards the pads, and
leaves the space between the pins clear.  Occasionally
there will be some tiny balls sitting between the pins,
but they clean up when I clean the board with alcohol
and a brush...not that they hurt anything anyway.

The chips self center while they are floating on the
molten solder.  No need to touch them with a soldering
iron, or anything else.

I use a lab grade hot plate to bring the board up to reflow
temperature.  And I am off to the races.

For disassembly, I use an IR underboard heater, and a
hot air source... about 1/8 inch diameter, and move it
around the pin area until it melts, and then lift the
part free.

To put parts on an already populated board, I pre heat
the underside of the board to about 1/2-2/3 the way to
the solder melting temperature, and use a little gentle
hot air source to head the pads the rest of the way to
molten.  No need for soldering irons.

Practice on junk boards until it becomes natural.

-Chuck Harris

Bert Kehren via time-nuts wrote:
> We have looked at the LMK devices but with my 74 years would not try to
> solder it. There are other neat parts out there but again who is able to
> solder  them.
> Bert Kehren
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Re: [time-nuts] low noise multiplication to 100 MHz

[Gerhard Hoffmann]

Am 25.01.2016 um 18:20 schrieb Graham / KE9H:

There are clock distribution parts designed to do this low noise frequency
conversion and distribution.

Consider TI  LMK04100


150 fs class jitter.


But only if you integrate the noise only from 12 kHz offset to 20 MHz.
It is a telecom spec.

regards, Gerhard
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Re: [time-nuts] low noise multiplication to 100 MHz

[Bert Kehren via time-nuts]

We have looked at the LMK devices but with my 74 years would not try to  
solder it. There are other neat parts out there but again who is able to 
solder  them.
Bert Kehren
 
 
In a message dated 1/25/2016 8:11:14 P.M. Eastern Standard Time,  
b...@hsmicrowave.com writes:

Aaah -  but then you need a microprocessor (and its noise if you're not 
careful)  to control it. IMHO - too complicated an approach. Hard to beat 
a  "careful" straight multiplier approach for simple or a phased locked 
100  MHz VCXO for the best phase noise.

Bill - N6GHz

On 1/25/2016  9:20 AM, Graham / KE9H wrote:
> There are clock distribution parts  designed to do this low noise 
frequency
> conversion and  distribution.
>
> Consider TI  LMK04100
>
>  Ignore PLL1
> Put your 10 MHz as the reference input to PLL2.
>  Set Internal VCO to ~1200 MHz
> Set the internal dividers to get 100 MHz  out, and 10 MHz back to the PLL2
> phase detector.
>
> Get  reasonable noise and 100 MHz output with your choice of 2VPECL, LVDS,
>  LVCMOS output levels.
>
> If you have a dirty input  clock/reference, or multiple sources, you can 
use
> PLL1 and an external  crystal in a VCO to clean it up before you multiply 
it
> to 1200  MHz.
>
> And you can get up to four other frequencies out of the  part at the same
> time.
>
> 150 fs class  jitter.
>
> $13 cost, quantity one.
>
> ---  Graham
>
> ==
>
>
>
>
>
> On  Mon, Jan 25, 2016 at 9:22 AM, Bert Kehren via time-nuts <
>  time-nuts@febo.com> wrote:
>
>> If not good enough an XOR  with filter and one of the Crystek VCXO's
>> previously mentioned may  do it.
>> Bert Kehren
>>
>>
>> In a  message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time,
>>  mag...@rubidium.dyndns.org writes:
>>
>> Also, it  will  be systematic, with idle tones. Because of the delay
>> elements  used,  they will not be long-term static but move  around.
>>
>> I agree, this is  quite noisy. If the  noise is tolerable, it is indeed a
>> small solution. 100  ps  1-sigma for 5 MHz in 100 MHz out isn't what I
>> would consider   low.
>>
>>  https://www.idt.com/document/dst/570-datasheet
>>
>>  Cheers,
>> Magnus
>>
>> On  01/24/2016 11:12  PM, Bruce Griffiths wrote:
>>> Unfortunately the ICS570   (like all zero delay buffers) has an output
>> jitter approaching  about 1000  times the likely RF ADC internal sampling
>> jitter.  The resultant SNR  degradation may be a little excessive for  
this
>> application..
>>>Bruce
>>>
>>>
>>> On Monday, 25 January 2016  11:00 AM, Bert Kehren via  time-nuts
>>    wrote:
>>>
>>>With all the discussions  in a small  100 MHz source I asked my 
project
>>> partner  Juerg in Switzerland to run  some data on the ICS 570 that we  
use
>> on the
>>> majority of our projects  with  excellent results. Using the HP53132A we
>>  see
>>
>>> + - 1  count at E10-11 ignore the large  jumps those come from the Tbolt
>>>   frequency   change to correct the 1 pps. Depending on the application
>>  this  is an
>>> excellent  device.
>>>  Bert  Kehren
>>>
>>>
>>> In a message  dated 1/23/2016 6:02:23 P.M.  Eastern Standard Time,
>>>  dk...@arcor.de writes:
>>>
>>> Am22.01.2016 um 22:40 schrieb jimlux:
 the oscillator is a  HCMOS  output,  so figure swinging about 3.5V
  Output.. I'm feeding  differential clock  inputs on ADCs.  I'll  bet a
 +/-  300mV swing would   work.

> 4)Title said "Low   Noise"  needs better  definition as to what kind  
of
>   noise and how far down. Are we to   be  concerned about harmonic and
>> spur
>  content as compared to  real random white   noise?
 This is time-nuts.. it has to beperfect..

 But realistically, my source  is probably  going to be  about -90dBc/Hz
 at 1  Hz, -125 at 10Hz, -145 at  100 Hz.  I'm  going up by a factor  of
 10, so I'd expect  20 dB worse plus a   little..(nothing is perfect,
>> eh?)
 Call it  maybe -100 to -95 at  10 Hz, -125 to  -120 at 100 Hz and  so
>> forth.
 harmonics areinteresting: it's the sample clock into an ADC. So
  harmonics of  the  100 aren't a big deal.  harmonics of the 10  or 20
   are.  If  you have significant  90 or 110 contaminating the 100,  
then
 you get   weird spurs..  (I had this problem on a  software radio  
where
 the  50 MHz sample clock was  contaminated  with some 66 MHz from the
>> CPU)
Spurs cause the same issues.

 ON the  other   hand... spurs that are pretty low don't make  much
 difference  if  you're digitizing a signal  that is close to the noise
   floor: the  spur  multiplied by the desired signal is usually lower  
 and
 down in the  noise.  Strong CW in band  signals,  though, are a real
>>  pain.

>>> <
>>>
>>  
https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377
>>>8
>>> I think that top left board would not be far   away:
>>>
>>> in :  10 MHz LVDS or  CMOS
>>> in:   3V3
>>> out: 100 MHz CMOS  3V3
>>>
>>> just a  few hours wall  clock  

Re: [time-nuts] low noise multiplication to 100 MHz

[Hal Murray]

b...@hsmicrowave.com said:
> Aaah - but then you need a microprocessor (and its noise if you're not
> careful) to control it. IMHO - too complicated an approach.

Yes, but you don't need many smarts to send a few bits to configure a PLL 
chip.

You can get low end microprocessors in 8 pin packages.  They don't even need 
an external clock or crystal, just a bypass cap.  If you are concerned about 
noise, they can go into deep sleep mode.  Most of them have really low power 
modes designed so that the battery for a chip can run close to shelf life.


-- 
These are my opinions.  I hate spam.



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Re: [time-nuts] low noise multiplication to 100 MHz

[Magnus Danielson]

Also, it will be systematic, with idle tones. Because of the delay 
elements used, they will not be long-term static but move around.


I agree, this is quite noisy. If the noise is tolerable, it is indeed a 
small solution. 100 ps 1-sigma for 5 MHz in 100 MHz out isn't what I 
would consider low.


https://www.idt.com/document/dst/570-datasheet

Cheers,
Magnus

On 01/24/2016 11:12 PM, Bruce Griffiths wrote:

Unfortunately the ICS570 (like all zero delay buffers) has an output jitter 
approaching about 1000 times the likely RF ADC internal sampling jitter. The 
resultant SNR degradation may be a little excessive for this application..
Bruce


 On Monday, 25 January 2016 11:00 AM, Bert Kehren via time-nuts 
 wrote:


  With all the discussions in a small 100 MHz source I asked my project
partner Juerg in Switzerland to run some data on the ICS 570 that we use on the
majority of our projects with excellent results. Using the HP53132A we see
+ - 1  count at E10-11 ignore the large jumps those come from the Tbolt
frequency  change to correct the 1 pps. Depending on the application this is an
excellent  device.
Bert Kehren


In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time,
dk...@arcor.de writes:

Am  22.01.2016 um 22:40 schrieb jimlux:

the oscillator is a HCMOS output,  so figure swinging about 3.5V
Output.. I'm feeding differential clock  inputs on ADCs.  I'll bet a
+/- 300mV swing would  work.


4)Title said "Low Noise"  needs better  definition as to what kind of
noise and how far down. Are we to  be  concerned about harmonic and spur
content as compared to  real random white noise?


This is time-nuts.. it has to be  perfect..

But realistically, my source is probably going to be  about -90dBc/Hz
at 1 Hz, -125 at 10Hz, -145 at 100 Hz.  I'm  going up by a factor of
10, so I'd expect 20 dB worse plus a  little..(nothing is perfect, eh?)

Call it maybe -100 to -95 at  10 Hz, -125 to -120 at 100 Hz and so forth.

harmonics are  interesting: it's the sample clock into an ADC. So
harmonics of the  100 aren't a big deal.  harmonics of the 10 or 20
are.  If  you have significant 90 or 110 contaminating the 100, then
you get  weird spurs..  (I had this problem on a software radio where
the  50 MHz sample clock was contaminated with some 66 MHz from the  CPU)

Spurs cause the same issues.

ON the other  hand... spurs that are pretty low don't make much
difference if  you're digitizing a signal that is close to the noise
floor: the spur  multiplied by the desired signal is usually lower and
down in the  noise.  Strong CW in band signals, though, are a real  pain.



<
https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377
8




I think that top left board would not be far away:

in :  10 MHz LVDS or CMOS
in:  3V3
out: 100 MHz CMOS 3V3

just a  few hours wall clock time from layout to working as a
ham radio weekender,  so please excuse my diy home board
production process.

Ok, the use  of a 4046 descendant may not be the last word
from a timenut perspective,  but I'll redo it with an osc of
my own anyway. Divider 100/10 is a LVC163  (161?) + lvc04.


<  http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf  >

Digi-Key has 153 of them on a tape and  441 of a similar one  , even
cheaper that seems to point to the same data sheet.

<
http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128




You can get the few dB missing close-in by transfer from your  reference.

In the picture:
The bottom row of boards is a doubler  100->200 MHz using 2*BF862, slight
gain,
and diode doubler 200 ->  400 MHz, SAW filter to get rid of
100/200/300/500/600 +/-10  etc,
post amp to get a usable level again.

Still missing  400-> 800, 800->1600 to feed  _my_ ADC clock input..

regards,  Gerhard

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Re: [time-nuts] low noise multiplication to 100 MHz

[Bert Kehren via time-nuts]

If not good enough an XOR with filter and one of the Crystek VCXO's  
previously mentioned may do it.
Bert Kehren
 
 
In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time,  
mag...@rubidium.dyndns.org writes:

Also, it  will be systematic, with idle tones. Because of the delay 
elements used,  they will not be long-term static but move around.

I agree, this is  quite noisy. If the noise is tolerable, it is indeed a 
small solution. 100  ps 1-sigma for 5 MHz in 100 MHz out isn't what I 
would consider  low.

https://www.idt.com/document/dst/570-datasheet

Cheers,
Magnus

On  01/24/2016 11:12 PM, Bruce Griffiths wrote:
> Unfortunately the ICS570  (like all zero delay buffers) has an output 
jitter approaching about 1000  times the likely RF ADC internal sampling 
jitter. The resultant SNR  degradation may be a little excessive for this 
application..
>  Bruce
>
>
>  On Monday, 25 January 2016  11:00 AM, Bert Kehren via time-nuts 
  wrote:
>
>
>   With all the discussions in a small  100 MHz source I asked my project
> partner Juerg in Switzerland to run  some data on the ICS 570 that we use 
on the
> majority of our projects  with excellent results. Using the HP53132A we 
see

> + - 1   count at E10-11 ignore the large jumps those come from the Tbolt
>  frequency  change to correct the 1 pps. Depending on the application 
this  is an
> excellent  device.
> Bert  Kehren
>
>
> In a message dated 1/23/2016 6:02:23 P.M.  Eastern Standard Time,
> dk...@arcor.de writes:
>
> Am   22.01.2016 um 22:40 schrieb jimlux:
>> the oscillator is a HCMOS  output,  so figure swinging about 3.5V
>> Output.. I'm feeding  differential clock  inputs on ADCs.  I'll bet a
>> +/-  300mV swing would  work.
>>
>>> 4)Title said "Low  Noise"  needs better  definition as to what kind of
>>>  noise and how far down. Are we to  be  concerned about harmonic and  
spur
>>> content as compared to  real random white  noise?
>>
>> This is time-nuts.. it has to be   perfect..
>>
>> But realistically, my source is probably  going to be  about -90dBc/Hz
>> at 1 Hz, -125 at 10Hz, -145 at  100 Hz.  I'm  going up by a factor of
>> 10, so I'd expect  20 dB worse plus a  little..(nothing is perfect,  eh?)
>>
>> Call it maybe -100 to -95 at  10 Hz, -125 to  -120 at 100 Hz and so 
forth.
>>
>> harmonics are   interesting: it's the sample clock into an ADC. So
>> harmonics of  the  100 aren't a big deal.  harmonics of the 10 or 20
>>  are.  If  you have significant 90 or 110 contaminating the 100,  then
>> you get  weird spurs..  (I had this problem on a  software radio where
>> the  50 MHz sample clock was  contaminated with some 66 MHz from the  
CPU)
>>
>>  Spurs cause the same issues.
>>
>> ON the other   hand... spurs that are pretty low don't make much
>> difference  if  you're digitizing a signal that is close to the noise
>>  floor: the spur  multiplied by the desired signal is usually lower  and
>> down in the  noise.  Strong CW in band signals,  though, are a real  
pain.
>>
>>
> <
>  
https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377
>  8
>>
>
> I think that top left board would not be far  away:
>
> in :  10 MHz LVDS or CMOS
> in:   3V3
> out: 100 MHz CMOS 3V3
>
> just a  few hours wall  clock time from layout to working as a
> ham radio weekender,  so  please excuse my diy home board
> production process.
>
>  Ok, the use  of a 4046 descendant may not be the last word
> from a  timenut perspective,  but I'll redo it with an osc of
> my own  anyway. Divider 100/10 is a LVC163  (161?) +  lvc04.
>
>
> <   http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf   >
>
> Digi-Key has 153 of them on a tape and  441 of a  similar one  , even
> cheaper that seems to point to the same data  sheet.
>
> <
>  
http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128
>
>>
>  You can get the few dB missing close-in by transfer from your   
reference.
>
> In the picture:
> The bottom row of boards is  a doubler  100->200 MHz using 2*BF862, slight
> gain,
>  and diode doubler 200 ->  400 MHz, SAW filter to get rid of
>  100/200/300/500/600 +/-10  etc,
> post amp to get a usable level  again.
>
> Still missing  400-> 800, 800->1600 to  feed  _my_ ADC clock input..
>
> regards,   Gerhard
>
>  ___
> time-nuts   mailing list -- time-nuts@febo.com
> To unsubscribe, go to
>  https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow  the  instructions there.
>
>
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> To unsubscribe, go to  
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> and follow the  instructions there.
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>
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> and follow the  instructions  there.
>

Re: [time-nuts] low noise multiplication to 100 MHz

[Graham / KE9H]

There are clock distribution parts designed to do this low noise frequency
conversion and distribution.

Consider TI  LMK04100

Ignore PLL1
Put your 10 MHz as the reference input to PLL2.
Set Internal VCO to ~1200 MHz
Set the internal dividers to get 100 MHz out, and 10 MHz back to the PLL2
phase detector.

Get reasonable noise and 100 MHz output with your choice of 2VPECL, LVDS,
LVCMOS output levels.

If you have a dirty input clock/reference, or multiple sources, you can use
PLL1 and an external crystal in a VCO to clean it up before you multiply it
to 1200 MHz.

And you can get up to four other frequencies out of the part at the same
time.

150 fs class jitter.

$13 cost, quantity one.

--- Graham

==





On Mon, Jan 25, 2016 at 9:22 AM, Bert Kehren via time-nuts <
time-nuts@febo.com> wrote:

> If not good enough an XOR with filter and one of the Crystek VCXO's
> previously mentioned may do it.
> Bert Kehren
>
>
> In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time,
> mag...@rubidium.dyndns.org writes:
>
> Also, it  will be systematic, with idle tones. Because of the delay
> elements used,  they will not be long-term static but move around.
>
> I agree, this is  quite noisy. If the noise is tolerable, it is indeed a
> small solution. 100  ps 1-sigma for 5 MHz in 100 MHz out isn't what I
> would consider  low.
>
> https://www.idt.com/document/dst/570-datasheet
>
> Cheers,
> Magnus
>
> On  01/24/2016 11:12 PM, Bruce Griffiths wrote:
> > Unfortunately the ICS570  (like all zero delay buffers) has an output
> jitter approaching about 1000  times the likely RF ADC internal sampling
> jitter. The resultant SNR  degradation may be a little excessive for this
> application..
> >  Bruce
> >
> >
> >  On Monday, 25 January 2016  11:00 AM, Bert Kehren via time-nuts
>   wrote:
> >
> >
> >   With all the discussions in a small  100 MHz source I asked my project
> > partner Juerg in Switzerland to run  some data on the ICS 570 that we use
> on the
> > majority of our projects  with excellent results. Using the HP53132A we
> see
>
> > + - 1   count at E10-11 ignore the large jumps those come from the Tbolt
> >  frequency  change to correct the 1 pps. Depending on the application
> this  is an
> > excellent  device.
> > Bert  Kehren
> >
> >
> > In a message dated 1/23/2016 6:02:23 P.M.  Eastern Standard Time,
> > dk...@arcor.de writes:
> >
> > Am   22.01.2016 um 22:40 schrieb jimlux:
> >> the oscillator is a HCMOS  output,  so figure swinging about 3.5V
> >> Output.. I'm feeding  differential clock  inputs on ADCs.  I'll bet a
> >> +/-  300mV swing would  work.
> >>
> >>> 4)Title said "Low  Noise"  needs better  definition as to what kind of
> >>>  noise and how far down. Are we to  be  concerned about harmonic and
> spur
> >>> content as compared to  real random white  noise?
> >>
> >> This is time-nuts.. it has to be   perfect..
> >>
> >> But realistically, my source is probably  going to be  about -90dBc/Hz
> >> at 1 Hz, -125 at 10Hz, -145 at  100 Hz.  I'm  going up by a factor of
> >> 10, so I'd expect  20 dB worse plus a  little..(nothing is perfect,
> eh?)
> >>
> >> Call it maybe -100 to -95 at  10 Hz, -125 to  -120 at 100 Hz and so
> forth.
> >>
> >> harmonics are   interesting: it's the sample clock into an ADC. So
> >> harmonics of  the  100 aren't a big deal.  harmonics of the 10 or 20
> >>  are.  If  you have significant 90 or 110 contaminating the 100,  then
> >> you get  weird spurs..  (I had this problem on a  software radio where
> >> the  50 MHz sample clock was  contaminated with some 66 MHz from the
> CPU)
> >>
> >>  Spurs cause the same issues.
> >>
> >> ON the other   hand... spurs that are pretty low don't make much
> >> difference  if  you're digitizing a signal that is close to the noise
> >>  floor: the spur  multiplied by the desired signal is usually lower  and
> >> down in the  noise.  Strong CW in band signals,  though, are a real
> pain.
> >>
> >>
> > <
> >
>
> https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377
> >  8
> >>
> >
> > I think that top left board would not be far  away:
> >
> > in :  10 MHz LVDS or CMOS
> > in:   3V3
> > out: 100 MHz CMOS 3V3
> >
> > just a  few hours wall  clock time from layout to working as a
> > ham radio weekender,  so  please excuse my diy home board
> > production process.
> >
> >  Ok, the use  of a 4046 descendant may not be the last word
> > from a  timenut perspective,  but I'll redo it with an osc of
> > my own  anyway. Divider 100/10 is a LVC163  (161?) +  lvc04.
> >
> >
> > <   http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf   >
> >
> > Digi-Key has 153 of them on a tape and  441 of a  similar one  , even
> > cheaper that seems to point to the same data  sheet.
> >
> > <
> >
>
> http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128
> >
> >>
> >  You can get the few dB missing close-in by transfer from your
> reference.
> >
> > In the picture:
> > The 

Re: [time-nuts] low noise multiplication to 100 MHz

[Bill]

Aaah - but then you need a microprocessor (and its noise if you're not 
careful) to control it. IMHO - too complicated an approach. Hard to beat 
a "careful" straight multiplier approach for simple or a phased locked 
100 MHz VCXO for the best phase noise.


Bill - N6GHz

On 1/25/2016 9:20 AM, Graham / KE9H wrote:

There are clock distribution parts designed to do this low noise frequency
conversion and distribution.

Consider TI  LMK04100

Ignore PLL1
Put your 10 MHz as the reference input to PLL2.
Set Internal VCO to ~1200 MHz
Set the internal dividers to get 100 MHz out, and 10 MHz back to the PLL2
phase detector.

Get reasonable noise and 100 MHz output with your choice of 2VPECL, LVDS,
LVCMOS output levels.

If you have a dirty input clock/reference, or multiple sources, you can use
PLL1 and an external crystal in a VCO to clean it up before you multiply it
to 1200 MHz.

And you can get up to four other frequencies out of the part at the same
time.

150 fs class jitter.

$13 cost, quantity one.

--- Graham

==





On Mon, Jan 25, 2016 at 9:22 AM, Bert Kehren via time-nuts <
time-nuts@febo.com> wrote:


If not good enough an XOR with filter and one of the Crystek VCXO's
previously mentioned may do it.
Bert Kehren


In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time,
mag...@rubidium.dyndns.org writes:

Also, it  will be systematic, with idle tones. Because of the delay
elements used,  they will not be long-term static but move around.

I agree, this is  quite noisy. If the noise is tolerable, it is indeed a
small solution. 100  ps 1-sigma for 5 MHz in 100 MHz out isn't what I
would consider  low.

https://www.idt.com/document/dst/570-datasheet

Cheers,
Magnus

On  01/24/2016 11:12 PM, Bruce Griffiths wrote:

Unfortunately the ICS570  (like all zero delay buffers) has an output

jitter approaching about 1000  times the likely RF ADC internal sampling
jitter. The resultant SNR  degradation may be a little excessive for this
application..

  Bruce


  On Monday, 25 January 2016  11:00 AM, Bert Kehren via time-nuts

  wrote:


   With all the discussions in a small  100 MHz source I asked my project
partner Juerg in Switzerland to run  some data on the ICS 570 that we use

on the

majority of our projects  with excellent results. Using the HP53132A we

see


+ - 1   count at E10-11 ignore the large jumps those come from the Tbolt
  frequency  change to correct the 1 pps. Depending on the application

this  is an

excellent  device.
Bert  Kehren


In a message dated 1/23/2016 6:02:23 P.M.  Eastern Standard Time,
dk...@arcor.de writes:

Am   22.01.2016 um 22:40 schrieb jimlux:

the oscillator is a HCMOS  output,  so figure swinging about 3.5V
Output.. I'm feeding  differential clock  inputs on ADCs.  I'll bet a
+/-  300mV swing would  work.


4)Title said "Low  Noise"  needs better  definition as to what kind of
  noise and how far down. Are we to  be  concerned about harmonic and

spur

content as compared to  real random white  noise?

This is time-nuts.. it has to be   perfect..

But realistically, my source is probably  going to be  about -90dBc/Hz
at 1 Hz, -125 at 10Hz, -145 at  100 Hz.  I'm  going up by a factor of
10, so I'd expect  20 dB worse plus a  little..(nothing is perfect,

eh?)

Call it maybe -100 to -95 at  10 Hz, -125 to  -120 at 100 Hz and so

forth.

harmonics are   interesting: it's the sample clock into an ADC. So
harmonics of  the  100 aren't a big deal.  harmonics of the 10 or 20
  are.  If  you have significant 90 or 110 contaminating the 100,  then
you get  weird spurs..  (I had this problem on a  software radio where
the  50 MHz sample clock was  contaminated with some 66 MHz from the

CPU)

  Spurs cause the same issues.

ON the other   hand... spurs that are pretty low don't make much
difference  if  you're digitizing a signal that is close to the noise
  floor: the spur  multiplied by the desired signal is usually lower  and
down in the  noise.  Strong CW in band signals,  though, are a real

pain.



<


https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377

  8
I think that top left board would not be far  away:

in :  10 MHz LVDS or CMOS
in:   3V3
out: 100 MHz CMOS 3V3

just a  few hours wall  clock time from layout to working as a
ham radio weekender,  so  please excuse my diy home board
production process.

  Ok, the use  of a 4046 descendant may not be the last word
from a  timenut perspective,  but I'll redo it with an osc of
my own  anyway. Divider 100/10 is a LVC163  (161?) +  lvc04.


<   http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf   >

Digi-Key has 153 of them on a tape and  441 of a  similar one  , even
cheaper that seems to point to the same data  sheet.

<


http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128

  You can get the few dB missing close-in by transfer from your

reference.

In the picture:
The bottom row of boards is  a doubler  100->200 MHz using 

Re: [time-nuts] low noise multiplication to 100 MHz

[Bruce Griffiths]

Unfortunately the ICS570 (like all zero delay buffers) has an output jitter 
approaching about 1000 times the likely RF ADC internal sampling jitter. The 
resultant SNR degradation may be a little excessive for this application..
Bruce
  

On Monday, 25 January 2016 11:00 AM, Bert Kehren via time-nuts 
 wrote:
 

 With all the discussions in a small 100 MHz source I asked my project  
partner Juerg in Switzerland to run some data on the ICS 570 that we use on the 
 
majority of our projects with excellent results. Using the HP53132A we see 
+ - 1  count at E10-11 ignore the large jumps those come from the Tbolt 
frequency  change to correct the 1 pps. Depending on the application this is an 
excellent  device.
Bert Kehren
 
 
In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time,  
dk...@arcor.de writes:

Am  22.01.2016 um 22:40 schrieb jimlux:
> the oscillator is a HCMOS output,  so figure swinging about 3.5V
> Output.. I'm feeding differential clock  inputs on ADCs.  I'll bet a 
> +/- 300mV swing would  work.
>
>> 4)Title said "Low Noise"  needs better  definition as to what kind of
>> noise and how far down. Are we to  be  concerned about harmonic and spur
>> content as compared to  real random white noise?
>
> This is time-nuts.. it has to be  perfect..
>
> But realistically, my source is probably going to be  about -90dBc/Hz 
> at 1 Hz, -125 at 10Hz, -145 at 100 Hz.  I'm  going up by a factor of 
> 10, so I'd expect 20 dB worse plus a  little..(nothing is perfect, eh?)
>
> Call it maybe -100 to -95 at  10 Hz, -125 to -120 at 100 Hz and so forth.
>
> harmonics are  interesting: it's the sample clock into an ADC. So 
> harmonics of the  100 aren't a big deal.  harmonics of the 10 or 20 
> are.  If  you have significant 90 or 110 contaminating the 100, then 
> you get  weird spurs..  (I had this problem on a software radio where 
> the  50 MHz sample clock was contaminated with some 66 MHz from the  CPU)
>
> Spurs cause the same issues.
>
> ON the other  hand... spurs that are pretty low don't make much 
> difference if  you're digitizing a signal that is close to the noise 
> floor: the spur  multiplied by the desired signal is usually lower and 
> down in the  noise.  Strong CW in band signals, though, are a real  pain.
>
>
<  
https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377
8  
>

I think that top left board would not be far away:

in :  10 MHz LVDS or CMOS
in:  3V3
out: 100 MHz CMOS 3V3

just a  few hours wall clock time from layout to working as a
ham radio weekender,  so please excuse my diy home board
production process.

Ok, the use  of a 4046 descendant may not be the last word
from a timenut perspective,  but I'll redo it with an osc of
my own anyway. Divider 100/10 is a LVC163  (161?) + lvc04.


<  http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf  >

Digi-Key has 153 of them on a tape and  441 of a similar one  , even
cheaper that seems to point to the same data sheet.

<  
http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128
  
>
You can get the few dB missing close-in by transfer from your  reference.

In the picture:
The bottom row of boards is a doubler  100->200 MHz using 2*BF862, slight 
gain,
and diode doubler 200 ->  400 MHz, SAW filter to get rid of 
100/200/300/500/600 +/-10  etc,
post amp to get a usable level again.

Still missing  400-> 800, 800->1600 to feed  _my_ ADC clock input..

regards,  Gerhard

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[time-nuts] low noise multiplication to 100 MHz

[Bert Kehren via time-nuts]

With all the discussions in a small 100 MHz source I asked my project  
partner Juerg in Switzerland to run some data on the ICS 570 that we use on the 
 
majority of our projects with excellent results. Using the HP53132A we see 
+ - 1  count at E10-11 ignore the large jumps those come from the Tbolt 
frequency  change to correct the 1 pps. Depending on the application this is an 
excellent  device.
Bert Kehren
 
 
In a message dated 1/23/2016 6:02:23 P.M. Eastern Standard Time,  
dk...@arcor.de writes:

Am  22.01.2016 um 22:40 schrieb jimlux:
> the oscillator is a HCMOS output,  so figure swinging about 3.5V
> Output.. I'm feeding differential clock  inputs on ADCs.  I'll bet a 
> +/- 300mV swing would  work.
>
>> 4)Title said "Low Noise"  needs better  definition as to what kind of
>> noise and how far down. Are we to  be  concerned about harmonic and spur
>> content as compared to  real random white noise?
>
> This is time-nuts.. it has to be  perfect..
>
> But realistically, my source is probably going to be  about -90dBc/Hz 
> at 1 Hz, -125 at 10Hz, -145 at 100 Hz.  I'm  going up by a factor of 
> 10, so I'd expect 20 dB worse plus a  little..(nothing is perfect, eh?)
>
> Call it maybe -100 to -95 at  10 Hz, -125 to -120 at 100 Hz and so forth.
>
> harmonics are  interesting: it's the sample clock into an ADC. So 
> harmonics of the  100 aren't a big deal.  harmonics of the 10 or 20 
> are.  If  you have significant 90 or 110 contaminating the 100, then 
> you get  weird spurs..  (I had this problem on a software radio where 
> the  50 MHz sample clock was contaminated with some 66 MHz from the  CPU)
>
> Spurs cause the same issues.
>
> ON the other  hand... spurs that are pretty low don't make much 
> difference if  you're digitizing a signal that is close to the noise 
> floor: the spur  multiplied by the desired signal is usually lower and 
> down in the  noise.  Strong CW in band signals, though, are a real  pain.
>
>
<  
https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377
8  
>

I think that top left board would not be far away:

in :  10 MHz LVDS or CMOS
in:  3V3
out: 100 MHz CMOS 3V3

just a  few hours wall clock time from layout to working as a
ham radio weekender,  so please excuse my diy home board
production process.

Ok, the use  of a 4046 descendant may not be the last word
from a timenut perspective,  but I'll redo it with an osc of
my own anyway. Divider 100/10 is a LVC163  (161?) + lvc04.


<  http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf  >

Digi-Key has 153 of them on a tape and  441 of a similar one  , even
cheaper that seems to point to the same data sheet.

<  
http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128
  
>
You can get the few dB missing close-in by transfer from your  reference.

In the picture:
The bottom row of boards is a doubler  100->200 MHz using 2*BF862, slight 
gain,
and diode doubler 200 ->  400 MHz, SAW filter to get rid of 
100/200/300/500/600 +/-10   etc,
post amp to get a usable level again.

Still missing   400-> 800, 800->1600 to feed  _my_ ADC clock input.

regards,  Gerhard

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Test_ICS570b.ods
Description: Binary data
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Re: [time-nuts] low noise multiplication to 100 MHz

[Alan Ambrose]

Do any of the SiLabs 'low jitter' synthesiser / clock generators / jitter 
attenuators etc help?

Alan
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Re: [time-nuts] low noise multiplication to 100 MHz

[Attila Kinali]

Moin Ulrich,

On Fri, 22 Jan 2016 10:00:58 -0800
"Tom Van Baak"  wrote:

> The attached plot is from Dr. Ulrich Rohde (ka2...@aol.com)
> "a PDF of a noise plot , AM FM noise, important technical data"
> (he had trouble posting it to the list, so I'm doing it for him)
> 
> R_S_SMA_SIG_GEN_100MHz-02.pdf

Could you explain what we are looking at here?

Attila Kinali


-- 
Reading can seriously damage your ignorance.
-- unknown
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Re: [time-nuts] low noise multiplication to 100 MHz

[Gerhard Hoffmann]

Am 22.01.2016 um 22:40 schrieb jimlux:

the oscillator is a HCMOS output, so figure swinging about 3.5V
Output.. I'm feeding differential clock inputs on ADCs.  I'll bet a 
+/- 300mV swing would work.



4)Title said "Low Noise"  needs better definition as to what kind of
noise and how far down. Are we to be  concerned about harmonic and spur
content as compared to real random white noise?


This is time-nuts.. it has to be perfect..

But realistically, my source is probably going to be about -90dBc/Hz 
at 1 Hz, -125 at 10Hz, -145 at 100 Hz.  I'm going up by a factor of 
10, so I'd expect 20 dB worse plus a little..(nothing is perfect, eh?)


Call it maybe -100 to -95 at 10 Hz, -125 to -120 at 100 Hz and so forth.

harmonics are interesting: it's the sample clock into an ADC. So 
harmonics of the 100 aren't a big deal.  harmonics of the 10 or 20 
are.  If you have significant 90 or 110 contaminating the 100, then 
you get weird spurs..  (I had this problem on a software radio where 
the 50 MHz sample clock was contaminated with some 66 MHz from the CPU)


Spurs cause the same issues.

ON the other hand... spurs that are pretty low don't make much 
difference if you're digitizing a signal that is close to the noise 
floor: the spur multiplied by the desired signal is usually lower and 
down in the noise.  Strong CW in band signals, though, are a real pain.



< 
https://picasaweb.google.com/103357048842463945642/Tronix#6079270188048833778 
>


I think that top left board would not be far away:

in : 10 MHz LVDS or CMOS
in:  3V3
out: 100 MHz CMOS 3V3

just a few hours wall clock time from layout to working as a
ham radio weekender, so please excuse my diy home board
production process.

Ok, the use of a 4046 descendant may not be the last word
from a timenut perspective, but I'll redo it with an osc of
my own anyway. Divider 100/10 is a LVC163 (161?) + lvc04.


< http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf >

Digi-Key has 153 of them on a tape and  441 of a similar one , even
cheaper that seems to point to the same data sheet.

< 
http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128 
>

You can get the few dB missing close-in by transfer from your reference.

In the picture:
The bottom row of boards is a doubler 100->200 MHz using 2*BF862, slight 
gain,
and diode doubler 200 -> 400 MHz, SAW filter to get rid of 
100/200/300/500/600 +/-10  etc,

post amp to get a usable level again.

Still missing  400-> 800, 800->1600 to feed  _my_ ADC clock input.

regards, Gerhard

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Re: [time-nuts] low noise multiplication to 100 MHz

[Dr. Ulrich Rohde via time-nuts]

Thank you , important new information
Sent from my iPhone

> On Jan 22, 2016, at 1:00 PM, "Tom Van Baak"  wrote:
> 
> The attached plot is from Dr. Ulrich Rohde (ka2...@aol.com)
> "a PDF of a noise plot , AM FM noise, important technical data"
> (he had trouble posting it to the list, so I'm doing it for him)
> 
> R_S_SMA_SIG_GEN_100MHz-02.pdf
> 
> /tvb
> 
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Re: [time-nuts] low noise multiplication to 100 MHz

[Artek Manuals]

On 1/22/2016 12:20 PM, jimlux wrote:

On 1/22/16 2:15 AM, REEVES Paul wrote:
Why not use something like an HP5254B/C ? They give out  50MHz 
harmonics up to the low Ghz region, all filtered by a nice high-Q 
tuneable cavity. All to typical HP build quality.
Of course, they have an amount of 'not needed' circuitry and are just 
a bit  . , well, bulky.  Good clean output from 10MHz in though.






I guess I wasn't totally clear in my original post. I was looking for 
ideas on circuits - I'm trying to fit this into a few square cm of 
board real estate.



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Jim

OK ...coming back to the original post and see if we can nail down ALL 
the design requirements


You said

"My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr, and
I'm looking at alternative schemes.
One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply them
up. I've got the Wenzel ap notes on 2diode and using HCMOS (and I've
used the packaged Wenzel multipliers), and I think I have some spare
board real estate on another board."

So I ask then, what is the real set of design requirements

1) Space of a few sq CM is the goal
2) 5X or 10X  frequency multiplication
3) Input and output level (?)
4)Title said "Low Noise"  needs better definition as to what kind of 
noise and how far down. Are we to be  concerned about harmonic and spur 
content as compared to real random white noise?

5) Power requirements (0 to 5V  at ?? ma ...or?)
6) Stability requirement in PPM?


Dave
NR1DX
ArtekManuals.com


--
Dave
manu...@artekmanuals.com
www.ArtekManuals.com


---
This email has been checked for viruses by Avast antivirus software.
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Re: [time-nuts] low noise multiplication to 100 MHz

[jimlux]

On 1/22/16 2:15 AM, REEVES Paul wrote:

Why not use something like an HP5254B/C ? They give out  50MHz harmonics up to 
the low Ghz region, all filtered by a nice high-Q tuneable cavity. All to 
typical HP build quality.
Of course, they have an amount of 'not needed' circuitry and are just a bit  
. , well, bulky.  Good clean output from 10MHz in though.





I guess I wasn't totally clear in my original post. I was looking for 
ideas on circuits - I'm trying to fit this into a few square cm of board 
real estate.


Sadly, if you put the 5254 into a big crusher and squeeze it down to the 
few cm size, the harmonic content seems to drop off dramatically 


I've got some fast Schottky diodes on order for another purpose, so I 
may breadboard the Wenzel circuit and see how it works. I'm thinking the 
1N914 in the Wenzel article might not work so well at 100MHz. I might 
not wind up using it this time, but it's useful to try it.


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Re: [time-nuts] low noise multiplication to 100 MHz

[timeok]

Have a look on this:

http://www.timeok.it/wp/wp-content/uploads/2015/08/10_to_100_mhz_multiplier1.pdf

Luciano
timeok

On Fri 22/01/16 11:15 , REEVES Paul <paul.ree...@uk.thalesgroup.com> wrote:

> Why not use something like an HP5254B/C ? They give out 50MHz harmonics up
> to the low Ghz region, all filtered by a nice high-Q tuneable cavity. All
> to typical HP build quality.
> Of course, they have an amount of 'not needed' circuitry and are just a
> bit . , well, bulky. Good clean output from 10MHz in though.
> 
> Paul G8GJA
> 
> -Original Message-
> From: time-nuts [time-nuts-boun...@febo.com] On Behalf Of Peter Reilley
> Sent: 21 January 2016 15:17
> To: time-nuts@febo.com
> Subject: Re: [time-nuts] low noise multiplication to 100 MHz
> 
> Have you considered synthesizers? I am using an Analog Devices AD9517
> to drive a A/D
> converter at 250 MHz. It has many clock outputs that are independently
> configurable.
> It is intended for low jitter applications.
> 
> Pete.
> 
> On 1/21/2016 9:43 AM, jimlux wrote:
> > My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr,
> > and I'm looking at alternative schemes.
> > One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply
> > them up. I've got the Wenzel ap notes on 2diode and using HCMOS (and
> > I've used the packaged Wenzel multipliers), and I think I have some
> > spare board real estate on another board.
> >
> > The 2diode multiplier describes using 1n5711 or 1n914, but I was
> > wondering if anyone has run this sort of multiplier up to 100 MHz?
> >
> > What sort of symmetry does the resulting waveform have (yeah, it's
> > basically a filtered sinewave, because you're picking a harmonic, but
> > I've been surprised before)?
> >
> >
> >
> >
> > I'm driving an FPGA and a couple of ADCs. The ADCs have differential
> > input that is 10kohms with 9pF in parallel offset from ground in the
> > usual way (we're using a transformer and appropriate bias resistors).
> > Not a 50 ohm load, in any case. And it wants a clock that is high for
> > about 47.5% to 52.5% in one mode and much wider (30%-70% in another)..
> > I need to check.
> >
> > The FPGA is less critical noise-wise, and has a AD8138 buffer in any
> > case, which can fix a variety of evils.
> >
> >
> >
> > ___
> > time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
> > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts [1]
> > and follow the instructions there.
> >
> 
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Re: [time-nuts] low noise multiplication to 100 MHz

[REEVES Paul]

Why not use something like an HP5254B/C ? They give out  50MHz harmonics up to 
the low Ghz region, all filtered by a nice high-Q tuneable cavity. All to 
typical HP build quality.
Of course, they have an amount of 'not needed' circuitry and are just a bit  
. , well, bulky.  Good clean output from 10MHz in though.

Paul   G8GJA

-Original Message-
From: time-nuts [mailto:time-nuts-boun...@febo.com] On Behalf Of Peter Reilley
Sent: 21 January 2016 15:17
To: time-nuts@febo.com
Subject: Re: [time-nuts] low noise multiplication to 100 MHz

Have you considered synthesizers?   I am using an Analog Devices AD9517 
to drive a A/D
converter at 250 MHz.   It has many clock outputs that are independently 
configurable.
It is intended for low jitter applications.

Pete.

On 1/21/2016 9:43 AM, jimlux wrote:
> My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr, 
> and I'm looking at alternative schemes.
> One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply 
> them up. I've got the Wenzel ap notes on 2diode and using HCMOS (and 
> I've used the packaged Wenzel multipliers), and I think I have some 
> spare board real estate on another board.
>
> The 2diode multiplier describes using 1n5711 or 1n914, but I was 
> wondering if anyone has run this sort of multiplier up to 100 MHz?
>
> What sort of symmetry does the resulting waveform have (yeah, it's 
> basically a filtered sinewave, because you're picking a harmonic, but 
> I've been surprised before)?
>
>
>
>
> I'm driving an FPGA and a couple of ADCs.  The ADCs have differential 
> input that is 10kohms with 9pF in parallel offset from ground in the 
> usual way (we're using a transformer and appropriate bias resistors).
> Not a 50 ohm load, in any case.  And it wants a clock that is high for 
> about 47.5% to 52.5% in one mode and much wider (30%-70% in another)..
> I need to check.
>
> The FPGA is less critical noise-wise, and has a AD8138 buffer in any 
> case, which can fix a variety of evils.
>
>
>
> ___
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Re: [time-nuts] low noise multiplication to 100 MHz

[jimlux]

On 1/22/16 12:43 PM, Artek Manuals wrote:


OK ...coming back to the original post and see if we can nail down ALL
the design requirements



well, I wasn't really thinking in terms of formal design requirements.. 
(I get more than enough of that at work)


I was more looking for potential circuits..

But, since you ask...




You said

"My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr, and
I'm looking at alternative schemes.
One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply them
up. I've got the Wenzel ap notes on 2diode and using HCMOS (and I've
used the packaged Wenzel multipliers), and I think I have some spare
board real estate on another board."

So I ask then, what is the real set of design requirements

1) Space of a few sq CM is the goal
2) 5X or 10X  frequency multiplication
3) Input and output level (?)

the oscillator is a HCMOS output, so figure swinging about 3.5V
Output.. I'm feeding differential clock inputs on ADCs.  I'll bet a +/- 
300mV swing would work.



4)Title said "Low Noise"  needs better definition as to what kind of
noise and how far down. Are we to be  concerned about harmonic and spur
content as compared to real random white noise?


This is time-nuts.. it has to be perfect..

But realistically, my source is probably going to be about -90dBc/Hz at 
1 Hz, -125 at 10Hz, -145 at 100 Hz.  I'm going up by a factor of 10, so 
I'd expect 20 dB worse plus a little..(nothing is perfect, eh?)


Call it maybe -100 to -95 at 10 Hz, -125 to -120 at 100 Hz and so forth.

harmonics are interesting: it's the sample clock into an ADC. So 
harmonics of the 100 aren't a big deal.  harmonics of the 10 or 20 are. 
 If you have significant 90 or 110 contaminating the 100, then you get 
weird spurs..  (I had this problem on a software radio where the 50 MHz 
sample clock was contaminated with some 66 MHz from the CPU)


Spurs cause the same issues.

ON the other hand... spurs that are pretty low don't make much 
difference if you're digitizing a signal that is close to the noise 
floor: the spur multiplied by the desired signal is usually lower and 
down in the noise.  Strong CW in band signals, though, are a real pain.







5) Power requirements (0 to 5V  at ?? ma ...or?)


Very low is nice..
the base oscillator is a few hundred mW. I'd say something like a watt 
all told would be acceptable..   But on the other hand, when you get up 
to "watts" and "big" then you might as well just buy another OCXO that 
is at 100 MHz instead of the nifty little tiny ones I was planning to 
use.  (of course, the big OCXOs tend to have +12V power, which I don't 
have..I have unregulated 7.5 to 8V and regulated 5 or 3.3.


It's an interesting tradeoff.


6) Stability requirement in PPM?


That's driven by the base oscillator. But in reality, I don't have a 
particularly tight long term frequency requirement.  I have a long term 
frequency knowledge requirement (which can be met by just counting the 
oscillator with the GPS 1pps).







Dave
NR1DX
ArtekManuals.com




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[time-nuts] low noise multiplication to 100 MHz

[jimlux]

My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr, and 
I'm looking at alternative schemes.
One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply them 
up. I've got the Wenzel ap notes on 2diode and using HCMOS (and I've 
used the packaged Wenzel multipliers), and I think I have some spare 
board real estate on another board.


The 2diode multiplier describes using 1n5711 or 1n914, but I was 
wondering if anyone has run this sort of multiplier up to 100 MHz?


What sort of symmetry does the resulting waveform have (yeah, it's 
basically a filtered sinewave, because you're picking a harmonic, but 
I've been surprised before)?





I'm driving an FPGA and a couple of ADCs.  The ADCs have differential 
input that is 10kohms with 9pF in parallel offset from ground in the 
usual way (we're using a transformer and appropriate bias resistors). 
Not a 50 ohm load, in any case.  And it wants a clock that is high for 
about 47.5% to 52.5% in one mode and much wider (30%-70% in another).. I 
need to check.


The FPGA is less critical noise-wise, and has a AD8138 buffer in any 
case, which can fix a variety of evils.




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Re: [time-nuts] low noise multiplication to 100 MHz

[Peter Reilley]

Have you considered synthesizers?   I am using an Analog Devices AD9517 
to drive a A/D
converter at 250 MHz.   It has many clock outputs that are independently 
configurable.

It is intended for low jitter applications.

Pete.

On 1/21/2016 9:43 AM, jimlux wrote:
My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr, 
and I'm looking at alternative schemes.
One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply 
them up. I've got the Wenzel ap notes on 2diode and using HCMOS (and 
I've used the packaged Wenzel multipliers), and I think I have some 
spare board real estate on another board.


The 2diode multiplier describes using 1n5711 or 1n914, but I was 
wondering if anyone has run this sort of multiplier up to 100 MHz?


What sort of symmetry does the resulting waveform have (yeah, it's 
basically a filtered sinewave, because you're picking a harmonic, but 
I've been surprised before)?





I'm driving an FPGA and a couple of ADCs.  The ADCs have differential 
input that is 10kohms with 9pF in parallel offset from ground in the 
usual way (we're using a transformer and appropriate bias resistors). 
Not a 50 ohm load, in any case.  And it wants a clock that is high for 
about 47.5% to 52.5% in one mode and much wider (30%-70% in another).. 
I need to check.


The FPGA is less critical noise-wise, and has a AD8138 buffer in any 
case, which can fix a variety of evils.




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Re: [time-nuts] low noise multiplication to 100 MHz

[Richard (Rick) Karlquist]

It is interesting that the HP8662A multiplies 10 MHz to 640 MHz,
in steps of 2X.  But there is a crystal filter at 80 MHz to
clean up the wideband noise of the 10811.  In the 11729, they
filter the 640 MHz from the 8662 with a SAW filter, again to
eliminate multiplied up wideband noise.  It's going to be
tough to replace a 100 MHz OCXO by multiplying.  You have
the additional problem that 100 MHz is not a power of 2
multiplication.  I think you're stuck waiting for your
OCXO's.

Rick Karlquist N6RK



On 1/21/2016 6:43 AM, jimlux wrote:

My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr, and
I'm looking at alternative schemes.
One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply them
up. I've got the Wenzel ap notes on 2diode and using HCMOS (and I've
used the packaged Wenzel multipliers), and I think I have some spare
board real estate on another board.

The 2diode multiplier describes using 1n5711 or 1n914, but I was
wondering if anyone has run this sort of multiplier up to 100 MHz?

What sort of symmetry does the resulting waveform have (yeah, it's
basically a filtered sinewave, because you're picking a harmonic, but
I've been surprised before)?




I'm driving an FPGA and a couple of ADCs.  The ADCs have differential
input that is 10kohms with 9pF in parallel offset from ground in the
usual way (we're using a transformer and appropriate bias resistors).
Not a 50 ohm load, in any case.  And it wants a clock that is high for
about 47.5% to 52.5% in one mode and much wider (30%-70% in another).. I
need to check.

The FPGA is less critical noise-wise, and has a AD8138 buffer in any
case, which can fix a variety of evils.



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Re: [time-nuts] low noise multiplication to 100 MHz

[jimlux]

On 1/21/16 7:17 AM, Peter Reilley wrote:

Have you considered synthesizers?   I am using an Analog Devices AD9517
to drive a A/D
converter at 250 MHz.   It has many clock outputs that are independently
configurable.
It is intended for low jitter applications.



So you run the PLL VCO at 1 GHz or something and program it to divide down?

I'm a bit leery of parts that talk about "low jitter" because they 
typically integrate from 10kHz out to some MHz, and I'm concerned about 
phase noise in the <10kHz offset range.


I guess that really depends on what the loop bandwidth is, the noise I'm 
concerned about is probably inside the loop and will be driven by my 
reference.


I'll take a look at the part.



Pete.

On 1/21/2016 9:43 AM, jimlux wrote:

My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr,
and I'm looking at alternative schemes.
One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply
them up. I've got the Wenzel ap notes on 2diode and using HCMOS (and
I've used the packaged Wenzel multipliers), and I think I have some
spare board real estate on another board.

The 2diode multiplier describes using 1n5711 or 1n914, but I was
wondering if anyone has run this sort of multiplier up to 100 MHz?

What sort of symmetry does the resulting waveform have (yeah, it's
basically a filtered sinewave, because you're picking a harmonic, but
I've been surprised before)?




I'm driving an FPGA and a couple of ADCs.  The ADCs have differential
input that is 10kohms with 9pF in parallel offset from ground in the
usual way (we're using a transformer and appropriate bias resistors).
Not a 50 ohm load, in any case.  And it wants a clock that is high for
about 47.5% to 52.5% in one mode and much wider (30%-70% in another)..
I need to check.

The FPGA is less critical noise-wise, and has a AD8138 buffer in any
case, which can fix a variety of evils.



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Re: [time-nuts] low noise multiplication to 100 MHz

[Gerhard Hoffmann]

Am 21.01.2016 um 15:43 schrieb jimlux:
My tiny 100 MHz low noise OCXOs are unexpectedly delayed at the mfr, 
and I'm looking at alternative schemes.
One is to get 10 or 20 MHz OCXOs (typically in stock) and multiply 
them up. I've got the Wenzel ap notes on 2diode and using HCMOS (and 
I've used the packaged Wenzel multipliers), and I think I have some 
spare board real estate on another board.



What about locking a 100MHz Crystek CVHD-950 to a 10 MHz ref?
Far out it will not be wonderful, but still better than a multiplied-up 
10 MHz,

close-in the 10 MHz rules.

Has anybody seen seen this simple Wenzel locking circuit?
< http://www.crovencrystals.com/pllclock.htm >

opinions?

regards, Gerhard

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Re: [time-nuts] low noise multiplication to 100 MHz

[jimlux]

On 1/21/16 9:26 AM, Richard (Rick) Karlquist wrote:

It is interesting that the HP8662A multiplies 10 MHz to 640 MHz,
in steps of 2X.  But there is a crystal filter at 80 MHz to
clean up the wideband noise of the 10811.  In the 11729, they
filter the 640 MHz from the 8662 with a SAW filter, again to
eliminate multiplied up wideband noise.  It's going to be
tough to replace a 100 MHz OCXO by multiplying.  You have
the additional problem that 100 MHz is not a power of 2
multiplication.  I think you're stuck waiting for your
OCXO's.

Rick Karlquist N6RK



Not so much the wait (which is painful, but can be accommodated), as the 
risk that they might not work at all, or that there's another slip. 
Unexpected delay is often "we couldn't get it to work yet". Or, it could 
be "Bob, the guy who does this, is snowbound for a week".  You never 
know for sure, eh?


So, I'm coming up with backup plans..
something like 20 MHz OCXO, x5 Wenzel 2 diode multiplier, PotatoSemi buffer.

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