Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 16:34:08 -0800 jimlux wrote: > On 1/20/20 3:40 PM, Mark Haun wrote: > > On Mon, 20 Jan 2020 17:31:51 -0500 > > Bob kb8tq wrote: > > > > Unfortunately I suspect the added digital power consumption in the > > FPGA would be greater than the analog power for a PLL solution. As > > much as it pains me to say that as a DSP guy ;) I need to think > > about this some more, though. > > Many (big) FPGAs these days have power consumption dominated by the > leakage current of all the gates. Even going back as far as the > Virtex 4, the dependence of power on clock rate and number of gates > toggling is pretty small. > > I've not checked something like a Zynq. This is why I'm targeting a small-ish Spartan 7, probably XC7S25. Datasheet quiescent current on all supplies is on the order of 70 mW. Pretty impressive when compared with only a couple of generations ago. And even this small FPGA gives you 80 DSP blocks and 1.6 Mbits of block RAM. Mark ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On 1/20/20 3:40 PM, Mark Haun wrote: On Mon, 20 Jan 2020 17:31:51 -0500 Bob kb8tq wrote: Unfortunately I suspect the added digital power consumption in the FPGA would be greater than the analog power for a PLL solution. As much as it pains me to say that as a DSP guy ;) I need to think about this some more, though. Many (big) FPGAs these days have power consumption dominated by the leakage current of all the gates. Even going back as far as the Virtex 4, the dependence of power on clock rate and number of gates toggling is pretty small. I've not checked something like a Zynq. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 15:40:08 -0800 Mark Haun wrote: > I was about to say that adding a second ADC channel is really expensive > (like $50 between AD9266 and AD9269), but I really like this idea... > just couple a reference oscillator into the main signal path at an > appropriate level, then use a parallel receive path in the FPGA > to trim the NCOs for the known beacon frequency. You don't need a high performance ADC for the reference as you are dealing with a narrow band signal of known frequency. Even a 10bit or 8bit ADC would be good enough. You can even go and sample at half frequency and save both money and power. This works because the required bandwidth of the signal to track properly is low, somewhere in the order of 1-10kHz should be enough. Thus working with just a few bits on the ADC and then decimating you get lots of bits. E.g. going from 40MHz to 40kHz results in approximately 9bits more. Starting from a 8bit ADC this gives something around 15bits (probably more like 12-14bits, not accounting for ADC and sampling noise and numerical precision), which is already good enough to track at a rate of 100-500Hz. If you choose a different frequency for the sampling clock, that is "odd", let's say 155.52MHz/2=77.76MHz, you can sample even further down (e.g. at 7.776MHz) and get to lower cost and lower power ADCs. There is one key parameter for this ADC that you should not skimp on, though. It's apperture jitter, as this directly translates into tracking noise of the reference. > Unfortunately I suspect the added digital power consumption in the FPGA > would be greater than the analog power for a PLL solution. As much as > it pains me to say that as a DSP guy ;) I need to think about this > some more, though. Hmm... My gut feeling would say that the ADC+tracking approach should be lower power... But I have not done the calculation, so I might be wrong. But yes, there are several design choices and trade-offs that need to be balanced, that directly affect cost and power consumption. Attila Kinali -- The bad part of Zurich is where the degenerates throw DARK chocolate at you. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Link does not work, but https://www.digikey.de/product-detail/de/ecs-inc/ECOC-2522-100.000-3FC/XC2265-ND/6578492 Sorry, Gerhard ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Am 20.01.20 um 22:57 schrieb Attila Kinali: On Mon, 20 Jan 2020 12:50:09 -0800 Mark Haun wrote: True enough, but remember that my motivation for using the OCXO in the first place was to combine the required phase-noise spec with OCXO-class frequency stability (this is for narrowband coherent modulation schemes on the shortwave bands where short-term stability of ~ 10^-10 is nice to have). The alternative is what Attila said, VCXO phase locked to an OCXO. The advantage of doing it this way is that I [potentially] reduce complexity, board space, and power. For an SDR application, the ABLNO allone would be the best option, IMHO. It's low power and low noise. Even for narrowband SW applications. If you look at the data, you see that the cross-over between the ABLNO is lower noise to the OCXO is lower noise is around 100Hz. Unless you are operating at much lower than 100baud, the ABLNO is going to be enough. If you are using something like AFSK31/PSK31 it's probably borderline which one is better and I would go with the ABLNO only for simpler construction and easier sourcing. If you are thinking about trpoposcatter, EME or similar things with really low baud rates, then I would go for the VCXO+PLL approach for one simple reason: Flexibility. With a PLL you have a choice what kind of reference you want to use. For a back burner project, motorcycle based portable 432 MHz EME, (i.e. collecting squares with a friend of mine who has a _huge_ antenna), I decided to use one of these < https://www.digikey.de/de/product-highlight/e/ecs/ecoc-2522-smd-ocxo > and call it a day. 432 - (4*100) = 32 MHz = somewhere in the middle of the Red Pitaya passband. And the Red Pitaya could also run on the 100 MHz. There happen to exist nice SAW-Filters for both 400 and 432 MHz. No tuning. There is no Baud rate on EME, just a 600 Hz side tone. :-) Or WSJE. regards, Gerhard, DK4XP ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 17:31:51 -0500 Bob kb8tq wrote: > > On Jan 20, 2020, at 5:16 PM, jimlux wrote: > > On 1/20/20 1:57 PM, Attila Kinali wrote: > >> And then there ia third way, which is IMHO even better: > >> Your application is an SDR system, i.e. you already need some > >> signal processing for the system to work. Why not extend this > >> to use it for the reference as well? Add another ADC and feed > >> the reference signal to that, then track the phase/frequency > >> relation between the sampling clock and the reference and > >> compensate any drift in the signal path. This way you get to > >> disable the reference if it is not needed and save a lot of power > >> and at the same time are able to use references with any frequency > >> and can change the "loop frequency" freely without the need to > >> worry about PLL stability or tempco of filters in the multiplier > >> version. > > > > This ... > > > > This is the way of the future. The problem is that there are > > enough legacy systems out there where you need "control" vs > > "knowledge" > > > > And, in the SDR world: while theoretically, you can do this in > > software, a lot of times the software is either a black box, or > > incomprehensible in finite time, or architected in a way that makes > > it hard, that it's actually faster and easier to discipline the > > reference oscillator than to fix the software. > > If your “reference” is a 10 MHz OCXO, that may well come down on top > / very near something you might want to receive. Having seen what WWV > uses as an exciter … indeed their noise “as transmitted” is pretty > darn good. > > If the reference is 16.384 …. hmmm …. maybe not so much. I can’t > think of much around there worth tuning in to. Simply feeding the > OCXO (at a very low level) into a single ADC might well do the trick. > ( yes, you have a number of things to dig into, it’s not quite the > slam dunk I’m making it out to be). I was about to say that adding a second ADC channel is really expensive (like $50 between AD9266 and AD9269), but I really like this idea... just couple a reference oscillator into the main signal path at an appropriate level, then use a parallel receive path in the FPGA to trim the NCOs for the known beacon frequency. Unfortunately I suspect the added digital power consumption in the FPGA would be greater than the analog power for a PLL solution. As much as it pains me to say that as a DSP guy ;) I need to think about this some more, though. Thanks for the ideas, Mark ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi > On Jan 20, 2020, at 5:16 PM, jimlux wrote: > > On 1/20/20 1:57 PM, Attila Kinali wrote: > >> And then there ia third way, which is IMHO even better: >> Your application is an SDR system, i.e. you already need some >> signal processing for the system to work. Why not extend this >> to use it for the reference as well? Add another ADC and feed >> the reference signal to that, then track the phase/frequency >> relation between the sampling clock and the reference and >> compensate any drift in the signal path. This way you get to >> disable the reference if it is not needed and save a lot of power >> and at the same time are able to use references with any frequency >> and can change the "loop frequency" freely without the need to >> worry about PLL stability or tempco of filters in the multiplier >> version. > > This ... > > This is the way of the future. The problem is that there are enough legacy > systems out there where you need "control" vs "knowledge" > > And, in the SDR world: while theoretically, you can do this in software, a > lot of times the software is either a black box, or incomprehensible in > finite time, or architected in a way that makes it hard, that it's actually > faster and easier to discipline the reference oscillator than to fix the > software. If your “reference” is a 10 MHz OCXO, that may well come down on top / very near something you might want to receive. Having seen what WWV uses as an exciter … indeed their noise “as transmitted” is pretty darn good. If the reference is 16.384 …. hmmm …. maybe not so much. I can’t think of much around there worth tuning in to. Simply feeding the OCXO (at a very low level) into a single ADC might well do the trick. ( yes, you have a number of things to dig into, it’s not quite the slam dunk I’m making it out to be). Bob > > I say this as someone who makes his living designing, building, and using > SDRs - a Curse on Matt Ettus and USRPs, gnuradio, pothos, etc. and their ease > of use, allowing positive legions of people to produce software which is > horrible, without realizing the implications and defects within. They should > all be consulting *me* before engaging in these ill advised implementations > based on textbook descriptions from Oppenheim and Schaefer, etc. > > > But yes, the *best* way to do it is to *measure* the oscillator and use that > to correct the digitized data, rather than driving the oscillator. > It is challenging, though, to do this in a system where there is a need for > full duplex operation (i.e. the transmitted signal needs to be adjusted to > match the received signal). > > > > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On 1/20/20 1:57 PM, Attila Kinali wrote: And then there ia third way, which is IMHO even better: Your application is an SDR system, i.e. you already need some signal processing for the system to work. Why not extend this to use it for the reference as well? Add another ADC and feed the reference signal to that, then track the phase/frequency relation between the sampling clock and the reference and compensate any drift in the signal path. This way you get to disable the reference if it is not needed and save a lot of power and at the same time are able to use references with any frequency and can change the "loop frequency" freely without the need to worry about PLL stability or tempco of filters in the multiplier version. This ... This is the way of the future. The problem is that there are enough legacy systems out there where you need "control" vs "knowledge" And, in the SDR world: while theoretically, you can do this in software, a lot of times the software is either a black box, or incomprehensible in finite time, or architected in a way that makes it hard, that it's actually faster and easier to discipline the reference oscillator than to fix the software. I say this as someone who makes his living designing, building, and using SDRs - a Curse on Matt Ettus and USRPs, gnuradio, pothos, etc. and their ease of use, allowing positive legions of people to produce software which is horrible, without realizing the implications and defects within. They should all be consulting *me* before engaging in these ill advised implementations based on textbook descriptions from Oppenheim and Schaefer, etc. But yes, the *best* way to do it is to *measure* the oscillator and use that to correct the digitized data, rather than driving the oscillator. It is challenging, though, to do this in a system where there is a need for full duplex operation (i.e. the transmitted signal needs to be adjusted to match the received signal). ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On 1/20/20 1:13 PM, Bob kb8tq wrote: Hi I think you will find that some fairly generic oscillators will hit the “more or less 1x10^-10” sort of spec needed for HF com work. A good OCXO will get you into the 1x10^-12 range. The limit generally is the “floor” imposed by propagation variance at HF. Bob And the source's phase noise. There are relatively few "spectrally pure" transmitters in the HF band that are sufficiently clean that you can measure the ionospheric effects. WWV/H, ARRL FMTs, ionosondes (maybe), and a few other things. For what it's worth, the decorrelation time for ionosphere is about 3 seconds. That is, the state of the ionosphere on any given path is almost entirely uncorrelated to the state 3 seconds earlier. So AVAR at 100 seconds isn't worth a whole lot, unless you're measuring the ionosphere. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On 1/20/20 12:50 PM, Mark Haun wrote: On Mon, 20 Jan 2020 15:25:00 -0500 Bob kb8tq wrote: On Jan 20, 2020, at 2:57 PM, Mark Haun wrote: Agree except you were starting from the VFOV numbers for the 100-MHz version. If you use their numbers for the 10-MHz version and add 20 dB for an ideal 10x multiplication, for comparing with the ABLNO spec at 100 MHz, you end up with offsetVFOV405 @ 10M, ideal 10x multiply ABLNO @ 100 M 10-100 -88 100 -120 -118 1k-140 -141 10k -145 -160 100k -145 -161 If indeed -145 is “good enough” then you have moved out of the “good phase noise” region into fairly generic sort of specs. A “couple of dollar” oscillator will give you -145 sort of noise floors. True enough, but remember that my motivation for using the OCXO in the first place was to combine the required phase-noise spec with OCXO-class frequency stability (this is for narrowband coherent modulation schemes on the shortwave bands where short-term stability of ~ 10^-10 is nice to have). The alternative is what Attila said, VCXO phase locked to an OCXO. The advantage of doing it this way is that I [potentially] reduce complexity, board space, and power. Hypothetically, sure, any old 80-MHz OCXO with "generic" phase-noise performance would suffice. But hobbyists can't just pick up the phone and order something like that; we're limited to surplus/used stock, where 80-ish MHz is unusual. And of course most surplus/used OCXOs would require high voltage (5V or above), high power (half a watt or more), or both. Sorry, I didn't plan to expound on my design rationale at such length, but you seemed curious :) Learning about design rationale is what this list is all about. As Bob and others have pointed out over the years, oscillator manufacturers will happily give you what ever you specify, for a price. But it's not unusual to have a low volume application where you're willing to take what you can get, as long as it meets some other requirement (cost, delivery time). The problem is that it's hard to convey all the trades in a requirements or spec document. "Sure, I'm happy to have high far out noise, but *I* care about noise between 10-1000 Hz" or "I don't care about absolute frequency stability over temperature or long term, because I'm putting it in an oven and I'm going to be able to discipline/measure it, but I want really good close in noise" The amateur radio person wanting to multiply their reference up to 10 GHz for narrow band CW is a fine example - They probably have way to measure frequency, so absolute stability isn't all that important. And they want low power (because you're sitting on some mountain top with batteries). And, there's only a few hundred people in the entire world who would conceivably be interested in it, and maybe 3 who would try, and they all want to spend less than $100. Vectron, Abracon, etc. do not have a business case that contemplates this idiosyncratic market (nor should they). But it is useful to know what the "care-abouts" are, because often, there is lore (that cannot be used as a spec) about stuff that might work. For my space OCXO need, I started by asking manufacturers if they could make me a small OCXO with the heater disconnected - so I didn't have to spend heater power or have a 15V power supply. I wound up with a OCXO that *did* have a heater, but the heater power is negligible. And, as a side effect, it actually gives me visibility into the internal state of the device, because by knowing just bus current vs time, I can tell approximately what temperature things were at when it was turned on. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 12:50:09 -0800 Mark Haun wrote: > True enough, but remember that my motivation for using the OCXO in the > first place was to combine the required phase-noise spec with > OCXO-class frequency stability (this is for narrowband coherent > modulation schemes on the shortwave bands where short-term stability of > ~ 10^-10 is nice to have). The alternative is what Attila said, > VCXO phase locked to an OCXO. The advantage of doing it this way is > that I [potentially] reduce complexity, board space, and power. For an SDR application, the ABLNO allone would be the best option, IMHO. It's low power and low noise. Even for narrowband SW applications. If you look at the data, you see that the cross-over between the ABLNO is lower noise to the OCXO is lower noise is around 100Hz. Unless you are operating at much lower than 100baud, the ABLNO is going to be enough. If you are using something like AFSK31/PSK31 it's probably borderline which one is better and I would go with the ABLNO only for simpler construction and easier sourcing. If you are thinking about trpoposcatter, EME or similar things with really low baud rates, then I would go for the VCXO+PLL approach for one simple reason: Flexibility. With a PLL you have a choice what kind of reference you want to use. E.g. converting the system to use a MV86 would be just a different footprint and different register settings for the PLL. And then there ia third way, which is IMHO even better: Your application is an SDR system, i.e. you already need some signal processing for the system to work. Why not extend this to use it for the reference as well? Add another ADC and feed the reference signal to that, then track the phase/frequency relation between the sampling clock and the reference and compensate any drift in the signal path. This way you get to disable the reference if it is not needed and save a lot of power and at the same time are able to use references with any frequency and can change the "loop frequency" freely without the need to worry about PLL stability or tempco of filters in the multiplier version. Attila Kinali -- The bad part of Zurich is where the degenerates throw DARK chocolate at you. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi I think you will find that some fairly generic oscillators will hit the “more or less 1x10^-10” sort of spec needed for HF com work. A good OCXO will get you into the 1x10^-12 range. The limit generally is the “floor” imposed by propagation variance at HF. Bob > On Jan 20, 2020, at 3:50 PM, Mark Haun wrote: > > On Mon, 20 Jan 2020 15:25:00 -0500 > Bob kb8tq wrote: >> On Jan 20, 2020, at 2:57 PM, Mark Haun wrote: >>> Agree except you were starting from the VFOV numbers for the 100-MHz >>> version. If you use their numbers for the 10-MHz version and add >>> 20 dB for an ideal 10x multiplication, for comparing with the ABLNO >>> spec at 100 MHz, you end up with >>> >>> offsetVFOV405 @ 10M, ideal 10x multiply ABLNO @ 100 M >>> 10-100 -88 >>> 100 -120 -118 >>> 1k-140 -141 >>> 10k -145 -160 >>> 100k -145 -161 >> >> If indeed -145 is “good enough” then you have moved out of the “good >> phase noise” region into fairly generic sort of specs. A “couple of >> dollar” oscillator will give you -145 sort of noise floors. > > True enough, but remember that my motivation for using the OCXO in the > first place was to combine the required phase-noise spec with > OCXO-class frequency stability (this is for narrowband coherent > modulation schemes on the shortwave bands where short-term stability of > ~ 10^-10 is nice to have). The alternative is what Attila said, > VCXO phase locked to an OCXO. The advantage of doing it this way is > that I [potentially] reduce complexity, board space, and power. > > Hypothetically, sure, any old 80-MHz OCXO with "generic" phase-noise > performance would suffice. But hobbyists can't just pick up the phone > and order something like that; we're limited to surplus/used stock, > where 80-ish MHz is unusual. And of course most surplus/used OCXOs > would require high voltage (5V or above), high power (half a watt or > more), or both. > > Sorry, I didn't plan to expound on my design rationale at such length, > but you seemed curious :) > > Regards, > Mark > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 15:25:00 -0500 Bob kb8tq wrote: > On Jan 20, 2020, at 2:57 PM, Mark Haun wrote: > > Agree except you were starting from the VFOV numbers for the 100-MHz > > version. If you use their numbers for the 10-MHz version and add > > 20 dB for an ideal 10x multiplication, for comparing with the ABLNO > > spec at 100 MHz, you end up with > > > > offsetVFOV405 @ 10M, ideal 10x multiply ABLNO @ 100 M > > 10-100 -88 > > 100 -120 -118 > > 1k-140 -141 > > 10k -145 -160 > > 100k -145 -161 > > If indeed -145 is “good enough” then you have moved out of the “good > phase noise” region into fairly generic sort of specs. A “couple of > dollar” oscillator will give you -145 sort of noise floors. True enough, but remember that my motivation for using the OCXO in the first place was to combine the required phase-noise spec with OCXO-class frequency stability (this is for narrowband coherent modulation schemes on the shortwave bands where short-term stability of ~ 10^-10 is nice to have). The alternative is what Attila said, VCXO phase locked to an OCXO. The advantage of doing it this way is that I [potentially] reduce complexity, board space, and power. Hypothetically, sure, any old 80-MHz OCXO with "generic" phase-noise performance would suffice. But hobbyists can't just pick up the phone and order something like that; we're limited to surplus/used stock, where 80-ish MHz is unusual. And of course most surplus/used OCXOs would require high voltage (5V or above), high power (half a watt or more), or both. Sorry, I didn't plan to expound on my design rationale at such length, but you seemed curious :) Regards, Mark ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi > On Jan 20, 2020, at 3:12 PM, jimlux wrote: > > On 1/20/20 11:44 AM, Bob kb8tq wrote: >> Hi >>> On Jan 20, 2020, at 2:38 PM, jimlux wrote: >>> >>> On 1/20/20 10:01 AM, Mark Haun wrote: >>> A fair question... in fact I was initially planning to use the ABLNO + a PLL. The OCXOs I found, however, are CTS VFOV405's with phase noise claimed to be just as good as the ABLNO or CVHD VCXOs: https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf They are reasonably low power, small[-ish], and have adequate stability for my needs. You can see why it is tempting to make the multiplier scheme work, as it should save on both power and board area. (The target application is a battery-powered SDR.) So far there don't seem to be any show-stopper issues with the plan, except that I am going to have to put together a phase-noise measurement system, or find a friend with one. >>> >>> Have you checked delivery times? - Just because it's listed in the catalog >>> does not mean you can get it in the next few weeks or months. If the online >>> sources (Digikey, mouser, Newark, etc.) have them in stock, then you're >>> good to go, but otherwise you could be looking at 6 months or more. >> …. and maybe nasty stuff like minimum order quantities in the range of 10 or >> 20 pieces ( or prices below that which work out to the same thing). > > > Been there, done that. I have a few extra 100 MHz tiny Vectron EX-421 OCXOs > at work because I had to order more than the 3 I needed. I need to find a > project at work to use them. Hmmm … wonder who talked you into that silliness …. :) :) :) Bob > > These are 100MHz units, ran about $262 each (in qty 6) (I'm going to guess > that Vectron has a minimum order of $1500 or something like that) > > The PN performance is better than either of the other two, but it's also not > a VCXO. It's probably "representative" of the performance that's achievable > in a small package at low power, though. > > FWIW, they seem to work fine in space, although they're not space qualified - > over 6 months or so, I didn't see any particular changes in frequency > compared to GPS or a CSAC that wouldn't just be aging. > > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi > On Jan 20, 2020, at 2:57 PM, Mark Haun wrote: > > On Mon, 20 Jan 2020 14:22:41 -0500 > Bob kb8tq wrote: >> On Jan 20, 2020, at 1:36 PM, Mark Haun wrote: >>> The VFOV405 datasheet lists typical phase noise for 10- and 100-MHz >>> units. (Mine are 16.384 MHz.) In comparing the two oscillators, I >>> have used the 100-MHz "typical" numbers which they both state: >> >> So taking the 14 db from multiplication into account: >> >> >> VFO405 ABLNO >> >> 1K -126-141 >> 10K -146-160 >> 100K -149-161 >> >> Looking at the plots on the ABLNO data sheets, the wide band noise >> gets down a bit below -161 on a “typical” basis. >> >> Locking an 80 MHz ABLNO to 16.384 is not going to be as easy as >> locking one to 16.000. Getting an ABLNO with an EFC at 16.384 x 5 may >> be a bit of a challenge. > > Agree except you were starting from the VFOV numbers for the 100-MHz > version. If you use their numbers for the 10-MHz version and add 20 dB > for an ideal 10x multiplication, for comparing with the ABLNO spec at > 100 MHz, you end up with > > offsetVFOV405 @ 10M, ideal 10x multiply ABLNO @ 100 M > 10-100 -88 > 100 -120 -118 > 1k-140 -141 > 10k -145 -160 > 100k -145 -161 If indeed -145 is “good enough” then you have moved out of the “good phase noise” region into fairly generic sort of specs. A “couple of dollar” oscillator will give you -145 sort of noise floors. The value of 12 db at 10 Hz offset is going to be pretty limited unless the application is very unusual. Bob > > so not bad apart from the raised floor. (I am assuming that an ideal 5x > multiplication on the 16.384-MHz version of the VFOV405 would yield a > similar comparison to an 80-MHz ABLNO.) > > Using this handy tool: https://rf-tools.com/jitter/ it looks like 0.5 > ps should be achievable as long as the floor is kept to -145 dBc/Hz > (integrating 10 Hz to 10 MHz). The multiplier scheme will need to > contribute very little residual noise far out. No idea how easy/hard > that will be. More than 0.5 ps jitter will start to degrade the ADC > performance significantly. > > Regards, > Mark > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 14:44:01 -0500 Bob kb8tq wrote: > > On Jan 20, 2020, at 2:38 PM, jimlux wrote: > > On 1/20/20 10:01 AM, Mark Haun wrote: > >> A fair question... in fact I was initially planning to use the > >> ABLNO + a PLL. The OCXOs I found, however, are CTS VFOV405's with > >> phase noise claimed to be just as good as the ABLNO or CVHD VCXOs: > >> https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf > >> They are reasonably low power, small[-ish], and have adequate > >> stability for my needs. You can see why it is tempting to make > >> the multiplier scheme work, as it should save on both power and > >> board area. (The target application is a battery-powered SDR.) So > >> far there don't seem to be any show-stopper issues with the plan, > >> except that I am going to have to put together a phase-noise > >> measurement system, or find a friend with one. > > > > Have you checked delivery times? - Just because it's listed in the > > catalog does not mean you can get it in the next few weeks or > > months. If the online sources (Digikey, mouser, Newark, etc.) have > > them in stock, then you're good to go, but otherwise you could be > > looking at 6 months or more. > > …. and maybe nasty stuff like minimum order quantities in the range > of 10 or 20 pieces ( or prices below that which work out to the same > thing). No, these are from Ebay. A guy in Texas has been salvaging them from (I assume) telecom equipment: https://www.ebay.com/itm/CTS-16-384MHz-OCXO-3-3V-Oven-Controlled-VFControl-50ppb-120mW-VFOV405-TCEDH/113877523761?hash=item1a83a11d31:g:3JQAAOSwxN5WXv4q Obviously all of the caveats about used OCXOs apply, but at least they weren't melted off of scrap PCBs by kids in China. This is a hobby project so I don't plan to build more than half a dozen of my design-in-progress. Assuming it happens at all ;) Regards, Mark ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 14:22:41 -0500 Bob kb8tq wrote: > On Jan 20, 2020, at 1:36 PM, Mark Haun wrote: > > The VFOV405 datasheet lists typical phase noise for 10- and 100-MHz > > units. (Mine are 16.384 MHz.) In comparing the two oscillators, I > > have used the 100-MHz "typical" numbers which they both state: > > So taking the 14 db from multiplication into account: > > > VFO405 ABLNO > > 1K-126-141 > 10K -146-160 > 100K -149-161 > > Looking at the plots on the ABLNO data sheets, the wide band noise > gets down a bit below -161 on a “typical” basis. > > Locking an 80 MHz ABLNO to 16.384 is not going to be as easy as > locking one to 16.000. Getting an ABLNO with an EFC at 16.384 x 5 may > be a bit of a challenge. Agree except you were starting from the VFOV numbers for the 100-MHz version. If you use their numbers for the 10-MHz version and add 20 dB for an ideal 10x multiplication, for comparing with the ABLNO spec at 100 MHz, you end up with offsetVFOV405 @ 10M, ideal 10x multiply ABLNO @ 100 M 10-100 -88 100 -120 -118 1k-140 -141 10k -145 -160 100k -145 -161 so not bad apart from the raised floor. (I am assuming that an ideal 5x multiplication on the 16.384-MHz version of the VFOV405 would yield a similar comparison to an 80-MHz ABLNO.) Using this handy tool: https://rf-tools.com/jitter/ it looks like 0.5 ps should be achievable as long as the floor is kept to -145 dBc/Hz (integrating 10 Hz to 10 MHz). The multiplier scheme will need to contribute very little residual noise far out. No idea how easy/hard that will be. More than 0.5 ps jitter will start to degrade the ADC performance significantly. Regards, Mark ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi > On Jan 20, 2020, at 2:38 PM, jimlux wrote: > > On 1/20/20 10:01 AM, Mark Haun wrote: > >> A fair question... in fact I was initially planning to use the ABLNO + >> a PLL. The OCXOs I found, however, are CTS VFOV405's with phase noise >> claimed to be just as good as the ABLNO or CVHD VCXOs: >> https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf >> They are reasonably low power, small[-ish], and have adequate stability >> for my needs. You can see why it is tempting to make the multiplier >> scheme work, as it should save on both power and board area. (The >> target application is a battery-powered SDR.) So far there don't seem >> to be any show-stopper issues with the plan, except that I am going to >> have to put together a phase-noise measurement system, or find a friend >> with one. > > Have you checked delivery times? - Just because it's listed in the catalog > does not mean you can get it in the next few weeks or months. If the online > sources (Digikey, mouser, Newark, etc.) have them in stock, then you're good > to go, but otherwise you could be looking at 6 months or more. …. and maybe nasty stuff like minimum order quantities in the range of 10 or 20 pieces ( or prices below that which work out to the same thing). Bob > > > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On 1/20/20 10:01 AM, Mark Haun wrote: A fair question... in fact I was initially planning to use the ABLNO + a PLL. The OCXOs I found, however, are CTS VFOV405's with phase noise claimed to be just as good as the ABLNO or CVHD VCXOs: https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf They are reasonably low power, small[-ish], and have adequate stability for my needs. You can see why it is tempting to make the multiplier scheme work, as it should save on both power and board area. (The target application is a battery-powered SDR.) So far there don't seem to be any show-stopper issues with the plan, except that I am going to have to put together a phase-noise measurement system, or find a friend with one. Have you checked delivery times? - Just because it's listed in the catalog does not mean you can get it in the next few weeks or months. If the online sources (Digikey, mouser, Newark, etc.) have them in stock, then you're good to go, but otherwise you could be looking at 6 months or more. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi > On Jan 20, 2020, at 1:36 PM, Mark Haun wrote: > > On Mon, 20 Jan 2020 13:13:00 -0500 > Bob kb8tq wrote: >> On Jan 20, 2020, at 1:01 PM, Mark Haun wrote: >>> A fair question... in fact I was initially planning to use the >>> ABLNO + a PLL. The OCXOs I found, however, are CTS VFOV405's with >>> phase noise claimed to be just as good as the ABLNO or CVHD VCXOs: >>> https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf >> >> If you are starting at 16 MHz and multiplying by 5, the phase noise >> will degrade by 20 log (N). In this case, that will be 14 db. The >> degradation may be more than that, but it can never be less. >> >> Another issue is just how the spec’s actually apply. On any >> oscillator that is spec’d over a range of frequencies, some may do a >> bit better than others. Will this device at that frequency exceed the >> spec by 6 db? Will another model at the same frequency “only” exceed >> the spec by one db? Without testing a bunch of them …. no way to know. > > Well, worse than that, the VFOV405 phase noise is a "typical" not a > "max" spec ;) On the other hand, I should have some leeway at only 80 > MSPS and no bandpass sampling. (The main spectrum of interest is 5-20 > MHz.) I am aware of the 20logN relationship and that there will be some > residual extra phase noise from my multiplier on top of it. > > The VFOV405 datasheet lists typical phase noise for 10- and 100-MHz > units. (Mine are 16.384 MHz.) In comparing the two oscillators, I have > used the 100-MHz "typical" numbers which they both state: > So taking the 14 db from multiplication into account: VFO405 ABLNO 1K -126-141 10K -146-160 100K-149-161 Looking at the plots on the ABLNO data sheets, the wide band noise gets down a bit below -161 on a “typical” basis. Locking an 80 MHz ABLNO to 16.384 is not going to be as easy as locking one to 16.000. Getting an ABLNO with an EFC at 16.384 x 5 may be a bit of a challenge. Bob > offsetVFOV405ABLNO > 10-90-88 > 100 -120 -118 > 1k-140 -141 > 10k -160 -160 > 100k -163 -161 > > (The ABLNO also provides a worst-case spec which is 3-5 dB worse.) > > Regards, > Mark > > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 13:13:00 -0500 Bob kb8tq wrote: > On Jan 20, 2020, at 1:01 PM, Mark Haun wrote: > > A fair question... in fact I was initially planning to use the > > ABLNO + a PLL. The OCXOs I found, however, are CTS VFOV405's with > > phase noise claimed to be just as good as the ABLNO or CVHD VCXOs: > > https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf > > If you are starting at 16 MHz and multiplying by 5, the phase noise > will degrade by 20 log (N). In this case, that will be 14 db. The > degradation may be more than that, but it can never be less. > > Another issue is just how the spec’s actually apply. On any > oscillator that is spec’d over a range of frequencies, some may do a > bit better than others. Will this device at that frequency exceed the > spec by 6 db? Will another model at the same frequency “only” exceed > the spec by one db? Without testing a bunch of them …. no way to know. Well, worse than that, the VFOV405 phase noise is a "typical" not a "max" spec ;) On the other hand, I should have some leeway at only 80 MSPS and no bandpass sampling. (The main spectrum of interest is 5-20 MHz.) I am aware of the 20logN relationship and that there will be some residual extra phase noise from my multiplier on top of it. The VFOV405 datasheet lists typical phase noise for 10- and 100-MHz units. (Mine are 16.384 MHz.) In comparing the two oscillators, I have used the 100-MHz "typical" numbers which they both state: offsetVFOV405ABLNO 10-90-88 100 -120 -118 1k-140 -141 10k -160 -160 100k -163 -161 (The ABLNO also provides a worst-case spec which is 3-5 dB worse.) Regards, Mark ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi > On Jan 20, 2020, at 1:01 PM, Mark Haun wrote: > > Hi Attila, > > On Mon, 20 Jan 2020 14:29:15 +0100 > Attila Kinali wrote: >> On Mon, 20 Jan 2020 11:13:46 +0100 >> Attila Kinali wrote: >> >>> With those constraints, and reading the discussion, I wonder why >>> don't consider a VCXO+PLL solution. Using something like the >>> Abracon ABLNO and a generic PLL (e.g. ADF4001) would give you above >>> performance. The ABLNO are so low noise enough, that you can use a >>> low BW loop filter (order of 500Hz) and get lower output noise than >>> the up-multiplied 16MHz signal above that and the (multiplied) OCXO >>> performance below that (with a slight bump due to the PLL around >>> the loop filter frequency). >> >> Addendum: I don't know your application, but in a general high-speed >> sampling systems, it's the white noise floor that you are worried >> about, not the 1/f^a noise. And in that case, having a lown noise XO >> produce your sampling clock is better than multiplying a low frequency >> OCXO and using this directly, even if the XO is free running. > > A fair question... in fact I was initially planning to use the ABLNO + > a PLL. The OCXOs I found, however, are CTS VFOV405's with phase noise > claimed to be just as good as the ABLNO or CVHD VCXOs: > https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf If you are starting at 16 MHz and multiplying by 5, the phase noise will degrade by 20 log (N). In this case, that will be 14 db. The degradation may be more than that, but it can never be less. Another issue is just how the spec’s actually apply. On any oscillator that is spec’d over a range of frequencies, some may do a bit better than others. Will this device at that frequency exceed the spec by 6 db? Will another model at the same frequency “only” exceed the spec by one db? Without testing a bunch of them …. no way to know. Bob > They are reasonably low power, small[-ish], and have adequate stability > for my needs. You can see why it is tempting to make the multiplier > scheme work, as it should save on both power and board area. (The > target application is a battery-powered SDR.) So far there don't seem > to be any show-stopper issues with the plan, except that I am going to > have to put together a phase-noise measurement system, or find a friend > with one. > > To that end, I wonder if something like Andrew Holme's project, > http://www.aholme.co.uk/PhaseNoise/Main.htm > is the best "bang for the buck" right now? It looks like that could be > put together for well under $1k (minus the Wenzel ULN oscillator :). A > simpler, sound-card-based approach is also appealing, but I have not > seen any ready-to-build projects published on the web, and I cannot > afford to put in the hundreds of hours it would take to design my own. > > Regards, > Mark > > ___ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Hi Attila, On Mon, 20 Jan 2020 14:29:15 +0100 Attila Kinali wrote: > On Mon, 20 Jan 2020 11:13:46 +0100 > Attila Kinali wrote: > > > With those constraints, and reading the discussion, I wonder why > > don't consider a VCXO+PLL solution. Using something like the > > Abracon ABLNO and a generic PLL (e.g. ADF4001) would give you above > > performance. The ABLNO are so low noise enough, that you can use a > > low BW loop filter (order of 500Hz) and get lower output noise than > > the up-multiplied 16MHz signal above that and the (multiplied) OCXO > > performance below that (with a slight bump due to the PLL around > > the loop filter frequency). > > Addendum: I don't know your application, but in a general high-speed > sampling systems, it's the white noise floor that you are worried > about, not the 1/f^a noise. And in that case, having a lown noise XO > produce your sampling clock is better than multiplying a low frequency > OCXO and using this directly, even if the XO is free running. A fair question... in fact I was initially planning to use the ABLNO + a PLL. The OCXOs I found, however, are CTS VFOV405's with phase noise claimed to be just as good as the ABLNO or CVHD VCXOs: https://www.ctscorp.com/wp-content/uploads/VFOV405.pdf They are reasonably low power, small[-ish], and have adequate stability for my needs. You can see why it is tempting to make the multiplier scheme work, as it should save on both power and board area. (The target application is a battery-powered SDR.) So far there don't seem to be any show-stopper issues with the plan, except that I am going to have to put together a phase-noise measurement system, or find a friend with one. To that end, I wonder if something like Andrew Holme's project, http://www.aholme.co.uk/PhaseNoise/Main.htm is the best "bang for the buck" right now? It looks like that could be put together for well under $1k (minus the Wenzel ULN oscillator :). A simpler, sound-card-based approach is also appealing, but I have not seen any ready-to-build projects published on the web, and I cannot afford to put in the hundreds of hours it would take to design my own. Regards, Mark ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, 20 Jan 2020 11:13:46 +0100 Attila Kinali wrote: > With those constraints, and reading the discussion, I wonder why don't > consider a VCXO+PLL solution. Using something like the Abracon ABLNO and > a generic PLL (e.g. ADF4001) would give you above performance. The ABLNO > are so low noise enough, that you can use a low BW loop filter (order of > 500Hz) > and get lower output noise than the up-multiplied 16MHz signal above that > and the (multiplied) OCXO performance below that (with a slight bump due > to the PLL around the loop filter frequency). Addendum: I don't know your application, but in a general high-speed sampling systems, it's the white noise floor that you are worried about, not the 1/f^a noise. And in that case, having a lown noise XO produce your sampling clock is better than multiplying a low frequency OCXO and using this directly, even if the XO is free running. Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neal Stephenson ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Sat, 18 Jan 2020 16:28:56 -0800 Mark Haun wrote: > Constraints in order of importance: > > 1. Don't degrade the nice phase noise of the OCXO (-90 @ 1, -120 @10, > -140 @ 100, -160 @ 1k) any more than necessary; at the very least, it > should not impact the ADC noise floor in the primary 0-40 MHz image. > (This should give quite a bit of leeway, but better is better :) > > 2. OCXO power consumption (~150 mW) should still dominate total > clock-system power. Would like to keep the multiplier/buffer under 50 mW. > > 3. No supply rail above 3.3V. > > This "ought to be" (?) easy, because the OCXO output is already rich in > odd harmonics. All that's needed is to isolate and perhaps buffer the > right one without screwing up my noise spec. This is where I could use > some help... With those constraints, and reading the discussion, I wonder why don't consider a VCXO+PLL solution. Using something like the Abracon ABLNO and a generic PLL (e.g. ADF4001) would give you above performance. The ABLNO are so low noise enough, that you can use a low BW loop filter (order of 500Hz) and get lower output noise than the up-multiplied 16MHz signal above that and the (multiplied) OCXO performance below that (with a slight bump due to the PLL around the loop filter frequency). The big advantage over the multiplier solution is that you don't have to deal with a high level of harmonics and get a very clean signal with almost no effort. Attila Kinali -- Science is made up of so many things that appear obvious after they are explained. -- Pardot Kynes ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
On Mon, Jan 20, 2020 at 12:49 AM Magnus Danielson wrote: > > I would be very interested to do exactly that. I've actually had issues > getting the Prologix do things exactly as I want, and I blame that on my > inability to focus long enough to read the manual to understand it > properly. The lack of being able to debug the GPIB properly helps with > the confusion. I need to do more GPIB programming, and perferably in > Linux as I feel right at home there in general. > The open-source and cross-platform sigrok (https://sigrok.org/wiki/Main_Page) capture/analysis tool has a protocol decoder for GPIB which will turn any supported 16-bit logic analyser into a GPIB sniffer. Recommended cheap capture tool is a Cyprus ez-usb dev board like https://www.ebay.com/itm/223633738735 The Cyprus board can be wired directly to a GPIB connector but I've produced a PCB that will adapt it to a pair of connectors for passthrough use : you can obtain it from https://oshpark.com/shared_projects/1FVMoqoQ Unfortunately Oshpark are surprisingly expensive for that board but if there's interest I'll happily put it on one of the chinese sharing sites such as pcbway. I don't really want to get involved in stocking and shipping them. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO
Try AbeBooks ... -Original Message- From: time-nuts [mailto:time-nuts-boun...@lists.febo.com] On Behalf Of Alex Pummer Sent: 20 January 2020 03:38 To: time-nuts@lists.febo.com Subject: Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO I got my German edition of T+S [16] for $120.- shipped to California, but don't be surprised some of the medicament's made in Europe costing 50 times more here. 73 KJ6UHN Alex ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
