On 1/20/20 3:40 PM, Mark Haun wrote:
On Mon, 20 Jan 2020 17:31:51 -0500
Bob kb8tq <kb...@n1k.org> wrote:
Unfortunately I suspect the added digital power consumption in the FPGA
would be greater than the analog power for a PLL solution. As much as
it pains me to say that as a DSP guy ;) I need to think about this
some more, though.
Many (big) FPGAs these days have power consumption dominated by the
leakage current of all the gates. Even going back as far as the Virtex
4, the dependence of power on clock rate and number of gates toggling is
pretty small.
I've not checked something like a Zynq.
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