[time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[skipp isaham via time-nuts]

Hello once again to the Group,

May I ask what the current relatively simple options are for
expanding a Thunderbolt or equivalent... output for distribution
to multiple devices?

Although I expect only two or three isolated / buffered outputs
will be required in my example. I'm worried about signal level
if a passive system (Mini Circuits divider or equivalent type)
is used.

Would appreciate a few quick opinions on what is practical and
seems to work well.

thank you in advance

regards,

skipp

skipp025 at yahoo dot com

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Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Bob kb8tq]

Hi

What are you driving? 

Most “normal” gear is pretty happy with a fairly wide range of input levels. 
Obviously things
like termination and long lengths of coax can get into the act. For 4 outputs, 
a passive splitter
with 6 db of loss should do just fine. You have only taken the output voltage 
down by 2:1 ….

Just for reference:

https://www.avionteq.com/Document/53131A-specification-sheet.pdf 


Calls out a 200 mv to 10V RMS input level as acceptable For a variety of 
reasons, 10V RMS
is a really bad idea (cross talk ….). Lower is better in this case.

Bob

> On Jan 21, 2020, at 4:19 AM, skipp isaham via time-nuts 
>  wrote:
> 
> Hello once again to the Group,
> 
> May I ask what the current relatively simple options are for
> expanding a Thunderbolt or equivalent... output for distribution
> to multiple devices?
> 
> Although I expect only two or three isolated / buffered outputs
> will be required in my example. I'm worried about signal level
> if a passive system (Mini Circuits divider or equivalent type)
> is used.
> 
> Would appreciate a few quick opinions on what is practical and
> seems to work well.
> 
> thank you in advance
> 
> regards,
> 
> skipp
> 
> skipp025 at yahoo dot com
> 
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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Attila Kinali]

On Tue, 21 Jan 2020 01:15:45 +0100
Attila Kinali  wrote:

> > I was about to say that adding a second ADC channel is really expensive
> > (like $50 between AD9266 and AD9269), but I really like this idea...
> > just couple a reference oscillator into the main signal path at an
> > appropriate level, then use a parallel receive path in the FPGA
> > to trim the NCOs for the known beacon frequency.
> 
> You don't need a high performance ADC for the reference as you are dealing
> with a narrow band signal of known frequency. Even a 10bit or 8bit ADC
> would be good enough. You can even go and sample at half frequency
> and save both money and power. 

I just spend a few minutes looking at ADCs and found the LTC2256-12
and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
Both have 170fs RMS apperture jitter and do 25Msps and 40Msps respectively.
3dB BW is 800MHz, so more then good enough to even use the 100MHz output
of an hydrogen maser, if you want a really good reference ;-)

Power consumption at max sample rate are 34mW and 47mW respectively.
That's slightly more than a PLL would use (~20mW, plus maybe another
5mW to 10mW for the opamps in the loopfilter). Power consumption goes
down a bit with decreasing sample rate, but not as much as one would
hope for.

Attila Kinali

-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
 -- Miss Matheson, The Diamond Age, Neal Stephenson

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Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Taka Kamiya via time-nuts]

I've tried daisy chaining 4 HP5335A.  By the time signal got to the 4th box, it 
was too weak to reliably drive the 1 pps.  I had a terminator at the last tee 
with short length of RG58s between boxes.  I guess some box puts relatively 
heavy load on the signal?

I'd like to know why 10V is a bad idea.  (besides too close to the upper limit) 
 Cross talk between what/where?  

To OP:I have video amplifiers Extron MDA-3V successfully used for this.  1 port 
in, 3 ports out ones by Extron are very inexpensive at 10 dollars+/-.  I never 
did formal testing but reading on all counters matched exactly.  They are 75 
ohms but it didn't matter in my use case.  You can change/adjust internal 
resisters if you are concerned.  

--- 
(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG
 

On Tuesday, January 21, 2020, 7:45:22 AM EST, Bob kb8tq  
wrote:  
 
 Hi

What are you driving? 

Most “normal” gear is pretty happy with a fairly wide range of input levels. 
Obviously things
like termination and long lengths of coax can get into the act. For 4 outputs, 
a passive splitter
with 6 db of loss should do just fine. You have only taken the output voltage 
down by 2:1 ….

Just for reference:

https://www.avionteq.com/Document/53131A-specification-sheet.pdf 


Calls out a 200 mv to 10V RMS input level as acceptable For a variety of 
reasons, 10V RMS
is a really bad idea (cross talk ….). Lower is better in this case.

Bob

> On Jan 21, 2020, at 4:19 AM, skipp isaham via time-nuts 
>  wrote:
> 
> Hello once again to the Group,
> 
> May I ask what the current relatively simple options are for
> expanding a Thunderbolt or equivalent... output for distribution
> to multiple devices?
> 
> Although I expect only two or three isolated / buffered outputs
> will be required in my example. I'm worried about signal level
> if a passive system (Mini Circuits divider or equivalent type)
> is used.
> 
> Would appreciate a few quick opinions on what is practical and
> seems to work well.
> 
> thank you in advance
> 
> regards,
> 
> skipp
> 
> skipp025 at yahoo dot com
> 
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Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Bob kb8tq]

Hi

Cross talk between the reference in and the measured signal on the 53131 series 
can be an
issue . The counter drops resolution in the vicinity of 10 MHz as a result. 
There is also an  issue 
with  the sampling process rather than direct feedthrough. 

If you are measuring things like phase noise, having a lot of 10 MHz running 
around the lab will put a 
spur in the phase noise plot. It may be close enough in that you don’t notice 
it every time. The same 
sort of spur will play nasties with things like ADEV measurements. Getting a 
10V RMS signal down 
120 db is tough …

Finally if you happen to be playing with radios, WWV is at 10 MHz. It does not 
take a lot of reference 
signal to get back into the typical receiving antenna.

==

If you are daisy chaining counters, there are several ways to do it:

1) Drive the “ext ref in” and daisy chain off of “ext ref out”. This way the 
signal is buffered at each device.
It may add a bit of noise, but you can go a long way doing this.

2) Put a coax Tee connector at each instrument. If the device is high Z in, 
this can do ok. If it is a 50 ohm
termination all the time … not so much. Even with the high Z input it’s better 
for short runs than long ones.

3) Mix the two approaches. If you have a variety of gear, use the ones with ref 
in / ref out as buffers. String
the other gear in-between those boxes. 

Bob

> On Jan 21, 2020, at 10:27 AM, Taka Kamiya via time-nuts 
>  wrote:
> 
> I've tried daisy chaining 4 HP5335A.  By the time signal got to the 4th box, 
> it was too weak to reliably drive the 1 pps.  I had a terminator at the last 
> tee with short length of RG58s between boxes.  I guess some box puts 
> relatively heavy load on the signal?
> 
> I'd like to know why 10V is a bad idea.  (besides too close to the upper 
> limit)  Cross talk between what/where?  
> 
> To OP:I have video amplifiers Extron MDA-3V successfully used for this.  1 
> port in, 3 ports out ones by Extron are very inexpensive at 10 dollars+/-.  I 
> never did formal testing but reading on all counters matched exactly.  They 
> are 75 ohms but it didn't matter in my use case.  You can change/adjust 
> internal resisters if you are concerned.  
> 
> --- 
> (Mr.) Taka Kamiya
> KB4EMF / ex JF2DKG
> 
> 
>On Tuesday, January 21, 2020, 7:45:22 AM EST, Bob kb8tq  
> wrote:  
> 
> Hi
> 
> What are you driving? 
> 
> Most “normal” gear is pretty happy with a fairly wide range of input levels. 
> Obviously things
> like termination and long lengths of coax can get into the act. For 4 
> outputs, a passive splitter
> with 6 db of loss should do just fine. You have only taken the output voltage 
> down by 2:1 ….
> 
> Just for reference:
> 
> https://www.avionteq.com/Document/53131A-specification-sheet.pdf 
> 
> 
> Calls out a 200 mv to 10V RMS input level as acceptable For a variety of 
> reasons, 10V RMS
> is a really bad idea (cross talk ….). Lower is better in this case.
> 
> Bob
> 
>> On Jan 21, 2020, at 4:19 AM, skipp isaham via time-nuts 
>>  wrote:
>> 
>> Hello once again to the Group,
>> 
>> May I ask what the current relatively simple options are for
>> expanding a Thunderbolt or equivalent... output for distribution
>> to multiple devices?
>> 
>> Although I expect only two or three isolated / buffered outputs
>> will be required in my example. I'm worried about signal level
>> if a passive system (Mini Circuits divider or equivalent type)
>> is used.
>> 
>> Would appreciate a few quick opinions on what is practical and
>> seems to work well.
>> 
>> thank you in advance
>> 
>> regards,
>> 
>> skipp
>> 
>> skipp025 at yahoo dot com
>> 
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>> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
>> and follow the instructions there.
> 
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Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Dana Whitlow]

Re cross talk, I'd suggest:

Fairly equal levels on all the used outputs, to minimize the effects of
crosstalk between them.  This is especially important if you're using
RG-58 or similar cable, which leaks like a sieve.  Crosstalk of this
sort will tend to screw up the edges of a PPS pulse, possibly in a way
as to lead to unreliable/unstable triggering of some of your devices.

As high a level as your devices will safely tolerate, unless you're
concerned
about leakage into other systems, like kb8tq's WWV receiver.  Again, I
suggest
avoiding RG-58 and similar single-braid-shielded cables.  This has been a
significant problem for me, receiving WWV at 10 MHz.  I've been able to
some-
what mitigate this with big clamp-on ferrite chokes, but I still have some
issues.

DanaK8YUM

On Tue, Jan 21, 2020 at 9:28 AM Taka Kamiya via time-nuts <
time-nuts@lists.febo.com> wrote:

> I've tried daisy chaining 4 HP5335A.  By the time signal got to the 4th
> box, it was too weak to reliably drive the 1 pps.  I had a terminator at
> the last tee with short length of RG58s between boxes.  I guess some box
> puts relatively heavy load on the signal?
>
> I'd like to know why 10V is a bad idea.  (besides too close to the upper
> limit)  Cross talk between what/where?
>
> To OP:I have video amplifiers Extron MDA-3V successfully used for this.  1
> port in, 3 ports out ones by Extron are very inexpensive at 10 dollars+/-.
> I never did formal testing but reading on all counters matched exactly.
> They are 75 ohms but it didn't matter in my use case.  You can
> change/adjust internal resisters if you are concerned.
>
> ---
> (Mr.) Taka Kamiya
> KB4EMF / ex JF2DKG
>
>
> On Tuesday, January 21, 2020, 7:45:22 AM EST, Bob kb8tq 
> wrote:
>
>  Hi
>
> What are you driving?
>
> Most “normal” gear is pretty happy with a fairly wide range of input
> levels. Obviously things
> like termination and long lengths of coax can get into the act. For 4
> outputs, a passive splitter
> with 6 db of loss should do just fine. You have only taken the output
> voltage down by 2:1 ….
>
> Just for reference:
>
> https://www.avionteq.com/Document/53131A-specification-sheet.pdf <
> https://www.avionteq.com/Document/53131A-specification-sheet.pdf>
>
> Calls out a 200 mv to 10V RMS input level as acceptable For a variety of
> reasons, 10V RMS
> is a really bad idea (cross talk ….). Lower is better in this case.
>
> Bob
>
> > On Jan 21, 2020, at 4:19 AM, skipp isaham via time-nuts <
> time-nuts@lists.febo.com> wrote:
> >
> > Hello once again to the Group,
> >
> > May I ask what the current relatively simple options are for
> > expanding a Thunderbolt or equivalent... output for distribution
> > to multiple devices?
> >
> > Although I expect only two or three isolated / buffered outputs
> > will be required in my example. I'm worried about signal level
> > if a passive system (Mini Circuits divider or equivalent type)
> > is used.
> >
> > Would appreciate a few quick opinions on what is practical and
> > seems to work well.
> >
> > thank you in advance
> >
> > regards,
> >
> > skipp
> >
> > skipp025 at yahoo dot com
> >
> > ___
> > time-nuts mailing list -- time-nuts@lists.febo.com
> > To unsubscribe, go to
> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> > and follow the instructions there.
>
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Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Brian Lloyd]

On 1/21/20 03:19, skipp isaham via time-nuts wrote:
> Hello once again to the Group,
>
> May I ask what the current relatively simple options are for
> expanding a Thunderbolt or equivalent... output for distribution
> to multiple devices?
TAPR TADD-3 for 1pps distribution.
https://tapr.org/?product=tadd-3-pulse-per-second-distribution-amplifier

TAPR TADD-1 for 10MHz distribution
https://tapr.org/?product=tadd-1-rf-distribution-amplifier

There are better solutions but these have a good cost:performance ratio.

-- 


 

Brian Lloyd
706 Flightline
Spring Branch, TX 78070
br...@lloyd.aero 
+1.210.802.8359


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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Prologix]

Dear Gerhard,

Prologix controllers pass data as is from the instrument to PC. It does not add 
any termination characters.
++eos command controls how termination is handled for data going the other way 
-- from PC to instrument.
Please consult instrument manual about how it terminates output.

Hope that helps.

Regards,
Abdul


-Original Message-
From: time-nuts [mailto:time-nuts-boun...@lists.febo.com] On Behalf Of Gerhard 
Hoffmann
Sent: Sunday, January 19, 2020 3:04 PM
To: time-nuts@lists.febo.com
Subject: Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO


Am 19.01.20 um 22:20 schrieb Magnus Danielson:
> Hi Mark,
>
> On 2020-01-19 18:19, Mark Haun wrote:
>
> I've read that I should avoid high-Q tuned circuits, because they will 
> introduce more noise with temperature variation.  Are there any rules 
> of thumb for how much Q is too much?

It's not that the high Q circuit generates noise, it's more

that the phase runs away when the resonant frequency runs away.

For a minimum phase network, you have +- 45° at the -3 dB points.


> with a bit of scaling to give you jitter. Home-brewing this should not 
> be too hard. Maybe it just lacks an example setup and some software 
> support.

Ha, that hurts! Sheer mockery! I have spent the entire weekend

trying to control my 89441A FFT analyzer from Linux via a

Prologix USB-to-IEEE488 dongle. Setting /dev/ttyUSB0 to raw

and getting rid of the buffering was easy. Telling if that !#&%§!!

Prologix thing terminates the strings to the computer with LF

or CRLF seems impossible to predict, in spite of a command to

set this. And there is no way to measure anything on that virtual

tty port to watch the traffic. Use of tees activates buffering, no

way around.

Typical Heisenbug. Observing it affects the outcome.


The idea was just to measure 1/f noise on my AF and RF transistors

in a circuit inspired by that in Art Of Electronics V3.

Good book. Must have.

---

I have cut out the output amplifier circuit of my OCXO support

board and removed the doubler option and the notch filter. It provides

22 dBm after a MV89A, enough for two ranks of power dividers in front

of the Timepod.  Transformers are still sub-optimum, esp. at the low end

and on the output side, but I wanted to avoid winding them myself.

DC emitter degeneration is 50 Ohm to fight 1/f, less than that above a

few 100 KHz as fits the gain. Push-pull common base.


A 10 MHz MV89A is internally 5 MHz, and you can see that in the spectrum.

External notch definitely required.


regards, Gerhard





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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mark Haun]

Hi Attila,

On Tue, 21 Jan 2020 15:08:16 +0100
Attila Kinali  wrote:
> On Tue, 21 Jan 2020 01:15:45 +0100
> Attila Kinali  wrote:
> > You don't need a high performance ADC for the reference as you are
> > dealing with a narrow band signal of known frequency. Even a 10bit
> > or 8bit ADC would be good enough. You can even go and sample at
> > half frequency and save both money and power.   
> 
> I just spend a few minutes looking at ADCs and found the LTC2256-12
> and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
> Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
> respectively. 3dB BW is 800MHz, so more then good enough to even use
> the 100MHz output of an hydrogen maser, if you want a really good
> reference ;-)
> 
> Power consumption at max sample rate are 34mW and 47mW respectively.
> That's slightly more than a PLL would use (~20mW, plus maybe another
> 5mW to 10mW for the opamps in the loopfilter). Power consumption goes
> down a bit with decreasing sample rate, but not as much as one would
> hope for.

I hope you will indulge one more newbie question on the analog PLL
option... as I have approximately zero experience designing them.

What are the adverse consequences of using large divisors in the loop,
as would be required for my odd OCXO frequency?  E.g. on paper, it would
seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
frequency.  How would this differ from a more "normal" ref clock
frequency of 10 or 16 MHz with smaller divisors?

Thanks,
Mark

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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Bob kb8tq]

Hi



> On Jan 21, 2020, at 1:41 PM, Mark Haun  wrote:
> 
> Hi Attila,
> 
> On Tue, 21 Jan 2020 15:08:16 +0100
> Attila Kinali  wrote:
>> On Tue, 21 Jan 2020 01:15:45 +0100
>> Attila Kinali  wrote:
>>> You don't need a high performance ADC for the reference as you are
>>> dealing with a narrow band signal of known frequency. Even a 10bit
>>> or 8bit ADC would be good enough. You can even go and sample at
>>> half frequency and save both money and power.   
>> 
>> I just spend a few minutes looking at ADCs and found the LTC2256-12
>> and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
>> Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
>> respectively. 3dB BW is 800MHz, so more then good enough to even use
>> the 100MHz output of an hydrogen maser, if you want a really good
>> reference ;-)
>> 
>> Power consumption at max sample rate are 34mW and 47mW respectively.
>> That's slightly more than a PLL would use (~20mW, plus maybe another
>> 5mW to 10mW for the opamps in the loopfilter). Power consumption goes
>> down a bit with decreasing sample rate, but not as much as one would
>> hope for.
> 
> I hope you will indulge one more newbie question on the analog PLL
> option... as I have approximately zero experience designing them.
> 
> What are the adverse consequences of using large divisors in the loop,
> as would be required for my odd OCXO frequency?  E.g. on paper, it would
> seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
> frequency.  How would this differ from a more "normal" ref clock
> frequency of 10 or 16 MHz with smaller divisors?

The dividers and the phase detectors have noise floors. As you go to higher
divide ratios these get in the way of “preserving” the reference phase noise.

Bob

> 
> Thanks,
> Mark
> 
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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[jimlux]

On 1/21/20 10:41 AM, Mark Haun wrote:

Hi Attila,

On Tue, 21 Jan 2020 15:08:16 +0100
Attila Kinali  wrote:

On Tue, 21 Jan 2020 01:15:45 +0100
Attila Kinali  wrote:

You don't need a high performance ADC for the reference as you are
dealing with a narrow band signal of known frequency. Even a 10bit
or 8bit ADC would be good enough. You can even go and sample at
half frequency and save both money and power.


I just spend a few minutes looking at ADCs and found the LTC2256-12
and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
respectively. 3dB BW is 800MHz, so more then good enough to even use
the 100MHz output of an hydrogen maser, if you want a really good
reference ;-)

Power consumption at max sample rate are 34mW and 47mW respectively.
That's slightly more than a PLL would use (~20mW, plus maybe another
5mW to 10mW for the opamps in the loopfilter). Power consumption goes
down a bit with decreasing sample rate, but not as much as one would
hope for.


I hope you will indulge one more newbie question on the analog PLL
option... as I have approximately zero experience designing them.

What are the adverse consequences of using large divisors in the loop,
as would be required for my odd OCXO frequency?  E.g. on paper, it would
seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
frequency.  How would this differ from a more "normal" ref clock
frequency of 10 or 16 MHz with smaller divisors?




You have potential spurs at the PFD frequency and multiples of it, so it 
kind of depends on what bandwidths you have in things like the loop 
filter and downstream in the output path.  A higher comparison frequency 
puts the first spur farther out.



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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mike Ingle]

Hi All,

I am not an expert here, but I can say with some certainty that a divided
clock works well.  I have a system with a 4GSPS RF ADC and a aux ADC which
runs at 1/64th the RF ADC.  The whole clock chain is a 10MHz ext ref -> a
LMX2581 synth -> RF ADC -> RF ADC DCO -> nb4l52 clk in with a D coming from
an FPGA as the AUX ADC clock.  The AUX ADC is able to time stamp a 1pps to
a 1sigma of less than 15ps (difference between the 1PPS into the AUX ADC
and a copy into the RF channel).

The point being what is wrong with a good 80MHz ocxo or tcxo for the main
ADC and and a divided by 4 or 5 to an aux ADC?  And, I have made an HF
transceiver with a ltc2195 and a simple 125MHz ECL oscillator, and some
250MSPS Analog devices DAC which managed QAM256.

It seems like this is being a little over thought.

Run your main ADC at 80MSPS, and free run your oscillator, and present a
reference either through a aux ADC, or as a secondary clock to an FPGA.  No
need to multiply.

-- mike





On Tue, Jan 21, 2020 at 8:25 PM jimlux  wrote:

> On 1/21/20 10:41 AM, Mark Haun wrote:
> > Hi Attila,
> >
> > On Tue, 21 Jan 2020 15:08:16 +0100
> > Attila Kinali  wrote:
> >> On Tue, 21 Jan 2020 01:15:45 +0100
> >> Attila Kinali  wrote:
> >>> You don't need a high performance ADC for the reference as you are
> >>> dealing with a narrow band signal of known frequency. Even a 10bit
> >>> or 8bit ADC would be good enough. You can even go and sample at
> >>> half frequency and save both money and power.
> >>
> >> I just spend a few minutes looking at ADCs and found the LTC2256-12
> >> and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
> >> Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
> >> respectively. 3dB BW is 800MHz, so more then good enough to even use
> >> the 100MHz output of an hydrogen maser, if you want a really good
> >> reference ;-)
> >>
> >> Power consumption at max sample rate are 34mW and 47mW respectively.
> >> That's slightly more than a PLL would use (~20mW, plus maybe another
> >> 5mW to 10mW for the opamps in the loopfilter). Power consumption goes
> >> down a bit with decreasing sample rate, but not as much as one would
> >> hope for.
> >
> > I hope you will indulge one more newbie question on the analog PLL
> > option... as I have approximately zero experience designing them.
> >
> > What are the adverse consequences of using large divisors in the loop,
> > as would be required for my odd OCXO frequency?  E.g. on paper, it would
> > seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
> > frequency.  How would this differ from a more "normal" ref clock
> > frequency of 10 or 16 MHz with smaller divisors?
> >
>
>
> You have potential spurs at the PFD frequency and multiples of it, so it
> kind of depends on what bandwidths you have in things like the loop
> filter and downstream in the output path.  A higher comparison frequency
> puts the first spur farther out.
>
>
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Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Bryan _]

On the point of using a MDA-3V at the hobbyist bench level, any issues that one 
needs to be concerned about. A few modification projects online, but none 
really comment on any issues or performance.

-=Bryan=-


From: time-nuts  on behalf of Bob kb8tq 

Sent: January 21, 2020 7:57 AM
To: Taka Kamiya ; Discussion of precise time and frequency 
measurement 
Subject: Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver 
options?

Hi

Cross talk between the reference in and the measured signal on the 53131 series 
can be an
issue . The counter drops resolution in the vicinity of 10 MHz as a result. 
There is also an  issue
with  the sampling process rather than direct feedthrough.

If you are measuring things like phase noise, having a lot of 10 MHz running 
around the lab will put a
spur in the phase noise plot. It may be close enough in that you don’t notice 
it every time. The same
sort of spur will play nasties with things like ADEV measurements. Getting a 
10V RMS signal down
120 db is tough …

Finally if you happen to be playing with radios, WWV is at 10 MHz. It does not 
take a lot of reference
signal to get back into the typical receiving antenna.

==

If you are daisy chaining counters, there are several ways to do it:

1) Drive the “ext ref in” and daisy chain off of “ext ref out”. This way the 
signal is buffered at each device.
It may add a bit of noise, but you can go a long way doing this.

2) Put a coax Tee connector at each instrument. If the device is high Z in, 
this can do ok. If it is a 50 ohm
termination all the time … not so much. Even with the high Z input it’s better 
for short runs than long ones.

3) Mix the two approaches. If you have a variety of gear, use the ones with ref 
in / ref out as buffers. String
the other gear in-between those boxes.

Bob

> On Jan 21, 2020, at 10:27 AM, Taka Kamiya via time-nuts 
>  wrote:
>
> I've tried daisy chaining 4 HP5335A.  By the time signal got to the 4th box, 
> it was too weak to reliably drive the 1 pps.  I had a terminator at the last 
> tee with short length of RG58s between boxes.  I guess some box puts 
> relatively heavy load on the signal?
>
> I'd like to know why 10V is a bad idea.  (besides too close to the upper 
> limit)  Cross talk between what/where?
>
> To OP:I have video amplifiers Extron MDA-3V successfully used for this.  1 
> port in, 3 ports out ones by Extron are very inexpensive at 10 dollars+/-.  I 
> never did formal testing but reading on all counters matched exactly.  They 
> are 75 ohms but it didn't matter in my use case.  You can change/adjust 
> internal resisters if you are concerned.
>
> ---
> (Mr.) Taka Kamiya
> KB4EMF / ex JF2DKG
>
>
>On Tuesday, January 21, 2020, 7:45:22 AM EST, Bob kb8tq  
> wrote:
>
> Hi
>
> What are you driving?
>
> Most “normal” gear is pretty happy with a fairly wide range of input levels. 
> Obviously things
> like termination and long lengths of coax can get into the act. For 4 
> outputs, a passive splitter
> with 6 db of loss should do just fine. You have only taken the output voltage 
> down by 2:1 ….
>
> Just for reference:
>
> https://www.avionteq.com/Document/53131A-specification-sheet.pdf 
> 
>
> Calls out a 200 mv to 10V RMS input level as acceptable For a variety of 
> reasons, 10V RMS
> is a really bad idea (cross talk ….). Lower is better in this case.
>
> Bob
>
>> On Jan 21, 2020, at 4:19 AM, skipp isaham via time-nuts 
>>  wrote:
>>
>> Hello once again to the Group,
>>
>> May I ask what the current relatively simple options are for
>> expanding a Thunderbolt or equivalent... output for distribution
>> to multiple devices?
>>
>> Although I expect only two or three isolated / buffered outputs
>> will be required in my example. I'm worried about signal level
>> if a passive system (Mini Circuits divider or equivalent type)
>> is used.
>>
>> Would appreciate a few quick opinions on what is practical and
>> seems to work well.
>>
>> thank you in advance
>>
>> regards,
>>
>> skipp
>>
>> skipp025 at yahoo dot com
>>
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>> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
>> and follow the instructions there.
>
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Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Bob kb8tq]

Hi

If all you are doing is driving a 5335 and running at 1 second gate times, then 
there’s not
a lot to worry about. If indeed you are multiplying this or that up to X band 
for various purposes
then  ….. that’s different. Both are in the “hobbyist” range.

Spurs matter for some things and don’t matter much for others. A spur at -120 
at 10 MHz 
may be up around -60 db at 10 GHz. It might matter there … it might not. A -60 
db spur 
at 10 MHz gets into the “yikes” range if directly multiplied. 

How big is your bench? How long are your feed cables? You are getting into a 
significant 
fraction of a wavelength at 10’ of cable. If unterminated (and / or poorly 
shielded) it will spray
a bit of RF. 

Lots of details and no single answer without digging deeper into what you are 
trying to do.

Bob

> On Jan 21, 2020, at 4:06 PM, Bryan _  wrote:
> 
> On the point of using a MDA-3V at the hobbyist bench level, any issues that 
> one needs to be concerned about. A few modification projects online, but none 
> really comment on any issues or performance.
> 
> -=Bryan=-
> 
> 
> From: time-nuts  on behalf of Bob kb8tq 
> 
> Sent: January 21, 2020 7:57 AM
> To: Taka Kamiya ; Discussion of precise time and 
> frequency measurement 
> Subject: Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver 
> options?
> 
> Hi
> 
> Cross talk between the reference in and the measured signal on the 53131 
> series can be an
> issue . The counter drops resolution in the vicinity of 10 MHz as a result. 
> There is also an  issue
> with  the sampling process rather than direct feedthrough.
> 
> If you are measuring things like phase noise, having a lot of 10 MHz running 
> around the lab will put a
> spur in the phase noise plot. It may be close enough in that you don’t notice 
> it every time. The same
> sort of spur will play nasties with things like ADEV measurements. Getting a 
> 10V RMS signal down
> 120 db is tough …
> 
> Finally if you happen to be playing with radios, WWV is at 10 MHz. It does 
> not take a lot of reference
> signal to get back into the typical receiving antenna.
> 
> ==
> 
> If you are daisy chaining counters, there are several ways to do it:
> 
> 1) Drive the “ext ref in” and daisy chain off of “ext ref out”. This way the 
> signal is buffered at each device.
> It may add a bit of noise, but you can go a long way doing this.
> 
> 2) Put a coax Tee connector at each instrument. If the device is high Z in, 
> this can do ok. If it is a 50 ohm
> termination all the time … not so much. Even with the high Z input it’s 
> better for short runs than long ones.
> 
> 3) Mix the two approaches. If you have a variety of gear, use the ones with 
> ref in / ref out as buffers. String
> the other gear in-between those boxes.
> 
> Bob
> 
>> On Jan 21, 2020, at 10:27 AM, Taka Kamiya via time-nuts 
>>  wrote:
>> 
>> I've tried daisy chaining 4 HP5335A.  By the time signal got to the 4th box, 
>> it was too weak to reliably drive the 1 pps.  I had a terminator at the last 
>> tee with short length of RG58s between boxes.  I guess some box puts 
>> relatively heavy load on the signal?
>> 
>> I'd like to know why 10V is a bad idea.  (besides too close to the upper 
>> limit)  Cross talk between what/where?
>> 
>> To OP:I have video amplifiers Extron MDA-3V successfully used for this.  1 
>> port in, 3 ports out ones by Extron are very inexpensive at 10 dollars+/-.  
>> I never did formal testing but reading on all counters matched exactly.  
>> They are 75 ohms but it didn't matter in my use case.  You can change/adjust 
>> internal resisters if you are concerned.
>> 
>> ---
>> (Mr.) Taka Kamiya
>> KB4EMF / ex JF2DKG
>> 
>> 
>>   On Tuesday, January 21, 2020, 7:45:22 AM EST, Bob kb8tq  
>> wrote:
>> 
>> Hi
>> 
>> What are you driving?
>> 
>> Most “normal” gear is pretty happy with a fairly wide range of input levels. 
>> Obviously things
>> like termination and long lengths of coax can get into the act. For 4 
>> outputs, a passive splitter
>> with 6 db of loss should do just fine. You have only taken the output 
>> voltage down by 2:1 ….
>> 
>> Just for reference:
>> 
>> https://www.avionteq.com/Document/53131A-specification-sheet.pdf 
>> 
>> 
>> Calls out a 200 mv to 10V RMS input level as acceptable For a variety of 
>> reasons, 10V RMS
>> is a really bad idea (cross talk ….). Lower is better in this case.
>> 
>> Bob
>> 
>>> On Jan 21, 2020, at 4:19 AM, skipp isaham via time-nuts 
>>>  wrote:
>>> 
>>> Hello once again to the Group,
>>> 
>>> May I ask what the current relatively simple options are for
>>> expanding a Thunderbolt or equivalent... output for distribution
>>> to multiple devices?
>>> 
>>> Although I expect only two or three isolated / buffered outputs
>>> will be required in my example. I'm worried about signal level
>>> if a passive system (Mini Circuits div

Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Taka Kamiya via time-nuts]

I'm not the OP but I was just throwing some ideas about cheap way to distribute.
But the responses were very timely.  I am, indeed, using HP53132A, RG58, and 
were doing ADEV measurement of a 10MHz signal.  I have my answers already so I 
won't go into details but I was seeing some explainable indications.  It might 
very likely be leak from or into the reference/input.  I will use double 
shielded and phase stable cables and see if I can eliminate the issue.

Thanks a-bunch!
--- 
(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG
 

On Tuesday, January 21, 2020, 4:27:26 PM EST, Bob kb8tq  
wrote:  
 
 Hi

If all you are doing is driving a 5335 and running at 1 second gate times, then 
there’s not
a lot to worry about. If indeed you are multiplying this or that up to X band 
for various purposes
then  ….. that’s different. Both are in the “hobbyist” range.

Spurs matter for some things and don’t matter much for others. A spur at -120 
at 10 MHz 
may be up around -60 db at 10 GHz. It might matter there … it might not. A -60 
db spur 
at 10 MHz gets into the “yikes” range if directly multiplied. 

How big is your bench? How long are your feed cables? You are getting into a 
significant 
fraction of a wavelength at 10’ of cable. If unterminated (and / or poorly 
shielded) it will spray
a bit of RF. 

Lots of details and no single answer without digging deeper into what you are 
trying to do.

Bob

> On Jan 21, 2020, at 4:06 PM, Bryan _  wrote:
> 
> On the point of using a MDA-3V at the hobbyist bench level, any issues that 
> one needs to be concerned about. A few modification projects online, but none 
> really comment on any issues or performance.
> 
> -=Bryan=-
> 
> 
> From: time-nuts  on behalf of Bob kb8tq 
> 
> Sent: January 21, 2020 7:57 AM
> To: Taka Kamiya ; Discussion of precise time and 
> frequency measurement 
> Subject: Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver 
> options?
> 
> Hi
> 
> Cross talk between the reference in and the measured signal on the 53131 
> series can be an
> issue . The counter drops resolution in the vicinity of 10 MHz as a result. 
> There is also an  issue
> with  the sampling process rather than direct feedthrough.
> 
> If you are measuring things like phase noise, having a lot of 10 MHz running 
> around the lab will put a
> spur in the phase noise plot. It may be close enough in that you don’t notice 
> it every time. The same
> sort of spur will play nasties with things like ADEV measurements. Getting a 
> 10V RMS signal down
> 120 db is tough …
> 
> Finally if you happen to be playing with radios, WWV is at 10 MHz. It does 
> not take a lot of reference
> signal to get back into the typical receiving antenna.
> 
> ==
> 
> If you are daisy chaining counters, there are several ways to do it:
> 
> 1) Drive the “ext ref in” and daisy chain off of “ext ref out”. This way the 
> signal is buffered at each device.
> It may add a bit of noise, but you can go a long way doing this.
> 
> 2) Put a coax Tee connector at each instrument. If the device is high Z in, 
> this can do ok. If it is a 50 ohm
> termination all the time … not so much. Even with the high Z input it’s 
> better for short runs than long ones.
> 
> 3) Mix the two approaches. If you have a variety of gear, use the ones with 
> ref in / ref out as buffers. String
> the other gear in-between those boxes.
> 
> Bob
> 
>> On Jan 21, 2020, at 10:27 AM, Taka Kamiya via time-nuts 
>>  wrote:
>> 
>> I've tried daisy chaining 4 HP5335A.  By the time signal got to the 4th box, 
>> it was too weak to reliably drive the 1 pps.  I had a terminator at the last 
>> tee with short length of RG58s between boxes.  I guess some box puts 
>> relatively heavy load on the signal?
>> 
>> I'd like to know why 10V is a bad idea.  (besides too close to the upper 
>> limit)  Cross talk between what/where?
>> 
>> To OP:I have video amplifiers Extron MDA-3V successfully used for this.  1 
>> port in, 3 ports out ones by Extron are very inexpensive at 10 dollars+/-.  
>> I never did formal testing but reading on all counters matched exactly.  
>> They are 75 ohms but it didn't matter in my use case.  You can change/adjust 
>> internal resisters if you are concerned.
>> 
>> ---
>> (Mr.) Taka Kamiya
>> KB4EMF / ex JF2DKG
>> 
>> 
>>  On Tuesday, January 21, 2020, 7:45:22 AM EST, Bob kb8tq  
>>wrote:
>> 
>> Hi
>> 
>> What are you driving?
>> 
>> Most “normal” gear is pretty happy with a fairly wide range of input levels. 
>> Obviously things
>> like termination and long lengths of coax can get into the act. For 4 
>> outputs, a passive splitter
>> with 6 db of loss should do just fine. You have only taken the output 
>> voltage down by 2:1 ….
>> 
>> Just for reference:
>> 
>> https://www.avionteq.com/Document/53131A-specification-sheet.pdf 
>> 
>> 
>> Calls

Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line driver options?

[Bob kb8tq]

Hi

If you are doing direct measurements on a 10 MHz signal *and* counting on the 
expanded
frequency resolution of a 53131, that’s not going to work. There is an HP app 
note somewhere
that explains why in great detail. The quick read version is that the sampling 
process falls apart.

Bob

> On Jan 21, 2020, at 4:49 PM, Taka Kamiya via time-nuts 
>  wrote:
> 
> I'm not the OP but I was just throwing some ideas about cheap way to 
> distribute.
> But the responses were very timely.  I am, indeed, using HP53132A, RG58, and 
> were doing ADEV measurement of a 10MHz signal.  I have my answers already so 
> I won't go into details but I was seeing some explainable indications.  It 
> might very likely be leak from or into the reference/input.  I will use 
> double shielded and phase stable cables and see if I can eliminate the issue.
> 
> Thanks a-bunch!
> --- 
> (Mr.) Taka Kamiya
> KB4EMF / ex JF2DKG
> 
> 
>On Tuesday, January 21, 2020, 4:27:26 PM EST, Bob kb8tq  
> wrote:  
> 
> Hi
> 
> If all you are doing is driving a 5335 and running at 1 second gate times, 
> then there’s not
> a lot to worry about. If indeed you are multiplying this or that up to X band 
> for various purposes
> then  ….. that’s different. Both are in the “hobbyist” range.
> 
> Spurs matter for some things and don’t matter much for others. A spur at -120 
> at 10 MHz 
> may be up around -60 db at 10 GHz. It might matter there … it might not. A 
> -60 db spur 
> at 10 MHz gets into the “yikes” range if directly multiplied. 
> 
> How big is your bench? How long are your feed cables? You are getting into a 
> significant 
> fraction of a wavelength at 10’ of cable. If unterminated (and / or poorly 
> shielded) it will spray
> a bit of RF. 
> 
> Lots of details and no single answer without digging deeper into what you are 
> trying to do.
> 
> Bob
> 
>> On Jan 21, 2020, at 4:06 PM, Bryan _  wrote:
>> 
>> On the point of using a MDA-3V at the hobbyist bench level, any issues that 
>> one needs to be concerned about. A few modification projects online, but 
>> none really comment on any issues or performance.
>> 
>> -=Bryan=-
>> 
>> 
>> From: time-nuts  on behalf of Bob kb8tq 
>> 
>> Sent: January 21, 2020 7:57 AM
>> To: Taka Kamiya ; Discussion of precise time and 
>> frequency measurement 
>> Subject: Re: [time-nuts] Simple GPSDO Multiple Outputs - buffered line 
>> driver options?
>> 
>> Hi
>> 
>> Cross talk between the reference in and the measured signal on the 53131 
>> series can be an
>> issue . The counter drops resolution in the vicinity of 10 MHz as a result. 
>> There is also an  issue
>> with  the sampling process rather than direct feedthrough.
>> 
>> If you are measuring things like phase noise, having a lot of 10 MHz running 
>> around the lab will put a
>> spur in the phase noise plot. It may be close enough in that you don’t 
>> notice it every time. The same
>> sort of spur will play nasties with things like ADEV measurements. Getting a 
>> 10V RMS signal down
>> 120 db is tough …
>> 
>> Finally if you happen to be playing with radios, WWV is at 10 MHz. It does 
>> not take a lot of reference
>> signal to get back into the typical receiving antenna.
>> 
>> ==
>> 
>> If you are daisy chaining counters, there are several ways to do it:
>> 
>> 1) Drive the “ext ref in” and daisy chain off of “ext ref out”. This way the 
>> signal is buffered at each device.
>> It may add a bit of noise, but you can go a long way doing this.
>> 
>> 2) Put a coax Tee connector at each instrument. If the device is high Z in, 
>> this can do ok. If it is a 50 ohm
>> termination all the time … not so much. Even with the high Z input it’s 
>> better for short runs than long ones.
>> 
>> 3) Mix the two approaches. If you have a variety of gear, use the ones with 
>> ref in / ref out as buffers. String
>> the other gear in-between those boxes.
>> 
>> Bob
>> 
>>> On Jan 21, 2020, at 10:27 AM, Taka Kamiya via time-nuts 
>>>  wrote:
>>> 
>>> I've tried daisy chaining 4 HP5335A.  By the time signal got to the 4th 
>>> box, it was too weak to reliably drive the 1 pps.  I had a terminator at 
>>> the last tee with short length of RG58s between boxes.  I guess some box 
>>> puts relatively heavy load on the signal?
>>> 
>>> I'd like to know why 10V is a bad idea.  (besides too close to the upper 
>>> limit)  Cross talk between what/where?
>>> 
>>> To OP:I have video amplifiers Extron MDA-3V successfully used for this.  1 
>>> port in, 3 ports out ones by Extron are very inexpensive at 10 dollars+/-.  
>>> I never did formal testing but reading on all counters matched exactly.  
>>> They are 75 ohms but it didn't matter in my use case.  You can 
>>> change/adjust internal resisters if you are concerned.
>>> 
>>> ---
>>> (Mr.) Taka Kamiya
>>> KB4EMF / ex JF2DKG
>>> 
>>> 
>>>   On Tuesday, January 21, 2020, 7:45:22 AM EST, Bob kb8tq  
>>> wrote:
>>> 

Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Magnus Danielson]

Hi Mark,

On 2020-01-21 19:41, Mark Haun wrote:
> Hi Attila,
>
> On Tue, 21 Jan 2020 15:08:16 +0100
> Attila Kinali  wrote:
>> On Tue, 21 Jan 2020 01:15:45 +0100
>> Attila Kinali  wrote:
>>> You don't need a high performance ADC for the reference as you are
>>> dealing with a narrow band signal of known frequency. Even a 10bit
>>> or 8bit ADC would be good enough. You can even go and sample at
>>> half frequency and save both money and power.   
>> I just spend a few minutes looking at ADCs and found the LTC2256-12
>> and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
>> Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
>> respectively. 3dB BW is 800MHz, so more then good enough to even use
>> the 100MHz output of an hydrogen maser, if you want a really good
>> reference ;-)
>>
>> Power consumption at max sample rate are 34mW and 47mW respectively.
>> That's slightly more than a PLL would use (~20mW, plus maybe another
>> 5mW to 10mW for the opamps in the loopfilter). Power consumption goes
>> down a bit with decreasing sample rate, but not as much as one would
>> hope for.
> I hope you will indulge one more newbie question on the analog PLL
> option... as I have approximately zero experience designing them.
>
> What are the adverse consequences of using large divisors in the loop,
> as would be required for my odd OCXO frequency?  E.g. on paper, it would
> seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
> frequency.  How would this differ from a more "normal" ref clock
> frequency of 10 or 16 MHz with smaller divisors?

>From my experience, such factors and rate of phase comparator is
relatively easy to work with and get to work reasonably well for most
purposes. I recommend you to use a PI-loop.

For a step-up you want to keep the PLL bandwidth fairly large, and that
helps making it easy.

I've been tempted to do a bunch of such loops in various kinds of
equipment to solve issues. I should to more of them. One should have a
nice little lock-up board to just apply.

Cheers,
Magnus



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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mark Haun]

On Wed, 22 Jan 2020 00:30:12 +0100
Magnus Danielson  wrote:
> > What are the adverse consequences of using large divisors in the
> > loop, as would be required for my odd OCXO frequency?  E.g. on
> > paper, it would seem that I could use 80 MHz / 625 = 16.384 MHz /
> > 128 = 128 kHz PFD frequency.  How would this differ from a more
> > "normal" ref clock frequency of 10 or 16 MHz with smaller divisors?
> 
> From my experience, such factors and rate of phase comparator is
> relatively easy to work with and get to work reasonably well for most
> purposes. I recommend you to use a PI-loop.
> 
> For a step-up you want to keep the PLL bandwidth fairly large, and
> that helps making it easy.

Why is this?  In my primitive understanding, the loop bandwidth sets the
point where the phase-noise characteristics of the reference and the
VCO are "glued together."  Because my VCXO has good phase noise, and
lacks only stability (say 0.1 to 1 sec and longer), I would have
thought I would want a small bandwidth---basically I want to preserve
the phase-noise characteristics but keep it from drifting.

I know ADI has a nice tool for PLL design; I'll check it out.

Regards,
Mark


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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[jimlux]

On 1/21/20 3:30 PM, Magnus Danielson wrote:

Hi Mark,

On 2020-01-21 19:41, Mark Haun wrote:

Hi Attila,

On Tue, 21 Jan 2020 15:08:16 +0100
Attila Kinali  wrote:

On Tue, 21 Jan 2020 01:15:45 +0100
Attila Kinali  wrote:

You don't need a high performance ADC for the reference as you are
dealing with a narrow band signal of known frequency. Even a 10bit
or 8bit ADC would be good enough. You can even go and sample at
half frequency and save both money and power.

I just spend a few minutes looking at ADCs and found the LTC2256-12
and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
respectively. 3dB BW is 800MHz, so more then good enough to even use
the 100MHz output of an hydrogen maser, if you want a really good
reference ;-)

Power consumption at max sample rate are 34mW and 47mW respectively.
That's slightly more than a PLL would use (~20mW, plus maybe another
5mW to 10mW for the opamps in the loopfilter). Power consumption goes
down a bit with decreasing sample rate, but not as much as one would
hope for.

I hope you will indulge one more newbie question on the analog PLL
option... as I have approximately zero experience designing them.

What are the adverse consequences of using large divisors in the loop,
as would be required for my odd OCXO frequency?  E.g. on paper, it would
seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
frequency.  How would this differ from a more "normal" ref clock
frequency of 10 or 16 MHz with smaller divisors?


 From my experience, such factors and rate of phase comparator is
relatively easy to work with and get to work reasonably well for most
purposes. I recommend you to use a PI-loop.

For a step-up you want to keep the PLL bandwidth fairly large, and that
helps making it easy.

I've been tempted to do a bunch of such loops in various kinds of
equipment to solve issues. I should to more of them. One should have a
nice little lock-up board to just apply.



One might also look at a fractional-N PLL - just a bit more flexibility 
in where the spurs go.



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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Bob kb8tq]

Hi

Pretty much everybody who wants to sell you a PLL chip also has free 
simulation software to give you some idea what that chip does. None of 
them are perfect. They all take a bit of time to get used to. Some of them 
(Analog Devices stuff) will deal with noise. You can get a pretty good feel 
for the noise floor and spur issues involved. 

Bob

> On Jan 21, 2020, at 7:11 PM, jimlux  wrote:
> 
> On 1/21/20 3:30 PM, Magnus Danielson wrote:
>> Hi Mark,
>> On 2020-01-21 19:41, Mark Haun wrote:
>>> Hi Attila,
>>> 
>>> On Tue, 21 Jan 2020 15:08:16 +0100
>>> Attila Kinali  wrote:
 On Tue, 21 Jan 2020 01:15:45 +0100
 Attila Kinali  wrote:
> You don't need a high performance ADC for the reference as you are
> dealing with a narrow band signal of known frequency. Even a 10bit
> or 8bit ADC would be good enough. You can even go and sample at
> half frequency and save both money and power.
 I just spend a few minutes looking at ADCs and found the LTC2256-12
 and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
 Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
 respectively. 3dB BW is 800MHz, so more then good enough to even use
 the 100MHz output of an hydrogen maser, if you want a really good
 reference ;-)
 
 Power consumption at max sample rate are 34mW and 47mW respectively.
 That's slightly more than a PLL would use (~20mW, plus maybe another
 5mW to 10mW for the opamps in the loopfilter). Power consumption goes
 down a bit with decreasing sample rate, but not as much as one would
 hope for.
>>> I hope you will indulge one more newbie question on the analog PLL
>>> option... as I have approximately zero experience designing them.
>>> 
>>> What are the adverse consequences of using large divisors in the loop,
>>> as would be required for my odd OCXO frequency?  E.g. on paper, it would
>>> seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
>>> frequency.  How would this differ from a more "normal" ref clock
>>> frequency of 10 or 16 MHz with smaller divisors?
>> From my experience, such factors and rate of phase comparator is
>> relatively easy to work with and get to work reasonably well for most
>> purposes. I recommend you to use a PI-loop.
>> For a step-up you want to keep the PLL bandwidth fairly large, and that
>> helps making it easy.
>> I've been tempted to do a bunch of such loops in various kinds of
>> equipment to solve issues. I should to more of them. One should have a
>> nice little lock-up board to just apply.
> 
> One might also look at a fractional-N PLL - just a bit more flexibility in 
> where the spurs go.
> 
> 
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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Magnus Danielson]

Hi,

On 2020-01-22 01:05, Mark Haun wrote:
> On Wed, 22 Jan 2020 00:30:12 +0100
> Magnus Danielson  wrote:
>>> What are the adverse consequences of using large divisors in the
>>> loop, as would be required for my odd OCXO frequency?  E.g. on
>>> paper, it would seem that I could use 80 MHz / 625 = 16.384 MHz /
>>> 128 = 128 kHz PFD frequency.  How would this differ from a more
>>> "normal" ref clock frequency of 10 or 16 MHz with smaller divisors?
>> From my experience, such factors and rate of phase comparator is
>> relatively easy to work with and get to work reasonably well for most
>> purposes. I recommend you to use a PI-loop.
>>
>> For a step-up you want to keep the PLL bandwidth fairly large, and
>> that helps making it easy.
> Why is this?  In my primitive understanding, the loop bandwidth sets the
> point where the phase-noise characteristics of the reference and the
> VCO are "glued together."  Because my VCXO has good phase noise, and
> lacks only stability (say 0.1 to 1 sec and longer), I would have
> thought I would want a small bandwidth---basically I want to preserve
> the phase-noise characteristics but keep it from drifting.

With higher bandwidth, it follows the reference tighter. Consider that
the bandwidth of the PLL is related to the time-constant for it to react
to both the reference and the steered oscillator, and it will low-pass
filter the reference and high-pass filter the steered oscillator, and
higher bandwidth thus suppress more variations of the steered
oscillator, relaxing thermal issues for instance.

If you have a loop filter being a low-pass filter rather than PI-loop,
then you also get better lock-range, quicker lock-in and smaller
phase-errors due to thermal effects or oscillator differences. For a
PI-loop you essentially remove it from being an issue anyway and you can
focus your bandwidth on phase-noise considerations, but the high-pass
vs. low-pass balance remains an issue for compromise.

For step-up PLLs, you typically wants a high bandwidth to keep tight
phase with the reference, but for a clean-up PLL you want a low
bandwidth to filter out as much noise from the reference.

As you compare the phase-noise of the reference and steered oscillator,
as compared on the same frequency, the optimum bandwidth is usually
where they cross each other. This assumes that you actually considered
all the variations.

Cheers,
Magnus




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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[jimlux]

On 1/21/20 4:19 PM, Bob kb8tq wrote:

Hi

Pretty much everybody who wants to sell you a PLL chip also has free
simulation software to give you some idea what that chip does. None of
them are perfect. They all take a bit of time to get used to. Some of them
(Analog Devices stuff) will deal with noise. You can get a pretty good feel
for the noise floor and spur issues involved.

Bob


Dean Banerjee's book is also useful. You used to be able to download it 
from National Semiconductor, but now they're part of TI.



You can buy the 5th edition on paper, but here it is as a pdf

http://www.ti.com/lit/ml/snaa106c/snaa106c.pdf

you can read it, but not print it.


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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Bob kb8tq]

Hi

> On Jan 21, 2020, at 8:21 PM, Magnus Danielson  wrote:
> 
> Hi,
> 
> On 2020-01-22 01:05, Mark Haun wrote:
>> On Wed, 22 Jan 2020 00:30:12 +0100
>> Magnus Danielson  wrote:
 What are the adverse consequences of using large divisors in the
 loop, as would be required for my odd OCXO frequency?  E.g. on
 paper, it would seem that I could use 80 MHz / 625 = 16.384 MHz /
 128 = 128 kHz PFD frequency.  How would this differ from a more
 "normal" ref clock frequency of 10 or 16 MHz with smaller divisors?
>>> From my experience, such factors and rate of phase comparator is
>>> relatively easy to work with and get to work reasonably well for most
>>> purposes. I recommend you to use a PI-loop.
>>> 
>>> For a step-up you want to keep the PLL bandwidth fairly large, and
>>> that helps making it easy.
>> Why is this?  In my primitive understanding, the loop bandwidth sets the
>> point where the phase-noise characteristics of the reference and the
>> VCO are "glued together."  Because my VCXO has good phase noise, and
>> lacks only stability (say 0.1 to 1 sec and longer), I would have
>> thought I would want a small bandwidth---basically I want to preserve
>> the phase-noise characteristics but keep it from drifting.
> 
> With higher bandwidth, it follows the reference tighter. Consider that
> the bandwidth of the PLL is related to the time-constant for it to react
> to both the reference and the steered oscillator, and it will low-pass
> filter the reference and high-pass filter the steered oscillator, and
> higher bandwidth thus suppress more variations of the steered
> oscillator, relaxing thermal issues for instance.
> 
> If you have a loop filter being a low-pass filter rather than PI-loop,
> then you also get better lock-range, quicker lock-in and smaller
> phase-errors due to thermal effects or oscillator differences. For a
> PI-loop you essentially remove it from being an issue anyway and you can
> focus your bandwidth on phase-noise considerations, but the high-pass
> vs. low-pass balance remains an issue for compromise.
> 
> For step-up PLLs, you typically wants a high bandwidth to keep tight
> phase with the reference, but for a clean-up PLL you want a low
> bandwidth to filter out as much noise from the reference.
> 
> As you compare the phase-noise of the reference and steered oscillator,
> as compared on the same frequency, the optimum bandwidth is usually
> where they cross each other. This assumes that you actually considered
> all the variations.


…….. and *assuming* the noise floor of the dividers and the noise floor of the 
phase
detector is anywhere near good enough to be useful compared to your super duper
low noise oscillators ….. With good OCXO’s and VCXO’s this may indeed be a 
gotcha. 
With a simple VCO and TCXO from “low bidder industries” , maybe not so much. 

( in genera with good oscillators l, this forces you to a narrower loop than 
you might 
have anticipated ….) 

Again, playing with simulation software  just might be a good idea. For the 
brave, you
can buy various books and dig up all sorts of formulas. Those can be dumped 
into 
spread sheets and validated ….. 

Bob


> 
> Cheers,
> Magnus
> 
> 
> 
> 
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Re: [time-nuts] Odd-order multiplication of CMOS-output OCXO

[Charles Steinmetz]

Jim wrote:

> Dean Banerjee's book is also useful.   *  *  *
> You can buy the 5th edition on paper, but here it is as a pdf
> you can read it, but not print it.

The 4th ed. is available at 



It is a  fully functional PDF file.  File name is "PLL Performance 
Simulation Design 4th 2006 BANNERJEE.pdf" [NOTE misspelling of author's 
name]


Best regards,

Charles



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