On Wed, 22 Jan 2020 00:30:12 +0100 Magnus Danielson <mag...@rubidium.se> wrote: > > What are the adverse consequences of using large divisors in the > > loop, as would be required for my odd OCXO frequency? E.g. on > > paper, it would seem that I could use 80 MHz / 625 = 16.384 MHz / > > 128 = 128 kHz PFD frequency. How would this differ from a more > > "normal" ref clock frequency of 10 or 16 MHz with smaller divisors? > > From my experience, such factors and rate of phase comparator is > relatively easy to work with and get to work reasonably well for most > purposes. I recommend you to use a PI-loop. > > For a step-up you want to keep the PLL bandwidth fairly large, and > that helps making it easy.
Why is this? In my primitive understanding, the loop bandwidth sets the point where the phase-noise characteristics of the reference and the VCO are "glued together." Because my VCXO has good phase noise, and lacks only stability (say 0.1 to 1 sec and longer), I would have thought I would want a small bandwidth---basically I want to preserve the phase-noise characteristics but keep it from drifting. I know ADI has a nice tool for PLL design; I'll check it out. Regards, Mark _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.