Re: [time-nuts] low power divide by 5
Hi, a divide by five should possible with a synchronous state-machine made of 3 ( sufficiently fast-) JK-FlipFlops. All 3 FFs are clocked with the input freq. , the outputs of the FFs are fed back to the the JK-inputs, the divided freq. is output of one of the FFs. Additional constraints: no external ANDs or ORs or NOTs, the state-machine does not get stuck in the 3 unused states. This turned out to be a very interesting problem and I do not yet come up with a solution. Maybe there is none. Analytical solutions all failed, I will try a brute force enumeration attack tomorrow. lots of fun ! Cheers Detlef Am 30.06.2020 um 08:37 schrieb Hal Murray: You might try the 74AC161, which works to 73MHz at 3.3V or 103 MHz at 5V, -40 to 85C. Set the data inputs to DCBA = 1011 and connect an inverter from the carry output (pin 15) to the Load input (pin 9) to divide by 5. See http:// www.techlib.com/electronics/74161Divider.htm You didn't read the data sheet carefully enough. That 73 MHz is the bragging number for sales people, often not useful. For something like this, you need to add the clock-to-out for the ripple carry, prop time through inverter, and setup time at the load input. I was going to ask whether 73MHz included the delay through the inverter, but it's much worse than that. The clock to out on the RCO pin is 21 ns. Even without the inverter, it won't make 50 MHz. You can save a few ns if you use a FF with inverting output instead of an inverter. That adds a pipeline stage so you have to adjust the constant that gets loaded. Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually only 39.5). At 5V, AC161 clk-RCO is 15.2 AC74 setup is 3.1 So that works - 54.6 MHz. Using an inverter: AC161 clk-RCO is 15.2 AC04 prop 5.9 AC161 setup 5.3 That's 37.9 MHz (That's all assuming I didn't fatfinger anything.) I like Richard Karlquist's trick of using a data bit to reload. Unfortunately, for the AC161, the data out isn't significantly faster than the carry out. If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] low power divide by 5
hm, first example of divide by 5 needs an additional AND, second example gets stuck in an unused state :( Cheers Detlef Am 01.07.2020 um 02:14 schrieb David: Here's a web page with several JK flip-flop dividers, including divide by 5: http://www.play-hookey.com/digital/counters/frequency_dividers.html Dave On 2020-06-30 15:47, dschuecker wrote: Hi, a divide by five should possible with a synchronous state-machine made of 3 ( sufficiently fast-) JK-FlipFlops. All 3 FFs are clocked with the input freq. , the outputs of the FFs are fed back to the the JK-inputs, the divided freq. is output of one of the FFs. Additional constraints: no external ANDs or ORs or NOTs, the state-machine does not get stuck in the 3 unused states. This turned out to be a very interesting problem and I do not yet come up with a solution. Maybe there is none. Analytical solutions all failed, I will try a brute force enumeration attack tomorrow. lots of fun ! Cheers Detlef Am 30.06.2020 um 08:37 schrieb Hal Murray: You might try the 74AC161, which works to 73MHz at 3.3V or 103 MHz at 5V, -40 to 85C. Set the data inputs to DCBA = 1011 and connect an inverter from the carry output (pin 15) to the Load input (pin 9) to divide by 5. See http:// www.techlib.com/electronics/74161Divider.htm [1] You didn't read the data sheet carefully enough. That 73 MHz is the bragging number for sales people, often not useful. For something like this, you need to add the clock-to-out for the ripple carry, prop time through inverter, and setup time at the load input. I was going to ask whether 73MHz included the delay through the inverter, but it's much worse than that. The clock to out on the RCO pin is 21 ns. Even without the inverter, it won't make 50 MHz. You can save a few ns if you use a FF with inverting output instead of an inverter. That adds a pipeline stage so you have to adjust the constant that gets loaded. Setup time on a 3V AC74 is 4.3 ns which gets to 40 MHz (actually only 39.5). At 5V, AC161 clk-RCO is 15.2 AC74 setup is 3.1 So that works - 54.6 MHz. Using an inverter: AC161 clk-RCO is 15.2 AC04 prop 5.9 AC161 setup 5.3 That's 37.9 MHz (That's all assuming I didn't fatfinger anything.) I like Richard Karlquist's trick of using a data bit to reload. Unfortunately, for the AC161, the data out isn't significantly faster than the carry out. If I did the numbers correctly, that's 35 MHz at 3.3V and 49.3 MHz at 5V. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. Links: -- [1] http://www.techlib.com/electronics/74161Divider.htm ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] David Allan amusing notes on ADEV, MDEV, TDEV etc.
Hi, I managed to obtain the Lighthill book 'Introduction to Fourier Analysis and Generalised Functions' and I scanned it. It provides a different look on Fourier Analysis. Feel free to download it from my private cloud: dschuecker.dyndns.org name/pw guest1 have fun. Cheers Detlef Am 07.10.2020 um 12:05 schrieb Magnus Danielson: Hi, I found this little text that may be an amusing read on how ADEV and MDEV came to be among other things. https://ethw.org/w/images/5/5f/Allan_OH_-_MVAR_TVAR_and_OptimumPrediction.pdf The Lighthill book is very important little thing, which few seems to know. It works on Fourier transform quite differently than any other book on Fourier transforms I've seen. It is not meant as a strict book, but a book to help students on their way, and it did help Jim and Dave in their studies for sure. Similarly the Snyder pre-cursor to MDEV seems to be read by few. It provides the necessary sqrt(N) improvement as achieved with overlapping frequency estimations. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
Re: [time-nuts] David Allan amusing notes on ADEV, MDEV, TDEV etc.
Hi, I managed to obtain the Lighthill book 'Introduction to Fourier Analysis and Generalised Functions' and I scanned it. It provides a different look on Fourier Analysis. Feel free to download it from my private cloud: ftp://dschuecker.dyndns.org/Lighthill_Introduction_to_Fourier_Analysis_and_generalised_functions.pdf name/pw guest1 have fun. Cheers ___ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
[time-nuts] Re: Complex PLL
Hi, In the code you sent you used a division for phase detection as far as I can tell. Yes, but it is the Matlab model code, so I dont care about division. In 'real life' I multiply with the conjugate complex value. It has the same angle and different length, but I normalize anyway. And the 'atan' is always 'atan2', sure. For a non-complex PLL I beat down to zero the angle of the phase discriminator. In this complex PLL I beat down to zero the imaginary part of the quotient. Another very interesting detail: The carrier I pll on is at 2400Hz, I have to demodulate with a synched 1800Hz. This means that I have to find the complex value which has 3/4 of the angle without atan/cos/sin, sqrt is ok. This C-Code does the trick: cpl4.re=sqrt((1.0+cpl3.re)/2.0f); cpl4.im=sqrt((1.0-cpl3.re)/2.0f); cpl5.re=sqrt((1.0+cpl4.re)/2.0f); cpl5.im=sqrt((1.0-cpl4.re)/2.0f); CMUL(cpl5,cpl5,cpl4); CMUL(cpl4,cpl5,cpl3); CROT(T3,cpl3); much fun ! Math rulez ! Cheers Detlef Am 19.03.2021 um 13:23 schrieb Magnus Danielson: Hi, On 2021-03-18 13:59, Detlef Schuecker via time-nuts wrote: Hi, yes, got it, I think, thanks. I calculate the complex quotient of the incoming complex signal and the local complex oscillator. I feed the imaginary part of the quotient to the PI controller, thus forcing it to zero. The local oscillator is updated by multiplying it with ( real(quotient)+j*PIOutput ). Forcing the imaginary part of the quotient to zero means that incoming signal and local oscillator are in phase. See Matlab code and the image. No atan/cos/sin, just mere multiplication :)) In the code you sent you used a division for phase detection as far as I can tell. The modeling approach you used is different enough that it took some time to decode it, and maybe I would have used a different set of variable names, but that's more me than the model. I often use a phase-accumulator / integrator to model (and synthesize) in PLL simulations. Anyway, good that you are on track. Once you have that basic I think you can quickly enough vary the theme. You could move over from imag to real and it would only change subtly. Cheers, Magnus Thanks Cheers Detlef Schücker DD4WV clear n=1; T1=0; T2=0.01; s0=exp(j*2*pi*200*(0:n-1)/n); s1=zeros(1,n); s2=zeros(1,n); s3=zeros(1,n); for(k=1:n) s1(k)=(s0(k)/T2); T1=T1+imag(s1(k))/4000; s2(k)=0.03*imag(s1(k))+T1; s3(k)=T2; T2=T2*(real(s1(k))+j*s2(k)); end; plot(1:n,real(s3),'b.-',1:n,real(s0),'r.-') return "Magnus Danielson" schrieb am 17.03.2021 19:20:49: Von: "Magnus Danielson" An: time-nuts@lists.febo.com Datum: 17.03.2021 19:59 Betreff: [time-nuts] Re: Complex PLL Hi, On 2021-03-17 17:20, Detlef Schuecker via time-nuts wrote: Hi time-nuts, a PLL takes the phase difference of the incoming signal and the synthesized signal and feeds that in a loop filter. The output of the loop filter is used to steer the local oscillator. In my setup I have an incoming complex signal and my local oscillator is generating a complex signal as well. So calculation of the phase difference is just the quotient of the incoming signal and the local oscillator, it is a sampled system. I take the quotient, calculate the angle using the atan function and then I feed it in the loop filter, a PI controller. The output of the loop filter is converted to a complex phase increment for the local oscillator with the sin and cos function. Now I have to get rid of the atan, cos and sin functions. I am looking for a loop filter which takes the quotient of the incoming/synthesized signal as a complex value. The output of this loop filter should be the phase increment for the local oscillator. It should not use the angle of the complex value explicitly, as this will involve the atan/cos/sin functions. Is someone aware of such a loop filter? I surfed through Gardners' 'Phaselock Techniques' but did not find a hint. That book is full of hints. Costas loop is one. Actually, you could just do complex multiplication and only use the real output (and thus remove half the complex multiplication) and use that output of the multiplication as input to normal PI-regulator, that will lock up and achieve everything you want. You can then also remove the sine with a squarewave. There is some benefits and losses in doing that, which may or may not be relevant. There is a richness of complex detectors to be found in GPS literature, such as that of "Understanding GPS principles and applications" of Kaplan and Hegarty. You can also look at "Phase-locked loop circuit design" by Wolaver for additional inspiration. You end up finding that Garners' book is actually very comprehensive if you only take time to dwell into it. Let me know if you need more hints. Cheers and 73, Magnus SA0MAD ___ time-nuts mailing list -- time-nuts@lists.febo.com -- To unsubscribe send an email to time-nuts-le...@lists.febo.com To unsubscribe, go to a
[time-nuts] Re Another reason to monitor line frequency
Hi, here in Germany police is recording line frequency since 2010, just as I do :). https://en.wikipedia.org/wiki/Electrical_network_frequency_analysis https://de.wikipedia.org/wiki/Netzfrequenz_als_Grundlage_f%C3%BCr_forensische_Analysen Don't know if they brought someone to jail with this. With newer audio equipment you should get lower hum levels. I do not think that you find any harmonics of 50Hz or 60Hz for, say the audio track of a youtube video, I never tried, though. For my audio tape recorder of the 1970s you will surely get a hum signature. Maybe there is also a chance to find the hum in the brightness of the video signal. There are other strange aspects on grid frequency: for the first 15min of some hours of the day grid frequency is systematic high or low. This has to do with the spot market trade period of 15 min and a systematic over/underestimate of the demand/production. A too high demand brings grid frequency down and vice versa. Cheers Detlef Am 19.01.2022 um 12:31 schrieb Hal Murray: The hidden background noise that can catch criminals https://www.youtube.com/watch?v=e0elNU0iOMY 5 1/2 minutes. He's good in a geeky sort of way. Time sink warning. Why European Clocks are Running Slow, and British Clocks Aren't https://www.youtube.com/watch?v=bij-JjzCa7o 4 minutes Here is his rant on time zones. :) The Problem with Time & Timezones - Computerphile https://www.youtube.com/watch?v=-5wpm-gesOY 10 minutes. ___ time-nuts mailing list -- time-nuts@lists.febo.com -- To unsubscribe send an email to time-nuts-le...@lists.febo.com To unsubscribe, go to and follow the instructions there.
