Re: [U-Boot] [PATCH v2 0/4] [ARM] Add KGDB support for ARM platforms
splitting patches is good, but you cant use the same exact summary for each one with no changelog -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] KGDB set / remove breakpoints
On Monday 19 April 2010 04:54:50 Tonny Tzeng wrote: > >> Please note, after applying this patch, those architectures, which > >> already enabled KGDB support, have to create a new asm/kgdb.h and > >> define the length of the break instruction (BREAK_INSTR_SIZE) in that > >> file. > > > > i dont think breaking build is a good idea. i would have the code simply > > disable itself if BREAK_INSTR_SIZE isnt set. > > That's why I used ifndef in the previous patch, and set > BREAK_INSTR_SIZE to 4 if it isn't set, but I thought you prefer "an > undefined size should be used as a tip that the arch doesnt yet > support break points"? i meant have the functions always return an error. have the header do: #ifndef BREAK_INSTR_SIZE #define BREAK_INSTR_SIZE 0 #endif and then in gdb_cmd_break(), do something at the top like: if (BREAK_INSTR_SIZE == 0) return; > In Linux kgdb code, there is an arch independent header file > include/linux/kgdb.h, which includes arch dependent header asm/kgdb.h. > I am trying to include this concept here, unfortunately current > u-boot code only has linux/kgdb.h, if we want to define arch specific > code in asm/kgdb.h, we may need to include asm/kgdb.h from > linux/kgdb.h, so it looks to me it will definitely break other arch, > do you have any suggestion for that? just post a patch to add asm/kgdb.h stubs for the few arches that you dont implement yourself. i think only blackfin/i386/ppc support kgdb atm. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] OpenRD: Bring PCIe endpoint out of reset
There exists PCIe endpoints(not all) that remains in reset state till PERST# line (A11 on the PCIe connector) is hold low. They come out of reset only when this line is high. In case of OpenRD, this line was in tri-state. So, some of the PCIe devices would never appear on the PCIe bus. This patch makes PERST# line high while booting to bring such PCIe devices out of reset. XGI Vollari Z11 GPU and Intel WiFi 4965 are the ones who doesn't care about this line. Where as Broadcom's BCM970012 won't appear on the PCIe bus until PERST# is high. With this patch both kinds of device would appear on the PCIe bus. Signed-off-by: Tanmay Upadhyay Signed-off-by: Dhaval Vasa --- board/Marvell/openrd_base/openrd_base.h |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h index f3daf17..bf75fc6 100644 --- a/board/Marvell/openrd_base/openrd_base.h +++ b/board/Marvell/openrd_base/openrd_base.h @@ -30,10 +30,10 @@ #ifndef __OPENRD_BASE_H #define __OPENRD_BASE_H -#define OPENRD_OE_LOW (~(1<<28))/* RS232 / RS485 */ -#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ -#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ -#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ +#define OPENRD_OE_LOW (~((1<<28) | (1<<7))) /* RS232 / RS485, PCIe */ +#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ +#define OPENRD_OE_VAL_LOW (1<<7)/* Sel RS232, PCIe out of reset */ +#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ /* PHY related */ #define MV88E1116_LED_FCTRL_REG10 -- 1.6.6.1 -- _ Disclaimer: This e-mail message and all attachments transmitted with it are intended solely for the use of the addressee and may contain legally privileged and confidential information. If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution, copying, or other use of this message or its attachments is strictly prohibited. If you have received this message in error, please notify the sender immediately by replying to this message and please delete it from your computer. Any views expressed in this message are those of the individual sender unless otherwise stated.Company has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email. _ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5] net: add altera triple speeds ethernet mac driver
This driver supports the Altera triple speeds 10/100/1000 ethernet
mac.
Signed-off-by: Thomas Chou
---
sort the code to remove func proto.
change initialization, with dev_num and bases.
add tse_set_mac_address().
sgdma code is not folded due to increased code size.
drivers/net/Makefile |1 +
drivers/net/altera_tse.c | 935 ++
drivers/net/altera_tse.h | 494
include/netdev.h |2 +
4 files changed, 1432 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/altera_tse.c
create mode 100644 drivers/net/altera_tse.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0e68e52..b75c02f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libnet.a
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
+COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
new file mode 100644
index 000..5927904
--- /dev/null
+++ b/drivers/net/altera_tse.c
@@ -0,0 +1,935 @@
+/*
+ * Altera 10/100/1000 triple speed ethernet mac driver
+ *
+ * Copyright (C) 2008 Altera Corporation.
+ * Copyright (C) 2010 Thomas Chou
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "altera_tse.h"
+
+/* sgdma debug - print descriptor */
+static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc)
+{
+ debug("SGDMA DEBUG :\n");
+ debug("desc->source : 0x%x \n", (unsigned int)desc->source);
+ debug("desc->destination : 0x%x \n", (unsigned int)desc->destination);
+ debug("desc->next : 0x%x \n", (unsigned int)desc->next);
+ debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad);
+ debug("desc->destination_pad : 0x%x \n",
+ (unsigned int)desc->destination_pad);
+ debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad);
+ debug("desc->bytes_to_transfer : 0x%x \n",
+ (unsigned int)desc->bytes_to_transfer);
+ debug("desc->actual_bytes_transferred : 0x%x \n",
+ (unsigned int)desc->actual_bytes_transferred);
+ debug("desc->descriptor_status : 0x%x \n",
+ (unsigned int)desc->descriptor_status);
+ debug("desc->descriptor_control : 0x%x \n",
+ (unsigned int)desc->descriptor_control);
+}
+
+/* This is a generic routine that the SGDMA mode-specific routines
+ * call to populate a descriptor.
+ * arg1:pointer to first SGDMA descriptor.
+ * arg2:pointer to next SGDMA descriptor.
+ * arg3:Address to where data to be written.
+ * arg4:Address from where data to be read.
+ * arg5:no of byte to transaction.
+ * arg6:variable indicating to generate start of packet or not
+ * arg7:read fixed
+ * arg8:write fixed
+ * arg9:read burst
+ * arg10:write burst
+ * arg11:atlantic_channel number
+ */
+static void alt_sgdma_construct_descriptor_burst(
+ volatile struct alt_sgdma_descriptor *desc,
+ volatile struct alt_sgdma_descriptor *next,
+ unsigned int *read_addr,
+ unsigned int *write_addr,
+ unsigned short length_or_eop,
+ int generate_eop,
+ int read_fixed,
+ int write_fixed_or_sop,
+ int read_burst,
+ int write_burst,
+ unsigned char atlantic_channel)
+{
+ /*
+* Mark the "next" descriptor as "not" owned by hardware. This prevents
+* The SGDMA controller from continuing to process the chain. This is
+* done as a single IO write to bypass cache, without flushing
+* the entire descriptor, since only the 8-bit descriptor status must
+* be flushed.
+*/
+ if (!next)
+ debug("Next descriptor not defined!!\n");
+
+ next->descriptor_control = (next->descriptor_control &
+ ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK);
+
+ desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFF);
+ desc->destination =
+ (unsigned int *)((unsigned int)write_addr & 0x1FFF);
+ desc->next = (unsigned int *)((unsigned int)next & 0x1FFF);
+ desc->source_pad = 0x0;
+ desc->destination_pad = 0x0;
+ desc->next_pad = 0x0;
+ desc->bytes_to_transfer = length_or_eop;
+ desc->actual_bytes_transferred = 0;
+ desc->descriptor_status = 0x0;
+
+ /* SGDMA burst not currently supported */
+ desc->read_burst = 0;
+ desc->write_burst = 0;
+
+ /*
[U-Boot] [PATCH] nios2: consolidate reset initialization
Global interrupt should be disabled from the beginning. Signed-off-by: Thomas Chou --- arch/nios2/cpu/start.S |9 - 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 31cd5b0..d1016ea 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -34,6 +34,7 @@ .global _start _start: + wrctl status, r0 /* Disable interrupts */ /* ICACHE INIT -- only the icache line at the reset address * is invalidated at reset. So the init must stay within * the cache line size (8 words). If GERMS is used, we'll @@ -43,10 +44,9 @@ _start: ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE) movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE) ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE) - mov r6, r0 -0: initi r6 - add r6, r6, r4 - bltur6, r5, 0b +0: initi r5 + sub r5, r5, r4 + bgt r5, r0, 0b br _except_end /* Skip the tramp */ /* EXCEPTION TRAMPOLINE -- the following gets copied @@ -62,7 +62,6 @@ _except_end: /* INTERRUPTS -- for now, all interrupts masked and globally * disabled. */ - wrctl status, r0 /* Disable interrupts */ wrctl ienable, r0 /* All disabled */ /* DCACHE INIT -- if dcache not implemented, initd behaves as -- 1.6.6.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] please help me to Unsubscribe
because my email box z...@hebut.edu.cn is little size, I do not want to receive email any more, please help me to Unsubscribe. Thanks 2010-04-20 zs ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
On Mon, Apr 19, 2010 at 4:37 PM, Kim Phillips wrote: >> That's not what I was asking. The ITX was different from other 83xx >> boards. It doesn't define CONFIG_MPC83xx (and with this patch, it > > why doesn't it, btw? It's been a while, but I believe the reason the ITX does not defined CONFIG_MPC83xx is specifically so that this code: #if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx) icache_enable (); /* it's time to enable the instruction cache */ #endif is *not* executed. That is, on the ITX, calling icache_enable() at that point causes U-Boot to hang or crash. Therefore, I don't think any 83xx cache-related patch is complete until MPC8349ITX.h includes CONFIG_MPC83xx. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
Kim Phillips wrote: > On Mon, 19 Apr 2010 15:19:24 -0500 > Scott Wood wrote: >> Shouldn't you be using icache_enable(), or at least using HID0_INIT to >> do invalidation and lock clearing? > > the invalidation should occur whether or not the cache enable bit is > set in HID0_INIT, OK, was thinking of some other caches that don't automatically clear out the random junk on power-on -- but e300 manual says it does. > But I see your point; we should be using a more > formal approach. I'll see what I can do - it's just that this patch > preserved the existing code size, which could be important for e.g., > future nand bootstrap development. Right. It looks like we could shrink the NAND SPL some more by #ifndefing the cache functions in start.S. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
On Mon, 19 Apr 2010 15:19:24 -0500 Scott Wood wrote: > Kim Phillips wrote: > > On Fri, 16 Apr 2010 20:06:02 +0300 > > Michael Zaidman wrote: > > > >> On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips > >> wrote: > >>> before, MPC8349ITX boots u-boot in 4.3sec: > >> [snip] > >>> after, MPC8349ITX boots u-boot in 3.0sec: > >> Thanks for the good news! Memory POST test on my board with icach > >> disabled was lasting for hours until I enabled icach locally before > >> and disabled it after time consuming tests. > >> > >> BTW is there any reason that you enable icach in board specific rather > >> than in common code? > > > > not really, was just following the existing HID0-setting paradigm - > > I presume the paradigm came about to allow different cpu/board > > combinations to enable/disable different HID bits. Does that not sound > > valid to you? > > Shouldn't you be using icache_enable(), or at least using HID0_INIT to > do invalidation and lock clearing? the invalidation should occur whether or not the cache enable bit is set in HID0_INIT, and there is no locking being done prior to this point in the code. But I see your point; we should be using a more formal approach. I'll see what I can do - it's just that this patch preserved the existing code size, which could be important for e.g., future nand bootstrap development. Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
On Mon, 19 Apr 2010 16:05:11 -0500 Timur Tabi wrote: > On Mon, Apr 19, 2010 at 3:41 PM, Scott Wood wrote: > > >> What was so special about the 8349ITX that icache() didn't work? > >> You're changing the HDI0 values for all of the 83xx boards, but AFAIK, > >> only the ITX had this problem. > > > > All 83xx boards had the performance problem of not enabling icache until > > after relocation. > > That's not what I was asking. The ITX was different from other 83xx > boards. It doesn't define CONFIG_MPC83xx (and with this patch, it why doesn't it, btw? > still won't define it), so a lot of things weren't happening, > including this: > #if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx) > icache_enable (); /* it's time to enable the instruction cache */ > #endif > > Kim references the ITX in this patch, but I don't see how the problem > I just described is fixed. patch submission snafu; I'll send another version that includes the ITX. Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 2/6] MX: RTC13783 uses general function to access PMIC
The RTC is part of the Freescale's PMIC controller.
Use general function to access to PMIC internal registers.
Signed-off-by: Stefano Babic
---
Changes since last version: configuration of the RTC must be
updated for the boards that are using it.
drivers/rtc/mc13783-rtc.c | 72 --
include/configs/imx31_litekit.h |9 +++--
include/configs/mx31ads.h |8 +++--
include/configs/mx31pdk.h |9 +++--
4 files changed, 31 insertions(+), 67 deletions(-)
diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c
index 416f50d..4e18f80 100644
--- a/drivers/rtc/mc13783-rtc.c
+++ b/drivers/rtc/mc13783-rtc.c
@@ -23,53 +23,30 @@
#include
#include
#include
-
-static struct spi_slave *slave;
+#include
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
- u32 reg;
- int err, tim, i = 0;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 100,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
-
- if (spi_claim_bus(slave))
- return -1;
+ int tim, i = 0;
do {
- reg = 0x2c00;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- if (err)
- return err;
-
- reg = 0x2800;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day1 = pmic_reg_read(REG_RTC_DAY);
+ if (day1 < 0)
+ return -1;
- if (err)
- return err;
+ time = pmic_reg_read(REG_RTC_TIME);
+ if (time < 0)
+ return -1;
- reg = 0x2c00;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day2 = pmic_reg_read(REG_RTC_DAY);
+ if (day2 < 0)
+ return -1;
- if (err)
- return err;
} while (day1 != day2 && i++ < 3);
- spi_release_bus(slave);
-
tim = day1 * 86400 + time;
+
to_tm(tim, rtc);
rtc->tm_yday = 0;
@@ -80,34 +57,15 @@ int rtc_get(struct rtc_time *rtc)
int rtc_set(struct rtc_time *rtc)
{
- u32 time, day, reg;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 100,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
+ u32 time, day;
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
- if (spi_claim_bus(slave))
- return -1;
-
- reg = 0x2c00 | day | 0x8000;
- spi_xfer(slave, 32, (uchar *)®, (uchar *)&day,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- reg = 0x2800 | time | 0x8000;
- spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- spi_release_bus(slave);
+ pmic_reg_write(REG_RTC_DAY, day);
+ pmic_reg_write(REG_RTC_TIME, time);
return 0;
}
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 6131008..c025890 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -68,10 +68,13 @@
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE(SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK100
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2 and SS0 */
-#define CONFIG_MC13783_SPI_BUS 1
-#define CONFIG_MC13783_SPI_CS 0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index ec1c905..dedecd7 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -65,10 +65,12 @@
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE(SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK100
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1
-/* MC13783 connected to CSPI2
[U-Boot] [PATCH V3 4/6] SPI: added support for MX51 to mxc_spi
This patch add SPI support for the MX51 processor.
Signed-off-by: Stefano Babic
---
Changes: line errouneously removed before submitting the patch
(Thanks Magnus Lilja to point out the mistake).
drivers/spi/mxc_spi.c | 230
1 files changed, 210 insertions(+), 20 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 3a45200..dd465f9 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -31,7 +31,7 @@
#error "i.MX27 CSPI not supported due to drastic differences in register
definisions" \
"See linux mxc_spi driver from Freescale for details."
-#else
+#elif defined(CONFIG_MX31)
#include
@@ -56,6 +56,9 @@
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS 0x1f
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
@@ -65,12 +68,63 @@ static unsigned long spi_bases[] = {
0x53f84000,
};
+#define OUTMX31_GPIO_DIRECTION_OUT
+#define mxc_gpio_direction mx31_gpio_direction
+#define mxc_gpio_set mx31_gpio_set
+#elif defined(CONFIG_MX51)
+#include
+#include
+
+#define MXC_CSPIRXDATA 0x00
+#define MXC_CSPITXDATA 0x04
+#define MXC_CSPICTRL 0x08
+#define MXC_CSPICON0x0C
+#define MXC_CSPIINT0x10
+#define MXC_CSPIDMA0x14
+#define MXC_CSPISTAT 0x18
+#define MXC_CSPIPERIOD 0x1C
+#define MXC_CSPIRESET 0x00
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL 12
+
+static unsigned long spi_bases[] = {
+ CSPI1_BASE_ADDR,
+ CSPI2_BASE_ADDR,
+ CSPI3_BASE_ADDR,
+};
+#define mxc_gpio_direction(gpio, dir) (0)
+#define mxc_gpio_set(gpio, value) {}
+#define OUT1
+#else
+#error "Unsupported architecture"
#endif
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
u32 ctrl_reg;
+#if defined(CONFIG_MX51)
+ u32 cfg_reg;
+#endif
int gpio;
};
@@ -89,34 +143,161 @@ static inline void reg_write(unsigned long addr, u32 val)
*(volatile unsigned long*)addr = val;
}
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ if (mxcs->gpio > 0)
+ mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ if (mxcs->gpio > 0)
+ mxc_gpio_set(mxcs->gpio,
+ !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+}
+
+#ifdef CONFIG_MX51
+static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
+ s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
+ u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+
+ if (max_hz == 0) {
+ printf("Error: desired clock is 0\n");
+ return -1;
+ }
+
+ reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
+
+ /* Reset spi */
+ reg_write(mxcs->base + MXC_CSPICTRL, 0);
+ reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
+
+ /*
+* The following computation is taken directly from Freescale's code.
+*/
+ if (clk_src > max_hz) {
+ pre_div = clk_src / max_hz;
+ if (pre_div > 16) {
+ post_div = pre_div / 16;
+ pre_div = 15;
+ }
+ if (post_div != 0) {
+ for (i = 0; i < 16; i++) {
+ if ((1 << i) >= post_div)
+ break;
+ }
+ if (i == 16) {
+ printf("Error: no divider for the freq: %d\n",
+ max_hz)
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
On Mon, Apr 19, 2010 at 3:41 PM, Scott Wood wrote: >> What was so special about the 8349ITX that icache() didn't work? >> You're changing the HDI0 values for all of the 83xx boards, but AFAIK, >> only the ITX had this problem. > > All 83xx boards had the performance problem of not enabling icache until > after relocation. That's not what I was asking. The ITX was different from other 83xx boards. It doesn't define CONFIG_MPC83xx (and with this patch, it still won't define it), so a lot of things weren't happening, including this: #if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx) icache_enable (); /* it's time to enable the instruction cache */ #endif Kim references the ITX in this patch, but I don't see how the problem I just described is fixed. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Couture Brands Inc.
Your email client cannot read this email. To view it online, please go here: http://entourage-group.com/Marketing/display.php?M=13316&C=e39d6aea7c75dea17561e294f3c5c716&S=11&L=7&N=14 To stop receiving these emails:http://entourage-group.com/Marketing/unsubscribe.php?M=13316&C=e39d6aea7c75dea17561e294f3c5c716&L=7&N=11 Powered by Interspire ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] CFI interface and PPC440EP EBC chipselects
Hi, I am porting u-boot to a PPC 440EP custom board that is very similar to Yosemite. I have two chips (32 MB each) of NOR flash running through ECB at CS0 and CS1 and using the CFI interface. I was wondering where u-boot maps the chip selects so that multiple flash chips can be used. I have one bank running (CS0 copied from Yosemite port) but would like access to both. Thanks ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] Move arch/ppc to arch/powerpc
On Fri, 16 Apr 2010 18:59:30 +0200 Stefan Roese wrote: > [PATCH v3] Move arch/ppc to arch/powerpc > > As discussed on the list, move "arch/ppc" to "arch/powerpc" to > better match the Linux directory structure. > > Please note that this patch also changes the "ppc" target in > MAKEALL to "powerpc" to match this new infrastructure. But "ppc" > is kept as an alias for now, to not break compatibility with > scripts using this name. > > Signed-off-by: Stefan Roese > Acked-by: Wolfgang Denk > Acked-by: Detlev Zundel > Cc: Peter Tyser > Cc: Anatolij Gustschin this patch is missing an update to the Directory Hierarchy section in the main README file. Other than that, Acked-by: Kim Phillips Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Nios] Pull Request
Wolfgang, Wolfgang Denk wrote: > Um... Scott, I have a few other NIOS2 related patches in my queue > that seem to be pending, could you please have a look at these? > > 03/25 Thomas Chou [PATCH v2] nios2: add dma_alloc_coherent with > asm-nios2/dma-mapping.h > 03/27 Thomas Chou [PATCH] nios2: add 64 bits swab support in > asm-nios2/byteorder.h > 03/27 Thomas Chou [PATCH] nios2: add gpio based status led driver > 03/31 Thomas Chou [PATCH v5] nios2: add altera cf reset > 04/17 Thomas Chou [PATCH] nios2: allow link script overriding from boards > 04/17 Thomas Chou [PATCH 1/5 v3] nios2: add nios2-generic board Will do. The broken builds simply jumped to highest priority. Regards, --Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
Timur Tabi wrote: > On Thu, Apr 15, 2010 at 5:36 PM, Kim Phillips > wrote: > >> #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ >> -HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) >> +HID0_ENABLE_INSTRUCTION_CACHE | \ >> +HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) > > What was so special about the 8349ITX that icache() didn't work? > You're changing the HDI0 values for all of the 83xx boards, but AFAIK, > only the ITX had this problem. All 83xx boards had the performance problem of not enabling icache until after relocation. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cmd_nand.c: converted to new style subcmd handling
On Sun, Apr 04, 2010 at 09:53:16PM +0200, Frans Meulenbroeks wrote:
> converted to new style subcmd handling.
> partly tested on sheevaplug
> read and information commands tested on sheevaplug
> (sorry did not want to nuke my device so I did not want to
> test things like nand scrub)
>
> Signed-off-by: Frans Meulenbroeks
Sorry for the delay...
> +static int do_nand_read(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
> +{
The read and write functions are quite similar, and were not duplicated
previously. Use one function, distinguishing with argv[0] (i.e. use subcmd
only where it makes sense).
Likewise for erase and scrub.
> + if (argc < 4)
> + {
> + cmd_usage(cmdtp);
> + return 1;
> }
The opening brace should be on the same line as the "if".
-Scott
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Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
On Thu, Apr 15, 2010 at 5:36 PM, Kim Phillips wrote: > #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ > - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) > + HID0_ENABLE_INSTRUCTION_CACHE | \ > + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) What was so special about the 8349ITX that icache() didn't work? You're changing the HDI0 values for all of the 83xx boards, but AFAIK, only the ITX had this problem. -- Timur Tabi Linux kernel developer at Freescale ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
Kim Phillips wrote: > On Fri, 16 Apr 2010 20:06:02 +0300 > Michael Zaidman wrote: > >> On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips >> wrote: >>> before, MPC8349ITX boots u-boot in 4.3sec: >> [snip] >>> after, MPC8349ITX boots u-boot in 3.0sec: >> Thanks for the good news! Memory POST test on my board with icach >> disabled was lasting for hours until I enabled icach locally before >> and disabled it after time consuming tests. >> >> BTW is there any reason that you enable icach in board specific rather >> than in common code? > > not really, was just following the existing HID0-setting paradigm - > I presume the paradigm came about to allow different cpu/board > combinations to enable/disable different HID bits. Does that not sound > valid to you? Shouldn't you be using icache_enable(), or at least using HID0_INIT to do invalidation and lock clearing? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
On Fri, 16 Apr 2010 20:06:02 +0300 Michael Zaidman wrote: > On Fri, Apr 16, 2010 at 1:36 AM, Kim Phillips > wrote: > > before, MPC8349ITX boots u-boot in 4.3sec: > [snip] > > after, MPC8349ITX boots u-boot in 3.0sec: > > Thanks for the good news! Memory POST test on my board with icach > disabled was lasting for hours until I enabled icach locally before > and disabled it after time consuming tests. > > BTW is there any reason that you enable icach in board specific rather > than in common code? not really, was just following the existing HID0-setting paradigm - I presume the paradigm came about to allow different cpu/board combinations to enable/disable different HID bits. Does that not sound valid to you? Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] MX: Added Freescale Power Management Driver
Magnus Lilja wrote: > Hi > Hi Magnus, > On 04/19/2010 09:56 AM, Stefano Babic wrote: >> The patch add supports for the Freescale's Power >> Management Controller (known as Atlas) used together with i.MX31/51 >> processors. It was tested with a MC13783 (MX31) and >> MC13892 (MX51). > > You should try and compile all i.MX31 boards with your patches. I tried > i.MX31 Litekit and it failed: > mxc_spi.c: In function 'spi_setup_slave': > mxc_spi.c:406: error: 'ctrl_reg' undeclared (first use in this function) > mxc_spi.c:406: error: (Each undeclared identifier is reported only once > mxc_spi.c:406: error: for each function it appears in.) > > I applied your patches on top of the u-boot-imx-tree. Thanks for testing, I see. I will check with all MX.31 boards and I will resubmit an updated version of the patches soon. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] tsec: Wait for both RX and TX to stop
When gracefully stopping the controller, the driver was continuing if *either* RX or TX had stopped. We need to wait for both, or the controller could get into an invalid state. Signed-off-by: Andy Fleming --- drivers/net/tsec.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index fd49eff..3e4c3bd 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1082,7 +1082,8 @@ static void tsec_halt(struct eth_device *dev) regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); - while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ; + while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)) + != (IEVENT_GRSC | IEVENT_GTSC)) ; regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); -- 1.6.5.2.g6ff9a ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] MX: Added Freescale Power Management Driver
Hi On 04/19/2010 09:56 AM, Stefano Babic wrote: > The patch add supports for the Freescale's Power > Management Controller (known as Atlas) used together with i.MX31/51 > processors. It was tested with a MC13783 (MX31) and > MC13892 (MX51). You should try and compile all i.MX31 boards with your patches. I tried i.MX31 Litekit and it failed: mxc_spi.c: In function 'spi_setup_slave': mxc_spi.c:406: error: 'ctrl_reg' undeclared (first use in this function) mxc_spi.c:406: error: (Each undeclared identifier is reported only once mxc_spi.c:406: error: for each function it appears in.) I applied your patches on top of the u-boot-imx-tree. Regards, Magnus Lilja ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Porting U-Boot on MIPS Au1x00 Family
Hi All, i have a RMI Alchemy Au1350 Board which has 1MB NOR Flash, 512MB SDRAM and 4GB moniNAND. i am customizing the present u-boot board source code available in u-boot. I need information regarding the porting U-boot on MIPS as i need to change lot of things here. i am using BDI3000 for programming and debugging purpose. If i just customize the available config file Au1x00.h is enough or i need to do some other changes too. please let me know the more information regarding booting from NOR Flash, i dint find SDRAM initialization and how to enable eMMC (moviNAND) support in U-boot. what all the changes i need to do for u-boot to boot like UART, NOR, SDRAM etc. Even i need to build Linux kernel for the same. i am using ELDK 4.1 for MIPS. U-boot is 1.2.0. With Thanks and Regards, Gurumurthy Gowdar Hyundai - Mobis Senior Software Engineer - Software Development Centre - Hyderabad INDIA ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC] PPC: post_word_{load/store} - eliminate redundant code
Hi All,
In order to eliminate redundant code for powerPC architecture when
defining post_word_{load/store} routines I suggest moving them into
the arch/ppc/lib/commproc.c file rather than adding them to every
arch/ppc/cpu/.
Also, defining them with weak attribute will permit overriding them
for particular board or CPU.
I'll send the patch later, of course if no one has any objections
against this solution.
Regards,
Michael
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Re: [U-Boot] NAND bootloader, SPL<->NUB offset for large page NAND
On Fri, 16 Apr 2010 23:37:42 +0200, Scott Wood wrote: > We do use the remaining 124 KiB for the payload -- see e.g. > MPC8536DS.h. We > just set CONFIG_SYS_NAND_U_BOOT_OFFS to zero, and > CONFIG_SYS_NAND_U_BOOT_START to 4KiB after the destination. The SPL > will be > loaded twice, but who cares? Thanks a lot, that really helped me. -- Peter Vollmer Innominate Security Technologies AG Berlin / Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 1/3] ARM1176: Coexist with other ARM1176 platforms
The current ARM1176 CPU specific code is too specific to the SMDK6400 architecture. The following changes were necessary prerequisites for the addition of other SoCs based on ARM1176. Existing board's (SMDK6400) configuration has been modified to keep behavior unchanged despite these changes. 1. Peripheral port remap configurability The earlier code had hardcoded remap values specific to s3c64xx in start.S. This change makes the peripheral port remap addresses and sizes configurable. 2. Skip low level initialization Ability to skip low level initialization if necessary. Many other platforms have a similar capability, and this is quite useful during debug/bring-up. 3. U-Boot code relocation support Most architectures allow u-boot code to run initially at a different address (possibly in NOR) and then get relocated to its final resting place in RAM. Added support for this capability in ARM1176 architecture. 4. Disable TCM if necessary If a ROM based bootloader happened to have initialized TCM, we disable it here to keep things sane. 5. Remove unnecessary SoC specific includes ARM1176 code does not really need this SoC specific include. The presence of this include prevents builds on other ARM1176 archs. 6. ARM926 style MMU disable when !CONFIG_ENABLE_MMU The original MMU disable code masks out too many bits from the load address when it tries to figure out the physical address of the jump target label. Consequently, it ends up branching to the wrong address after disabling the MMU. Signed-off-by: Cyril Chemparathy --- v5: rebased on master in u-boot-arm.git v4: rebased on next in u-boot-arm.git v3: unchanged from v2 v2: unchanged from v1 arch/arm/cpu/arm1176/cpu.c |3 -- arch/arm/cpu/arm1176/start.S | 62 ++--- include/configs/smdk6400.h |6 3 files changed, 57 insertions(+), 14 deletions(-) diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c index befa0cd..c0fd114 100644 --- a/arch/arm/cpu/arm1176/cpu.c +++ b/arch/arm/cpu/arm1176/cpu.c @@ -33,9 +33,6 @@ #include #include -#ifdef CONFIG_S3C64XX -#include -#endif #include static void cache_flush (void); diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index e2b6c9b..beec574 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -1,5 +1,5 @@ /* - * armboot - Startup Code for S3C6400/ARM1176 CPU-core + * armboot - Startup Code for ARM1176 CPU-core * * Copyright (c) 2007 Samsung Electronics * @@ -35,9 +35,6 @@ #ifdef CONFIG_ENABLE_MMU #include #endif -#ifdef CONFIG_S3C64XX -#include -#endif #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE @@ -147,6 +144,7 @@ reset: * * */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * we do sys-critical inits only at reboot, * not when booting from ram! @@ -172,6 +170,8 @@ cpu_init_crit: bic r0, r0, #0x0087 @ clear bits 7, 2:0 (B--- -CAM) orr r0, r0, #0x0002 @ set bit 2 (A) Align orr r0, r0, #0x1000 @ set bit 12 (I) I-Cache + +#ifdef CONFIG_ENABLE_MMU /* Prepare to disable the MMU */ adr r1, mmu_disable_phys /* We presume we're within the first 1024 bytes */ @@ -189,13 +189,32 @@ mmu_disable: nop nop mov pc, r2 +mmu_disable_phys: +#else + mcr p15, 0, r0, c1, c0, 0 #endif -mmu_disable_phys: -#ifdef CONFIG_S3C64XX +#ifdef CONFIG_DISABLE_TCM + /* +* Disable the TCMs +*/ + mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ + cmp r0, #0 + beq skip_tcmdisable + mov r1, #0 + mov r2, #1 + tst r0, r2 + mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ + tst r0, r2, LSL #16 + mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ +skip_tcmdisable: +#endif +#endif + +#ifdef CONFIG_PERIPORT_REMAP /* Peri port setup */ - ldr r0, =0x7000 - orr r0, r0, #0x13 + ldr r0, =CONFIG_PERIPORT_BASE + orr r0, r0, #CONFIG_PERIPORT_SIZE mcr p15,0,r0,c15,c2,4 @ 256M (0x7000 - 0x7fff) #endif @@ -203,8 +222,27 @@ mmu_disable_phys: * Go setup Memory and board specific bits prior to relocation. */ bl lowlevel_init /* go setup pll,mux,memory */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ +
[U-Boot] [PATCH v5 0/3] TI: tnetv107x patch series
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This patch series generalizes current ARM1176 code to allow for the addition of new ARM1176 SOCs. The remaining patches in this series add arch and board support. Cyril Chemparathy (3): ARM1176: Coexist with other ARM1176 platforms ARM1176: TI: TNETV107X soc initial support TI: TNETV107X EVM initial support MAINTAINERS |4 + MAKEALL |1 + Makefile|3 + arch/arm/cpu/arm1176/cpu.c |3 - arch/arm/cpu/arm1176/start.S| 62 +++- arch/arm/cpu/arm1176/tnetv107x/Makefile | 44 ++ arch/arm/cpu/arm1176/tnetv107x/aemif.c | 151 +++ arch/arm/cpu/arm1176/tnetv107x/clock.c | 542 +++ arch/arm/cpu/arm1176/tnetv107x/init.c | 41 ++ arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 25 + arch/arm/cpu/arm1176/tnetv107x/mux.c| 463 +++ arch/arm/cpu/arm1176/tnetv107x/timer.c | 125 ++ arch/arm/cpu/arm1176/tnetv107x/wdt.c| 172 +++ arch/arm/include/asm/arch-tnetv107x/clock.h | 50 ++ arch/arm/include/asm/arch-tnetv107x/emif_defs.h |1 + arch/arm/include/asm/arch-tnetv107x/hardware.h | 184 arch/arm/include/asm/arch-tnetv107x/mux.h | 307 + arch/arm/include/asm/arch-tnetv107x/nand_defs.h | 38 ++ board/ti/tnetv107xevm/Makefile | 49 ++ board/ti/tnetv107xevm/config.mk | 20 + board/ti/tnetv107xevm/sdb_board.c | 66 +++ include/configs/smdk6400.h |6 + include/configs/tnetv107x_evm.h | 214 + 23 files changed, 2557 insertions(+), 14 deletions(-) create mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile create mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S create mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/wdt.c create mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/emif_defs.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/nand_defs.h create mode 100644 board/ti/tnetv107xevm/Makefile create mode 100644 board/ti/tnetv107xevm/config.mk create mode 100644 board/ti/tnetv107xevm/sdb_board.c create mode 100644 include/configs/tnetv107x_evm.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 3/3] TI: TNETV107X EVM initial support
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a bunch on on-chip integrated peripherals. This patch adds support for the TNETV107X EVM board. Signed-off-by: Cyril Chemparathy --- v5: rebased on master in u-boot-arm.git (unchanged) v4: rebased on next in u-boot-arm.git (unchanged) v3: Added NAND MTDID comment in board config v2: Added maintainers entry v2: Fixed sort order in main makefile v2: Remove board specific linker script v2: Style fixes - multiline comments v2: Replaced clk_get() with clk_get_rate() MAINTAINERS |4 + MAKEALL |1 + Makefile |3 + board/ti/tnetv107xevm/Makefile| 49 + board/ti/tnetv107xevm/config.mk | 20 board/ti/tnetv107xevm/sdb_board.c | 66 +++ include/configs/tnetv107x_evm.h | 214 + 7 files changed, 357 insertions(+), 0 deletions(-) create mode 100644 board/ti/tnetv107xevm/Makefile create mode 100644 board/ti/tnetv107xevm/config.mk create mode 100644 board/ti/tnetv107xevm/sdb_board.c create mode 100644 include/configs/tnetv107x_evm.h diff --git a/MAINTAINERS b/MAINTAINERS index 0e759c9..44369fe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -62,6 +62,10 @@ Oliver Brown gw8260 MPC8260 +Cyril Chemparathy + + tnetv107x_evm tnetv107x + Conn Clark ESTEEM192E MPC8xx diff --git a/MAKEALL b/MAKEALL index b15d407..e10fead 100755 --- a/MAKEALL +++ b/MAKEALL @@ -625,6 +625,7 @@ LIST_ARM11="\ mx31pdk_nand\ qong\ smdk6400\ + tnetv107x_evm \ " # diff --git a/Makefile b/Makefile index 8b4e0b9..92aa3be 100644 --- a/Makefile +++ b/Makefile @@ -3319,6 +3319,9 @@ smdk6400_config : unconfig fi @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk +tnetv107x_evm_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm1176 tnetv107xevm ti tnetv107x + # # i386 # diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile new file mode 100644 index 000..2446c2a --- /dev/null +++ b/board/ti/tnetv107xevm/Makefile @@ -0,0 +1,49 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS += sdb_board.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +.PHONY: all + +all: $(LIB) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +# +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk new file mode 100644 index 000..d24d49a --- /dev/null +++ b/board/ti/tnetv107xevm/config.mk @@ -0,0 +1,20 @@ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +TEXT_BASE = 0x83FC diff --git a/board/ti/tnetv107
[U-Boot] [GIT PULL] Pull request: u-boot-imx
Hi Tom, The following changes since commit 7c33c16f3bf53e563aa57e25e2399d0069a08749: Stefano Babic (1): Moved board specific values in config file are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master John Rigby (1): MX25 print arm clock instead of mpllclk on boot Stefano Babic (8): mkimage: correct spelling error in imximage mx51evk: correct list of possible BOOT_FROM values MX31: add accessor function to get a gpio MX31: add pin definitions for NAND controller MX31: Add support for NAND to QONG board MX31: Support 128MB RAM on QONG module MX31: Add UBI support to QONG module MX31: Removed erroneous board name from QONG arch/arm/cpu/arm926ejs/mx25/generic.c |2 +- arch/arm/include/asm/arch-mx31/mx31-regs.h | 15 +++ arch/arm/include/asm/arch-mx31/mx31.h |5 + board/davedenx/qong/lowlevel_init.S| 130 +--- board/davedenx/qong/qong.c | 95 - board/davedenx/qong/qong_fpga.h|4 +- board/freescale/mx51evk/imximage.cfg |2 +- drivers/gpio/mx31_gpio.c | 15 +++ include/configs/qong.h | 40 - tools/imximage.c |2 +- 10 files changed, 246 insertions(+), 64 deletions(-) Thanks, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-ppc4xx/master
The following changes since commit 2a72e9ed18d2164eb7fe569119342eb631b568da: Stefan Roese (1): ppc4xx: Add option for PPC440SPe ports without old Rev. A support are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Stefan Roese (1): ppc4xx: TLB init file cleanup arch/ppc/include/asm/mmu.h |5 +++ board/amcc/bamboo/init.S| 26 +++--- board/amcc/canyonlands/init.S | 48 +- board/amcc/ebony/init.S | 12 +++--- board/amcc/katmai/init.S| 52 ++-- board/amcc/luan/init.S | 20 +- board/amcc/ocotea/init.S| 12 +++--- board/amcc/redwood/init.S | 26 +++--- board/amcc/sequoia/init.S | 34 +- board/amcc/taishan/init.S | 61 - board/amcc/yosemite/init.S | 69 ++--- board/amcc/yucca/init.S | 58 board/esd/du440/init.S | 30 board/esd/pmc440/init.S | 28 board/gdsys/gdppc440etx/init.S | 16 board/gdsys/intip/init.S| 20 +- board/korat/init.S | 22 ++-- board/lwmon5/init.S | 30 board/netstal/hcu5/init.S | 30 board/pcs440ep/init.S | 65 +-- board/prodrive/alpr/init.S | 71 +++--- board/prodrive/p3p440/init.S| 62 - board/sandburst/karef/init.S| 66 +-- board/sandburst/metrobox/init.S | 66 +-- board/xes/xpedite1000/init.S| 60 25 files changed, 313 insertions(+), 676 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc4xx: TLB init file cleanup
On Wednesday 14 April 2010 13:57:18 Stefan Roese wrote: > This patch adds new macros, with frequently used combinations of the > 4xx TLB access control and storage attibutes. Additionally the 4xx init.S > files are updated to make use of these new macros. Resulting in easier > to read TLB definitions. > > Additionally some init.S files are updated to use the mmu header for the > TLB defines, instead of defining their own macros. Applied to u-boot-ppc4xx/master. Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] mmc command
Hello all, I build u-boot-2009.11.1 for the board AT91SAM9G45ek. I have two questions. 1 - Under the folder board/atmel/, the board at91sam9g45ek is not listed. The closest one is at91sam9m10g45ek. Is it Ok to use that? 2 - I want to try SD card boot on the board. After building u-boot (using at91sam9m10g45ek); i dont see a mmc or mmcinit command. Is there something that I missed while building? Many Thanks. -- Aman. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-boot on Lite5200B Evaluation Board
Ockie van Schalkwyk wrote: > Hi. We recently bought the Freescale Lite5200B Evaluation Board. A CD > which (supposedly) has the u-boot source code accompanied this board, > only it seems to be incomplete, with a great many empty folders and > missing source files. I downloaded u-boot v1.1.6 from Sourceforge, This is really too old... > but that distribution does not seem to support the Lite5200B. I'll > contact Freescale about their incomplete CD, but I just wanted to > find out from the list whether the Lite5200B was ever supported by > the mainstream u-boot distribution and if that support was removed at > some stage, or wether Freescale's port of u-boot was never part the > u-boot distribution? The Lite5200b is supported since a long in the main line. I suggest you to get the last u-boot sources instead of starting with this old obsolete version. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] pm9263 converted to at91 soc access
Signed-off-by: Asen Dimov
---
board/ronetix/pm9263/led.c| 15 ++--
board/ronetix/pm9263/pm9263.c | 195 +
include/configs/pm9263.h | 87 +-
3 files changed, 152 insertions(+), 145 deletions(-)
diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c
index fe1a1d2..4e585a4 100644
--- a/board/ronetix/pm9263/led.c
+++ b/board/ronetix/pm9263/led.c
@@ -26,18 +26,19 @@
#include
#include
#include
-#include
+#include
#include
void coloured_LED_init(void)
{
+ at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
- 1 << AT91SAM9263_ID_PIOCDE);
+ writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer);
- at91_set_gpio_output(CONFIG_RED_LED, 1);
- at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_pio_output(CONFIG_RED_LED, 1);
+ at91_set_pio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_RED_LED, 0);
- at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_pio_value(CONFIG_RED_LED, 0);
+ at91_set_pio_value(CONFIG_GREEN_LED, 1);
}
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 23ea154..c7835de 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -27,13 +27,13 @@
#include
#include
#include
-#include
#include
#include
#include
#include
+#include
+#include
#include
-#include
#include
#include
#include
@@ -55,52 +55,59 @@ DECLARE_GLOBAL_DATA_PTR;
static void pm9263_nand_hw_init(void)
{
unsigned long csa;
+ at91_smc_t *smc= (at91_smc_t *) AT91_SMC0_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- at91_sys_write(AT91_MATRIX_EBI0CSA,
- csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
+ AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
+ AT91_SMC_MODE_DBW_8 |
#endif
- AT91_SMC_TDF_(2));
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void pm9263_macb_hw_init(void)
{
+ at91_pmc_t *pmc= (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pio_t *pio= (at91_pio_t *) AT91_PIO_BASE;
+
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
- at91_set_gpio_output(AT91_PIN_PB27, 1);
- at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
+ at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
+ at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+ writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
@@ -110,19 +117,15 @@ static void pm9263_macb_hw_init(void)
*
* PHY has internal pull-down
*/
- writel(pin_to_mask(AT91_PIN_PC25),
-
[U-Boot] [PATCH v2] at91: define matrix registers bit fields
Signed-off-by: Asen Dimov
---
arch/arm/include/asm/arch-at91/at91_matrix.h | 138 ++
1 files changed, 138 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h
b/arch/arm/include/asm/arch-at91/at91_matrix.h
index 981ec20..f99b1d4 100644
--- a/arch/arm/include/asm/arch-at91/at91_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91_matrix.h
@@ -113,4 +113,142 @@ typedef struct at91_matrix {
#define AT91_MATRIX_CSA_EBI1_CS2A 0x0008
+#if defined CONFIG_AT91SAM9261
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#defineAT91_MATRIX_MCFG_RCB0 (1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#defineAT91_MATRIX_MCFG_RCB1 (1 << 1)
+#endif
+
+/* Undefined Length Burst Type */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x
+#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x0001
+#define AT91_MATRIX_MCFG_ULBT_FOUR 0x0002
+#define AT91_MATRIX_MCFG_ULBT_EIGHT0x0003
+#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x0004
+#endif
+#if defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO0x0005
+#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR0x0006
+#define AT91_MATRIX_MCFG_ULBT_128 0x0007
+#endif
+
+/* Default Master Type */
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x0001
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED0x0002
+
+/* Fixed Index of Default Master */
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
+#defineAT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
+#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
+#defineAT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
+#endif
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#if defined(CONFIG_AT91SAM9G45)
+#defineAT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
+ defined(CONFIG_AT91SAM9263)
+#defineAT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
+#endif
+
+/* Arbitration Type */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
+#defineAT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x
+#defineAT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY0x0100
+#endif
+
+/* Master Remap Control Register */
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9G45)
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#defineAT91_MATRIX_MRCR_RCB0 (1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#defineAT91_MATRIX_MRCR_RCB1 (1 << 1)
+#endif
+#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
+#defineAT91_MATRIX_MRCR_RCB2 0x0004
+#defineAT91_MATRIX_MRCR_RCB3 0x0008
+#defineAT91_MATRIX_MRCR_RCB4 0x0010
+#defineAT91_MATRIX_MRCR_RCB5 0x0020
+#defineAT91_MATRIX_MRCR_RCB6 0x0040
+#defineAT91_MATRIX_MRCR_RCB7 0x0080
+#defineAT91_MATRIX_MRCR_RCB8 0x0100
+#endif
+#if defined(CONFIG_AT91SAM9G45)
+#defineAT91_MATRIX_MRCR_RCB9 0x0200
+#defineAT91_MATRIX_MRCR_RCB10 0x0400
+#defineAT91_MATRIX_MRCR_RCB11 0x0800
+#endif
+
+/* TCM Configuration Register */
+#if defined(CONFIG_AT91SAM9G45)
+/* Size of ITCM enabled memory block */
+#defineAT91_MATRIX_TCMR_ITCM_0 0x
+#defineAT91_MATRIX_TCMR_ITCM_320x0040
+/* Size of DTCM enabled memory block */
+#defineAT91_MATRIX_TCMR_DTCM_0 0x
+#defineAT91_MATRIX_TCMR_DTCM_320x0060
+#defineAT91_MATRIX_TCMR_DTCM_640x0070
+/* Wait state TCM register */
+#defineAT91_MATRIX_TCMR_TCM_NO_WS 0x
+#defineAT91_MATRIX_TCMR_TCM_ONE_WS 0x0800
+#endif
+#if defined(CONFIG_AT91SAM9263)
+/* Size of ITCM enabled memory block */
+#defineAT91_MATRIX_TCMR_ITCM_0 0x
+#defineAT91_MATRIX_TCMR_ITCM_160x0005
+#defineAT91_MATRIX_TCMR_ITCM_320x0006
+/* Size of DTCM enabled memory block */
+#defineAT91_MATRIX_TCMR_DTCM_0 0x
+#defineAT91_MATRIX_TCMR_DTCM_160x0050
+#defineAT91_MATRIX_TCMR_DTCM_320x0060
+#endif
+#if defined(CONFIG_AT91SAM9261)
+/* Size of ITCM enabled memory block */
+#defineAT91_MATRIX_TCMR_ITCM_0 0x
+#defineAT91_MATRIX_TCMR_ITCM_160x0005
+#defineAT91_MATRIX_TCMR_ITCM_320x0006
+#defineAT91_MATRIX_TCMR_ITCM_640x0007
+/* Size of DTCM enabled memory block */
+#defineAT91_MATRIX_TCMR_DTCM_0 0x
+#define
Re: [U-Boot] tlbentry for U3 bit
Hi Ronny, On Monday 19 April 2010 12:42:29 Ronny D wrote: > I am using ppc440 based board. I have > added one tlbentry in init.S for memctrl register with U3 bit enable. > > When I check the tlb entry through > BDI I found that U3 bit is disabled. > > I have done the same thing using > change_tlb then I have seen U3 bit enabled through BDI. > > Please let me know > > Is there any limitation of initS > for setting tlbenty with U3 bit enable? Take a look at the "tlbentry" macro (arch/ppc/include/mmu.h). As you can see, the TLB2 macro does not allow changing any of the Ux bits: #define tlbentry(epn,sz,rpn,erpn,attr)\ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) #define TLB2(a) ((a) & 0x0fbf) So you need to change TLB2 if you need to set those Ux bits. BTW: The PPC440 users manual mentions that the U3 storage attribute has no effect on PPC440. So I'm wondering what you are trying to achieve by setting this bit. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: off...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] U-boot on Lite5200B Evaluation Board
Hi. We recently bought the Freescale Lite5200B Evaluation Board. A CD which (supposedly) has the u-boot source code accompanied this board, only it seems to be incomplete, with a great many empty folders and missing source files. I downloaded u-boot v1.1.6 from Sourceforge, but that distribution does not seem to support the Lite5200B. I'll contact Freescale about their incomplete CD, but I just wanted to find out from the list whether the Lite5200B was ever supported by the mainstream u-boot distribution and if that support was removed at some stage, or wether Freescale's port of u-boot was never part the u-boot distribution? Thank you. Ockie van Schalkwyk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] EABI 4.2
Hi Tom, > Wolfgang Denk wrote: >> Dear Tom, >> >> In message <20100317084833.364b2...@marrow.netinsight.se> Simon Kagstrom >> wrote: >>> (Sorry if this has already been taken up, I've not been following the >>> discussion closely) >>> >>> On Thu, 11 Mar 2010 11:11:09 +0100 >>> "Martin Krause" wrote: >>> >> Does this mean, my toolchain is broken? I use ELDK4.2 for ARM. > I belive so, how many bytes is in dirent.namelen? alloca can not I compiled the original code with VLA with ELDK4.1 and there everything works. And also the '__builtin_alloca' Version works with ELDK4.1. >>> I had a similar problem a few months ago, which turned out to be a >>> stack alignment issue: >>> >>> http://www.mail-archive.com/u-boot@lists.denx.de/msg23202.html >>> >>> the behavior was pretty similar, with code built with some compilers >>> working (by chance) and some others breaking. >>> >>> (The patch above is in U-boot since november something I think) >> >> Is there any chance to have this fixed for all ARM variants during >> this release cycle? >> > > Yes. I will take this up. > Please send me some instruction on how to get just the eldk4.2 toolchain. ELDK4.2 is "atomic", i.e. you have to do a regular install to get the toolchain[1]. Cheers Detlev [1] http://www.denx.de/wiki/view/DULG/ELDKAvailability -- The proprietary-Unix players proved so ponderous, so blind, and so inept at marketing that Microsoft was able to grab away a large part of their market with the shockingly inferior technology of its Windows operating system. -- "A Brief History of Hackerdom" by Eric Steven Raymond -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: d...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request - u-boot-microblaze
Hi Wolfgang, please pull the following changes. Thanks, Michal The following changes since commit 2a72e9ed18d2164eb7fe569119342eb631b568da: Stefan Roese (1): ppc4xx: Add option for PPC440SPe ports without old Rev. A support are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master Arun Bhanu (1): microblaze: Add FDT support Michal Simek (9): microblaze: Fix irq.S code microblaze: Move timer initialization to board.c microblaze: Move FSL initialization to board.c microblaze: Fix interrupt handler code microblaze: Change cache report messages microblaze: Change initialization sequence microblaze: Support system with WB cache microblaze: Flush cache before jumping to kernel microblaze: Consolidate cache code arch/microblaze/cpu/cache.c| 28 +++ arch/microblaze/cpu/interrupts.c | 41 ++ arch/microblaze/cpu/irq.S | 182 +++- arch/microblaze/cpu/timer.c|3 +- arch/microblaze/lib/Makefile |1 - arch/microblaze/lib/board.c| 31 +++- arch/microblaze/lib/bootm.c| 47 +- arch/microblaze/lib/cache.c| 43 - .../xilinx/microblaze-generic/microblaze-generic.c |7 +- 9 files changed, 174 insertions(+), 209 deletions(-) delete mode 100644 arch/microblaze/lib/cache.c -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] tlbentry for U3 bit
I am using ppc440 based board. I have added one tlbentry in init.S for memctrl register with U3 bit enable. When I check the tlb entry through BDI I found that U3 bit is disabled. I have done the same thing using change_tlb then I have seen U3 bit enabled through BDI. Please let me know Is there any limitation of init.S for setting tlbenty with U3 bit enable? -Ronny Send free SMS to your Friends on Mobile from your Yahoo! Messenger. Download Now! http://messenger.yahoo.com/download.php___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request u-boot-marvell.git
Hi Tom Pls pull the following The following changes since commit 07739bcef5da07cc4a4edef8b91014ccc332eda3: Stefano Babic (1): Moved board specific values in config file are available in the git repository at: http://git.denx.de/u-boot/u-boot-marvell.git master branch Frans Meulenbroeks (2): configs/sheevaplug: added a few additional commands configs/openrd_base.h: reordered macros Siddarth Gore (1): Marvell GuruPlug Board Support MAINTAINERS |4 + MAKEALL |1 + Makefile|3 + board/Marvell/guruplug/Makefile | 51 + board/Marvell/guruplug/config.mk| 27 + board/Marvell/guruplug/guruplug.c | 167 + board/Marvell/guruplug/guruplug.h | 39 +++ board/Marvell/guruplug/kwbimage.cfg | 162 include/configs/guruplug.h | 198 +++ include/configs/openrd_base.h |4 +- include/configs/sheevaplug.h| 27 - 11 files changed, 676 insertions(+), 7 deletions(-) create mode 100644 board/Marvell/guruplug/Makefile create mode 100644 board/Marvell/guruplug/config.mk create mode 100644 board/Marvell/guruplug/guruplug.c create mode 100644 board/Marvell/guruplug/guruplug.h create mode 100644 board/Marvell/guruplug/kwbimage.cfg create mode 100644 include/configs/guruplug.h Regards.. Prafulla . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] at91: define matrix registers bit fields
Signed-off-by: Asen Dimov
---
arch/arm/include/asm/arch-at91/at91_matrix.h | 138 ++
1 files changed, 138 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h
b/arch/arm/include/asm/arch-at91/at91_matrix.h
index 981ec20..60fd75b 100644
--- a/arch/arm/include/asm/arch-at91/at91_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91_matrix.h
@@ -113,4 +113,142 @@ typedef struct at91_matrix {
#define AT91_MATRIX_CSA_EBI1_CS2A 0x0008
+#if defined(CONFIG_AT91SAM9261)
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#defineAT91_MATRIX_MCFG_RCB0 (1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#defineAT91_MATRIX_MCFG_RCB1 (1 << 1)
+#endif
+
+/* Undefined Length Burst Type */
+#if defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x
+#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x0001
+#define AT91_MATRIX_MCFG_ULBT_FOUR 0x0002
+#define AT91_MATRIX_MCFG_ULBT_EIGHT0x0003
+#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x0004
+#endif
+#if defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO0x0005
+#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR0x0006
+#define AT91_MATRIX_MCFG_ULBT_128 0x0007
+#endif
+
+/* Default Master Type */
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x0001
+#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED0x0002
+
+/* Fixed Index of Default Master */
+#if defiled(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263)
+#defineAT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
+#elif defiled(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
+#defineAT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
+#endif
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#if defiled(CONFIG_AT91SAM9G45)
+#defineAT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
+#elif defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9G45)
+#defineAT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
+#endif
+
+/* Arbitration Type */
+#if defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
+#defineAT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x
+#defineAT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY0x0100
+#endif
+
+/* Master Remap Control Register */
+#elif defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
+ defined(CONFIG_AT91SAM9G45)
+/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#defineAT91_MATRIX_MRCR_RCB0 (1 << 0)
+/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#defineAT91_MATRIX_MRCR_RCB1 (1 << 1)
+#endif
+#if defiled(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45)
+#defineAT91_MATRIX_MRCR_RCB2 0x0004
+#defineAT91_MATRIX_MRCR_RCB3 0x0008
+#defineAT91_MATRIX_MRCR_RCB4 0x0010
+#defineAT91_MATRIX_MRCR_RCB5 0x0020
+#defineAT91_MATRIX_MRCR_RCB6 0x0040
+#defineAT91_MATRIX_MRCR_RCB7 0x0080
+#defineAT91_MATRIX_MRCR_RCB8 0x0100
+#endif
+#if defiled(CONFIG_AT91SAM9G45)
+#defineAT91_MATRIX_MRCR_RCB9 0x0200
+#defineAT91_MATRIX_MRCR_RCB10 0x0400
+#defineAT91_MATRIX_MRCR_RCB11 0x0800
+#endif
+
+/* TCM Configuration Register */
+#if defiled(CONFIG_AT91SAM9G45)
+/* Size of ITCM enabled memory block */
+#defineAT91_MATRIX_TCMR_ITCM_0 0x
+#defineAT91_MATRIX_TCMR_ITCM_320x0040
+/* Size of DTCM enabled memory block */
+#defineAT91_MATRIX_TCMR_DTCM_0 0x
+#defineAT91_MATRIX_TCMR_DTCM_320x0060
+#defineAT91_MATRIX_TCMR_DTCM_640x0070
+/* Wait state TCM register */
+#defineAT91_MATRIX_TCMR_TCM_NO_WS 0x
+#defineAT91_MATRIX_TCMR_TCM_ONE_WS 0x0800
+#endif
+#if defiled(CONFIG_AT91SAM9263)
+/* Size of ITCM enabled memory block */
+#defineAT91_MATRIX_TCMR_ITCM_0 0x
+#defineAT91_MATRIX_TCMR_ITCM_160x0005
+#defineAT91_MATRIX_TCMR_ITCM_320x0006
+/* Size of DTCM enabled memory block */
+#defineAT91_MATRIX_TCMR_DTCM_0 0x
+#defineAT91_MATRIX_TCMR_DTCM_160x0050
+#defineAT91_MATRIX_TCMR_DTCM_320x0060
+#endif
+#if defiled(CONFIG_AT91SAM9261)
+/* Size of ITCM enabled memory block */
+#defineAT91_MATRIX_TCMR_ITCM_0 0x
+#defineAT91_MATRIX_TCMR_ITCM_160x0005
+#defineAT91_MATRIX_TCMR_ITCM_320x0006
+#defineAT91_MATRIX_TCMR_ITCM_640x0007
+/* Size of DTCM enabled memory block */
+#defineAT91_MATRIX_TCMR_DTCM_0 0x
+#define
Re: [U-Boot] [PATCH] KGDB set / remove breakpoints
Thanks for the review, Mike. >> Please note, after applying this patch, those architectures, which >> already enabled KGDB support, have to create a new asm/kgdb.h and >> define the length of the break instruction (BREAK_INSTR_SIZE) in that >> file. > > i dont think breaking build is a good idea. i would have the code simply > disable itself if BREAK_INSTR_SIZE isnt set. That's why I used ifndef in the previous patch, and set BREAK_INSTR_SIZE to 4 if it isn't set, but I thought you prefer "an undefined size should be used as a tip that the arch doesnt yet support break points"? In Linux kgdb code, there is an arch independent header file include/linux/kgdb.h, which includes arch dependent header asm/kgdb.h. I am trying to include this concept here, unfortunately current u-boot code only has linux/kgdb.h, if we want to define arch specific code in asm/kgdb.h, we may need to include asm/kgdb.h from linux/kgdb.h, so it looks to me it will definitely break other arch, do you have any suggestion for that? Best Regards, Tonny ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
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[U-Boot] [PATCH V2 6/6] Add SPI support to mx51evk board
The patch adds SPI devices to the mx51evk board.
The MC13892 chip (PMIC) is supported.
Signed-off-by: Stefano Babic
---
Version 2 of the patch is rearranged due to changes in the
mxc_spi driver. Other changes:
Comments by Tom Rix:
- Atmel SPI flash is not supported - removed
- Removed unneded define inside C file
- Replaced all hard-coded values with an or-ing
of bit
board/freescale/mx51evk/mx51evk.c | 139 +
include/configs/mx51evk.h | 15
2 files changed, 154 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx51evk/mx51evk.c
b/board/freescale/mx51evk/mx51evk.c
index f0b7abc..e9f01f6 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -27,9 +27,12 @@
#include
#include
#include
+#include
#include
#include
#include
+#include
+#include
#include "mx51evk.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -147,6 +150,130 @@ static void setup_iomux_fec(void)
mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
}
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+ /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
+ mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
+
+ /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
+
+ /* de-select SS1 of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
+
+ /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
+
+ /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
+
+ /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
+}
+#endif
+
+static void power_init(void)
+{
+ unsigned int val;
+ unsigned int reg;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+ /* Write needed to Power Gate 2 register */
+ val = pmic_reg_read(REG_POWER_MISC);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(REG_POWER_MISC, val);
+
+ /* Write needed to update Charger 0 */
+ pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 | VCHRG2 |
+ ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | ICHRGTR0 |
+ OVCTRL1 | UCHEN | CHRGLEDEN | CYCLB);
+
+ /* power up the system first */
+ pmic_reg_write(REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ val = pmic_reg_read(REG_SW_0);
+ val = (val & (~0x1F)) | 0x14;
+ pmic_reg_write(REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ val = pmic_reg_read(REG_SW_1);
+ val = (val & (~0x1F)) | 0x1A;
+ pmic_reg_write(REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ val = pmic_reg_read(REG_SW_2);
+ val = (val & (~0x1F)) | 0x1A;
+ pmic_reg_write(REG_SW_2, val);
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, &mxc_ccm->cacrr);
+
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ val = pmic_reg_read(REG_SW_4);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg_read(REG_SW_5);
+ val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+ pmic_reg_write(REG_SW_5, val);
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+ val = pmic_reg_read(REG_SETTING_0);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+ pmic_reg_write(REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ val = pmic_reg_read(REG_SETTING_1);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+ pmic_reg_write(REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(REG_MODE_1, val);
+ udelay(200);
+
+ reg = readl(GPIO2_BASE_AD
[U-Boot] [PATCH V2 4/6] SPI: added support for MX51 to mxc_spi
This patch add SPI support for the MX51 processor.
Signed-off-by: Stefano Babic
---
This is the second version to get support for MX51 in the driver.
As reported by Tom Rix, the previous patch broke several MX31 boards
and mixed supporting the MX51 processor with fixing some issues.
This patch adds only support for the MX51 processor and postpone
(if required) supporting not-word aligned buffers to a later patch.
Other changes I can summarize:
Comments from Tom Rix:
- do no make common definition of certain registers
- consistency inside code
Comments from Liu Hui:
- most comments drop out because are related to fix
not word aligned buffers.
- added CONFIG_MX51 to protect only MX51 related code
drivers/spi/mxc_spi.c | 231 -
1 files changed, 210 insertions(+), 21 deletions(-)
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 3a45200..65f43ad 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -31,7 +31,7 @@
#error "i.MX27 CSPI not supported due to drastic differences in register
definisions" \
"See linux mxc_spi driver from Freescale for details."
-#else
+#elif defined(CONFIG_MX31)
#include
@@ -56,6 +56,9 @@
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC(1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS 0x1f
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
@@ -65,12 +68,63 @@ static unsigned long spi_bases[] = {
0x53f84000,
};
+#define OUTMX31_GPIO_DIRECTION_OUT
+#define mxc_gpio_direction mx31_gpio_direction
+#define mxc_gpio_set mx31_gpio_set
+#elif defined(CONFIG_MX51)
+#include
+#include
+
+#define MXC_CSPIRXDATA 0x00
+#define MXC_CSPITXDATA 0x04
+#define MXC_CSPICTRL 0x08
+#define MXC_CSPICON0x0C
+#define MXC_CSPIINT0x10
+#define MXC_CSPIDMA0x14
+#define MXC_CSPISTAT 0x18
+#define MXC_CSPIPERIOD 0x1C
+#define MXC_CSPIRESET 0x00
+#define MXC_CSPICTRL_EN(1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC(1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL4
+#define MXC_CSPICON_PHA0
+#define MXC_CSPICON_SSPOL 12
+
+static unsigned long spi_bases[] = {
+ CSPI1_BASE_ADDR,
+ CSPI2_BASE_ADDR,
+ CSPI3_BASE_ADDR,
+};
+#define mxc_gpio_direction(gpio, dir) (0)
+#define mxc_gpio_set(gpio, value) {}
+#define OUT1
+#else
+#error "Unsupported architecture"
#endif
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
u32 ctrl_reg;
+#if defined(CONFIG_MX51)
+ u32 cfg_reg;
+#endif
int gpio;
};
@@ -89,34 +143,161 @@ static inline void reg_write(unsigned long addr, u32 val)
*(volatile unsigned long*)addr = val;
}
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ if (mxcs->gpio > 0)
+ mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ if (mxcs->gpio > 0)
+ mxc_gpio_set(mxcs->gpio,
+ !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+}
+
+#ifdef CONFIG_MX51
+static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
+ s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
+ u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+
+ if (max_hz == 0) {
+ printf("Error: desired clock is 0\n");
+ return -1;
+ }
+
+ reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
+
+ /* Reset spi */
+ reg_write(mxcs->base + MXC_CSPICTRL, 0);
+ reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
+
+ /*
+* The following computation is taken directly from Freescale's code.
+*/
+ if (clk_src > max_hz) {
+
[U-Boot] [PATCH 5/6] MX: Added definition file for MC13892
The MC13892 is a Power Controller used with processors of the family MX.51. The file adds definitions to be used to setup the internal registers via SPI. Signed-off-by: Stefano Babic --- include/mc13892.h | 160 + 1 files changed, 160 insertions(+), 0 deletions(-) create mode 100644 include/mc13892.h diff --git a/include/mc13892.h b/include/mc13892.h new file mode 100644 index 000..b291757 --- /dev/null +++ b/include/mc13892.h @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sba...@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __MC13892_H__ +#define __MC13892_H__ + +/* REG_CHARGE */ + +#define VCHRG0 0 +#define VCHRG1 (1 << 1) +#define VCHRG2 (1 << 2) +#define ICHRG0 (1 << 3) +#define ICHRG1 (1 << 4) +#define ICHRG2 (1 << 5) +#define ICHRG3 (1 << 6) +#define ICHRGTR0 (1 << 7) +#define ICHRGTR1 (1 << 8) +#define ICHRGTR2 (1 << 9) +#define FETOVRD(1 << 10) +#define FETCTRL(1 << 11) +#define RVRSMODE (1 << 13) +#define OVCTRL0(1 << 15) +#define OVCTRL1(1 << 16) +#define UCHEN (1 << 17) +#define CHRGLEDEN (1 << 18) +#define CHRGRAWPDEN(1 << 19) +#define CHGRESTART (1 << 20) +#define CHGAUTOB (1 << 21) +#define CYCLB (1 << 22) +#define CHGAUTOVIB (1 << 23) + +/* REG_SETTING_0/1 */ +#define VO_1_20V 0 +#define VO_1_30V 1 +#define VO_1_50V 2 +#define VO_1_80V 3 +#define VO_1_10V 4 +#define VO_2_00V 5 +#define VO_2_77V 6 +#define VO_2_40V 7 + +#define VIOL 2 +#define VDIG 4 +#define VGEN 6 + +/* SWxMode for Normal/Standby Mode */ +#define SWMODE_OFF_OFF 0 +#define SWMODE_PWM_OFF 1 +#define SWMODE_PWMPS_OFF 2 +#define SWMODE_PFM_OFF 3 +#define SWMODE_AUTO_OFF4 +#define SWMODE_PWM_PWM 5 +#define SWMODE_PWM_AUTO6 +#define SWMODE_AUTO_AUTO 8 +#define SWMODE_PWM_PWMPS 9 +#define SWMODE_PWMS_PWMPS 10 +#define SWMODE_PWMS_AUTO 11 +#define SWMODE_AUTO_PFM12 +#define SWMODE_PWM_PFM 13 +#define SWMODE_PWMS_PFM14 +#define SWMODE_PFM_PFM 15 +#define SWMODE_MASK0x0F + +#define SWMODE1_SHIFT 0 +#define SWMODE2_SHIFT 10 +#define SWMODE3_SHIFT 0 +#define SWMODE4_SHIFT 8 + +/* Fields in REG_SETTING_1 */ +#define VVIDEO_2_7 (0 << 2) +#define VVIDEO_2_775 (1 << 2) +#define VVIDEO_2_5 (2 << 2) +#define VVIDEO_2_6 (3 << 2) +#define VVIDEO_MASK(3 << 2) +#define VAUDIO_2_3 (0 << 4) +#define VAUDIO_2_5 (1 << 4) +#define VAUDIO_2_775 (2 << 4) +#define VAUDIO_3_0 (3 << 4) +#define VAUDIO_MASK(3 << 4) +#define VSD_1_8(0 << 6) +#define VSD_2_0(1 << 6) +#define VSD_2_6(2 << 6) +#define VSD_2_7(3 << 6) +#define VSD_2_8(4 << 6) +#define VSD_2_9(5 << 6) +#define VSD_3_0(6 << 6) +#define VSD_3_15 (7 << 6) +#define VSD_MASK (7 << 6) +#define VGEN1_1_2 0 +#define VGEN1_1_5 1 +#define VGEN1_2_7752 +#define VGEN1_3_15 3 +#define VGEN1_MASK 3 +#define VGEN2_1_2 (0 << 6) +#define VGEN2_1_5 (1 << 6) +#define VGEN2_1_6 (2 << 6) +#define VGEN2_1_8 (3 << 6) +#define VGEN2_2_7 (4 << 6) +#define VGEN2_2_8 (5 << 6) +#define VGEN2_3_0 (6 << 6) +#define VGEN2_3_15 (7 << 6) +#define VGEN2_MASK (7 << 6) + +/* Fields in REG_SETTING_1 */ +#define VGEN3_1_8 (0 << 14) +#define VGEN3_2_9 (1 << 14) +#define VGEN3_MASK (1 << 14) +#define VDIG_1_05 (0 << 4) +#define VDIG_1_25 (1 << 4) +#define VDIG_1_65 (2 << 4) +#define VDIG_1_8 (3 << 4) +#define VDIG_MASK (3 << 4) +#define VCAM_2_5 (0 << 16) +#define VCAM_2_6 (1 << 16) +#define VCAM_2_75 (2 << 16) +#define VCAM_3_0 (3 << 16) +#define VCAM_MASK (3 << 16
[U-Boot] [PATCH 3/6] MX31: Add support for PMIC to the QONG module
Add support for the PMIC (MC13783) controller
and enables charging of the RTC battery.
Signed-off-by: Stefano Babic
---
board/davedenx/qong/qong.c | 20
include/configs/qong.h | 14 ++
2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index eb9218e..781333b 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include "qong_fpga.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -128,6 +129,13 @@ int board_init (void)
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+ /* setup pins for SPI (pmic) */
+ mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+ mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+ mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+ mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+ mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_QONG;
gd->bd->bi_boot_params = (0x8100); /* adress of boot parameters */
@@ -135,6 +143,18 @@ int board_init (void)
return 0;
}
+int board_late_init(void)
+{
+ u32 val;
+
+ /* Enable RTC battery */
+ val = pmic_reg_read(REG_POWER_CTL0);
+ pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
+ pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
+
+ return 0;
+}
+
int checkboard (void)
{
printf("Board: DAVE/DENX Qong\n");
diff --git a/include/configs/qong.h b/include/configs/qong.h
index 178c8e7..1d187d0 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -54,6 +54,17 @@
#define CONFIG_MX31_GPIO
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS 1
+#define CONFIG_DEFAULT_SPI_MODE(SPI_MODE_2 | SPI_CS_HIGH)
+#define CONFIG_RTC_MC13783
+
+#define CONFIG_FSL_PMIC
+#define CONFIG_FSL_PMIC_BUS1
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK10
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
+
/* FPGA */
#define CONFIG_QONG_FPGA 1
#define CONFIG_FPGA_BASE (CS1_BASE)
@@ -87,6 +98,9 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+#define BOARD_LATE_INIT
/*
* You can compile in a MAC address and your custom net settings by using
--
1.6.3.3
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[U-Boot] [PATCH 2/6] MX: RTC13783 uses general function to access PMIC
The RTC is part of the Freescale's PMIC controller.
Use general function to access to PMIC internal registers.
Signed-off-by: Stefano Babic
---
drivers/rtc/mc13783-rtc.c | 72 +---
1 files changed, 15 insertions(+), 57 deletions(-)
diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c
index 416f50d..4e18f80 100644
--- a/drivers/rtc/mc13783-rtc.c
+++ b/drivers/rtc/mc13783-rtc.c
@@ -23,53 +23,30 @@
#include
#include
#include
-
-static struct spi_slave *slave;
+#include
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
- u32 reg;
- int err, tim, i = 0;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 100,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
-
- if (spi_claim_bus(slave))
- return -1;
+ int tim, i = 0;
do {
- reg = 0x2c00;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- if (err)
- return err;
-
- reg = 0x2800;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day1 = pmic_reg_read(REG_RTC_DAY);
+ if (day1 < 0)
+ return -1;
- if (err)
- return err;
+ time = pmic_reg_read(REG_RTC_TIME);
+ if (time < 0)
+ return -1;
- reg = 0x2c00;
- err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day2 = pmic_reg_read(REG_RTC_DAY);
+ if (day2 < 0)
+ return -1;
- if (err)
- return err;
} while (day1 != day2 && i++ < 3);
- spi_release_bus(slave);
-
tim = day1 * 86400 + time;
+
to_tm(tim, rtc);
rtc->tm_yday = 0;
@@ -80,34 +57,15 @@ int rtc_get(struct rtc_time *rtc)
int rtc_set(struct rtc_time *rtc)
{
- u32 time, day, reg;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 100,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
+ u32 time, day;
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
- if (spi_claim_bus(slave))
- return -1;
-
- reg = 0x2c00 | day | 0x8000;
- spi_xfer(slave, 32, (uchar *)®, (uchar *)&day,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- reg = 0x2800 | time | 0x8000;
- spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- spi_release_bus(slave);
+ pmic_reg_write(REG_RTC_DAY, day);
+ pmic_reg_write(REG_RTC_TIME, time);
return 0;
}
--
1.6.3.3
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[U-Boot] [PATCH 1/6] MX: Added Freescale Power Management Driver
The patch add supports for the Freescale's Power
Management Controller (known as Atlas) used together with i.MX31/51
processors. It was tested with a MC13783 (MX31) and
MC13892 (MX51).
Signed-off-by: Stefano Babic
---
This replaces: Added MC13892VK Power Management driver.
As I saw that the same code could be used for both
Power Management controllers MC13873/MC13892, I changed
the name in a more neutral way, as Freescale already did.
Main changes from the first version:
Comments by Tom Rix:
- removed unneeded endianess conversions
- use coherent of accessors function
- hide slave structure inside the driver
to avoid the caller mus always check for
its status
As reported by Tom, the original patches must be combined into a
patchset. It was tested on both processors i-MX31 (QONG) and
i.MX51(mx51evk).
drivers/misc/Makefile |1 +
drivers/misc/fsl_pmic.c | 200 +++
include/fsl_pmic.h | 128 ++
3 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 drivers/misc/fsl_pmic.c
create mode 100644 include/fsl_pmic.h
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f6df60f..96aa331 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
+COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c
new file mode 100644
index 000..87f0aed
--- /dev/null
+++ b/drivers/misc/fsl_pmic.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct spi_slave *slave;
+
+struct spi_slave *pmic_spi_probe(void)
+{
+ return spi_setup_slave(CONFIG_FSL_PMIC_BUS,
+ CONFIG_FSL_PMIC_CS,
+ CONFIG_FSL_PMIC_CLK,
+ CONFIG_FSL_PMIC_MODE);
+}
+
+void pmic_spi_free(struct spi_slave *slave)
+{
+ if (slave)
+ spi_free_slave(slave);
+}
+
+u32 pmic_reg(u32 reg, u32 val, u32 write)
+{
+ u32 pmic_tx, pmic_rx;
+
+ if (!slave) {
+ slave = pmic_spi_probe();
+
+ if (!slave)
+ return -1;
+ }
+
+ if (reg > 63 || write > 1) {
+ printf(" = %d is invalid. Should be less then 63\n",
+ reg);
+ return -1;
+ }
+
+ if (spi_claim_bus(slave))
+ return -1;
+
+ pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FF);
+
+ if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ spi_release_bus(slave);
+ return -1;
+ }
+
+ if (write) {
+ pmic_tx &= ~(1 << 31);
+ if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ spi_release_bus(slave);
+ return -1;
+ }
+ }
+
+ spi_release_bus(slave);
+ return pmic_rx;
+}
+
+void pmic_reg_write(u32 reg, u32 value)
+{
+ pmic_reg(reg, value, 1);
+}
+
+u32 pmic_reg_read(u32 reg)
+{
+ return pmic_reg(reg, 0, 0);
+}
+
+void pmic_show_pmic_info(void)
+{
+ u32 rev_id;
+
+ rev_id = pmic_reg_read(REG_IDENTIFICATION);
+ printf("PMIC ID: 0x%08x [Rev: ", rev_id);
+ switch (rev_id & 0x1F) {
+ case 0x1:
+ puts("1.0");
+ break;
+ case 0x9:
+ puts("1.1");
+ break;
+ case 0xA:
+ puts("1.2");
+ break;
+ case 0x10:
+ puts("2.0");
+ break;
+ case 0x11:
+ puts("2.1");
+ break;
+ case 0x18:
+ puts("3.0");
+ break;
+ case 0x19:
+ puts("3.1");
+ break;
+ case 0x1A:
+ puts("3
[U-Boot] [PATCH] MX51evk: Removed warnings
Changes reflect modifications in the fsl_esdhc driver
(the clk_enable field war removed in the configuration structure).
Signed-off-by: Stefano Babic
---
board/freescale/mx51evk/mx51evk.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx51evk/mx51evk.c
b/board/freescale/mx51evk/mx51evk.c
index e9f01f6..75d642b 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -42,8 +42,8 @@ struct io_board_ctrl *mx51_io_board;
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR, 1, 1},
- {MMC_SDHC2_BASE_ADDR, 1, 1},
+ {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC2_BASE_ADDR, 1},
};
#endif
--
1.6.3.3
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Re: [U-Boot] Modify boot parameters using nandwrite?
On Sun, Apr 18, 2010 at 22:11, Norbert Wegener wrote: > At the U-Boot boot prompt I can change among others the boot parameters. > Is it possible to modify those boot parameters when the Plug has booted > into Linux via e.g. nandwrite and some parameters? > Is there any documentation that I might read? I guess you're looking for the fw_printenv (and fw_setenv sym.link). The code is found under tools/env/ in the U-Boot source tree. Regards, Anders ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
