[U-Boot] [PATCH v2] cpuat91: unbreak ethernet
* the following problems are met :
config was set to use the new driver as a default but
- RMII was not enabled for the new driver
- the new driver didn't compile with RMII enabled
- the new driver initialize a PHY at address O when the PHY of
this board is at 1 thus we get "AT91 EMAC RMII: No PHY present"
* to fix these problems, this patch :
- enable RMII for the new driver
- fix the wrong define used in the at91_emac.c
- allow the config file to set a default phy address (and use
0 as a default as in the actual at91_emac.c driver)
Signed-off-by: Eric Bénard
---
v2 :
fix line lengths
drivers/net/at91_emac.c | 32 ++--
include/configs/cpuat91.h |9 +++--
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index 2399569..cf0a7c0 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -53,6 +53,10 @@
Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
#endif
+#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
+#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
+#endif
+
/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
#if (AT91C_MASTER_CLOCK > 8000)
#define HCLK_DIVAT91_EMAC_CFG_MCLK_64
@@ -198,12 +202,15 @@ static int at91emac_phy_reset(struct eth_device *netdev)
emac = (at91_emac_t *) netdev->iobase;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
- at91emac_write(emac, 0, MII_ADVERTISE, adv);
+ at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_ADVERTISE, adv);
VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
- at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
+ at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
+ (BMCR_ANENABLE | BMCR_ANRESTART));
for (i = 0; i < 10 / 100; i++) {
- at91emac_read(emac, 0, MII_BMSR, &status);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_BMSR, &status);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
@@ -229,13 +236,15 @@ static int at91emac_phy_init(struct eth_device *netdev)
emac = (at91_emac_t *) netdev->iobase;
/* Check if the PHY is up to snuff... */
- at91emac_read(emac, 0, MII_PHYSID1, &phy_id);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_PHYSID1, &phy_id);
if (phy_id == 0x) {
printf("%s: No PHY present\n", netdev->name);
return 1;
}
- at91emac_read(emac, 0, MII_BMSR, &status);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_BMSR, &status);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
@@ -243,7 +252,8 @@ static int at91emac_phy_init(struct eth_device *netdev)
return 2;
for (i = 0; i < 10 / 100; i++) {
- at91emac_read(emac, 0, MII_BMSR, &status);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_BMSR, &status);
if (status & BMSR_LSTATUS)
break;
udelay(100);
@@ -253,8 +263,10 @@ static int at91emac_phy_init(struct eth_device *netdev)
VERBOSEP("%s: link down\n", netdev->name);
return 3;
} else {
- at91emac_read(emac, 0, MII_ADVERTISE, &adv);
- at91emac_read(emac, 0, MII_LPA, &lpa);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_ADVERTISE, &adv);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+ MII_LPA, &lpa);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
@@ -271,7 +283,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
{
unsigned short stat1;
- at91emac_read(emac, 0, MII_BMSR, &stat1);
+ at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
if (!(stat1 & BMSR_LSTATUS))/* link status up? */
return 1;
@@ -372,7 +384,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t
*bd)
value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
HCLK_DIV;
#ifdef CONFIG_RMII
- value |= AT91C_EMAC_RMII;
+ value |= AT91_EMAC_CFG_RMII;
#endif
writel(value, &emac->cfg);
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index b4fda76..049298c 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -131,15 +131,12 @@
(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
#define CONFIG_NET_MULTI 1
-#ifdef CONFIG
[U-Boot] [PATCH v2] at91_emac: Write MAC address automatically
tested on cpuat91.
Signed-off-by: Eric Bénard
---
v2 :
don't check if the MAC address is valid
drivers/net/at91_emac.c | 28
1 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index cf0a7c0..1213a1a 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -360,14 +360,6 @@ static int at91emac_init(struct eth_device *netdev, bd_t
*bd)
writel(1 << AT91_ID_EMAC, &pmc->pcer);
writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
- DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
- cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
- cpu_to_le32(*((u32 *)netdev->enetaddr)));
- writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
- writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
- DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
- readl(&emac->sa2h), readl(&emac->sa2l));
-
/* Init Ethernet buffers */
for (i = 0; i < RBF_FRAMEMAX; i++) {
dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
@@ -468,6 +460,25 @@ static int at91emac_recv(struct eth_device *netdev)
return 0;
}
+static int at91emac_write_hwaddr(struct eth_device *netdev)
+{
+ emac_device *dev;
+ at91_emac_t *emac;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ emac = (at91_emac_t *) netdev->iobase;
+ dev = (emac_device *) netdev->priv;
+
+ writel(1 << AT91_ID_EMAC, &pmc->pcer);
+ DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
+ cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
+ cpu_to_le32(*((u32 *)netdev->enetaddr)));
+ writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
+ writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
+ DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
+ readl(&emac->sa2h), readl(&emac->sa2l));
+ return 0;
+}
+
int at91emac_register(bd_t *bis, unsigned long iobase)
{
emac_device *emac;
@@ -500,6 +511,7 @@ int at91emac_register(bd_t *bis, unsigned long iobase)
dev->halt = at91emac_halt;
dev->send = at91emac_send;
dev->recv = at91emac_recv;
+ dev->write_hwaddr = at91emac_write_hwaddr;
eth_register(dev);
--
1.6.3.3
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Re: [U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu
Dear Ilya Yanok, In message <1277055168-18596-2-git-send-email-ya...@emcraft.com> you wrote: > This patch adds basic support for Freescale MPC8308 CPU. Serial ports, > NOR flash and integrated Ethernet controllers are supported. > PCI Express is also supported. eSDHC, NAND and USB may work but aren't > tested (using ULPI PHY requires additional patch). > > Signed-off-by: Ilya Yanok ... > -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || > defined(CONFIG_MPC8315) > +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || \ > + defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308) Please sort this list. > -#elif defined(CONFIG_MPC8315) > +#elif defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308) Ditto. > -#elif defined(CONFIG_MPC8315) > +#elif defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308) Ditto. ... and so on. > +#if defined(CONFIG_MPC8308) > +#define SCCR_SDHCCM 0x0c00 > +#define SCCR_SDHCCM_SHIFT26 > +#define SCCR_SDHCCM_00x > +#define SCCR_SDHCCM_10x0400 > +#define SCCR_SDHCCM_20x0800 > +#define SCCR_SDHCCM_30x0c00 > +#endif Would it make sense to write this as: And: why do we need the #ifdef? Unused defines should not hurt? #define SCCR_SDHCCM_MASK0x0c00 /* is it a mask? */ #define SCCR_SDHCCM_SHIFT 26 #define SCCR_SDHCCM(arg)((arg)< #define SCCR_USBDRCM 0x00c0 > #define SCCR_USBDRCM_SHIFT 22 > #define SCCR_USBDRCM_0 0x > @@ -757,6 +767,7 @@ > #define SCCR_USBDRCM_2 0x0080 > #define SCCR_USBDRCM_3 0x00c0 Ah, I see you just follow precedent code. If Kim accepts this, I'm fine with it, too. > +#if defined(CONFIG_MPC8315) > #define SCCR_SATA1CM 0x3000 > #define SCCR_SATA1CM_SHIFT 12 > #define SCCR_SATACM 0x3c00 > @@ -765,6 +776,7 @@ > #define SCCR_SATACM_10x1400 > #define SCCR_SATACM_20x2800 > #define SCCR_SATACM_30x3c00 > +#endif Do we need that #ifdef? Ok, the #defines don't apply to the 8308, but do they hurt if they are just there, unused? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The world is no nursery. - Sigmund Freud ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale
Dear Ilya Yanok,
In message <1277055168-18596-3-git-send-email-ya...@emcraft.com> you wrote:
> This patch provides support for MPC8308ERDB development board from
> Freescale with a minimal set of features:
> Dual UART is supported
> NOR flash is supported
> Both TSEC Ethernet controllers are supported
> PCI Express initialization is supported
>
> The following features are enabled in configuration but not fully tested:
> I2C (used to get the board revision)
> I2C-connected RTC
> VSC7385 switch
...
> MAKEALL |1 +
> Makefile |3 +
> board/freescale/mpc8308erdb/Makefile | 52 +++
> board/freescale/mpc8308erdb/config.mk |1 +
> board/freescale/mpc8308erdb/mpc8308erdb.c | 154
> board/freescale/mpc8308erdb/sdram.c | 126 +++
> include/configs/MPC8308ERDB.h | 572
> +
> 7 files changed, 909 insertions(+), 0 deletions(-)
> create mode 100644 board/freescale/mpc8308erdb/Makefile
> create mode 100644 board/freescale/mpc8308erdb/config.mk
> create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
> create mode 100644 board/freescale/mpc8308erdb/sdram.c
> create mode 100644 include/configs/MPC8308ERDB.h
Entry to MAINTAINERS missing.
> diff --git a/Makefile b/Makefile
> index 55bb964..0dc2678 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2233,6 +2233,9 @@ TASREG_config : unconfig
> kmeter1_config: unconfig
> @$(MKCONFIG) kmeter1 powerpc mpc83xx kmeter1 keymile
>
> +MPC8308ERDB_config: unconfig
> + @$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
NAK. Please rebase your code against the "next" branch. We don't
accept any board entries to the top level Makefile any more. Please
add to boards.cfg instead.
> --- /dev/null
> +++ b/board/freescale/mpc8308erdb/mpc8308erdb.c
> @@ -0,0 +1,154 @@
> +/*
> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, ya...@emcraft.com
> + *
> + * Author: Freescale unknown
Maybe "Initial author" ?
> +int board_early_init_f(void)
> +{
> + immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> +
> + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
> + gd->flags |= GD_FLG_SILENT;
What exactly is this good for?
> +/*
> + * Miscellaneous late-boot configurations
> + *
> + * If a VSC7385 microcode image is present, then upload it.
> +*/
> +int misc_init_r(void)
> +{
> + int rc = 0;
Please drop the variable.
> +#ifdef CONFIG_VSC7385_IMAGE
> + if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
> + CONFIG_VSC7385_IMAGE_SIZE)) {
> + puts("Failure uploading VSC7385 microcode.\n");
> + rc = 1;
return 1;
> + }
> +#endif
> +
> + return rc;
return 0;
> +int board_eth_init(bd_t *bis)
> +{
> + cpu_eth_init(bis); /* Initialize TSECs first */
I think it's wrong to ignore the return code here.
> + return pci_eth_init(bis);
> +}
> +
> +
Please remove trailing empty lines.
> +/* Fixed sdram init -- doesn't use serial presence detect.
> + *
> + * This is useful for faster booting in configs where the RAM is unlikely
> + * to be changed, or for things like NAND booting where space is tight.
> + */
> +static long fixed_sdram(void)
> +{
> + immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
> + u32 msize_log2 = __ilog2(msize);
> +
> + out_be32(&im->sysconf.ddrlaw[0].bar,
> + CONFIG_SYS_DDR_SDRAM_BASE & 0xf000);
> + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
> + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
> +
> + /*
> + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
> + * or the DDR2 controller may fail to initialize correctly.
> + */
> + udelay(5);
> +
> + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
> + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
> +
> + /* Currently we use only one CS, so disable the other bank. */
> + out_be32(&im->ddr.cs_config[1], 0);
> +
> + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
> + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
> + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
> + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
> + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
> +
> + if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
> + out_be32(&im->ddr.sdram_cfg,
> + CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
> + } else {
> + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
> + }
> +
> + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
> + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
> + out_be32(&im->ddr.sdram_mode2
Re: [U-Boot] [PATCH 2/2] at91_emac: Write MAC address automatically
Hi Ben,
Le 21/06/2010 07:59, Ben Warren a écrit :
> On 6/15/2010 5:36 AM, Eric Bénard wrote:
>> +
>> +if (netdev->enetaddr != 0) {
>>
> This check's not necessary. The caller checks if the MAC address is
> valid ( a more extensive check than you do here)
OK, fixed patch sent, thanks.
Eric
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Re: [U-Boot] [PATCH] ARM: remove unused ATAG
Hi Wolfgang, Wolfgang Denk wrote on Friday, June 18, 2010 8:18 PM: > Dear Martin, > > In message > <47f3f98010ff784ebee6526eaab078d10635e...@tq-mailsrv.tq-net.de> you > wrote: >> >> If you reference to the trab board, then yes it is still running. But >> on this board a very very old version of U-Boot is running, and I >> don't see, that this would change during the remaining lifetime of >> the board. Thus it's fine by me to break/remove the board support >> from current U-Boot. > > Should we remove the whole trab support, then? If it helps in any way to make U-Boot better (make the code more maintainable, remove some special configuration options, which are only used on trab board, etc.), and no one has objections, then the whole trab board support can be removed. Best Regards, Martin Krasue ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Davinci: SPI performance enhancements
The following restructuring and optimisations increase the SPI
read performance from 1.3MiB/s (on da850) to 2.87MiB/s (on da830):
Remove continual revaluation of driver state from the core of the
copy loop. State can not change during the copy loop, so it is
possible to move these evaluations to before the copy loop.
Cost is more code space as loop variants are required for each set
of possible configurations. The loops are simpler however, so the
extra is only 128bytes on da830 with CONFIG_SPI_HALF_DUPLEX
defined.
Unrolling the first copy loop iteration allows the TX buffer to be
pre-loaded reducing SPI clock starvation.
Unrolling the last copy loop iteration removes testing for the
final loop iteration every time round the loop.
Using the RX buffer empty flag as a transfer throttle allows the
assumption that it is always safe to write to the TX buffer, so
polling of TX buffer full flag can be removed.
Signed-off-by: Nick Thompson
---
da850 and da830 are similar devices. The SPI module is common to
both, but da850 uses DDR and da830 uses SDRAM. The EVM's might
not actually be comparable, but they appear to be at least similar.
The speed was tested with a 8MiB transfer from SPI FLASH using:
sf read 0xc0008000 0 0x80
drivers/spi/davinci_spi.c | 195 +---
1 files changed, 128 insertions(+), 67 deletions(-)
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 08f837b..4518ecb 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -66,7 +66,7 @@ void spi_free_slave(struct spi_slave *slave)
int spi_claim_bus(struct spi_slave *slave)
{
struct davinci_spi_slave *ds = to_davinci_spi(slave);
- unsigned int scalar, data1_reg_val = 0;
+ unsigned int scalar;
/* Enable the SPI hardware */
writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
@@ -93,11 +93,6 @@ int spi_claim_bus(struct spi_slave *slave)
writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
- /* hold cs active at end of transfer until explicitly de-asserted */
- data1_reg_val = (1 << SPIDAT1_CSHOLD_SHIFT) |
- (slave->cs << SPIDAT1_CSNR_SHIFT);
- writel(data1_reg_val, &ds->regs->dat1);
-
/*
* Including a minor delay. No science here. Should be good even with
* no delay
@@ -113,8 +108,7 @@ int spi_claim_bus(struct spi_slave *slave)
writel(0, &ds->regs->lvl);
/* enable SPI */
- writel((readl(&ds->regs->gcr1) |
- SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
+ writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
return 0;
}
@@ -127,14 +121,125 @@ void spi_release_bus(struct spi_slave *slave)
writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
}
+/*
+ * This functions needs to act like a macro to avoid pipeline reloads in the
+ * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
+ * appears to be zero bytes (da830).
+ */
+__attribute__((always_inline))
+static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
+{
+ u32 buf_reg_val;
+
+ /* send out data */
+ writel(data, &ds->regs->dat1);
+
+ /* wait for the data to clock in/out */
+ while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
+ ;
+
+ return buf_reg_val;
+}
+
+static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
+ u8 *rxp, unsigned long flags)
+{
+ struct davinci_spi_slave *ds = to_davinci_spi(slave);
+ unsigned int data1_reg_val;
+
+ /* enable CS hold, CS[n] and clear the data bits */
+ data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
+(slave->cs << SPIDAT1_CSNR_SHIFT));
+
+ /* wait till TXFULL is deasserted */
+ while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
+ ;
+
+ /* preload the TX buffer to avoid clock starvation */
+ writel(data1_reg_val, &ds->regs->dat1);
+
+ /* keep reading 1 byte until only 1 byte left */
+ while ((len--) > 1)
+ *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
+
+ /* clear CS hold when we reach the end */
+ if (flags & SPI_XFER_END)
+ data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
+
+ /* read the last byte */
+ *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
+
+ return 0;
+}
+
+static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
+ const u8 *txp, unsigned long flags)
+{
+ struct davinci_spi_slave *ds = to_davinci_spi(slave);
+ unsigned int data1_reg_val;
+
+ /* enable CS hold and clear the data bits */
+ data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
+(slave->cs << SPIDAT1_CSNR_SHIFT));
+
+ /* wait till TXFULL is deasserted */
+ while (readl(&d
[U-Boot] mpc8343: TSEC1 @ RGMII stopped working
Kim, the 2nd TSEC has stopped working on both U-Boot and Linux on our MPC8343 based system (MVBLM7). Actually I stumbled over this by accident... TSEC0+1 are using an VSC8601 connected via RGMII. Since both Bootloader (U-Boot 2010.3) and OS (Linux 2.6.26.27) are affected I suspect a configuration problem. The PHY is working fine according to LED signalling. mvBL-M7> mii info ->TSEC0 unplugged: PHY 0x10: OUI = 0x01C1, Model = 0x02, Rev = 0x01, 10baseT, HDX ->TSEC1 plugged into GigE Network. PHY 0x11: OUI = 0x01C1, Model = 0x02, Rev = 0x01, 100baseT, FDX PHY 0x1F: OUI = 0x, Model = 0x00, Rev = 0x00, 10baseT, HDX mvBL-M7> set ethact TSEC1 mvBL-M7> bootp Speed: 1000, full duplex Random delay: 603 ms... BOOTP broadcast 1 Any hints where to look ? Have I missed some changes lately ? Regards, André MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] cpuat91: convert to new at91 soc architecture
convert the board to the new soc architecture
update default config
i2c upgrade taken from eb_cpux9k2.h & board/BuS/eb_cpux9k2/cpux9k2.c
Signed-off-by: Eric Bénard
---
v2 : send to Tom Rix's new email
Makefile |2 +-
board/eukrea/cpuat91/cpuat91.c | 53 ---
include/configs/cpuat91.h | 45 +++--
3 files changed, 54 insertions(+), 46 deletions(-)
diff --git a/Makefile b/Makefile
index c26e491..ffc749d 100644
--- a/Makefile
+++ b/Makefile
@@ -2693,7 +2693,7 @@ CPUAT91_RAM_config \
CPUAT91_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
- @$(MKCONFIG) -a cpuat91 arm arm920t cpuat91 eukrea at91rm9200
+ @$(MKCONFIG) -a cpuat91 arm arm920t cpuat91 eukrea at91
csb637_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200
diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c
index 0017962..cd4d42c 100644
--- a/board/eukrea/cpuat91/cpuat91.c
+++ b/board/eukrea/cpuat91/cpuat91.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006 Eukrea Electromatique
+ * (C) Copyright 2006-2010 Eukrea Electromatique
* Eric Benard
* based on at91rm9200dk.c which is :
* (C) Copyright 2002
@@ -27,13 +27,11 @@
#include
#include
-#include
-#include
-#if defined(CONFIG_DRIVER_ETHER)
-#include
-#include
-#endif
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -61,31 +59,7 @@ int dram_init(void)
return 0;
}
-#if defined(CONFIG_DRIVER_ETHER)
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- * at91rm9200_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
-{
- p_phyops->Init = ks8721_initphy;
- p_phyops->IsPhyConnected = ks8721_isphyconnected;
- p_phyops->GetLinkSpeed = ks8721_getlinkspeed;
- p_phyops->AutoNegotiate = ks8721_autonegotiate;
-}
-
-#endif /* CONFIG_CMD_NET */
-#endif /* CONFIG_DRIVER_ETHER */
#ifdef CONFIG_DRIVER_AT91EMAC
-
int board_eth_init(bd_t *bis)
{
int rc = 0;
@@ -93,3 +67,20 @@ int board_eth_init(bd_t *bis)
return rc;
}
#endif
+
+#ifdef CONFIG_SOFT_I2C
+void i2c_init_board(void)
+{
+ u32 pin;
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
+ writel(1 << AT91_ID_PIOA, &pmc->pcer);
+ pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+ writel(pin, &pio->pioa.idr);
+ writel(pin, &pio->pioa.pudr);
+ writel(pin, &pio->pioa.per);
+ writel(pin, &pio->pioa.oer);
+ writel(pin, &pio->pioa.sodr);
+}
+#endif
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 049298c..b012782 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -1,5 +1,5 @@
/*
- * CPUAT91 by (C) Copyright 2006 Eric Benard
+ * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
* e...@eukrea.com
*
* Configuration settings for the CPUAT91 board.
@@ -23,15 +23,12 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_AT91_LEGACY
+#ifndef _CONFIG_CPUAT91_H
+#define _CONFIG_CPUAT91_H
#ifdef CONFIG_CPUAT91_RAM
#define CONFIG_SKIP_LOWLEVEL_INIT 1
#define CONFIG_SKIP_RELOCATE_UBOOT 1
-#define CONFIG_CPUAT91 1
#else
#define CONFIG_BOOTDELAY 1
#endif
@@ -43,6 +40,7 @@
#define CONFIG_ARM920T 1
#define CONFIG_AT91RM9200 1
+#define CONFIG_CPUAT91 1
#undef CONFIG_USE_IRQ
#define USE_920T_MMU 1
@@ -89,16 +87,36 @@
#undef CONFIG_USART0
#undef CONFIG_USART1
-#define CONFIG_HARD_I2C1
+#undef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C1
+#define AT91_PIN_SDA (1<<25)
+#define AT91_PIN_SCL (1<<26)
+
+#define CONFIG_SYS_I2C_INIT_BOARD 1
+#defineCONFIG_SYS_I2C_SPEED5
+#define CONFIG_SYS_I2C_SLAVE 0
+
+#define I2C_INIT i2c_init_board();
+#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
+#define I2C_SDA(bit) \
+ if (bit)\
+ writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
+ else\
+ writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
+#define I2C_SCL(bit) \
+ if (bit)\
+ writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
+ els
[U-Boot] [PATCH v2 2/2] cpuat91: update defaut environement
Signed-off-by: Eric Bénard
---
v2 : send to Tom Rix's new email
include/configs/cpuat91.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index b012782..9ef4523 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -223,7 +223,7 @@
"mtdparts=physmap-flash.0:" \
"128k(u-boot)ro," \
"128k(u-boot-env)," \
- "1408k(kernel),"\
+ "1792k(kernel),"\
"-(rootfs)"
#define CONFIG_BOOTARGS\
@@ -238,11 +238,11 @@
"1001; erase 1000 1001; cp.b 2100 " \
"1000 ${filesize}\0"\
"flui=tftp 2100 cpuat91/uImage; protect off 1004 " \
- "1019; erase 1004 1019; cp.b 2100 " \
+ "1019; erase 1004 101f; cp.b 2100 " \
"1004 ${filesize}\0"\
"flrfs=tftp 2100 cpuat91/rootfs.jffs2; protect off "\
- "101a 10ff; erase 101a 10ff; cp.b " \
- "2100 101A ${filesize}\0" \
+ "1020 10ff; erase 1020 10ff; cp.b " \
+ "2100 1020 ${filesize}\0" \
"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
"flashboot=run ramargs;bootm 1004\0"\
"netboot=run ramargs;tftpboot 2100 cpuat91/uImage;" \
--
1.6.3.3
___
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[U-Boot] Accessing 64bit address
I am using ppc440 based board. Board is having 64bit memory controll register. To access the memory controll region i have added one tlb entry i.e tlbentry( 0xc70e, SZ_64K, 0xc70e, 0xf, AC_R|AC_X|AC_W|SA_I) What is the way to access the 64bit register in u-boot? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] TOT u-boot makes P1020RDB unbootable
Hi, I've tried to flash TOT u-boot complied with ELDK 4.2 for P1020_config into my P1020RDB RevD and bricked it. The same u-boot boots fine on P2020RDB revC. I don't have BDI3000 at the moment to debug the problem. It would be great to fix it before the release. Below is u-boot output from P1020RDB running with u-boot-2009.11 from FSL BSP U-Boot 2009.11-1-g4458602-dirty (Feb 27 2010 - 11:13:42) CPU0: P1020E, Version: 1.0, (0x80ec0010) Core: E500, Version: 5.0, (0x80212050) Clock Configuration: CPU0:800 MHz, CPU1:800 MHz, CCB:400 MHz, DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:25 MHz L1:D-cache 32 kB enabled I-cache 32 kB enabled Board: P1020RDB RevD I2C: ready SPI: ready DRAM: Configuring DDR for 666.667 MT/s data rate DDR: 512 MB NOR Flash Bank : Primary SD/MMC : 4-bit Mode eSPI : Enabled FLASH: 16 MB L2:256 KB enabled NAND: 32 MiB MMC: FSL_ESDHC: 0 EEPROM: Read failed. eTSEC2 is in sgmii mode. PCIE2 connected to Slot 1 as Root Complex (base addr ffe09000) PCIE2 on bus 00 - 01 PCIE1 connected to Slot 2 as Root Complex (base addr ffe0a000) PCIE1 on bus 02 - 02 In:serial Out: serial Err: serial Net: uploading VSC7385 microcode from ef00 eTSEC1: No support for PHY id ; assuming generic eTSEC1, eTSEC2, eTSEC3 Thanks. Felix. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] TOT u-boot makes P1020RDB unbootable
There are few changes which need to be done for RevD and are not in TOT. I will send the patches for it soon. Regards Poonam > -Original Message- > From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] > On Behalf Of Felix Radensky > Sent: Monday, June 21, 2010 3:49 PM > To: U-Boot-Denx; Kumar Gala > Subject: [U-Boot] TOT u-boot makes P1020RDB unbootable > > Hi, > > I've tried to flash TOT u-boot complied with ELDK 4.2 for P1020_config > into my P1020RDB RevD and bricked it. The same u-boot boots fine on > P2020RDB revC. > > I don't have BDI3000 at the moment to debug the problem. It would be > great to fix it before the release. > > Below is u-boot output from P1020RDB running with u-boot-2009.11 from FSL > BSP > > U-Boot 2009.11-1-g4458602-dirty (Feb 27 2010 - 11:13:42) > > CPU0: P1020E, Version: 1.0, (0x80ec0010) > Core: E500, Version: 5.0, (0x80212050) > Clock Configuration: >CPU0:800 MHz, CPU1:800 MHz, >CCB:400 MHz, >DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:25 > MHz > L1:D-cache 32 kB enabled >I-cache 32 kB enabled > Board: P1020RDB RevD > I2C: ready > SPI: ready > DRAM: Configuring DDR for 666.667 MT/s data rate > DDR: 512 MB > NOR Flash Bank : Primary > SD/MMC : 4-bit Mode > eSPI : Enabled > FLASH: 16 MB > L2:256 KB enabled > NAND: 32 MiB > MMC: FSL_ESDHC: 0 > EEPROM: Read failed. > eTSEC2 is in sgmii mode. > > PCIE2 connected to Slot 1 as Root Complex (base addr ffe09000) > PCIE2 on bus 00 - 01 > > PCIE1 connected to Slot 2 as Root Complex (base addr ffe0a000) > PCIE1 on bus 02 - 02 > > In:serial > Out: serial > Err: serial > Net: uploading VSC7385 microcode from ef00 > eTSEC1: No support for PHY id ; assuming generic eTSEC1, eTSEC2, > eTSEC3 > > Thanks. > > Felix. > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] TOT u-boot makes P1020RDB unbootable
Dear "Aggrwal Poonam-B10812", In message <8660da277dc57b4baac78225f03146b6b08...@zin33exm24.fsl.freescale.net> you wrote: > There are few changes which need to be done for RevD and are not in TOT. > > I will send the patches for it soon. Please hurry up. There is not much time left before the release. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "Beware of programmers carrying screwdrivers." - Chip Salzenberg ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc8343: TSEC1 @ RGMII stopped working
Hi Andre, André Schwarz wrote: > Kim, > > the 2nd TSEC has stopped working on both U-Boot and Linux on our MPC8343 > based system (MVBLM7). Actually I stumbled over this by accident... > > TSEC0+1 are using an VSC8601 connected via RGMII. > > Since both Bootloader (U-Boot 2010.3) and OS (Linux 2.6.26.27) are > affected I suspect a configuration problem. > > The PHY is working fine according to LED signalling. > > mvBL-M7> mii info > ->TSEC0 unplugged: > PHY 0x10: OUI = 0x01C1, Model = 0x02, Rev = 0x01, 10baseT, HDX > ->TSEC1 plugged into GigE Network. > PHY 0x11: OUI = 0x01C1, Model = 0x02, Rev = 0x01, 100baseT, FDX > PHY 0x1F: OUI = 0x, Model = 0x00, Rev = 0x00, 10baseT, HDX > > > mvBL-M7> set ethact TSEC1 > mvBL-M7> bootp > Speed: 1000, full duplex > Random delay: 603 ms... > BOOTP broadcast 1 > > > I have the same problem on P2020RDB (VSC7385 with RGMII) with TOT u-boot. The last working version seems to be u-boot-2009.11. Didn't have time to git-bisect that yet. Felix. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc8343: TSEC1 @ RGMII stopped working
Felix, > > > > > I have the same problem on P2020RDB (VSC7385 with RGMII) with TOT u-boot. > The last working version seems to be u-boot-2009.11. Didn't have time to > git-bisect that yet. huh - this is good news :-) Thought we have a production issue... Hopefully I find some time next week to dig into this. Nevertheless I'm waiting for Kim's comment. Regards, André > > Felix. MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] DaVinci: EMAC: Get EMAC_MDIO_PHY_NUM from config files
Currently EMAC_MDIO_PHY_NUM is defined as 1 in emac_defs.h. Because of this, EMAC does not work on EVMs which do not have phy connected at 1. Moving the macro to board config file makes this configurable depending on where the phy is connected on the MDIO bus. This patch fixes the board reset issue observed during network access on DM365EVM. EMAC driver was assuming EMAC_MDIO_PHY_NUM as 1 but it is 0 on DM365EVM. This patch is verified on da830/omap-l137, dm365 and dm644x evms. Signed-off-by: Prakash PM --- arch/arm/include/asm/arch-davinci/emac_defs.h |2 +- include/configs/da830evm.h|1 + include/configs/davinci_dm365evm.h|1 + include/configs/davinci_dvevm.h |1 + include/configs/davinci_schmoogie.h |1 + include/configs/davinci_sffsdr.h |1 + 6 files changed, 6 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h index b0ec8f5..35a1585 100644 --- a/arch/arm/include/asm/arch-davinci/emac_defs.h +++ b/arch/arm/include/asm/arch-davinci/emac_defs.h @@ -85,7 +85,7 @@ #endif /* PHY mask - set only those phy number bits where phy is/can be connected */ -#define EMAC_MDIO_PHY_NUM 1 +#define EMAC_MDIO_PHY_NUM CONFIG_EMAC_MDIO_PHY_NUM #define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM) /* Ethernet Min/Max packet size */ diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 0f58e11..621bae4 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -87,6 +87,7 @@ * Network & Ethernet Configuration */ #ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 6f99ae0..76a3b0c 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -58,6 +58,7 @@ /* Network Configuration */ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 0 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 5774df5..21f7a80 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -102,6 +102,7 @@ /* Network & Ethernet Configuration */ /*==*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 3972ebc..f28d073 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -69,6 +69,7 @@ /* Network & Ethernet Configuration */ /*==*/ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 94be9dc..d1ed918 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -66,6 +66,7 @@ #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 1 #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS -- 1.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mpc8308: support for Freescale MPC8308 cpu
Dear Wolfgang, thanks for your review. On 21.06.2010 11:44, Wolfgang Denk wrote: >> This patch adds basic support for Freescale MPC8308 CPU. Serial ports, >> NOR flash and integrated Ethernet controllers are supported. >> PCI Express is also supported. eSDHC, NAND and USB may work but aren't >> tested (using ULPI PHY requires additional patch). >> >> Signed-off-by: Ilya Yanok >> > ... > >> -#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || >> defined(CONFIG_MPC8315) >> +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || \ >> +defined(CONFIG_MPC8315) || defined(CONFIG_MPC8308) >> > Please sort this list. > Fixed. >> +#if defined(CONFIG_MPC8308) >> +#define SCCR_SDHCCM 0x0c00 >> +#define SCCR_SDHCCM_SHIFT 26 >> +#define SCCR_SDHCCM_0 0x >> +#define SCCR_SDHCCM_1 0x0400 >> +#define SCCR_SDHCCM_2 0x0800 >> +#define SCCR_SDHCCM_3 0x0c00 >> +#endif >> > Would it make sense to write this as: > > And: why do we need the #ifdef? Unused defines should not hurt? > > #define SCCR_SDHCCM_MASK0x0c00 /* is it a mask? */ > #define SCCR_SDHCCM_SHIFT 26 > #define SCCR_SDHCCM(arg)((arg)< > As you already mentioned I'm just following the style used in this file. >> +#if defined(CONFIG_MPC8315) >> #define SCCR_SATA1CM 0x3000 >> #define SCCR_SATA1CM_SHIFT 12 >> #define SCCR_SATACM0x3c00 >> @@ -765,6 +776,7 @@ >> #define SCCR_SATACM_1 0x1400 >> #define SCCR_SATACM_2 0x2800 >> #define SCCR_SATACM_3 0x3c00 >> +#endif >> > Do we need that #ifdef? Ok, the #defines don't apply to the 8308, but > do they hurt if they are just there, unused? > Well, it seems to be safer not to have unused defines so that you can't erroneously use some define not applicable for current CPU, but if you wish I'll remove these ifdefs. Regards, Ilya. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] add support for arm926ejs-based pollux CPU
On Tue, Jun 1, 2010 at 3:38 PM, Wolfgang Denk wrote:
> Dear Brian Cavagnolo,
>
> In message <1275417750-10020-1-git-send-email-br...@cozybit.com> you wrote:
>>
>>
>> Signed-off-by: Brian Cavagnolo
>> Signed-off-by: Andrey Yurovsky
>
> Please be a bit more verbose - who is manufacturing this pollux
> thingy, who will be maintaining the code, etc.
>
>> arch/arm/cpu/arm926ejs/pollux/Makefile | 51
>> arch/arm/cpu/arm926ejs/pollux/reset.S | 49
>> arch/arm/cpu/arm926ejs/pollux/timer.c | 190
>> +
>
> Why exactly do we need a new directory for it?
This appears to be the convention in the source tree and it seems
straightforward and clean. Is there a different preferred way to add
new CPUs?
I understand your other comments.
Thanks,
Brian
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/pollux/reset.S
>> @@ -0,0 +1,49 @@
> ...
>> + .align 5
>> +.globl reset_cpu
>> +reset_cpu:
>> + ldr r1, rstctl1 /* get clkm1 reset ctl */
>> + mov r3, #0x0
>> + strh r3, [r1] /* clear it */
>> + mov r3, #0x8
>> + strh r3, [r1] /* force dsp+arm reset */
>> +_loop_forever:
>> + b _loop_forever
>> +
>> +rstctl1:
>> + .word 0xfffece10
>
> This seems identical to /arm/cpu/arm926ejs/omap/reset.S and
> arch/arm/cpu/arm926ejs/versatile/reset.S to me. Why do we need a 3rd
> copy of the same code?
>
> Please factor out common code.
>
>> diff --git a/arch/arm/cpu/arm926ejs/pollux/timer.c
>> b/arch/arm/cpu/arm926ejs/pollux/timer.c
>> new file mode 100644
>> index 000..fc6c699
>> --- /dev/null
>> +++ b/arch/arm/cpu/arm926ejs/pollux/timer.c
> ...
>> +#ifndef CONFIG_SYS_TIMERBASE
>> +#error "Please define CONFIG_SYS_TIMERBASE to a suitable TIMERx_BASE"
>> +#endif
>> +#define TIMERBASE CONFIG_SYS_TIMERBASE
>> +
>> +#define TIMER_LOAD_VAL 0x
>> +
>> +static ulong inline read_timer(void)
>> +{
>> + REG32(TIMERBASE + TMRCONTROL) |= (1<> + return REG32(TIMERBASE + TMRMATCH);
>> +}
>
> We don;t allow register accesses through base address + offset any
> more. Please declare porper C structs and use proper I/O accessors.
> Please fix globally.
>
>> + if (lastdec >= now) { /* normal mode (non roll) */
>> + /* normal mode */
>> + timestamp += lastdec - now; /* move stamp fordward with
>> absoulte diff ticks */
>
> LIne too long. Please fix globally.
>
>> + } else { /* we have overflow of the count down
>> timer */
>> + /* nts = ts + ld + (TLV - now)
>> + * ts=old stamp, ld=time that passed before passing through -1
>> + * (TLV-now) amount of time after passing though -1
>> + * nts = new "advancing time stamp"...it could also roll and
>> cause problems.
>> + */
>
> Incorrect multiline comment style. Please fix globally.
>
>> +/* Clock and Power Control Registers */
>> +#define CLKPWR_BASE 0xC000F000
>> +#define CLKMODEREG (CLKPWR_BASE + 0x000)
>> +#define PLLSETREG0 (CLKPWR_BASE + 0x004)
>> +#define PLLSETREG1 (CLKPWR_BASE + 0x008)
>> +#define GPIOWAKEUPENB (CLKPWR_BASE + 0x040)
>> +#define RTCWAKEUPENB (CLKPWR_BASE + 0x044)
>> +#define GPIOWAKEUPRISEENB (CLKPWR_BASE + 0x048)
>> +#define GPIOWAKEUPFALLENB (CLKPWR_BASE + 0x04C)
>> +#define GPIOPEND (CLKPWR_BASE + 0x050)
>> +#define INTPENDSPAD (CLKPWR_BASE + 0x058)
>> +#define PWRRSTSTATUS (CLKPWR_BASE + 0x05C)
>> +#define INTENB (CLKPWR_BASE + 0x060)
>> +#define PWRMODE (CLKPWR_BASE + 0x07C)
>> +#define PADSTRENGTHGPIOAL (CLKPWR_BASE + 0x100)
>> +#define PADSTRENGTHGPIOAH (CLKPWR_BASE + 0x104)
>> +#define PADSTRENGTHGPIOBL (CLKPWR_BASE + 0x108)
>> +#define PADSTRENGTHGPIOBH (CLKPWR_BASE + 0x10C)
>> +#define PADSTRENGTHGPIOCL (CLKPWR_BASE + 0x110)
>> +#define PADSTRENGTHGPIOCH (CLKPWR_BASE + 0x114)
>> +#define PADSTRENGTHBUS (CLKPWR_BASE + 0x118)
>
> NAK! See above - please declare proper C structs instead.
>
>> diff --git a/arch/arm/include/asm/arch-pollux/gpio.h
>> b/arch/arm/include/asm/arch-pollux/gpio.h
>> new file mode 100644
>> index 000..f6ddd1b
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-pollux/gpio.h
> ...
>> +/* GPIO registers */
>> +#define GPIO_BASE 0xC000A000
>> +
>> +#define GPIOAOUT (GPIO_BASE + 0x00)
>> +#define GPIOAOUTENB (GPIO_BASE + 0x04)
>> +#define GPIOADETMODE0 (GPIO_BASE + 0x08)
>> +#define GPIOADETMODE1 (GPIO_BASE + 0x0C)
>> +#define GPIOAINTENB (GPIO_BASE + 0x10)
>> +#define GPIOADET (GPIO_BASE + 0x14)
>> +#define GPIOAPAD (GPIO_BASE + 0x18)
>> +#define GPIOAPUENB (GPIO_BASE + 0x1C)
>> +#define GPIOAALTFN0 (GPIO_BASE + 0x20)
>> +#define GPIOAALTFN1 (GPIO_BASE + 0x24)
>
> NAK again
Re: [U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale
Dear Wolfgang,
On 21.06.2010 11:44, Wolfgang Denk wrote:
>> MAKEALL |1 +
>> Makefile |3 +
>> board/freescale/mpc8308erdb/Makefile | 52 +++
>> board/freescale/mpc8308erdb/config.mk |1 +
>> board/freescale/mpc8308erdb/mpc8308erdb.c | 154
>> board/freescale/mpc8308erdb/sdram.c | 126 +++
>> include/configs/MPC8308ERDB.h | 572
>> +
>> 7 files changed, 909 insertions(+), 0 deletions(-)
>> create mode 100644 board/freescale/mpc8308erdb/Makefile
>> create mode 100644 board/freescale/mpc8308erdb/config.mk
>> create mode 100644 board/freescale/mpc8308erdb/mpc8308erdb.c
>> create mode 100644 board/freescale/mpc8308erdb/sdram.c
>> create mode 100644 include/configs/MPC8308ERDB.h
>>
> Entry to MAINTAINERS missing.
>
Should I add you as a maintainer or myself?
>> diff --git a/Makefile b/Makefile
>> index 55bb964..0dc2678 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -2233,6 +2233,9 @@ TASREG_config :unconfig
>> kmeter1_config: unconfig
>> @$(MKCONFIG) kmeter1 powerpc mpc83xx kmeter1 keymile
>>
>> +MPC8308ERDB_config: unconfig
>> +@$(MKCONFIG) -a MPC8308ERDB powerpc mpc83xx mpc8308erdb freescale
>>
> NAK. Please rebase your code against the "next" branch. We don't
> accept any board entries to the top level Makefile any more. Please
> add to boards.cfg instead.
>
Done.
>> --- /dev/null
>> +++ b/board/freescale/mpc8308erdb/mpc8308erdb.c
>> @@ -0,0 +1,154 @@
>> +/*
>> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, ya...@emcraft.com
>> + *
>> + * Author: Freescale unknown
>>
> Maybe "Initial author" ?
>
Dropped this line.
>> +int board_early_init_f(void)
>> +{
>> +immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
>> +
>> +if (in_be32(&im->pmc.pmccr1)& PMCCR1_POWER_OFF)
>> +gd->flags |= GD_FLG_SILENT;
>>
> What exactly is this good for?
>
That's for making board silent then it comes out of sleep (not printing
version info, checkcpu() output and so on). Actually I've not tested
sleep/wakeup functionality but the code looks correct.
>> +/*
>> + * Miscellaneous late-boot configurations
>> + *
>> + * If a VSC7385 microcode image is present, then upload it.
>> +*/
>> +int misc_init_r(void)
>> +{
>> +int rc = 0;
>>
> Please drop the variable.
>
Done.
>> +#ifdef CONFIG_VSC7385_IMAGE
>> +if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
>> +CONFIG_VSC7385_IMAGE_SIZE)) {
>> +puts("Failure uploading VSC7385 microcode.\n");
>> +rc = 1;
>>
> return 1;
>
>
>> +}
>> +#endif
>> +
>> +return rc;
>>
> return 0;
>
>
>> +int board_eth_init(bd_t *bis)
>> +{
>> +cpu_eth_init(bis); /* Initialize TSECs first */
>>
> I think it's wrong to ignore the return code here.
>
What makes you think so? What can we do with the return code here? Print
warning? If we return error from board_eth_init() calling code will call
cpu_eth_init() again which is useless as we have already called it.
>> +return pci_eth_init(bis);
>> +}
>> +
>> +
>>
> Please remove trailing empty lines.
>
Fixed.
>> +/* Fixed sdram init -- doesn't use serial presence detect.
>> + *
>> + * This is useful for faster booting in configs where the RAM is unlikely
>> + * to be changed, or for things like NAND booting where space is tight.
>> + */
>> +static long fixed_sdram(void)
>> +{
>> +immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
>> +u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
>> +u32 msize_log2 = __ilog2(msize);
>> +
>> +out_be32(&im->sysconf.ddrlaw[0].bar,
>> +CONFIG_SYS_DDR_SDRAM_BASE& 0xf000);
>> +out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
>> +out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
>> +
>> +/*
>> + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
>> + * or the DDR2 controller may fail to initialize correctly.
>> + */
>> +udelay(5);
>> +
>> +out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1)>> 24);
>> +out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
>> +
>> +/* Currently we use only one CS, so disable the other bank. */
>> +out_be32(&im->ddr.cs_config[1], 0);
>> +
>> +out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
>> +out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
>> +out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
>> +out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
>> +out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
>> +
>> +if (in_be32(&im->pmc.pmccr1)& PMCCR1_POWER_OFF) {
>> +out_be32(&im->ddr.sdram_cfg,
>> +CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CF
Re: [U-Boot] [PATCH 2/3] add serial driver for pollux CPU
On Tue, Jun 1, 2010 at 3:42 PM, Wolfgang Denk wrote: > Dear Brian Cavagnolo, > > In message <1275417750-10020-2-git-send-email-br...@cozybit.com> you wrote: >> >> Signed-off-by: Brian Cavagnolo >> Signed-off-by: Andrey Yurovsky >> --- >> drivers/serial/Makefile | 1 + >> drivers/serial/serial_pollux.c | 116 >> >> 2 files changed, 117 insertions(+), 0 deletions(-) >> create mode 100644 drivers/serial/serial_pollux.c > > Please see previous comments about using C structs with I/O accessors, > coding style etc. Understood. > General question: do we really need a new UART driver, or can this be > generalized with other drivers? The s3c44b0 serial hardware is quite similar to that of the pollux. There are some quirks (e.g., the pollux's registers are 16 bits and the s3c44b0's are 32), but I think there are some reasonable ways to address that. I'll use that driver in v2. Thanks, Brian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] s3c44b0 serial driver questions
Hello,
I'm hoping to use the s3c44b0 serial driver for a CPU with very similar serial
hardware. One change that I must make is to calculate the baud rate divisor
with a macro because this operation is board-specific. I propose to clean up
the large switch statement in the existing code with a macro that calculates
the BRD using the formula in the datasheet ("S3C44B0X RISC MICROPROCESSOR"
pg. 10-7; See proposed patch below.) However, the BRD values in the current
code for the 66MHz case do not match the formula in the data sheet. They are
all skewed high. Is this a bug?
Ciao,
Brian
diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h
b/arch/arm/include/asm/arch-s3c44b0/hardware.h
index 146e265..38ff32c 100644
--- a/arch/arm/include/asm/arch-s3c44b0/hardware.h
+++ b/arch/arm/include/asm/arch-s3c44b0/hardware.h
@@ -11,7 +11,8 @@
#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr))
#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr))
#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr))
-
+#define BRD(bps) (DIV_ROUND(CONFIG_S3C44B0_CLOCK_SPEED * 100, \
+ (bps)*16) - 1)
/*/
/* CPU Wrapper Registers */
diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c
index 95d0266..e6c535c 100644
--- a/drivers/serial/serial_s3c44b0.c
+++ b/drivers/serial/serial_s3c44b0.c
@@ -70,68 +70,7 @@ static int serial_flush_output(void)
void serial_setbrg (void)
{
- u32 divisor = 0;
-
- /* get correct divisor */
- switch(gd->baudrate) {
-
- case 1200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 3124;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 3905;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
- break;
-
- case 9600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 390;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 487;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
- break;
-
- case 19200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 194;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 243;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
- break;
-
- case 38400:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 97;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 121;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
-
- case 57600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 64;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 80;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
-
- case 115200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
- divisor = 32;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
- divisor = 40;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
- }
+ u32 divisor = BRD(gd->baudrate);
serial_flush_output();
serial_flush_input();
___
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[U-Boot] [PATCH] Makefile: always call date with LANG=C set
Ensure that date is called only with LANG=C locale set to make dates locale neutral thus preventing lurking of non-ASCII characters into U-Boot binary. Signed-off-by: Ilya Yanok --- Makefile |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 3e11f6f..685b7ef 100644 --- a/Makefile +++ b/Makefile @@ -385,8 +385,8 @@ $(VERSION_FILE): @cmp -s $@ $...@.tmp && rm -f $...@.tmp || mv -f $...@.tmp $@ $(TIMESTAMP_FILE): - @date +'#define U_BOOT_DATE "%b %d %C%y"' > $@ - @date +'#define U_BOOT_TIME "%T"' >> $@ + @LANG=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@ + @LANG=C date +'#define U_BOOT_TIME "%T"' >> $@ gdbtools: $(MAKE) -C tools/gdb all || exit 1 @@ -2476,6 +2476,6 @@ endif backup: F=`basename $(TOPDIR)` ; cd .. ; \ - gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F + gtar --force-local -zcvf `LANG=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F # -- 1.6.2.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] DaVinci: EMAC: Get EMAC_MDIO_PHY_NUM from config files
> > Currently EMAC_MDIO_PHY_NUM is defined as 1 in emac_defs.h. > Because of this, EMAC does not work on EVMs which do not have phy > connected at 1. Moving the macro to board config file makes this > configurable depending on where the phy is connected on the MDIO bus. > > This patch fixes the board reset issue observed during network access > on DM365EVM. EMAC driver was assuming EMAC_MDIO_PHY_NUM as 1 > but it is 0 on DM365EVM. > > This patch is verified on da830/omap-l137, dm365 and dm644x evms. > > Signed-off-by: Prakash PM > --- Thanks Will apply to u-boot-ti Sandeep ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Davinci: SPI performance enhancements
>
> The following restructuring and optimisations increase the SPI
> read performance from 1.3MiB/s (on da850) to 2.87MiB/s (on da830):
>
> Remove continual revaluation of driver state from the core of the
> copy loop. State can not change during the copy loop, so it is
> possible to move these evaluations to before the copy loop.
>
> Cost is more code space as loop variants are required for each set
> of possible configurations. The loops are simpler however, so the
> extra is only 128bytes on da830 with CONFIG_SPI_HALF_DUPLEX
> defined.
>
> Unrolling the first copy loop iteration allows the TX buffer to be
> pre-loaded reducing SPI clock starvation.
>
> Unrolling the last copy loop iteration removes testing for the
> final loop iteration every time round the loop.
>
> Using the RX buffer empty flag as a transfer throttle allows the
> assumption that it is always safe to write to the TX buffer, so
> polling of TX buffer full flag can be removed.
>
> Signed-off-by: Nick Thompson
> ---
> da850 and da830 are similar devices. The SPI module is common to
> both, but da850 uses DDR and da830 uses SDRAM. The EVM's might
> not actually be comparable, but they appear to be at least similar.
>
> The speed was tested with a 8MiB transfer from SPI FLASH using:
>
> sf read 0xc0008000 0 0x80
>
> drivers/spi/davinci_spi.c | 195 +---
This patch does not apply against Wolfgang's next.
The patch should be against u-boot/next.
>
> 1 files changed, 128 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
> index 08f837b..4518ecb 100644
> --- a/drivers/spi/davinci_spi.c
> +++ b/drivers/spi/davinci_spi.c
> @@ -66,7 +66,7 @@ void spi_free_slave(struct spi_slave *slave)
> int spi_claim_bus(struct spi_slave *slave)
> {
> struct davinci_spi_slave *ds = to_davinci_spi(slave);
> - unsigned int scalar, data1_reg_val = 0;
> + unsigned int scalar;
>
> /* Enable the SPI hardware */
> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
> @@ -93,11 +93,6 @@ int spi_claim_bus(struct spi_slave *slave)
> writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
> (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
>
> - /* hold cs active at end of transfer until explicitly de-asserted */
> - data1_reg_val = (1 << SPIDAT1_CSHOLD_SHIFT) |
> - (slave->cs << SPIDAT1_CSNR_SHIFT);
> - writel(data1_reg_val, &ds->regs->dat1);
> -
> /*
>* Including a minor delay. No science here. Should be good even
> with
>* no delay
> @@ -113,8 +108,7 @@ int spi_claim_bus(struct spi_slave *slave)
> writel(0, &ds->regs->lvl);
>
> /* enable SPI */
> - writel((readl(&ds->regs->gcr1) |
> - SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
> + writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs-
> >gcr1);
>
> return 0;
> }
> @@ -127,14 +121,125 @@ void spi_release_bus(struct spi_slave *slave)
> writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
> }
>
> +/*
> + * This functions needs to act like a macro to avoid pipeline reloads in
> the
> + * loops below. Use always_inline. This gains us about 160KiB/s and the
> bloat
> + * appears to be zero bytes (da830).
> + */
> +__attribute__((always_inline))
> +static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32
> data)
> +{
> + u32 buf_reg_val;
> +
> + /* send out data */
> + writel(data, &ds->regs->dat1);
> +
> + /* wait for the data to clock in/out */
> + while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
> + ;
> +
> + return buf_reg_val;
> +}
> +
> +static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
> + u8 *rxp, unsigned long flags)
> +{
> + struct davinci_spi_slave *ds = to_davinci_spi(slave);
> + unsigned int data1_reg_val;
> +
> + /* enable CS hold, CS[n] and clear the data bits */
> + data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
> + (slave->cs << SPIDAT1_CSNR_SHIFT));
> +
> + /* wait till TXFULL is deasserted */
> + while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
> + ;
> +
> + /* preload the TX buffer to avoid clock starvation */
> + writel(data1_reg_val, &ds->regs->dat1);
> +
> + /* keep reading 1 byte until only 1 byte left */
> + while ((len--) > 1)
> + *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
> +
> + /* clear CS hold when we reach the end */
> + if (flags & SPI_XFER_END)
> + data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
> +
> + /* read the last byte */
> + *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
> +
> + return 0;
> +}
> +
> +static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
> + const u8 *txp, unsigned long flags)
> +{
> + struct davinci_spi_slave *ds = to_davinci_spi(slave);
> + un
Re: [U-Boot] [PATCH] Davinci: SPI performance enhancements
On 21/06/10 15:41, Paulraj, Sandeep wrote: > > >> >> The following restructuring and optimisations increase the SPI >> read performance from 1.3MiB/s (on da850) to 2.87MiB/s (on da830): >> >> Remove continual revaluation of driver state from the core of the >> copy loop. State can not change during the copy loop, so it is >> possible to move these evaluations to before the copy loop. >> >> Cost is more code space as loop variants are required for each set >> of possible configurations. The loops are simpler however, so the >> extra is only 128bytes on da830 with CONFIG_SPI_HALF_DUPLEX >> defined. >> >> Unrolling the first copy loop iteration allows the TX buffer to be >> pre-loaded reducing SPI clock starvation. >> >> Unrolling the last copy loop iteration removes testing for the >> final loop iteration every time round the loop. >> >> Using the RX buffer empty flag as a transfer throttle allows the >> assumption that it is always safe to write to the TX buffer, so >> polling of TX buffer full flag can be removed. >> >> Signed-off-by: Nick Thompson >> --- >> da850 and da830 are similar devices. The SPI module is common to >> both, but da850 uses DDR and da830 uses SDRAM. The EVM's might >> not actually be comparable, but they appear to be at least similar. >> >> The speed was tested with a 8MiB transfer from SPI FLASH using: >> >> sf read 0xc0008000 0 0x80 >> >> drivers/spi/davinci_spi.c | 195 +--- > > This patch does not apply against Wolfgang's next. > The patch should be against u-boot/next. The patch is based on u-boot as updated this morning. It applies directly after Delio's patch, which is in u-boot/next, and the last change to this file. u-boot/next is at the tip and is three days old. I don't understand why it doesn't apply. What failure do you see? $ git log drivers/spi/davinci_spi.c commit 15c4e0802caed209ca021de25ec607658ae35720 Author: Nick Thompson Date: Mon Jun 21 09:48:22 2010 +0100 Davinci: SPI performance enhancements The following restructuring and optimisations increase the SPI [...skip to next log...] commit 9268236529161312c877e638a14c011fd3c883e1 Author: Delio Brignoli Date: Mon Jun 7 17:16:13 2010 -0400 DaVinci: Improve DaVinci SPI speed. I have updated this patch based on the comments [1] by Wolfgang Denk and ... Nick. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Davinci: SPI performance enhancements
On 21/06/10 15:41, Paulraj, Sandeep wrote: > > >> >> The following restructuring and optimisations increase the SPI >> read performance from 1.3MiB/s (on da850) to 2.87MiB/s (on da830): >> >> Remove continual revaluation of driver state from the core of the >> copy loop. State can not change during the copy loop, so it is >> possible to move these evaluations to before the copy loop. >> >> Cost is more code space as loop variants are required for each set >> of possible configurations. The loops are simpler however, so the >> extra is only 128bytes on da830 with CONFIG_SPI_HALF_DUPLEX >> defined. >> >> Unrolling the first copy loop iteration allows the TX buffer to be >> pre-loaded reducing SPI clock starvation. >> >> Unrolling the last copy loop iteration removes testing for the >> final loop iteration every time round the loop. >> >> Using the RX buffer empty flag as a transfer throttle allows the >> assumption that it is always safe to write to the TX buffer, so >> polling of TX buffer full flag can be removed. >> >> Signed-off-by: Nick Thompson >> --- >> da850 and da830 are similar devices. The SPI module is common to >> both, but da850 uses DDR and da830 uses SDRAM. The EVM's might >> not actually be comparable, but they appear to be at least similar. >> >> The speed was tested with a 8MiB transfer from SPI FLASH using: >> >> sf read 0xc0008000 0 0x80 >> >> drivers/spi/davinci_spi.c | 195 +--- > > This patch does not apply against Wolfgang's next. > The patch should be against u-boot/next. It looks like Delio's patch ended up being pulled into main via Tom's tree and yours. On u-boot I see 9268236529161312c877e638a14c011fd3c883e1, but the same commit has id 23911740486c59851df57521c49bfd81ce1865ec on on u-boot-ti. I guess this is the source of the confusion? My patch was against u-boot, not u-boot-ti. Nick. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] [U-BOOT] Zoom3: Add support for OMAP3630 Zoom3 board.
> > From: Aldo Brett Cedillo Martinez > > This patch gives basic funcionality to OMAP3630 Zoom3 board. > > Signed-off-by: Aldo Brett Cedillo Martinez > --- > MAINTAINERS|4 + > MAKEALL|1 + > Makefile |3 + > board/logicpd/zoom3/Makefile | 54 +++ > board/logicpd/zoom3/config.mk | 33 + > board/logicpd/zoom3/debug_board.c | 66 + > board/logicpd/zoom3/led.c | 133 ++ > board/logicpd/zoom3/zoom3.c| 201 ++ > board/logicpd/zoom3/zoom3.h| 163 ++ > board/logicpd/zoom3/zoom3_serial.c | 132 + > board/logicpd/zoom3/zoom3_serial.h | 76 ++ > common/serial.c|2 + > include/configs/omap3_zoom3.h | 271 > > include/serial.h |7 + > 14 files changed, 1146 insertions(+), 0 deletions(-) > create mode 100644 board/logicpd/zoom3/Makefile > create mode 100644 board/logicpd/zoom3/config.mk > create mode 100644 board/logicpd/zoom3/debug_board.c > create mode 100644 board/logicpd/zoom3/led.c > create mode 100644 board/logicpd/zoom3/zoom3.c > create mode 100644 board/logicpd/zoom3/zoom3.h > create mode 100644 board/logicpd/zoom3/zoom3_serial.c > create mode 100644 board/logicpd/zoom3/zoom3_serial.h > create mode 100644 include/configs/omap3_zoom3.h This patch had 31 checkpatch errors. Please fix. Also while resubmitting, the patch should be against u-boot/next Thanks, Sandeep ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] NAND: show manufacturer and device ID for unknown chips
On Sun, Jun 20, 2010 at 03:40:55PM +0200, Florian Fainelli wrote:
> Le Saturday 12 June 2010 20:59:25, Florian Fainelli a écrit :
> > When the NAND part is not supported, it is useful to show the manufacturer
> > and device ID to help debugging and reporting.
> >
> > Signed-off-by: Florian Fainelli
>
> Scott, anything from with the patch? Thanks!
I just got back from vacation, but the patches look reasonable.
> > ---
> > diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> > index 7171bdd..c1657de 100644
> > --- a/drivers/mtd/nand/nand_base.c
> > +++ b/drivers/mtd/nand/nand_base.c
> > @@ -2652,8 +2652,12 @@ static struct nand_flash_dev
> > *nand_get_flash_type(struct mtd_info *mtd, }
> > }
> >
> > - if (!type)
> > + if (!type) {
> > + printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID :"
I'd leave out the space before the colon ("foo: bar", not "foo : bar"),
though. I think that may be a regional style issue, but let's stick with
what the rest of the code does.
-Scott
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Re: [U-Boot] [PATCH v2] AX88180: use standard I/O accessors
On Monday, June 21, 2010 01:41:54 Ben Warren wrote: > On 6/2/2010 6:03 PM, Mike Frysinger wrote: > > The current dm9000x driver accesses its memory mapped registers directly > > instead of using the standard I/O accessors. This can cause problems on > > Blackfin systems as the accesses can get out of order. So convert the > > direct volatile dereferences to use the normal in/out macros. > > > > Signed-off-by: Mike Frysinger > > Tested-by: Hoan Hoang > > --- > > I can't get this to apply. Please rebase against TOT. you need the first two in the series: Applying: AX88180: add support for the Marvell 88E1118 phy Applying: AX88180: make OUTW handle 32bit/16bit defines too -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Makefile: always call date with LANG=C set
On Monday, June 21, 2010 10:13:21 Ilya Yanok wrote: > Ensure that date is called only with LANG=C locale set to make dates > locale neutral thus preventing lurking of non-ASCII characters into > U-Boot binary. use LC_ALL, not LANG -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] cpuat91: unbreak ethernet
Hi Eric, On 6/21/2010 12:40 AM, Eric Bénard wrote: > * the following problems are met : > config was set to use the new driver as a default but > - RMII was not enabled for the new driver > - the new driver didn't compile with RMII enabled > - the new driver initialize a PHY at address O when the PHY of > this board is at 1 thus we get "AT91 EMAC RMII: No PHY present" > > * to fix these problems, this patch : > - enable RMII for the new driver > - fix the wrong define used in the at91_emac.c > - allow the config file to set a default phy address (and use > 0 as a default as in the actual at91_emac.c driver) > > Signed-off-by: Eric Bénard > --- > Applied to net/next repo. regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] at91_emac: Write MAC address automatically
Hi Eric, On 6/21/2010 12:41 AM, Eric Bénard wrote: > tested on cpuat91. > > Signed-off-by: Eric Bénard > --- > v2 : > don't check if the MAC address is valid > > drivers/net/at91_emac.c | 28 > 1 files changed, 20 insertions(+), 8 deletions(-) > Applied to net/next repo. regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] AX88180: use standard I/O accessors
Hi Mike, On 6/21/2010 10:25 AM, Mike Frysinger wrote: > On Monday, June 21, 2010 01:41:54 Ben Warren wrote: > >> On 6/2/2010 6:03 PM, Mike Frysinger wrote: >> >>> The current dm9000x driver accesses its memory mapped registers directly >>> instead of using the standard I/O accessors. This can cause problems on >>> Blackfin systems as the accesses can get out of order. So convert the >>> direct volatile dereferences to use the normal in/out macros. >>> >>> Signed-off-by: Mike Frysinger >>> Tested-by: Hoan Hoang >>> --- >>> >> I can't get this to apply. Please rebase against TOT. >> > you need the first two in the series: > Applying: AX88180: add support for the Marvell 88E1118 phy > Applying: AX88180: make OUTW handle 32bit/16bit defines too > -mike > Sorry I missed those. All three are now in net/text. regards, Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Davinci: SPI performance enhancements
Hello Nick, On 21/06/2010, at 11:27, Nick Thompson wrote: > The following restructuring and optimisations increase the SPI > read performance from 1.3MiB/s (on da850) to 2.87MiB/s (on da830): Using this patch I get 2.21MiB/s on my L138 EVM (da850), quite an improvement! I would like to see how much my original patch can be improved using some of your changes without splitting the code to handle the three cases. I will try later this week. [...] > + if (!dout) > + return davinci_spi_read(slave, len, din, flags); > + else if (!din) > + return davinci_spi_write(slave, len, dout, flags); > +#ifndef CONFIG_SPI_HALF_DUPLEX > + else > + return davinci_spi_read_write(slave, len, din, dout, flags); > +#endif I think there should always be an else branch at the end even if CONFIG_SPI_HALF_DUPLEX is not defined. Something like: #else flags |= SPI_XFER_END; #endif to terminate the transfer instead of failing silently. In fact it should signal the error condition somehow, but I do not know enough about u-boot to provide an advice on this. Thanks -- Delio ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mpc8343: TSEC1 @ RGMII stopped working
On Mon, 21 Jun 2010 13:04:40 +0200 André Schwarz wrote: > Felix, > > I have the same problem on P2020RDB (VSC7385 with RGMII) with TOT u-boot. > > The last working version seems to be u-boot-2009.11. Didn't have time to > > git-bisect that yet. > > huh - this is good news :-) > Thought we have a production issue... > > Hopefully I find some time next week to dig into this. > Nevertheless I'm waiting for Kim's comment. ToT seems to be working fine for me (using different PHYs though): U-Boot 2010.06-rc2-00035-g1f24126 (Jun 21 2010 - 11:16:54) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c1, MPC8349EA, Rev: 3.0 at 528 MHz, CSB: 264 MHz Board: Freescale MPC8349EMDS I2C: ready SPI: ready DRAM: 256 MiB (DDR2, 64-bit, ECC on, 264 MHz) FLASH: 32 MiB In:serial Out: serial Err: serial Net: TSEC0, TSEC1 Type "run flash_nfs" to mount root filesystem over NFS Hit any key to stop autoboot: 0 => tftp Speed: 1000, full duplex Using TSEC0 device TFTP from server 192.168.1.1; our IP address is 192.168.1.183 Filename 'kimphill/uImage-83xx'. Load address: 0x80 Loading: # # # done Bytes transferred = 2028499 (1ef3d3 hex) => setenv ethact TSEC1 => tftp Speed: 1000, full duplex Using TSEC1 device TFTP from server 192.168.1.1; our IP address is 192.168.1.183 Filename 'kimphill/uImage-83xx'. Load address: 0x80 Loading: # # # done Bytes transferred = 2028499 (1ef3d3 hex) => you can try applying commit 71bd860cce4493c5def07804723661e75271052b "mpc83xx: don't shift pre-shifted ACR, SPCR, SCCR bitfield masks in cpu_init." but I don't think that's the problem, since it doesn't affect the p2020. Upgrade to ToT? Start a git bisect? on drivers/net/tsec.c? Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] DaVinci: EMAC: Get EMAC_MDIO_PHY_NUM from config files
> > > > Currently EMAC_MDIO_PHY_NUM is defined as 1 in emac_defs.h. > > Because of this, EMAC does not work on EVMs which do not have phy > > connected at 1. Moving the macro to board config file makes this > > configurable depending on where the phy is connected on the MDIO bus. > > > > This patch fixes the board reset issue observed during network access > > on DM365EVM. EMAC driver was assuming EMAC_MDIO_PHY_NUM as 1 > > but it is 0 on DM365EVM. > > > > This patch is verified on da830/omap-l137, dm365 and dm644x evms. > > > > Signed-off-by: Prakash PM > > --- > When I ran MAKEALL, Davinci SONATA gave a warning. Please take care of that. It is an EVM based on the 6446. Sandeep ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Add support for LPC2468 from NXP
Dear Remco Poelstra, In message <4c064504.3010...@duran-audio.com> you wrote: > > >> + pfnct = (void (*)(void))(&(vic->vicaddr)); > >> + > >> + (*pfnct) (); > >> > > Please unify with code for the LPC2292 and get rid of the #ifdef. > > > > This is not possible. I do understand that there is a lot of similarity, > but I was asked to use C structures to access registers, but the lpc22xx > code uses direct access. I cannot convert the lpc22xx code, since I don't > have access to a board and it's a very error-prone process. I think it would > be better if the current lpc22xx maintainer converts the lpc22xx code to > use > C structures as well. Unfortunatly, the same holds for most of the code > merge/factor out > comments below. As you can see from MAINTAINERS file, the LPC2292 is an orphaned board; please unify the code as I asked you, even if you can only compile-test the LPC2292 configuration. > > Ditto here. > > This one is different. The lpc2468 uses an upward counting timer, > while the other ARM's seem to use a downward counting timer (as > far as I could judge from the code). What about the LPC2292? > >> +++ b/arch/arm/cpu/arm720t/lpc24xx/iap_entry.S > >> @@ -0,0 +1,7 @@ > >> +IAP_ADDRESS: .word 0x7FF1 > >> + > >> +.globl iap_entry > >> +iap_entry: > >> + ldr r2, IAP_ADDRESS > >> + bx r2 > >> + mov pc, lr > >> > > Verbatim copy of arch/arm/cpu/arm720t/lpc2292/iap_entry.S - please > > unify. > > > Can you give a hint on how I should accomplish that? Copy the > iap_netry.S to the parent directiry? If the code is generic to all arm720t systems, then moving it to the parent dir world be ok; otherwise it might make sense to put the common code into arch/arm/cpu/arm720t/lpc2xxx or so. > >> +#ifndef __ASM_ARCH_HARDWARE_H > >> +#define __ASM_ARCH_HARDWARE_H > >> + > >> +/* > >> > > ... > > > >> + */ > >> + > >> +#if defined(CONFIG_LPC2468) > >> +#else > >> +#error No hardware file defined for this configuration > >> +#endif > >> + > >> +#endif /* __ASM_ARCH_HARDWARE_H */ > >> > > Do we really need such an empty file? > > > > Yes, start.S needs this file, but since my code uses C structures, it's > empty. Maybe start.S can be fixed so it does not need this file? > > Do we _really_ need all this? > > Yes and no. Not all H/W is used. That may well change in > the future as more peripherals are supported. I do also believe As long as nobody uses this, the code makes no sense, especially as it's only place holders. Drop it. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Witch! Witch! They'll burn ya! -- Hag, "Tomorrow is Yesterday", stardate unknown ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MPC5200: workaround data corruption for unaligned local bus accesses
The MPC5200 has a nasty problem that will cause silent data corruption
when performing unaligned 16 or 32 byte accesses when reading from the
local bus - typically this affects reading from flash. The problem can
be easily shown:
=> md fc0c 10
fc0c: 323e4337 01626f6f 74636d64 3d72756e2>C7.bootcmd=run
fc0c0010: 206e6574 5f6e6673 00626f6f 7464656c net_nfs.bootdel
fc0c0020: 61793d35 00626175 64726174 653d3131ay=5.baudrate=11
fc0c0030: 35323030 00707265 626f6f74 3d6563685200.preboot=ech
=> md fc0c0001 10
fc0c0001: 65636801 0074 003d 0020echt...=...
fc0c0011: 005f 0074 0061..._...t...a
fc0c0021: 0064 0065 0035...d...e...5
fc0c0031: 0062 003d 006f...b...=...o
=> md.w fc0c0001 10
fc0c0001: 3701 6f74 643d 6e20..7...ot..d=..n
fc0c0011: 745f 7300 6f74 6c61..t_..s...ot..la
This commit implements a workaround at least for the most blatant
problem: using memcpy() from NOR flash. We rename the assembler
routine into __memcpy() and provide a wrapper, which will use a
byte-wise copy loop for source addresses in NOR flash, and branch to
the optimized __memcpy() otherwise.
Signed-off-by: Wolfgang Denk
---
arch/powerpc/cpu/mpc5xxx/Makefile |5 ++
arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c | 62 +
arch/powerpc/lib/Makefile |5 ++
3 files changed, 72 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c
diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile
b/arch/powerpc/cpu/mpc5xxx/Makefile
index 0ee0611..4ab2b7b 100644
--- a/arch/powerpc/cpu/mpc5xxx/Makefile
+++ b/arch/powerpc/cpu/mpc5xxx/Makefile
@@ -30,6 +30,11 @@ SOBJS= io.o firmware_sc_task_bestcomm.impl.o
COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \
loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
+# Workaround for local bus unaligned access problem on MPC5200
+#ifdef CONFIG_MPC5200
+COBJS += memcpy_mpc5200.o
+#endif
+
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c
b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c
new file mode 100644
index 000..5c2e64f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2010
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This is a workaround for issues on the MPC5200, where unaligned
+ * 32-bit-accesses to the local bus will deliver corrupted data. This
+ * happens for example when trying to use memcpy() from an odd NOR
+ * flash address; the behaviour can be also seen when using "md" on an
+ * odd NOR flash address (but there it is not a bug in U-Boot, which
+ * only shows the behaviour of this processor).
+ *
+ * For memcpy(), we test if the source address is in NOR flash, and
+ * perform byte-wise (slow) copy then; otherwise we use the optimized
+ * (fast) real __memcpy().
+ */
+
+#include
+#include
+#include
+
+void *memcpy(void *trg, const void *src, size_t len)
+{
+ extern void* __memcpy(void *, const void *, size_t);
+ char *s = (char *)src;
+ char *t = (char *)trg;
+ void *dest = src;
+
+ /*
+* Check is source address is in flash:
+* If not, we use the fast assembler code
+*/
+ if (addr2info((ulong)src) == NULL)
+ return __memcpy(trg, src, len);
+
+ /*
+* Copying from flash, perform byte by byte copy.
+*/
+ while (len-- > 0)
+ *t++ = *s++;
+
+ return dest;
+}
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 5f85502..4ba51b3 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -43,6 +43,11 @@ COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+# Workaround for local bus unaligned access problem on MPC5200
+#ifdef CONFIG_MPC5200
+$(obj)ppcstring.o: AF
[U-Boot] [PATCH] Fix wrong orion5x MPP and GIPO writel arguments
Signed-off-by: Albert Aribaud --- Orion5x MPP and GPIO setting code had writel arguments the wrong way around. Fixed and tested. arch/arm/cpu/arm926ejs/orion5x/cpu.c |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index c2f5253..03c6d06 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -260,10 +260,10 @@ int arch_misc_init(void) /* Set CPIOs and MPPs - values provided by board include file */ - writel(ORION5X_MPP_BASE+0x00, ORION5X_MPP0_7); - writel(ORION5X_MPP_BASE+0x04, ORION5X_MPP8_15); - writel(ORION5X_MPP_BASE+0x50, ORION5X_MPP16_23); - writel(ORION5X_GPIO_BASE+0x04, ORION5X_GPIO_OUT_ENABLE); + writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00); + writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04); + writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); + writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); return 0; } -- 1.6.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] microblaze: generic: enable FDT support
Signed-off-by: Stephan Linz --- include/configs/microblaze-generic.h |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 28cee47..89e6dbb 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -305,4 +305,12 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 + +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + + #endif /* __CONFIG_H */ -- 1.6.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] microblaze: enable LMB support
Foresighted to support flat device tree realocations we need to use the new Logical memory blocks library in a manner as been used by all other architectures. Signed-off-by: Stephan Linz --- arch/microblaze/include/asm/config.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 8a9064b..ec2c316 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -21,6 +21,8 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_LMB + /* Relocation to SDRAM works on all Microblaze boards */ #define CONFIG_RELOC_FIXUP_WORKS -- 1.6.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] microblaze: generic: rename MTD partition set to 'flash-0'
Signed-off-by: Stephan Linz
---
include/configs/microblaze-generic.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/microblaze-generic.h
b/include/configs/microblaze-generic.h
index c9ee76e..28cee47 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -260,10 +260,10 @@
#define CONFIG_CMD_MTDPARTS/* mtdparts command line support */
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=ml401-0"
+#define MTDIDS_DEFAULT "nor0=flash-0"
/* default mtd partition table */
-#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
+#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
"256k(env),3m(kernel),1m(romfs),"\
"1m(cramfs),-(jffs2)"
#endif
@@ -292,8 +292,8 @@
#defineCONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv
preboot;echo"
#defineCONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware
flash protection */\
- "nor0=ml401-0\0"\
- "mtdparts=mtdparts=ml401-0:"\
+ "nor0=flash-0\0"\
+ "mtdparts=mtdparts=flash-0:"\
"256k(u-boot),256k(env),3m(kernel),"\
"1m(romfs),1m(cramfs),-(jffs2)\0"
--
1.6.0.4
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] microblaze: generic: adding DHCP support
Signed-off-by: Stephan Linz --- include/configs/microblaze-generic.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 9b1569a..c9ee76e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -231,6 +231,7 @@ #undef CONFIG_CMD_NET #else #define CONFIG_CMD_PING + #define CONFIG_CMD_DHCP #endif #if defined(CONFIG_SYSTEMACE) -- 1.6.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] microblaze: generic: adding DHCP support
On Monday, June 21, 2010 16:58:09 Stephan Linz wrote: > #define CONFIG_CMD_PING > + #define CONFIG_CMD_DHCP > #endif not specific to this commit, but preprocessor statements really shouldnt be intended like this - #define FOO +# define FOO -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] microblaze: generic: adding DHCP support
Am Montag, 21. Juni 2010 23:21:02 schrieb Mike Frysinger: > On Monday, June 21, 2010 16:58:09 Stephan Linz wrote: > > #define CONFIG_CMD_PING > > + #define CONFIG_CMD_DHCP > > #endif > > not specific to this commit, but preprocessor statements really shouldnt be > intended like this > - #define FOO > +#define FOO > -mike You're right. But I modified only a small pices and not the whole file. -- Viele Grüße, Stephan Linz __ OpenDCC: http://www.li-pro.net/opendcc.phtml PC/M: http://www.li-pro.net/pcm.phtml CDK4AVR: http://cdk4avr.sourceforge.net/ CDK4NIOS: http://cdk4nios.sourceforge.net/ CDK4MSP: http://cdk4msp.sourceforge.net/ CPM4L: http://download.opensuse.org/repositories/home:/rexut:/CPM4L ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/6] Add support for TI OMAP4 SDP and Panda
This is version 4, which takes into account all feedback to date, and has
been rebased on the next branch.
The folowing series adds support for two boards based upon the TI
OMAP4430. The OMAP4430 is a Cortex-A9 based SOC from TI.
The first patch in this series renames the cpu arm_cortexa8 to armv7 so
that the existing cortex A8 code can be shared with cortex A9. Both A8 and
A9 are based on ARMV7 architecture.
The 2nd patch adds basic OMAP4 architecture support.
The 3rd patch restructures the OMAP mmc driver code so that it can be
shared by both OMAP3 and OMAP4 boards. This patch depends on a previously
submitted patch (OMAP: mmc: add support for second and third mmc channel):
http://www.mail-archive.com/u-boot@lists.denx.de/msg31765.html
The 4th patch restructures the OMAP i2c code so that it can be shared by
both OMAP3 and OMAP4 boards.
And, finally, the 5th and 6th patches add board support for Panda and SDP.
I build tested each step of the series for all ARMV7 boards (devkit8000
mx51evk omap3_beagle omap3_overo omap3_evm omap3_pandora omap3_sdp3430
omap3_zoom1 omap3_zoom2 smdkc100)
I did a run test at each step of the series for Overo to verify no
regressions on an existing board. Of couse I also run test the final two
steps of the series on SDP and Panda.
---
Steve Sakoman (6):
ARM: Rename arch/arm/cpu/arm_cortexa8 to armv7
ARMV7: Add basic support for TI OMAP4
ARMV7: Restructure OMAP mmc driver to allow code sharing between
OMAP3 and OMAP4
ARMV7: Restructure OMAP i2c driver to allow code sharing between
OMAP3 and OMAP4
ARMV7: Add support for TI OMAP4430 SDP
ARMV7: Add support for TI OMAP4 Panda
MAINTAINERS| 24 ++-
MAKEALL| 10 +-
Makefile |7 +
arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile |0
arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk |0
arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c |0
.../{arm_cortexa8 => armv7}/mx51/lowlevel_init.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c|0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c |0
.../cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds|2 +-
.../mx51 => armv7/omap-common}/Makefile| 10 +-
.../{arm_cortexa8 => armv7/omap-common}/config.mk |0
.../omap3 => armv7/omap-common}/reset.S|0
.../omap3 => armv7/omap-common}/timer.c|5 +
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile |2 -
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/emif4.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c |0
.../{arm_cortexa8 => armv7}/omap3/lowlevel_init.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sdrc.c |0
.../cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c |0
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c |0
.../{arm_cortexa8/s5pc1xx => armv7/omap4}/Makefile | 16 +-
arch/arm/cpu/armv7/omap4/board.c | 90
.../omap3/reset.S => armv7/omap4/lowlevel_init.S} | 40 +++--
.../omap3/reset.S => armv7/omap4/sys_info.c} | 50 +++--
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile |0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S|2 +-
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c|0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c |0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S|0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c|0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c|0
arch/arm/cpu/{arm_cortexa8 => armv7}/start.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds|2 +-
arch/arm/include/asm/arch-mx51/asm-offsets.h |2 +-
arch/arm/include/asm/arch-omap3/i2c.h | 149 +-
arch/arm/include/asm/arch-omap4/cpu.h | 94 +
arch/arm/include/asm/arch-omap4/i2c.h | 74 +++
arch/arm/include/asm/arch-omap4/mmc_host_def.h | 171 +++
arch/arm/include/asm/arch-omap4/omap4.h| 118 +++
.../reset.S => include/asm/arch-omap4/sys_proto.h} | 35 ++--
board/logicpd/zoom2/zoom2.c|2 +-
.../cpu/arm_cortexa8 => board/ti/panda}/Makefile | 24 ++-
.../cpu/arm_cortexa8 => board/ti/panda}/config.mk | 25 +--
.../u-boot.lds => board/ti/panda/panda.c | 65 +++---
.../cpu/arm_cortexa8 => board/ti/sdp4430}/Makefile | 24 ++-
.../arm_c
[U-Boot] [PATCH v4 1/6] ARM: Rename arch/arm/cpu/arm_cortexa8 to armv7
The purpose of this patch is to prepare for adding the OMAP4 architecture,
which is Cortex A9
Cortex A8 and A9 both belong to the armv7 architecture, hence the name change.
The two architectures are similar enough that substantial code can be shared.
Signed-off-by: Aneesh V
Signed-off-by: Steve Sakoman
---
MAINTAINERS| 22 ++--
MAKEALL|8 +++---
arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile |0
arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk |0
arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c |0
.../{arm_cortexa8 => armv7}/mx51/lowlevel_init.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c|0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c |0
.../cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds|2 +-
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/emif4.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c |0
.../{arm_cortexa8 => armv7}/omap3/lowlevel_init.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sdrc.c |0
.../cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c |0
.../arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c |0
arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c |0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile |0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S|2 +-
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c|0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c |0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S|0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c|0
.../cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c|0
arch/arm/cpu/{arm_cortexa8 => armv7}/start.S |0
arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds|2 +-
arch/arm/include/asm/arch-mx51/asm-offsets.h |2 +-
board/logicpd/zoom2/zoom2.c|2 +-
boards.cfg | 20 +-
include/configs/am3517_evm.h |2 +-
include/configs/devkit8000.h |2 +-
include/configs/omap3_beagle.h |2 +-
include/configs/omap3_evm.h|2 +-
include/configs/omap3_pandora.h|2 +-
include/configs/omap3_sdp3430.h|2 +-
include/configs/omap3_zoom1.h |2 +-
include/configs/omap3_zoom2.h |2 +-
include/configs/s5p_goni.h |2 +-
include/configs/smdkc100.h |2 +-
48 files changed, 40 insertions(+), 40 deletions(-)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds (97%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/emif4.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/lowlevel_init.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sdrc.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile (100%)
rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S (
[U-Boot] [PATCH v4 3/6] ARMV7: Restructure OMAP mmc driver to allow code sharing between OMAP3 and OMAP4
The architecture independent header is moved to drivers/mmc, and the
architecture
dependent headers reside in asm/arch-omap3 and asm/arch-omap4
Signed-off-by: Steve Sakoman
---
arch/arm/include/asm/arch-omap4/mmc_host_def.h | 171
drivers/mmc/omap3_mmc.c| 13 +-
.../arch-omap3/mmc.h => drivers/mmc/omap3_mmc.h|2 +-
3 files changed, 181 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/include/asm/arch-omap4/mmc_host_def.h
rename arch/arm/include/asm/arch-omap3/mmc.h => drivers/mmc/omap3_mmc.h (99%)
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
new file mode 100644
index 000..e5d8b53
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments,
+ * Syed Mohammed Khasim
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE 0x4809C100
+#define OMAP_HSMMC2_BASE 0x480B4100
+#define OMAP_HSMMC3_BASE 0x480AD100
+
+typedef struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate;/* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl;/* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie;/* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+} hsmmc_t;
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN(0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT(0x0 << 1)
+#define INIT_INITSTREAM(0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO(0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD(0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT(0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE(0x0 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET(4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define RSP_TYPE_OFFSET(16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48(0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK(0x1 << 21)
+#define DP_NO_DATA
[U-Boot] [PATCH v4 4/6] ARMV7: Restructure OMAP i2c driver to allow code sharing between OMAP3 and OMAP4
This patch modifies the omap24xx driver so that it will also work with OMAP4.
Signed-off-by: Steve Sakoman
---
arch/arm/include/asm/arch-omap3/i2c.h | 149 +---
arch/arm/include/asm/arch-omap4/i2c.h | 74 ++
drivers/i2c/omap24xx_i2c.c | 17 ++-
.../arch-omap3/i2c.h => drivers/i2c/omap24xx_i2c.h | 45 +--
4 files changed, 96 insertions(+), 189 deletions(-)
create mode 100644 arch/arm/include/asm/arch-omap4/i2c.h
copy arch/arm/include/asm/arch-omap3/i2c.h => drivers/i2c/omap24xx_i2c.h (85%)
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h
b/arch/arm/include/asm/arch-omap3/i2c.h
index 490e03b..7a4a73a 100644
--- a/arch/arm/include/asm/arch-omap3/i2c.h
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -20,9 +20,10 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _OMAP3_I2C_H_
+#define _OMAP3_I2C_H_
+#define I2C_BUS_MAX3
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
@@ -58,146 +59,4 @@ struct i2c {
unsigned short res15;
};
-#define I2C_BUS_MAX3
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_GC_IE (1 << 5)
-#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_SBD (1 << 15) /* Single byte data */
-#define I2C_STAT_BB(1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1 << 9) /* Address as slave */
-#define I2C_STAT_GC(1 << 5)
-#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL(1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK 7
-#define I2C_INTCODE_NONE 0
-#define I2C_INTCODE_AL 1 /* Arbitration lost */
-#define I2C_INTCODE_NAK2 /* No acknowledgement/general
call */
-#define I2C_INTCODE_ARDY 3 /* Register access ready */
-#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
-#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
-
-/* I2C Buffer Configuration Register (I2C_BUF): */
-
-#define I2C_BUF_RDMA_EN(1 << 15) /* Receive DMA channel enable
*/
-#define I2C_BUF_XDMA_EN(1 << 7) /* Transmit DMA channel
enable */
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN (1 << 15) /* I2C module enable */
-#define I2C_CON_BE (1 << 14) /* Big endian mode */
-#define I2C_CON_STB(1 << 11) /* Start byte mode (master mode only) */
-#define I2C_CON_MST(1 << 10) /* Master/slave mode */
-#define I2C_CON_TRX(1 << 9) /* Transmitter/receiver mode */
- /* (master mode only) */
-#define I2C_CON_XA (1 << 8) /* Expand address */
-#define I2C_CON_STP(1 << 1) /* Stop condition (master mode only) */
-#define I2C_CON_STT(1 << 0) /* Start condition (master mode only) */
-
-/* I2C System Test Register (I2C_SYSTEST): */
-
-#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
-#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
-#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
-#define I2C_SYSTEST_TMODE_SHIFT(12) /* Test mode select */
-#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
-#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
-#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
-#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
-
-#define I2C_SCLL_SCLL 0
-#define I2C_SCLL_SCLL_M0xFF
-#define I2C_SCLL_HSSCLL8
-#define I2C_SCLH_HSSCLL_M 0xFF
-#define I2C_SCLH_SCLH 0
-#define I2C_SCLH_SCLH_M0xFF
-#define I2C_SCLH_HSSCLH8
-#define I2C_SCLH_HSSCLH_M 0xFF
-
-#define OMAP_I2C_STANDARD 10
-#define OMAP_I2C_FAST_MODE 40
-#define OMAP_I2C_HIGH_SPEED340
-
-#define SYSTEM_CLOCK_121200
-#define SYSTEM_CLOCK_131300
-#define SYSTEM_CLOCK_192 1920
-#define SYSTEM_CLOCK_969600
-
-/* Use the reference value of 96MHz if not explicitly set by the board */
-#ifndef I2C_
[U-Boot] [PATCH v4 2/6] ARMV7: Add basic support for TI OMAP4
This patch adds minimum support for OMAP4. Code which can be shared
between OMAP3 and OMAP4 is placed in arch/arm/cpu/armv7/omap-common
Signed-off-by: Aneesh V
Signed-off-by: Steve Sakoman
---
Makefile |7 +
arch/arm/cpu/armv7/{omap3 => omap-common}/Makefile | 22 +---
arch/arm/cpu/armv7/omap-common/config.mk | 33 ++
arch/arm/cpu/armv7/{omap3 => omap-common}/reset.S |0
arch/arm/cpu/armv7/{omap3 => omap-common}/timer.c |5 +
arch/arm/cpu/armv7/omap3/Makefile |2 -
arch/arm/cpu/armv7/{omap3 => omap4}/Makefile | 16 +--
arch/arm/cpu/armv7/omap4/board.c | 90 +++
.../armv7/{omap3/reset.S => omap4/lowlevel_init.S} | 40 +---
.../cpu/armv7/{omap3/reset.S => omap4/sys_info.c} | 50 ++---
arch/arm/include/asm/arch-omap4/cpu.h | 94
arch/arm/include/asm/arch-omap4/omap4.h| 118
.../reset.S => include/asm/arch-omap4/sys_proto.h} | 35 +++---
13 files changed, 433 insertions(+), 79 deletions(-)
copy arch/arm/cpu/armv7/{omap3 => omap-common}/Makefile (77%)
create mode 100644 arch/arm/cpu/armv7/omap-common/config.mk
copy arch/arm/cpu/armv7/{omap3 => omap-common}/reset.S (100%)
rename arch/arm/cpu/armv7/{omap3 => omap-common}/timer.c (96%)
copy arch/arm/cpu/armv7/{omap3 => omap4}/Makefile (81%)
create mode 100644 arch/arm/cpu/armv7/omap4/board.c
copy arch/arm/cpu/armv7/{omap3/reset.S => omap4/lowlevel_init.S} (65%)
copy arch/arm/cpu/armv7/{omap3/reset.S => omap4/sys_info.c} (60%)
create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h
create mode 100644 arch/arm/include/asm/arch-omap4/omap4.h
rename arch/arm/{cpu/armv7/omap3/reset.S =>
include/asm/arch-omap4/sys_proto.h} (64%)
diff --git a/Makefile b/Makefile
index 3e11f6f..e520ec4 100644
--- a/Makefile
+++ b/Makefile
@@ -244,6 +244,13 @@ LIBS += lib/libfdt/libfdt.a
LIBS += api/libapi.a
LIBS += post/libpost.a
+ifeq ($(SOC),omap3)
+LIBS += $(CPUDIR)/omap-common/libomap-common.a
+endif
+ifeq ($(SOC),omap4)
+LIBS += $(CPUDIR)/omap-common/libomap-common.a
+endif
+
LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
diff --git a/arch/arm/cpu/armv7/omap3/Makefile
b/arch/arm/cpu/armv7/omap-common/Makefile
similarity index 77%
copy from arch/arm/cpu/armv7/omap3/Makefile
copy to arch/arm/cpu/armv7/omap-common/Makefile
index 7d63c6b..3a4a304 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -23,27 +23,15 @@
include $(TOPDIR)/config.mk
-LIB= $(obj)lib$(SOC).a
+LIB= $(obj)libomap-common.a
-SOBJS := lowlevel_init.o
-SOBJS += cache.o
-SOBJS += reset.o
-
-COBJS += board.o
-COBJS += clock.o
-COBJS += gpio.o
-COBJS += mem.o
-COBJS += syslib.o
-COBJS += sys_info.o
-COBJS += timer.o
-
-COBJS-$(CONFIG_EMIF4) += emif4.o
-COBJS-$(CONFIG_SDRC) += sdrc.o
+SOBJS := reset.o
+COBJS := timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-all:$(obj).depend $(LIB)
+all: $(obj).depend $(LIB)
$(LIB):$(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
diff --git a/arch/arm/cpu/armv7/omap-common/config.mk
b/arch/arm/cpu/armv7/omap-common/config.mk
new file mode 100644
index 000..49ac9c7
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering,
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
+# =
+#
+# Supply options according to compiler version
+#
+# =
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+ $(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/armv7/omap3/reset.S
b/arch/arm/cpu/armv7/omap-common/reset.S
similarity index 100%
copy from arch/arm/cpu/armv7/
[U-Boot] [PATCH v4 6/6] ARMV7: Add support for TI OMAP4 Panda
OMAP4 Panda is a reference board based on OMAP4430, an ARMV7 Cortex A9 CPU This patch adds basic support for booting the board. It includes i2c and mmc support. It assumes U-boot is loaded to SDRAM with the help of another small bootloader (x-load) running from SRAM. U-boot currently relies on x-load for clock, mux, and SDRAM initialization Signed-off-by: Steve Sakoman --- MAINTAINERS |1 + MAKEALL |1 + board/ti/panda/Makefile | 49 + board/ti/panda/config.mk | 32 ++ board/ti/panda/panda.c| 61 +++ boards.cfg|1 + include/configs/omap4_panda.h | 220 + 7 files changed, 365 insertions(+), 0 deletions(-) create mode 100644 board/ti/panda/Makefile create mode 100644 board/ti/panda/config.mk create mode 100644 board/ti/panda/panda.c create mode 100644 include/configs/omap4_panda.h diff --git a/MAINTAINERS b/MAINTAINERS index 36327ed..a5db970 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -756,6 +756,7 @@ Nomadik Linux Team Steve Sakoman omap3_overo ARM ARMV7 (OMAP3xx SoC) + omap4_panda ARM ARMV7 (OMAP4xx SoC) omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC) Jens Scharsig diff --git a/MAKEALL b/MAKEALL index 6acd69d..5413f6d 100755 --- a/MAKEALL +++ b/MAKEALL @@ -654,6 +654,7 @@ LIST_ARMV7="\ omap3_sdp3430 \ omap3_zoom1 \ omap3_zoom2 \ + omap4_panda \ omap4_sdp4430 \ s5p_goni\ smdkc100\ diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile new file mode 100644 index 000..81e5469 --- /dev/null +++ b/board/ti/panda/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := panda.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk new file mode 100644 index 000..7382263 --- /dev/null +++ b/board/ti/panda/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments Incorporated, +# +# OMAP 4430 SDP +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# SDRAM Address Space: +# 8000' - 9fff' (512 MB) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# Let's place u-boot 1MB before the end of SDRAM. +TEXT_BASE = 0x9ff0 diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c new file mode 100644 index 000..46a5d1d --- /dev/null +++ b/board/ti/panda/panda.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, + * Steve Sakoman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free s
[U-Boot] [PATCH v4 5/6] ARMV7: Add support for TI OMAP4430 SDP
OMAP4430 SDP is a reference board based on OMAP4430, an ARMV7 Cortex A9 CPU This patch adds basic support for booting the board. It includes i2c and mmc support. It assumes U-boot is loaded to SDRAM with the help of another small bootloader (x-load) running from SRAM. U-boot currently relies on x-load for clock, mux, and SDRAM initialization Signed-off-by: Aneesh V Signed-off-by: Steve Sakoman --- MAINTAINERS |1 + MAKEALL |1 + board/ti/sdp4430/Makefile | 49 + board/ti/sdp4430/config.mk | 32 ++ board/ti/sdp4430/sdp.c | 62 +++ boards.cfg |1 + include/configs/omap4_sdp4430.h | 221 +++ 7 files changed, 367 insertions(+), 0 deletions(-) create mode 100644 board/ti/sdp4430/Makefile create mode 100644 board/ti/sdp4430/config.mk create mode 100644 board/ti/sdp4430/sdp.c create mode 100644 include/configs/omap4_sdp4430.h diff --git a/MAINTAINERS b/MAINTAINERS index bce4bcc..36327ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -756,6 +756,7 @@ Nomadik Linux Team Steve Sakoman omap3_overo ARM ARMV7 (OMAP3xx SoC) + omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC) Jens Scharsig diff --git a/MAKEALL b/MAKEALL index d8510f6..6acd69d 100755 --- a/MAKEALL +++ b/MAKEALL @@ -654,6 +654,7 @@ LIST_ARMV7="\ omap3_sdp3430 \ omap3_zoom1 \ omap3_zoom2 \ + omap4_sdp4430 \ s5p_goni\ smdkc100\ " diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile new file mode 100644 index 000..2554c7b --- /dev/null +++ b/board/ti/sdp4430/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := sdp.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk new file mode 100644 index 000..7382263 --- /dev/null +++ b/board/ti/sdp4430/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments Incorporated, +# +# OMAP 4430 SDP +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# SDRAM Address Space: +# 8000' - 9fff' (512 MB) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# Let's place u-boot 1MB before the end of SDRAM. +TEXT_BASE = 0x9ff0 diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c new file mode 100644 index 000..6ae016c --- /dev/null +++ b/board/ti/sdp4430/sdp.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, + * Aneesh V + * Steve Sakoman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free soft
Re: [U-Boot] TOT u-boot makes P1020RDB unbootable
> -Original Message- > From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] > On Behalf Of Wolfgang Denk > Sent: Monday, June 21, 2010 4:25 PM > To: Aggrwal Poonam-B10812 > Cc: U-Boot-Denx; Kumar Gala > Subject: Re: [U-Boot] TOT u-boot makes P1020RDB unbootable > > Dear "Aggrwal Poonam-B10812", > > In message > <8660da277dc57b4baac78225f03146b6b08...@zin33exm24.fsl.freescale.net> you > wrote: > > There are few changes which need to be done for RevD and are not in > TOT. > > > > I will send the patches for it soon. > > Please hurry up. There is not much time left before the release. > I am right now testing it, will send the patch ASAP. Regards Poonam > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de > "Beware of programmers carrying screwdrivers." - Chip Salzenberg > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
