[U-Boot] [PATCH v7 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
Changes for v2:
- None
Changes for v3:
- None
Changes for V4:
- Added CONFIG_SYS_CLK_FREQ to trats.h
Changes for v5:
- None
Changes for v6:
- None
Changes for v7:
- None
arch/arm/cpu/armv7/exynos/clock.c |6 +-
include/configs/s5pc210_universal.h |1 +
include/configs/trats.h |1 +
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 0c199cd..4d92c53 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,10 +26,6 @@
#include asm/arch/clock.h
#include asm/arch/clk.h
-#ifndef CONFIG_SYS_CLK_FREQ_C210
-#define CONFIG_SYS_CLK_FREQ_C210 2400
-#endif
-
/* exynos4: return pll clock frequency */
static unsigned long exynos4_get_pll_clk(int pllreg)
{
@@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
/* SDIV [2:0] */
s = r 0x7;
- freq = CONFIG_SYS_CLK_FREQ_C210;
+ freq = CONFIG_SYS_CLK_FREQ;
if (pllreg == EPLL) {
k = k 0x;
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index be000cb..8286680 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -49,6 +49,7 @@
/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 2400
+#define CONFIG_SYS_CLK_FREQCONFIG_SYS_CLK_FREQ_C210
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
diff --git a/include/configs/trats.h b/include/configs/trats.h
index acb3241..10f11d9 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -49,6 +49,7 @@
/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 2400
+#define CONFIG_SYS_CLK_FREQCONFIG_SYS_CLK_FREQ_C210
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
--
1.7.5.4
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[U-Boot] [PATCH v7 0/4] Add SMDK5250 board support
This patchset add support for Samsung's SMDK5250 board based on EXYNOS5250 based SoC. It also adds support for MMC SPL booting. The porting is done by Samsung engineers at HQ in System LSI Team. I am contributing in upstreaming the code for the board. Based upon discussions following patches are dropped in this version: Exynos: Add CONFIG_EXYNOS4 Macro to EXYNOS4 based boards Exynos: Clock.c: Replace exynos4 prefix with exynos SMDK5250: enable device tree support is squashed with EXYNOS: Add SMDK5250 board support Chander Kashyap (4): Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro ARM: EXYNOS: Add support for Exynos5 based SoCs EXYNOS: Add SMDK5250 board support EXYNOS: SMDK5250: Add MMC SPL support MAINTAINERS |1 + arch/arm/cpu/armv7/exynos/clock.c | 214 +++- arch/arm/include/asm/arch-exynos/clock.h | 326 ++ arch/arm/include/asm/arch-exynos/cpu.h| 35 ++- arch/arm/include/asm/arch-exynos/dmc.h| 146 arch/arm/include/asm/arch-exynos/gpio.h | 99 +- arch/arm/include/asm/arch-exynos/tzpc.h | 52 +++ board/samsung/smdk5250/Makefile | 67 board/samsung/smdk5250/clock_init.c | 202 +++ board/samsung/smdk5250/dmc_init.c | 453 + board/samsung/smdk5250/lowlevel_init.S| 96 ++ board/samsung/smdk5250/mmc_boot.c | 58 board/samsung/smdk5250/setup.h| 448 board/samsung/smdk5250/smdk5250.c | 146 board/samsung/smdk5250/tools/mkexynos_image.c | 117 +++ board/samsung/smdk5250/tzpc_init.c| 48 +++ boards.cfg|1 + include/configs/s5pc210_universal.h |1 + include/configs/smdk5250.h| 197 +++ include/configs/trats.h |1 + 20 files changed, 2691 insertions(+), 17 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/dmc.h create mode 100644 arch/arm/include/asm/arch-exynos/tzpc.h create mode 100644 board/samsung/smdk5250/Makefile create mode 100644 board/samsung/smdk5250/clock_init.c create mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/lowlevel_init.S create mode 100644 board/samsung/smdk5250/mmc_boot.c create mode 100644 board/samsung/smdk5250/setup.h create mode 100644 board/samsung/smdk5250/smdk5250.c create mode 100644 board/samsung/smdk5250/tools/mkexynos_image.c create mode 100644 board/samsung/smdk5250/tzpc_init.c create mode 100644 include/configs/smdk5250.h -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7 2/4] ARM: EXYNOS: Add support for Exynos5 based SoCs
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
Changes for v2:
- This patch was part of EXYNOS: Add SMDK5250 board support
- Now it is seprated as SoC support.
Changes for v3:
- Populated complete exynos5 gpio structures
Changes for v4:
- Added dmc.h and tzpc.h header files
- Renamed EXYNOS5_PHY*_CTRL_BASE to EXYNOS5_DMC_PHY*_BASE
Changes for v5:
- None
Changes for v6:
- None
Changes for v7:
- None
arch/arm/cpu/armv7/exynos/clock.c| 208 +++-
arch/arm/include/asm/arch-exynos/clock.h | 326 ++
arch/arm/include/asm/arch-exynos/cpu.h | 35 +++-
arch/arm/include/asm/arch-exynos/dmc.h | 146 +
arch/arm/include/asm/arch-exynos/gpio.h | 99 +-
arch/arm/include/asm/arch-exynos/tzpc.h | 52 +
6 files changed, 854 insertions(+), 12 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/dmc.h
create mode 100644 arch/arm/include/asm/arch-exynos/tzpc.h
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 4d92c53..2f7048b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -92,6 +92,72 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
return fout;
}
+/* exynos5: return pll clock frequency */
+static unsigned long exynos5_get_pll_clk(int pllreg)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(clk-apll_con0);
+ break;
+ case MPLL:
+ r = readl(clk-mpll_con0);
+ break;
+ case EPLL:
+ r = readl(clk-epll_con0);
+ k = readl(clk-epll_con1);
+ break;
+ case VPLL:
+ r = readl(clk-vpll_con0);
+ k = readl(clk-vpll_con1);
+ break;
+ default:
+ printf(Unsupported PLL (%d)\n, pllreg);
+ return 0;
+ }
+
+ /*
+* APLL_CON: MIDV [25:16]
+* MPLL_CON: MIDV [25:16]
+* EPLL_CON: MIDV [24:16]
+* VPLL_CON: MIDV [24:16]
+*/
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r 16) mask;
+
+ /* PDIV [13:8] */
+ p = (r 8) 0x3f;
+ /* SDIV [2:0] */
+ s = r 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ;
+
+ if (pllreg == EPLL) {
+ k = k 0x;
+ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 65536) * (freq / (p * (1 s)));
+ } else if (pllreg == VPLL) {
+ k = k 0xfff;
+ /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 1024) * (freq / (p * (1 s)));
+ } else {
+ if (s 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 (s - 1;
+ }
+
+ return fout;
+}
+
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@@ -114,6 +180,28 @@ static unsigned long exynos4_get_arm_clk(void)
return armclk;
}
+/* exynos5: return ARM clock frequency */
+static unsigned long exynos5_get_arm_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long armclk;
+ unsigned int arm_ratio;
+ unsigned int arm2_ratio;
+
+ div = readl(clk-div_cpu0);
+
+ /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
+ arm_ratio = (div 0) 0x7;
+ arm2_ratio = (div 28) 0x7;
+
+ armclk = get_pll_clk(APLL) / (arm_ratio + 1);
+ armclk /= (arm2_ratio + 1);
+
+ return armclk;
+}
+
/* exynos4: return pwm clock frequency */
static unsigned long exynos4_get_pwm_clk(void)
{
@@ -157,6 +245,27 @@ static unsigned long exynos4_get_pwm_clk(void)
return pclk;
}
+/* exynos5: return pwm clock frequency */
+static unsigned long exynos5_get_pwm_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int ratio;
+
+ /*
+* CLK_DIV_PERIC3
+* PWM_RATIO [3:0]
+*/
+ ratio = readl(clk-div_peric3);
+ ratio = ratio 0xf;
+ sclk = get_pll_clk(MPLL);
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@@ -204,6 +313,53 @@ static unsigned long
[U-Boot] [PATCH v7 4/4] EXYNOS: SMDK5250: Add MMC SPL support
This patch adds support for MMC SPL booting.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
---
Changes for v2:
- None
Changes for v3:
- None
Changes for v4:
- None
Changes for v5:
- None
Changes for v6:
- None
Changes for v7:
- None
board/samsung/smdk5250/Makefile | 16
board/samsung/smdk5250/mmc_boot.c | 58
board/samsung/smdk5250/tools/mkexynos_image.c | 117 +
include/configs/smdk5250.h|7 ++
4 files changed, 198 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/mmc_boot.c
create mode 100644 board/samsung/smdk5250/tools/mkexynos_image.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 80e8be3..9bba6e7 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -29,18 +29,34 @@ SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
+
+ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+COBJS += mmc_boot.o
+endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
ALL:= $(obj).depend $(LIB)
+ifdef CONFIG_SPL_BUILD
+ALL+= $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
all: $(ALL)
$(LIB):$(OBJS)
$(call cmd_link_o_target, $(OBJS))
+ifdef CONFIG_SPL_BUILD
+$(OBJTREE)/tools/mk$(BOARD)spl:tools/mkexynos_image.c
+ $(HOSTCC) tools/mkexynos_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
#
# defines $(obj).depend target
diff --git a/board/samsung/smdk5250/mmc_boot.c
b/board/samsung/smdk5250/mmc_boot.c
new file mode 100644
index 000..449a919
--- /dev/null
+++ b/board/samsung/smdk5250/mmc_boot.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#includecommon.h
+#includeconfig.h
+
+/*
+* Copy U-boot from mmc to RAM:
+* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
+* Pointer to API (Data transfer from mmc to ram)
+*/
+void copy_uboot_to_ram(void)
+{
+ u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+
+ copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+}
+
+void board_init_f(unsigned long bootflag)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+ copy_uboot_to_ram();
+
+ /* Jump to U-Boot image */
+ uboot = (void *)CONFIG_SYS_TEXT_BASE;
+ (*uboot)();
+ /* Never returns Here */
+}
+
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+ /* Function attribute is no-return */
+ /* This Function never executes */
+ while (1)
+ ;
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/smdk5250/tools/mkexynos_image.c
b/board/samsung/smdk5250/tools/mkexynos_image.c
new file mode 100644
index 000..3159e7c
--- /dev/null
+++ b/board/samsung/smdk5250/tools/mkexynos_image.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include stdio.h
+#include stdlib.h
+#include unistd.h
+#include fcntl.h
+#include errno.h
+#include string.h
+#include sys/stat.h
+
+#define CHECKSUM_OFFSET(14*1024-4)
+#define
[U-Boot] [PATCH v7 3/4] EXYNOS: Add SMDK5250 board support
SMDK5250 board is based on Samsungs EXYNOS5250 SoC. Signed-off-by: Chander Kashyap chander.kash...@linaro.org --- Changes for v2: - This patch is bifurcated into borad support and SoC support - Fixed typo: s/EEYNOS/EXYNOS - Squashed patch SMDK5250: enable device tree support in this. Changes for v3: - None Changes for v4: - Converted assembly routines for clock, memory, uart and tzpc - init to c functions - Moved uart init to smdk5250.c Changes for v5: - Remove init of gpio1 - Fixed gpio configuration for uart Changes for v6: - Add gpio1 init in board_uart_init, which was removed in v5 Changes for v7: - Converted magic numbers in dmc_init.c with macro defines - Divided mem_ctrl_init() function in dmc_init.c in smaller modules. - Removed init of all uarts except uart2 in smdk5250.c file. - Removed values assigned for boolean defines. - Removed back-slashes used for continuation in smdk5250.c MAINTAINERS|1 + board/samsung/smdk5250/Makefile| 51 board/samsung/smdk5250/clock_init.c| 202 ++ board/samsung/smdk5250/dmc_init.c | 453 board/samsung/smdk5250/lowlevel_init.S | 96 +++ board/samsung/smdk5250/setup.h | 448 +++ board/samsung/smdk5250/smdk5250.c | 146 ++ board/samsung/smdk5250/tzpc_init.c | 48 boards.cfg |1 + include/configs/smdk5250.h | 190 + 10 files changed, 1636 insertions(+), 0 deletions(-) create mode 100644 board/samsung/smdk5250/Makefile create mode 100644 board/samsung/smdk5250/clock_init.c create mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/lowlevel_init.S create mode 100644 board/samsung/smdk5250/setup.h create mode 100644 board/samsung/smdk5250/smdk5250.c create mode 100644 board/samsung/smdk5250/tzpc_init.c create mode 100644 include/configs/smdk5250.h diff --git a/MAINTAINERS b/MAINTAINERS index a05ad46..f88a282 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -713,6 +713,7 @@ Chander Kashyap k.chan...@samsung.com origen ARM ARMV7 (EXYNOS4210 SoC) SMDKV310ARM ARMV7 (EXYNOS4210 SoC) + SMDK5250ARM ARMV7 (EXYNOS5250 SoC) Heungjun Kim riverful@samsung.com diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile new file mode 100644 index 000..80e8be3 --- /dev/null +++ b/board/samsung/smdk5250/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2012 Samsung Electronics +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +SOBJS := lowlevel_init.o + +COBJS := clock_init.o +COBJS += dmc_init.o +COBJS += tzpc_init.o +COBJS += smdk5250.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +ALL:= $(obj).depend $(LIB) + +all: $(ALL) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c new file mode 100644 index 000..3395005 --- /dev/null +++ b/board/samsung/smdk5250/clock_init.c @@ -0,0 +1,202 @@ +/* + * Clock setup for SMDK5250 board based on EXYNOS5 + * + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A
Re: [U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects
On 01/02/2012 20:31, Eric Nelson wrote: Hi Mike, My comment was the inverse: I can't test just the 'sf probe' updates unless I have the core SPI flash support for mx6qsabrelite. AFAIK, the update to cmd_sf doesn't have any dependencies and of course the README update doesn't. Then I think the best way is to proceed is as suggested by Mike - the patches are orthogonal, and they can applied to different trees - and merged together at the end by Wolfgang. Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] image: add support for Android's boot image format
Dear Wolfgang, On Tuesday 17 January 2012 02:46 PM, Aneesh V wrote: Dear Wolfgang, On Wednesday 23 November 2011 03:33 PM, Sebastian Andrzej Siewior wrote: * Wolfgang Denk | 2011-11-22 20:04:47 [+0100]: Dear Sebastian Andrzej Siewior, In message2022123007.ga5...@linutronix.de you wrote: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. Sorry, but this is not GPL compatible. Ehm. Is this the All rights reserved issue? If so then I assumed that I cleared up things in No, it's the Redistributions in binary form must reproduce... clause. How so? If you distribute it as source nothing changes. I don't see much difference in binary form either: section 1 of the GPL says |.. keep intact all the notices that refer to this License and to the |absence of any warranty; and give any other recipients of the Program a |copy of this License along with the Program. and this is no different. It does not mention whether the software has to be passed in source or binary form. The BSD part does not push any restrictions on the GPL, it wants the same thing. Section 6 of the GPL says that by redistributing the receiptient should receive a copy of this license. The section you mentioed is no different. If you distribute GPL in binary code you have let the receiptient know, that he is using GPL code. A note in the documentation is enough as far as I know [if remeber correctly Harald went after a few companies which were using Linux and were not letting the customers know about it]. If you look at the fresh released Quake3 source [0] you see that there is a readme file which points out that it is GPL code and enumerates various other licenses. So right now, I don't see why those two should not be compatible. Plus the FSF claims that they are [1]. [0] https://github.com/TTimo/doom3.gpl [1] http://www.gnu.org/licenses/license-list.html#FreeBSD What is your final call on this? The above arguments sound convincing to me, but I have to admit that I am no legal expert. Either way, it will be great to have a closure on this. Lack of fastboot support was the greatest impediment to adoption of mainline U-Boot in our previous platforms. It will be really unfortunate if the same happens to OMAP5 that has just arrived. Ping. br, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 4/7] arm, arm926ejs: Do not clear the V bit on DA850 SoCs
Hello Heiko and Sughosh, On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher h...@denx.de wrote: Sughosh Ganu wrote: On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch christian.rie...@omicron.at wrote: The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x. Signed-off-by: Christian Riesch christian.rie...@omicron.at Reported-by: Sughosh Ganu urwithsugh...@gmail.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com --- arch/arm/cpu/arm926ejs/start.S | 5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x2300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x0300 /* clear bits 9:8 ( --RS) */ +#ifndef CONFIG_SOC_DA850 + bic r0, r0, #0x2000 /* clear bit 13 (--V- ) */ +#endif Instead of checking for a particular SOC, can we introduce a generic config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other SOC's have a similar requirement, it won't be needed to keep adding checks here. It would also help in case this needs to be implemented for other arm cores, so that we can have a common config option for bypassing this V-bit clear. Just my suggestion. Maybe Tom and Albert can comment. Yep, I vote for this too, also this config option should be documented in the README. Ok, I'll change this to #ifdef CONFIG_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x2000 /* set bit 13 (--V- ) */ #else bic r0, r0, #0x2000 /* clear bit 13 (--V- ) */ #endif Or should it be CONFIG_SYS_EXCEPTION_VECTORS_HIGH? I think I don't understand the explanation in README whether it should be _SYS_ or not. Regards, Christian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 4/7] arm, arm926ejs: Do not clear the V bit on DA850 SoCs
Hello Christian, Christian Riesch wrote: Hello Heiko and Sughosh, On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher h...@denx.de wrote: Sughosh Ganu wrote: On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch christian.rie...@omicron.at wrote: The V bit of the c1 register of CP15 should not be cleared since the SoC has no valid memory at 0x. Signed-off-by: Christian Riesch christian.rie...@omicron.at Reported-by: Sughosh Ganu urwithsugh...@gmail.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com --- arch/arm/cpu/arm926ejs/start.S |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..b350480 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,7 +372,10 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x2300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x0300 /* clear bits 9:8 ( --RS) */ +#ifndef CONFIG_SOC_DA850 + bic r0, r0, #0x2000 /* clear bit 13 (--V- ) */ +#endif Instead of checking for a particular SOC, can we introduce a generic config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other SOC's have a similar requirement, it won't be needed to keep adding checks here. It would also help in case this needs to be implemented for other arm cores, so that we can have a common config option for bypassing this V-bit clear. Just my suggestion. Maybe Tom and Albert can comment. Yep, I vote for this too, also this config option should be documented in the README. Ok, I'll change this to #ifdef CONFIG_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x2000 /* set bit 13 (--V- ) */ #else bic r0, r0, #0x2000 /* clear bit 13 (--V- ) */ #endif Or should it be CONFIG_SYS_EXCEPTION_VECTORS_HIGH? I think I don't understand the explanation in README whether it should be _SYS_ or not. It should be CONFIG_SYS as this is a hardware dependend config option. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 7/7] arm, davinci: Add support for the Calimain board from OMICRON electronics
This patch adds support for the Calimain board from
OMICRON electronics GmbH. The board features a Texas Instruments AM1808
SoC, 128 MB DDR2 memory, and 64 MB NOR flash memory connected to CS2 and
CS3.
Signed-off-by: Christian Riesch christian.rie...@omicron.at
---
MAINTAINERS |5 +
board/omicron/calimain/Makefile | 45 +
board/omicron/calimain/calimain.c | 188 +++
boards.cfg|1 +
include/configs/calimain.h| 363 +
5 files changed, 602 insertions(+), 0 deletions(-)
create mode 100644 board/omicron/calimain/Makefile
create mode 100644 board/omicron/calimain/calimain.c
create mode 100644 include/configs/calimain.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 353f23d..61f9537 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -796,6 +796,11 @@ Thierry Reding thierry.red...@avionic-design.de
plutux Tegra2 (ARM7 A9 Dual Core)
medcom Tegra2 (ARM7 A9 Dual Core)
+Christian Riesch christian.rie...@omicron.at
+Manfred Rudigier manfred.rudig...@omicron.at
+
+ calimainARM926EJS (AM1808 SoC)
+
Tom Rini tr...@ti.com
omap3_evm ARM ARMV7 (OMAP3xx SoC)
diff --git a/board/omicron/calimain/Makefile b/board/omicron/calimain/Makefile
new file mode 100644
index 000..cd1f0d4
--- /dev/null
+++ b/board/omicron/calimain/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn k...@koi8.net
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/omicron/calimain/calimain.c
b/board/omicron/calimain/calimain.c
new file mode 100644
index 000..97ba74a
--- /dev/null
+++ b/board/omicron/calimain/calimain.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * Based on da850evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. nick.thomp...@gefanuc.com
+ * Copyright (C) 2007 Sergey Kubushyn k...@koi8.net
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include common.h
+#include i2c.h
+#include net.h
+#include netdev.h
+#include watchdog.h
+#include asm/io.h
+#include asm/arch/hardware.h
+#include asm/arch/gpio.h
+#include asm/arch/emif_defs.h
+#include asm/arch/emac_defs.h
+#include asm/arch/pinmux_defs.h
+#include asm/arch/davinci_misc.h
+#include asm/arch/timer_defs.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CALIMAIN_HWVERSION_MASK0x7f00
+#define CALIMAIN_HWVERSION_SHIFT 24
+
+/* Hardware version pinmux settings */
+const struct pinmux_config hwversion_pins[] = {
+ { pinmux(16), 8, 2 }, /* GP7[15] */
+ { pinmux(16), 8, 3 }, /* GP7[14] */
+ { pinmux(16), 8, 4 }, /* GP7[13] */
+ { pinmux(16), 8, 5 }, /* GP7[12] */
+ { pinmux(16), 8, 6 }, /* GP7[11] */
+ { pinmux(16), 8, 7 }, /* GP7[10] */
+ {
[U-Boot] [PATCH v6 5/7] arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined
Signed-off-by: Christian Riesch christian.rie...@omicron.at Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Acked-by: Heiko Schocher h...@denx.de Tested-by: Heiko Schocher h...@denx.de --- arch/arm/cpu/arm926ejs/start.S |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 525c112..6f05f1a 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -369,7 +369,8 @@ flush_dcache: mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ /* -* disable MMU and D cache, and enable I cache +* disable MMU and D cache +* enable I cache if CONFIG_SYS_ICACHE_OFF is not defined */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x0300 /* clear bits 9:8 ( --RS) */ @@ -380,7 +381,9 @@ flush_dcache: bic r0, r0, #0x2000 /* clear bit 13 (--V- ) */ #endif orr r0, r0, #0x0002 /* set bit 2 (A) Align */ +#ifndef CONFIG_SYS_ICACHE_OFF orr r0, r0, #0x1000 /* set bit 12 (I) I-Cache */ +#endif mcr p15, 0, r0, c1, c0, 0 /* -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 0/7] Change ARM926EJ-S startup code, hawkboard and calimain
Hi,
In this patchset I tried to put everything from the discussion
in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
Although this is the second version of this patchset, the version number
is v6 since Sughosh's patches were already v4.
Changes since v5:
- introduced CONFIG_SYS_EXCEPTION_VECTORS_HIGH as requested by Sughosh
and Heiko
- added Acked-bys and Tested-bys
Regards, Christian
Christian Riesch (5):
arm, davinci: Add lowlevel_init for SoCs other than DM644X
arm, arm926ejs: Do cpu critical inits only for boards that require it
arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not
defined
arm, davinci: Add support for the Calimain board from OMICRON
electronics
Sughosh Ganu (2):
arm, arm926ejs: Flush the data cache before disabling it
Changes to move hawkboard to the new spl infrastructure
MAINTAINERS|5 +
README |6 +
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c| 24 +-
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S |4 +
arch/arm/cpu/arm926ejs/davinci/spl.c |4 +-
arch/arm/cpu/arm926ejs/start.S | 28 ++-
arch/arm/include/asm/arch-davinci/da850_lowlevel.h |9 +
board/davinci/da8xxevm/da850evm.c |4 +-
board/davinci/da8xxevm/hawkboard.c | 23 ++
board/davinci/da8xxevm/hawkboard_nand_spl.c| 115 --
.../{u-boot-spl.lds = u-boot-spl-da850evm.lds}|0
.../davinci/da8xxevm/u-boot-spl-hawk.lds | 22 +-
board/enbw/enbw_cmc/enbw_cmc.c | 13 +-
board/omicron/calimain/Makefile| 45 +++
board/omicron/calimain/calimain.c | 188 ++
boards.cfg |2 +-
doc/README.hawkboard | 43 ++--
include/configs/calimain.h | 363
include/configs/cam_enc_4xx.h |6 -
include/configs/da850evm.h |7 +-
include/configs/enbw_cmc.h |6 +-
include/configs/hawkboard.h| 24 +-
nand_spl/board/davinci/da8xxevm/Makefile | 155 -
23 files changed, 750 insertions(+), 346 deletions(-)
delete mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c
rename board/davinci/da8xxevm/{u-boot-spl.lds = u-boot-spl-da850evm.lds}
(100%)
rename nand_spl/board/davinci/da8xxevm/u-boot.lds =
board/davinci/da8xxevm/u-boot-spl-hawk.lds (86%)
create mode 100644 board/omicron/calimain/Makefile
create mode 100644 board/omicron/calimain/calimain.c
create mode 100644 include/configs/calimain.h
delete mode 100644 nand_spl/board/davinci/da8xxevm/Makefile
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[U-Boot] [PATCH v6 3/7] arm, arm926ejs: Flush the data cache before disabling it
From: Sughosh Ganu urwithsugh...@gmail.com The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead. Also fix the comments to match code. Signed-off-by: Sughosh Ganu urwithsugh...@gmail.com Rebased and corrected commit message. Signed-off-by: Christian Riesch christian.rie...@omicron.at Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Acked-by: Heiko Schocher h...@denx.de Tested-by: Heiko Schocher h...@denx.de --- arch/arm/cpu/arm926ejs/start.S | 12 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index bb4d00b..b39ed8a 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -358,14 +358,18 @@ _dynsym_start_ofs: #ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* -* flush v4 I/D caches +* flush D cache before disabling it */ mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ +flush_dcache: + mrc p15, 0, r15, c7, c10, 3 + bne flush_dcache + + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ /* -* disable MMU stuff and caches +* disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x2300 /* clear bits 13, 9:8 (--V- --RS) */ -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 2/7] arm, arm926ejs: Do cpu critical inits only for boards that require it
This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416 arm, arm926ejs: always do cpu critical inits since it impacts all arm926ejs based configurations and caused problems, e.g., with the hawkboard. Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines from the board configurations that need low level initialization. Signed-off-by: Christian Riesch christian.rie...@omicron.at Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Heiko Schocher h...@denx.de Acked-by: Heiko Schocher h...@denx.de Tested-by: Heiko Schocher h...@denx.de --- arch/arm/cpu/arm926ejs/start.S |6 -- include/configs/cam_enc_4xx.h |6 -- include/configs/da850evm.h |1 - include/configs/enbw_cmc.h |1 - 4 files changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 6a09c02..bb4d00b 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -194,7 +194,9 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit +#endif /* Set stackpointer in internal RAM to call board_init_f */ call_board_init_f: @@ -353,6 +355,7 @@ _dynsym_start_ofs: * * */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -371,15 +374,14 @@ cpu_init_crit: orr r0, r0, #0x1000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* * Go setup Memory and board specific bits prior to relocation. */ mov ip, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ #ifndef CONFIG_SPL_BUILD /* diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index a21d448..f4fe444 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -265,12 +265,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS0xc #define CONFIG_SYS_NAND_U_BOOT_SIZE0x6 -/* - * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is - * done in board_init_f from c code. - */ -#define CONFIG_SKIP_LOWLEVEL_INIT - /* for UBL header */ #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index fcbbace..f15a0a6 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCKclk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc108 /* diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index c427dc7..21cf647 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCKclk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_DA850_LOWLEVEL #define CONFIG_ARCH_CPU_INIT #define CONFIG_DA8XX_GPIO -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 4/7] arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
The V bit of the c1 register of CP15 should not be cleared on DA850 SoCs since they have no valid memory at 0x. This patch introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH that allows setting the correct value for the V bit. Signed-off-by: Christian Riesch christian.rie...@omicron.at Reported-by: Sughosh Ganu urwithsugh...@gmail.com Cc: Albert Aribaud albert.u.b...@aribaud.net Cc: Tom Rini tr...@ti.com Cc: Sughosh Ganu urwithsugh...@gmail.com Cc: Heiko Schocher h...@denx.de --- README |6 ++ arch/arm/cpu/arm926ejs/start.S |7 ++- include/configs/da850evm.h |1 + include/configs/enbw_cmc.h |1 + include/configs/hawkboard.h|1 + 5 files changed, 15 insertions(+), 1 deletions(-) diff --git a/README b/README index 9d713e8..c5b0941 100644 --- a/README +++ b/README @@ -420,6 +420,12 @@ The following options need to be configured: XWAY SoCs for booting from NOR flash. The U-Boot image needs to be swapped if a flash programmer is used. +- ARM options: + CONFIG_SYS_EXCEPTION_VECTORS_HIGH + + Select high exception vectors of the ARM core, e.g., do not + clear the V bit of the c1 register of CP15. + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..525c112 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,8 +372,13 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x2300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x0300 /* clear bits 9:8 ( --RS) */ bic r0, r0, #0x0087 /* clear bits 7, 2:0 (B--- -CAM) */ +#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH + orr r0, r0, #0x2000 /* set bit 13 (--V- ) */ +#else + bic r0, r0, #0x2000 /* clear bit 13 (--V- ) */ +#endif orr r0, r0, #0x0002 /* set bit 2 (A) Align */ orr r0, r0, #0x1000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index f15a0a6..85016df 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -37,6 +37,7 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQclk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 2400 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 21cf647..0c9ab4c 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -40,6 +40,7 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQclk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 2400 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 12acb27..ce78d3c 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -35,6 +35,7 @@ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ #define CONFIG_SOC_DA850 /* TI DA850 SoC */ +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH #define CONFIG_SYS_CLK_FREQclk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 2400 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 6/7] Changes to move hawkboard to the new spl infrastructure
From: Sughosh Ganu urwithsugh...@gmail.com
This patch moves hawkboard to the new spl infrastructure from the
older nand_spl one.
Removed the hawkboard_nand_config build option -- The spl code now
gets compiled with hawkboard_config, after building the main u-boot
image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard
to reflect the same.
Signed-off-by: Sughosh Ganu urwithsugh...@gmail.com
Signed-off-by: Heiko Schocher h...@denx.de
Cc: Heiko Schocher h...@denx.de
Cc: Christian Riesch christian.rie...@omicron.at
Cc: Sudhakar Rajashekhara sudhakar@ti.com
Cc: Tom Rini tr...@ti.com
Acked-by: Christian Riesch christian.rie...@omicron.at
---
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c| 24 ++-
arch/arm/cpu/arm926ejs/davinci/spl.c |4 +-
arch/arm/include/asm/arch-davinci/da850_lowlevel.h |9 +
board/davinci/da8xxevm/da850evm.c |4 +-
board/davinci/da8xxevm/hawkboard.c | 23 +++
board/davinci/da8xxevm/hawkboard_nand_spl.c| 115 ---
.../{u-boot-spl.lds = u-boot-spl-da850evm.lds}|0
.../davinci/da8xxevm/u-boot-spl-hawk.lds | 22 ++-
board/enbw/enbw_cmc/enbw_cmc.c | 13 +--
boards.cfg |1 -
doc/README.hawkboard | 43 +++---
include/configs/da850evm.h |5 +-
include/configs/enbw_cmc.h |4 +-
include/configs/hawkboard.h| 23 +++-
nand_spl/board/davinci/da8xxevm/Makefile | 155
15 files changed, 114 insertions(+), 331 deletions(-)
delete mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c
rename board/davinci/da8xxevm/{u-boot-spl.lds = u-boot-spl-da850evm.lds}
(100%)
rename nand_spl/board/davinci/da8xxevm/u-boot.lds =
board/davinci/da8xxevm/u-boot-spl-hawk.lds (86%)
delete mode 100644 nand_spl/board/davinci/da8xxevm/Makefile
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index eec06bc..df7d6a2 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -32,6 +32,7 @@
#include asm/arch/emif_defs.h
#include asm/arch/pll_defs.h
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
void da850_waitloop(unsigned long loopcnt)
{
unsigned long i;
@@ -163,7 +164,9 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned
long pllmult)
return 0;
}
+#endif /* CONFIG_SYS_DA850_PLL_INIT */
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
int da850_ddr_setup(void)
{
unsigned long tmp;
@@ -242,6 +245,7 @@ int da850_ddr_setup(void)
return 0;
}
+#endif /* CONFIG_SYS_DA850_DDR_INIT */
__attribute__((weak))
void board_gpio_init(void)
@@ -249,10 +253,6 @@ void board_gpio_init(void)
return;
}
-/* pinmux_resource[] vector is defined in the board specific file */
-extern const struct pinmux_resource pinmuxes[];
-extern const int pinmuxes_size;
-
int arch_cpu_init(void)
{
/* Unlock kick registers */
@@ -266,13 +266,11 @@ int arch_cpu_init(void)
if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
return 1;
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
/* PLL setup */
da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
-
- /* GPIO setup */
- board_gpio_init();
-
+#endif
/* setup CSn config */
#if defined(CONFIG_SYS_DA850_CS2CFG)
writel(CONFIG_SYS_DA850_CS2CFG, davinci_emif_regs-ab1cr);
@@ -281,7 +279,12 @@ int arch_cpu_init(void)
writel(CONFIG_SYS_DA850_CS3CFG, davinci_emif_regs-ab2cr);
#endif
- lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
+ da8xx_configure_lpsc_items(lpsc, lpsc_size);
+
+ /* GPIO setup */
+ board_gpio_init();
+
+
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
@@ -293,6 +296,9 @@ int arch_cpu_init(void)
DAVINCI_UART_PWREMU_MGMT_UTRST),
davinci_uart2_ctrl_regs-pwremu_mgmt);
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
da850_ddr_setup();
+#endif
+
return 0;
}
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index f475f9b..74632e5 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -74,12 +74,12 @@ void board_init_f(ulong dummy)
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SOC_DM365
+#ifdef CONFIG_SPL_NAND_LOAD
nand_init();
puts(Nand boot...\n);
nand_boot();
#endif
-#ifdef CONFIG_SOC_DA8XX
+#ifdef CONFIG_SPL_SPI_LOAD
mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
diff --git
[U-Boot] [PATCH v6 1/7] arm, davinci: Add lowlevel_init for SoCs other than DM644X
The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X. Signed-off-by: Christian Riesch christian.rie...@omicron.at Cc: Tom Rini tr...@ti.com Cc: Sergey Kubushyn k...@koi8.net Acked-by: Heiko Schocher h...@denx.de Tested-by: Heiko Schocher h...@denx.de --- arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S index 7a169b1..5b39484 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S @@ -49,6 +49,7 @@ .globl lowlevel_init lowlevel_init: +#ifdef CONFIG_SOC_DM644X /*---* * Mask all IRQs by setting all bits in the EINT default * @@ -707,3 +708,6 @@ DDR2_START_ADDR: .word 0x8000 DUMMY_VAL: .word 0xa55aa55a +#else /* CONFIG_SOC_DM644X */ + mov pc, lr +#endif -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] arm: mmc: omap: spl size reduction by removing write/erase ops
spl for OMAP4 does not use mmc read/write.
Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc
write/erase operation is not needed in spl.
Use these CONFIGS to remove write/erase code in mmc.c and omap_hsmmc.c
This reduces the spl size by ~1128 Bytes
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/mmc.c | 17 +
drivers/mmc/omap_hsmmc.c |2 ++
include/configs/omap4_common.h |4
3 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 21665ec..852c896 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -31,6 +31,7 @@
#include malloc.h
#include linux/list.h
#include div64.h
+#include asm/errno.h
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
@@ -175,6 +176,7 @@ struct mmc *find_mmc_device(int dev_num)
return NULL;
}
+#ifndef CONFIG_MMC_NO_ERASE
static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
{
struct mmc_cmd cmd;
@@ -256,7 +258,15 @@ mmc_berase(int dev_num, unsigned long start, lbaint_t
blkcnt)
return blk;
}
+#else
+static unsigned long
+mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
+{
+ return -ENOSYS;
+}
+#endif
+#ifndef CONFIG_MMC_NO_WRITE
static ulong
mmc_write_blocks(struct mmc *mmc, ulong start, lbaint_t blkcnt, const void*src)
{
@@ -336,6 +346,13 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt,
const void*src)
return blkcnt;
}
+#else
+static ulong
+mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void *src)
+{
+ return -ENOSYS;
+}
+#endif
int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt)
{
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index c38b9e6..ce36481 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -360,6 +360,7 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf,
unsigned int size)
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int size)
{
+#ifndef CONFIG_MMC_NO_WRITE
unsigned int *input_buf = (unsigned int *)buf;
unsigned int mmc_stat;
unsigned int count;
@@ -406,6 +407,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const
char *buf,
break;
}
}
+#endif
return 0;
}
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index a989721..0ae2ab3 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -109,6 +109,10 @@
#define CONFIG_SYS_MMC_SET_DEV 1
#define CONFIG_DOS_PARTITION 1
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_MMC_NO_WRITE1
+#define CONFIG_MMC_NO_ERASE1
+#endif
/* USB */
#define CONFIG_MUSB_UDC1
--
1.7.0.4
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[U-Boot] [PATCH 2/2] da850evm: read mac address from I2C EEPROM on AM18x EVM
add support to read mac address for AM18x EVM manufactured from
Spectrum digital which have mac address stored in I2C EEPROM manfactured
by WINBOND. This patch reads mac address from I2C EEPROM and updates
environment variable if not set. Introduced a config option
CONFIG_MAC_ADDR_IN_EEPROM to where to look for the mac address.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
board/davinci/da8xxevm/da850evm.c | 12 ++--
boards.cfg|2 +-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/board/davinci/da8xxevm/da850evm.c
b/board/davinci/da8xxevm/da850evm.c
index dcb22cb..8963243 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -139,11 +139,12 @@ int misc_init_r(void)
{
dspwake();
-#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
uchar buff[8];
- int ret;
if (!eth_getenv_enetaddr(ethaddr, buff)) {
+#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+ int ret;
ret = get_mac_addr(buff);
if (ret != 0)
return -EINVAL;
@@ -154,6 +155,13 @@ int misc_init_r(void)
}
eth_setenv_enetaddr(ethaddr, buff);
+#else
+ uint8_t enetaddr[8];
+ /* Read Ethernet MAC address from EEPROM */
+ if (dvevm_read_mac_address(enetaddr))
+ /* Set Ethernet MAC address from EEPROM */
+ davinci_sync_env_enetaddr(enetaddr);
+#endif
}
#endif
return 0;
diff --git a/boards.cfg b/boards.cfg
index ad6c5b8..2e6d267 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -120,7 +120,7 @@ pm9263 arm arm926ejs pm9263
ronetix
pm9g45 arm arm926ejs pm9g45
ronetixat91pm9g45:AT91SAM9G45
cam_enc_4xx arm arm926ejs cam_enc_4xx ait
davinci cam_enc_4xx
da830evm arm arm926ejs da8xxevm
davincidavinci
-da850_am18xxevm arm arm926ejs da8xxevm
davincidavinci da850evm:DA850_AM18X_EVM
+da850_am18xxevm arm arm926ejs da8xxevm
davincidavinci
da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50
da850evm arm arm926ejs da8xxevm
davincidavinci da850evm:MAC_ADDR_IN_SPIFLASH
davinci_dm355evm arm arm926ejs dm355evm
davincidavinci
davinci_dm355leopard arm arm926ejs dm355leopard
davincidavinci
--
1.6.2.4
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[U-Boot] [PATCH 1/2] da850evm: add support to read mac address from spi flash
add support to read mac address for da850/L138 evm manufactued by
Logic PD which store mac address in SPI flash manufactued by ST
Microelectronics. This patch adds support to read mac address from
spi flash and set the mac address if it hasen't been set in environmet.
Introduced a config option CONFIG_MAC_ADDR_IN_SPIFLASH indicating
where to look mac address for.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
board/davinci/da8xxevm/da850evm.c | 58 +
boards.cfg|2 +-
2 files changed, 59 insertions(+), 1 deletions(-)
diff --git a/board/davinci/da8xxevm/da850evm.c
b/board/davinci/da8xxevm/da850evm.c
index 9bd3e71..dcb22cb 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -25,12 +25,15 @@
#include i2c.h
#include net.h
#include netdev.h
+#include spi.h
+#include spi_flash.h
#include asm/arch/hardware.h
#include asm/arch/emif_defs.h
#include asm/arch/emac_defs.h
#include asm/arch/pinmux_defs.h
#include asm/io.h
#include asm/arch/davinci_misc.h
+#include asm/errno.h
#include hwconfig.h
DECLARE_GLOBAL_DATA_PTR;
@@ -43,6 +46,43 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#endif /* CONFIG_DRIVER_TI_EMAC */
+#define CFG_MAC_ADDR_SPI_BUS 0
+#define CFG_MAC_ADDR_SPI_CS0
+#define CFG_MAC_ADDR_SPI_MAX_HZCONFIG_SF_DEFAULT_SPEED
+#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
+
+#define CFG_MAC_ADDR_OFFSET(flash-size - SZ_64K)
+
+#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+static int get_mac_addr(u8 *addr)
+{
+ struct spi_flash *flash;
+ int ret;
+
+ flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
+ CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
+ if (!flash) {
+ printf( Error - unable to probe SPI flash.\n);
+ ret = -1;
+ goto err_probe;
+ }
+
+ ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr);
+ if (ret) {
+ printf(Error - unable to read MAC address from SPI flash.\n);
+ goto err_read;
+ }
+
+err_read:
+ /* cannot call free currently since the free function calls free() for
+* spi_flash structure though it is not directly allocated through
+* malloc()
+*/
+err_probe:
+ return ret;
+}
+#endif
+
void dsp_lpsc_on(unsigned domain, unsigned int id)
{
dv_reg_p mdstat, mdctl, ptstat, ptcmd;
@@ -98,6 +138,24 @@ static void dspwake(void)
int misc_init_r(void)
{
dspwake();
+
+#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+ uchar buff[8];
+ int ret;
+
+ if (!eth_getenv_enetaddr(ethaddr, buff)) {
+ ret = get_mac_addr(buff);
+ if (ret != 0)
+ return -EINVAL;
+
+ if (!is_valid_ether_addr(buff)) {
+ printf(Invalid MAC address read.\n);
+ return -EINVAL;
+ }
+
+ eth_setenv_enetaddr(ethaddr, buff);
+ }
+#endif
return 0;
}
diff --git a/boards.cfg b/boards.cfg
index 2f90dbf..ad6c5b8 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -121,7 +121,7 @@ pm9g45 arm arm926ejs pm9g45
ronetix
cam_enc_4xx arm arm926ejs cam_enc_4xx ait
davinci cam_enc_4xx
da830evm arm arm926ejs da8xxevm
davincidavinci
da850_am18xxevm arm arm926ejs da8xxevm
davincidavinci da850evm:DA850_AM18X_EVM
-da850evm arm arm926ejs da8xxevm
davincidavinci
+da850evm arm arm926ejs da8xxevm
davincidavinci da850evm:MAC_ADDR_IN_SPIFLASH
davinci_dm355evm arm arm926ejs dm355evm
davincidavinci
davinci_dm355leopard arm arm926ejs dm355leopard
davincidavinci
davinci_dm365evm arm arm926ejs dm365evm
davincidavinci
--
1.6.2.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/2] da850evm: add board specific functions
There are two da850 SOC based EVMs, one from Spectrum digital and other from Logic PD. Boards from Spectrum digital have mac address stored in I2C EEPROM and they have spi flash manufactured by WINBOND. Boards from Logic PD store mac address in ST Microelectronics SPI flash. This patch series adds support to read mac address from the appropriate device. These patches have undergone a review previously, but since the tree has moved ahead Christian and Tom asked to resubmit the patches for review. (http://www.mail-archive.com/u-boot@lists.denx.de/msg76220.html) Manjunath Hadli (2): da850evm: add support to read mac address from spi flash da850evm: read mac address from I2C EEPROM on AM18x EVM board/davinci/da8xxevm/da850evm.c | 66 + boards.cfg|4 +- 2 files changed, 68 insertions(+), 2 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/3] addition of clocks command for davinci
This patch series adds new command - 'clocks' for davinci family of SOCs. This command prints CPU, DSP core and DDR frequency from the u-boot prompt. Also, support for printing frequency info during u-boot initialization is removed as it will delay u-boot coming up. These patches have undergone a review previously, but since the tree has moved ahead Christian and Tom asked to resubmit the patches for review. (http://www.mail-archive.com/u-boot@lists.denx.de/msg76220.html) Manjunath Hadli (3): davinci: move clock related functions to new file davinci: remove macro CONFIG_DISPLAY_CPUINFO davinci: add clocks command arch/arm/cpu/arm926ejs/davinci/Makefile |2 +- arch/arm/cpu/arm926ejs/davinci/cpu.c | 208 --- arch/arm/cpu/arm926ejs/davinci/speed.c | 230 ++ include/configs/cam_enc_4xx.h|1 - include/configs/davinci_dm355evm.h |1 - include/configs/davinci_dm355leopard.h |1 - include/configs/davinci_dm6467Tevm.h |1 - include/configs/davinci_dm6467evm.h |1 - include/configs/davinci_dvevm.h |1 - include/configs/davinci_schmoogie.h |1 - include/configs/davinci_sffsdr.h |1 - include/configs/davinci_sonata.h |1 - include/configs/enbw_cmc.h |1 - nand_spl/board/davinci/da8xxevm/Makefile |6 + 14 files changed, 237 insertions(+), 219 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/davinci/speed.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] davinci: remove macro CONFIG_DISPLAY_CPUINFO
remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'clocks' command. Also avoid building of print_cpuinfo() function
for SPL framework.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/cpu/arm926ejs/davinci/speed.c |5 +
include/configs/cam_enc_4xx.h |1 -
include/configs/davinci_dm355evm.h |1 -
include/configs/davinci_dm355leopard.h |1 -
include/configs/davinci_dm6467Tevm.h |1 -
include/configs/davinci_dm6467evm.h|1 -
include/configs/davinci_dvevm.h|1 -
include/configs/davinci_schmoogie.h|1 -
include/configs/davinci_sffsdr.h |1 -
include/configs/davinci_sonata.h |1 -
include/configs/enbw_cmc.h |1 -
11 files changed, 1 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c
b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 5285142..156419b 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -114,7 +114,7 @@ int clk_get(enum davinci_clk_ids id)
out:
return pll_out;
}
-#ifdef CONFIG_DISPLAY_CPUINFO
+#if !defined(CONFIG_SPL_BUILD) !defined(CONFIG_NAND_SPL)
int print_cpuinfo(void)
{
printf(Cores: ARM %d MHz,
@@ -127,8 +127,6 @@ int print_cpuinfo(void)
#endif
#else /* CONFIG_SOC_DA8XX */
-#ifdef CONFIG_DISPLAY_CPUINFO
-
static unsigned pll_div(unsigned pllbase, unsigned offset)
{
u32 div;
@@ -226,5 +224,4 @@ unsigned int davinci_clk_get(unsigned int div)
return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 100;
}
#endif
-#endif /* CONFIG_DISPLAY_CPUINFO */
#endif /* !CONFIG_SOC_DA8XX */
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index a21d448..419cfd4 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -257,7 +257,6 @@
#define CONFIG_POSTCONFIG_SYS_POST_MEMORY
#define _POST_WORD_ADDR0x0
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_INIT_SP_ADDRCONFIG_SPL_STACK
diff --git a/include/configs/davinci_dm355evm.h
b/include/configs/davinci_dm355evm.h
index ddf673c..8578730 100644
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -26,7 +26,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH/* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
diff --git a/include/configs/davinci_dm355leopard.h
b/include/configs/davinci_dm355leopard.h
index dfa0a00..eaff66e 100644
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -25,7 +25,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH/* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
diff --git a/include/configs/davinci_dm6467Tevm.h
b/include/configs/davinci_dm6467Tevm.h
index b3a4e44..f7c994e 100644
--- a/include/configs/davinci_dm6467Tevm.h
+++ b/include/configs/davinci_dm6467Tevm.h
@@ -23,7 +23,6 @@
/* Spectrum Digital TMS320DM6467T EVM board */
#define DAVINCI_DM6467EVM
#define DAVINCI_DM6467TEVM
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_SMALLPAGE
diff --git a/include/configs/davinci_dm6467evm.h
b/include/configs/davinci_dm6467evm.h
index c9a0cd1..ddfd3ed 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -22,7 +22,6 @@
/* Spectrum Digital TMS320DM6467 EVM board */
#define DAVINCI_DM6467EVM
-#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_SMALLPAGE
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index c052517..a2aa3c3 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -51,7 +51,6 @@
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
/*===*/
/* SoC Configuration */
/*===*/
diff --git a/include/configs/davinci_schmoogie.h
b/include/configs/davinci_schmoogie.h
index f4ddbea..e0a8ee9 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -26,7 +26,6 @@
#define SCHMOOGIE
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
-#define CONFIG_DISPLAY_CPUINFO
#define MACH_TYPE_SCHMOOGIE 1255
#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 0c65391..a2da65a 100644
[U-Boot] [PATCH 3/3] davinci: add clocks command
Add 'clocks' command to print various frequencies such as ARM
frequency, DSP core frequency and DDR frequency. Remove
print_cpuinfo() function as it is no longer required.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/cpu/arm926ejs/davinci/speed.c | 73 ---
1 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c
b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 156419b..eb969e5 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -21,6 +21,7 @@
*/
#include common.h
+#include command.h
#include asm/io.h
#include asm/arch/hardware.h
@@ -114,17 +115,6 @@ int clk_get(enum davinci_clk_ids id)
out:
return pll_out;
}
-#if !defined(CONFIG_SPL_BUILD) !defined(CONFIG_NAND_SPL)
-int print_cpuinfo(void)
-{
- printf(Cores: ARM %d MHz,
- clk_get(DAVINCI_ARM_CLKID) / 100);
- printf(\nDDR: %d MHz\n,
- /* DDR PHY uses an x2 input clock */
- clk_get(0x10001) / 100);
- return 0;
-}
-#endif
#else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(unsigned pllbase, unsigned offset)
@@ -181,47 +171,60 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr,
unsigned div)
return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
}
-int print_cpuinfo(void)
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 100;
+}
+#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 100;
+}
+#endif
+#endif /* !CONFIG_SOC_DA8XX */
+
+#if !defined(CONFIG_SPL_BUILD) !defined(CONFIG_NAND_SPL)
+int showclocks(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
{
/* REVISIT fetch and display CPU ID and revision information
* too ... that will matter as more revisions appear.
*/
-#if defined(CONFIG_SOC_DM365)
- printf(Cores: ARM %d MHz,
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+
+ puts(Clock configuration:\n);
+#if defined(CONFIG_SOC_DA8XX)
+ printf(Cores: ARM %d MHz, clk_get(DAVINCI_ARM_CLKID) / 100);
+ printf(\nDDR: %d MHz\n,
+ /* DDR PHY uses an x2 input clock */
+ clk_get(0x10001) / 100);
#else
- printf(Cores: ARM %d MHz,
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+ unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
+
+#if defined(CONFIG_SOC_DM365)
+ pllbase = DAVINCI_PLL_CNTRL1_BASE;
#endif
+ printf(Cores: ARM %d MHz, pll_sysclk_mhz(pllbase, ARM_PLLDIV));
#ifdef DSP_PLLDIV
printf(, DSP %d MHz,
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
#endif
+ pllbase = DAVINCI_PLL_CNTRL1_BASE;
+ #if defined(CONFIG_SOC_DM365)
+ pllbase = DAVINCI_PLL_CNTRL0_BASE;
+ #endif
printf(\nDDR: %d MHz\n,
/* DDR PHY uses an x2 input clock */
-#if defined(CONFIG_SOC_DM365)
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
- / 2);
-#else
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
- / 2);
+ pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2);
#endif
return 0;
}
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 100;
-}
-#endif
+U_BOOT_CMD(clocks, 1, 0, showclocks,
+ display clocks, );
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 100;
-}
#endif
-#endif /* !CONFIG_SOC_DA8XX */
--
1.6.2.4
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[U-Boot] [PATCH 1/3] davinci: move clock related functions to new file
Move the clock related function from cpu.c to new file
speed.c. Eliminate volatile keyword usage which made no
justification and also to keep checkpatch.pl happy. Replace
REG instructions by readl.
Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/cpu/arm926ejs/davinci/Makefile |2 +-
arch/arm/cpu/arm926ejs/davinci/cpu.c | 208 ---
arch/arm/cpu/arm926ejs/davinci/speed.c | 230 ++
nand_spl/board/davinci/da8xxevm/Makefile |6 +
4 files changed, 237 insertions(+), 209 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/speed.c
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile
b/arch/arm/cpu/arm926ejs/davinci/Makefile
index da7efac..81540fd 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-COBJS-y+= cpu.o misc.o timer.o psc.o pinmux.o
+COBJS-y+= cpu.o misc.o timer.o psc.o pinmux.o
speed.o
COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
COBJS-$(CONFIG_SOC_DM355) += dm355.o
COBJS-$(CONFIG_SOC_DM365) += dm365.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c
b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index 9ea9785..c2f72d6 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -22,214 +22,6 @@
#include common.h
#include netdev.h
-#include asm/arch/hardware.h
-#include asm/io.h
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL0x100
-#define PLLC_PLLM 0x110
-#define PLLC_PREDIV0x114
-#define PLLC_PLLDIV1 0x118
-#define PLLC_PLLDIV2 0x11c
-#define PLLC_PLLDIV3 0x120
-#define PLLC_POSTDIV 0x128
-#define PLLC_BPDIV 0x12c
-#define PLLC_PLLDIV4 0x160
-#define PLLC_PLLDIV5 0x164
-#define PLLC_PLLDIV6 0x168
-#define PLLC_PLLDIV7 0x16c
-#define PLLC_PLLDIV8 0x170
-#define PLLC_PLLDIV9 0x174
-
-#define BIT(x) (1 (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-unsigned int sysdiv[9] = {
- PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
- PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
- int pre_div;
- int pllm;
- int post_div;
- int pll_out;
- unsigned int pll_base;
-
- pll_out = CONFIG_SYS_OSCIN_FREQ;
-
- if (id == DAVINCI_AUXCLK_CLKID)
- goto out;
-
- if ((id 16) == 1)
- pll_base = (unsigned int)davinci_pllc1_regs;
- else
- pll_base = (unsigned int)davinci_pllc0_regs;
-
- id = 0x;
-
- /*
-* Lets keep this simple. Combining operations can result in
-* unexpected approximations
-*/
- pre_div = (readl(pll_base + PLLC_PREDIV)
- DAVINCI_PLLC_DIV_MASK) + 1;
- pllm = readl(pll_base + PLLC_PLLM) + 1;
-
- pll_out /= pre_div;
- pll_out *= pllm;
-
- if (id == DAVINCI_PLLM_CLKID)
- goto out;
-
- post_div = (readl(pll_base + PLLC_POSTDIV)
- DAVINCI_PLLC_DIV_MASK) + 1;
-
- pll_out /= post_div;
-
- if (id == DAVINCI_PLLC_CLKID)
- goto out;
-
- pll_out /= (readl(pll_base + sysdiv[id - 1])
- DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
- return pll_out;
-}
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
- printf(Cores: ARM %d MHz,
- clk_get(DAVINCI_ARM_CLKID) / 100);
- printf(\nDDR: %d MHz\n,
- /* DDR PHY uses an x2 input clock */
- clk_get(0x10001) / 100);
- return 0;
-}
-#endif
-#else /* CONFIG_SOC_DA8XX */
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
- u32 div;
-
- div = REG(pllbase + offset);
- return (div BIT(15)) ? (1 + (div 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
- /* this register read seems to fail on pll0 */
- if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
- return 8;
- else
- return pll_div(pllbase, PLLC_PREDIV);
-#elif defined(CONFIG_SOC_DM365)
- return pll_div(pllbase, PLLC_PREDIV);
-#endif
- return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#if defined(CONFIG_SOC_DM355) ||
Re: [U-Boot] [PATCH 0/2] da850evm: add board specific functions
Hi, Thank you for re-submitting the patchset! On Thu, Feb 2, 2012 at 2:42 PM, Manjunath Hadli manjunath.ha...@ti.com wrote: There are two da850 SOC based EVMs, one from Spectrum digital and other from Logic PD. Boards from Spectrum digital have mac address stored in I2C EEPROM and they have spi flash manufactured by WINBOND. Boards from Logic PD store mac address in ST Microelectronics SPI flash. This patch series adds support to read mac address from the appropriate device. Ok, so we have two configurations, we have da850evm which is for LogicPD's OMAP-L138 SoM and for LogicPD's AM1808 SoM, and we have da850_am18xxevm which must be used for the AM1808 board from Spectrum Digital. Is that correct? I wonder if we should change the name of the da850_am18xxevm configuration. It's quite confusing, until today I thought that the da850_am18xxevm was a configuration for LogicPD's AM1808 SoM... Are there also OMAP-L138 boards from Spectrum Digital? Regards, Christian These patches have undergone a review previously, but since the tree has moved ahead Christian and Tom asked to resubmit the patches for review. (http://www.mail-archive.com/u-boot@lists.denx.de/msg76220.html) Manjunath Hadli (2): da850evm: add support to read mac address from spi flash da850evm: read mac address from I2C EEPROM on AM18x EVM board/davinci/da8xxevm/da850evm.c | 66 + boards.cfg | 4 +- 2 files changed, 68 insertions(+), 2 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects
On 02/02/2012 02:18 AM, Stefano Babic wrote: On 01/02/2012 20:31, Eric Nelson wrote: Hi Mike, My comment was the inverse: I can't test just the 'sf probe' updates unless I have the core SPI flash support for mx6qsabrelite. AFAIK, the update to cmd_sf doesn't have any dependencies and of course the README update doesn't. Then I think the best way is to proceed is as suggested by Mike - the patches are orthogonal, and they can applied to different trees - and merged together at the end by Wolfgang. Stefano Okay. I'll leave the process stuff in your capable hands. Mine is just to code... (or so I like to think) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] i.MX28: Fix VDDIO and VDDA setup
Hi Marek, Ok, what happens if you replace mx28_dram_init() with: while (!readl(0x8001c280)) mx28_mem_init(); It's not entirely clear what you'd like me to try: mx28_dram_init is called in U-Boot, while mx28_mem_init is SPL code. I have tried to link SPL objects along, but I'm getting a number of duplicate symbols now. Before I start fixing that, I'd first like to know if that's really what you want me to try. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] arm: mmc: omap: spl size reduction by removing write/erase ops
On Thu, Feb 2, 2012 at 6:04 AM, Balaji T K balaj...@ti.com wrote: spl for OMAP4 does not use mmc read/write. Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc write/erase operation is not needed in spl. Use these CONFIGS to remove write/erase code in mmc.c and omap_hsmmc.c This reduces the spl size by ~1128 Bytes Are you running into a size limitation again? If not, I think we want to wait until we sort out how SPL includes/excludes stuff moving forward as this shows there's probably a lot of other unused code being pulled in. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V6 - Part 3 - 0/2] SPI flash enhancements: allow default bus and chip-selects
On Thursday 02 February 2012 04:18:45 Stefano Babic wrote: On 01/02/2012 20:31, Eric Nelson wrote: My comment was the inverse: I can't test just the 'sf probe' updates unless I have the core SPI flash support for mx6qsabrelite. AFAIK, the update to cmd_sf doesn't have any dependencies and of course the README update doesn't. Then I think the best way is to proceed is as suggested by Mike - the patches are orthogonal, and they can applied to different trees - and merged together at the end by Wolfgang. to be clear, i'm not trying to hoard patches or anything ... i just can't see there being a hard requirement here between the two sets. if people *really* want to merge patches for me, i don't mind ;). -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] davinci: add clocks command
On Thu, Feb 2, 2012 at 6:53 AM, Manjunath Hadli manjunath.ha...@ti.com wrote: Add 'clocks' command to print various frequencies such as ARM frequency, DSP core frequency and DDR frequency. Remove print_cpuinfo() function as it is no longer required. Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com Cc: Tom Rini tr...@ti.com NAK. The feedback from the last time you submitted this was to extend the functionality of 'bdinfo' to be able to include this. See http://patchwork.ozlabs.org/patch/120105/ -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] arm: mmc: omap: spl size reduction by removing write/erase ops
Tom, On Thursday 02 February 2012 10:02 PM, Tom Rini wrote: On Thu, Feb 2, 2012 at 6:04 AM, Balaji T Kbalaj...@ti.com wrote: spl for OMAP4 does not use mmc read/write. Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc write/erase operation is not needed in spl. Use these CONFIGS to remove write/erase code in mmc.c and omap_hsmmc.c This reduces the spl size by ~1128 Bytes Are you running into a size limitation again? If not, I think we want We are always on the border. Minor fluctuations are affecting us. And our EMU boards(secure devices) are permanently broken due to this. I am not sure if this one helps EMU devices though. to wait until we sort out how SPL includes/excludes stuff moving forward as this shows there's probably a lot of other unused code being pulled in. We use -ffunction-sections -fdata-sections and --gc-sections while building SPL. So, un-necessary stuff will not be included unless the function pointers are set in some structures and not used. I think that is what is happening in this case. Other than that I am not expecting much scope for improvement. One key experiment I want to do is Thumb mode build. I have some old patches that I may cleanup and post sometime soon. But Thumb mode had some tool-chain related issues last time I tried. br, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] i.MX28: Fix ref_cpu clock setup
On 2/2/12, Fabio Estevam feste...@gmail.com wrote: 2. Please grep the locations where hw_clkctrl_frac0 is assigned as 32-bit and change those as well. Please do the same for hw_clkctrl_frac1 as well. There is one location in clock.c where it is read as 32-bit. Thanks, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] arm: mmc: omap: spl size reduction by removing write/erase ops
On Thu, Feb 2, 2012 at 9:48 AM, Aneesh V ane...@ti.com wrote: Tom, On Thursday 02 February 2012 10:02 PM, Tom Rini wrote: On Thu, Feb 2, 2012 at 6:04 AM, Balaji T Kbalaj...@ti.com wrote: spl for OMAP4 does not use mmc read/write. Add CONFIG_MMC_NO_ERASE, CONFIG_MMC_NO_WRITE to platforms where mmc write/erase operation is not needed in spl. Use these CONFIGS to remove write/erase code in mmc.c and omap_hsmmc.c This reduces the spl size by ~1128 Bytes Are you running into a size limitation again? If not, I think we want We are always on the border. Minor fluctuations are affecting us. And our EMU boards(secure devices) are permanently broken due to this. I am not sure if this one helps EMU devices though. Ick, OK. So lets re-do this for now with #define CONFIG_FOO not #define CONFIG_FOO 1 and push for this going in now to solve problems with real devices. to wait until we sort out how SPL includes/excludes stuff moving forward as this shows there's probably a lot of other unused code being pulled in. We use -ffunction-sections -fdata-sections and --gc-sections while building SPL. So, un-necessary stuff will not be included unless the function pointers are set in some structures and not used. I think that is what is happening in this case. Other than that I am not expecting much scope for improvement. Exactly. I think part of the problem is that this discussion is buried in the thread about SPL YMODEM support, but Wolfgang isn't happy with some of the direction SPL stuff is heading. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] i.MX28: Fix ref_cpu clock setup
2. Please grep the locations where hw_clkctrl_frac0 is assigned as 32-bit and change those as well. Please do the same for hw_clkctrl_frac1 as well. There is one location in clock.c where it is read as 32-bit. I will check all hw_clkctrl_frac* register access, but tomorrow because the building closes is a couple of minutes. Ideally I'd like to set up these registers as uint8_t*. Any ideas? I'll also check if bye-lane shifting is done automatically here. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2] OMAP3: Add Corscience Tricorder board
On Sat, Jan 28, 2012 at 12:25 PM, Thomas Weber tho...@tweber.de wrote: From: Thomas Weber we...@corscience.de Tricorder is a board which is very similar to the Devkit8000. It is designed as a base platform for further medical devices. www.corscience.de/en/medical-engineering/products/multiparameter/mp10-board.html Signed-off-by: Thomas Weber we...@corscience.de Applied to u-boot-ti/master, thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()
On Tue, Jan 31, 2012 at 10:35 AM, Nicolas Dechesne n-deche...@ti.com wrote: In 8775471bb, the call to timer_init() was removed from common code and put in OMAP3 s_init() function. As a result the boot was broken on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix boot on all OMAP4 boards. Signed-off-by: Nicolas Dechesne n-deche...@ti.com Tested-by: Robert P. J. Day rpj...@crashcourse.ca Cc: Sandeep Paulraj s-paul...@ti.com Cc: Tom Rini tr...@ti.com Applied to u-boot-ti/master, thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm, davinci: cam_enc_4xx board updates
On Tue, Jan 17, 2012 at 12:20 AM, Heiko Schocher h...@denx.de wrote: - CONFIG_SYS_MMC_ENV_DEV, needed if environment on mmc - wait for 1 second timer in board_late_init() only, if timer is running. - add UBI/UBIFS support - add FIT images support - menu support - U-Boot max size now 0xa - SPL now Block 0 page 0 - new MTD partitioning 0x SPL 0x0002 UBL-Header 0x0004 UBL-Header 0x0006 UBL-Header 0x0008 UBoot (0xa(U-Boot length) + 0x6(3 spare blocks)) 0x0018 ENV- Variablen (1) 0x001a ENV- Variablen (2) 0x001c ENV- Variablen (reserved for Bad Block) 0x001e ENV- Variablen (reserved for Bad Block) 0x0020 UBI-Device UBI Volumes: „default“: contain environment-default values „rootfs1“: UBIFS root-fs (1); contain linux kernel image „rootfs2“: UBIFS root-fs (2); contain linux kernel image „data-ro“: UBIFS data (read only) „data-rw“: UBIFS data (read/write) - new environment variables: - app_reset (this is only passed per cmdline to linux) - dvn_app_vers string from ramdisk description contained in the FIT image - dvn_boot_vers string from ubootimage description contained in the FIT image - saveparms, restoreparms, restoretmpparms, savetmpparms helper for saving network parameter. - ubiargs set ubi kernel cmdlinargs for booting with a ubifs rootfs - ubi_ubi boot with reading kernel image from ubifs, and use a ubifs as rootfs Signed-off-by: Heiko Schocher h...@denx.de Cc: Sandeep Paulraj s-paul...@ti.com Cc: Tom Rini tom.r...@gmail.com Cc: Albert ARIBAUD albert.u.b...@aribaud.net Cc: Mike Frysinger vap...@gentoo.org Cc: Wolfgang Denk w...@denx.de --- - checkpatch shows no errors/warnings - patches needed for this patch: - arm, davinci: add workaround for not resetting DMA bus and VPSS modules http://patchwork.ozlabs.org/patch/136155/ - arm, davinci: add timer defines for tcr field http://patchwork.ozlabs.org/patch/136156/ - common, menu: enhancements http://lists.denx.de/pipermail/u-boot/2012-January/115904.html patches: - common: add possibility for readline_into_buffer timeout http://patchwork.ozlabs.org/patch/136415 - common, menu: add statusline support http://patchwork.ozlabs.org/patch/136417 - common, menu: show menu on startup if CONFIG_MENU_SHOW is defined http://patchwork.ozlabs.org/patch/136418 - a MAKEALL -a arm compiles fine with this patches All of these are now applied to u-boot-ti/master, thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-ti/master
Hello, The following changes since commit 78936e6d110bbcfe6db3406456c16a7a174ae031: Tom Rini (1): OMAP3: Correct get_sdr_cs_offset mask are available in the git repository at: git://git.denx.de/u-boot-ti.git master Dechesne, Nicolas (1): OMAP SPL: Fix missing timer_init() call in OMAP4 s_init() Heiko Schocher (7): arm, davinci: add workaround for not resetting DMA bus and VPSS modules arm, davinci: add timer defines for tcr field common: add possibility for readline_into_buffer timeout common, menu: add statusline support common, menu: show menu on startup if CONFIG_MENU_SHOW is defined common, menu: do not trigger timeout again, if a line is read arm, davinci: cam_enc_4xx board updates Thomas Weber (1): OMAP3: Add Corscience Tricorder board MAINTAINERS|1 + arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c| 52 ++- arch/arm/cpu/armv7/omap-common/hwinit-common.c |2 + arch/arm/include/asm/arch-davinci/dm365_lowlevel.h |1 - arch/arm/include/asm/arch-davinci/hardware.h |9 + arch/arm/include/asm/arch-davinci/timer_defs.h | 16 + board/ait/cam_enc_4xx/cam_enc_4xx.c| 667 +++- board/ait/cam_enc_4xx/ublimage.cfg |3 +- board/corscience/tricorder/Makefile| 46 ++ board/corscience/tricorder/tricorder.c | 105 +++ board/corscience/tricorder/tricorder.h | 375 +++ boards.cfg |1 + common/cmd_nvedit.c|2 +- common/main.c | 24 +- common/menu.c | 15 +- doc/README.menu| 10 + include/common.h |3 +- include/configs/cam_enc_4xx.h | 131 +++- include/configs/tricorder.h| 320 ++ include/menu.h |4 + 20 files changed, 1745 insertions(+), 42 deletions(-) create mode 100644 board/corscience/tricorder/Makefile create mode 100644 board/corscience/tricorder/tricorder.c create mode 100644 board/corscience/tricorder/tricorder.h create mode 100644 include/configs/tricorder.h After talking with Wolfgang off-list, he's fine with the common menu changes coming in via this tree. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Avoiding reload on ARM U-BOOT
Hello everyone im trying to port u-boot 2011-09 to a new board with an arm based SOC i found that u-boot will always relocate the code even if it is placed already in DDR which is the case with my SOC. is there any clean way to avoid relocating the u-boot ? does the various SPL configs have something to do with that ? if yes which one should i define ? Thanks in advance Yehuda -- View this message in context: http://old.nabble.com/Avoiding-reload-on-ARM-U-BOOT-tp33250726p33250726.html Sent from the Uboot - Users mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] i.MX28: Fix ref_cpu clock setup
On 2/2/12, Robert Deliën rob...@delien.nl wrote: Ideally I'd like to set up these registers as uint8_t*. Any ideas? I'll also check if bye-lane shifting is done automatically here. You can write: writeb(19 , clkctrl_regs-hw_clkctrl_frac0); Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] i.MX28: Fix ref_cpu clock setup
Hi, This patch fixes ref_cpu clock setup. This bug leads to a hanging board after rebooting from the Kernel, due to failing memory size detection: U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00) Freescale i.MX28 family I2C: ready DRAM: 0 Bytes The cause of the bug is register hw_clkctrl_frac0 being accessed as a 32-bit long, whereas the manual specifically states it can be accessed as bytes only. Applying this patch fixes this problem. Hi, you're only writing data to the register, not clearing them. So maybe some bits remain set? Anyway, can you please submit proper patch with git send-email? Thanks! M Signed-off-by: Robert Delien (rob...@delien.nl) From: Marek Vasut [marek.va...@gmail.com] Sent: 26 January 2012 19:32 To: Fabio Estevam Cc: Robert Deliën; u-boot@lists.denx.de Subject: Re: mx28 spl power cpu clock configuration Hi Robert, On 1/25/12, Marek Vasut marek.va...@gmail.com wrote: Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock gating - before disabling PLL bypass? This seems reasonable. Fabio, can you comment? Could you please post a patch with your proposed change so that we can test it? Hi Fabio, I bought a really crappy custom board a few days ago (some china-made crap) sporting mx287, but apparently I'm hitting similar issue you do here. When I swap power_init and mem_init though, the board boots fine, othervise it hangs. M ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] i.MX28: Fix ref_cpu clock setup
Hi, In addition to my first patch, please consider accepting this patch too. It prevents needless switching on and off PLL bypass mode and it allow single stepping through the SPL. Hi, this is how the imx-bootlets does it though. It's likely that FSL wants the PLL0 to run from XTAL when doing power configuration? M This patch removes mx28_power_clock2xtal, because all this function does is switching to reset-defaults, at a moment only reset defaults are already active. It removes mx28_power_clock2pll becasue it is incomplete and because mx28_mem_init_clock does the same thing a little later on and does it corectly. Maybe clock2pll should be fixed then ? M Signed-off-by: Robert Delien (rob...@delien.nl) From: Marek Vasut [marek.va...@gmail.com] Sent: 26 January 2012 19:32 To: Fabio Estevam Cc: Robert Deliën; u-boot@lists.denx.de Subject: Re: mx28 spl power cpu clock configuration Hi Robert, On 1/25/12, Marek Vasut marek.va...@gmail.com wrote: Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock gating - before disabling PLL bypass? This seems reasonable. Fabio, can you comment? Could you please post a patch with your proposed change so that we can test it? Hi Fabio, I bought a really crappy custom board a few days ago (some china-made crap) sporting mx287, but apparently I'm hitting similar issue you do here. When I swap power_init and mem_init though, the board boots fine, othervise it hangs. M ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Avoiding reload on ARM U-BOOT
Hello everyone im trying to port u-boot 2011-09 to a new board with an arm based SOC i found that u-boot will always relocate the code even if it is placed already in DDR which is the case with my SOC. The u-boot is always relocated to the end of the DRAM, which is likely what you want. And it's quite a quick process. So if you are manufacturing your soc with various size of RAM, you want the relocation to happen. What SoC is that anyway? is there any clean way to avoid relocating the u-boot ? does the various SPL configs have something to do with that ? Not really and you don't want this to happen. M if yes which one should i define ? Thanks in advance Yehuda ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 85xx custodianship
On Wednesday 01 February 2012 20:18:09 Andy Fleming wrote: Kumar, in connection with his imminent departure from Freescale, has asked Wolfgang to step down from custodianship for U-Boot for 85xx and 86xx. As such, I will be re-assuming those duties. Please make sure to copy me on all 85xx-related patches in the future (most of the patches have been, so this shouldn't be too disruptive a change). update doc/git-mailrc too ? :) -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 4/4] EXYNOS: SMDK5250: Add MMC SPL support
On Thursday 02 February 2012 04:11:27 Chander Kashyap wrote:
--- /dev/null
+++ b/board/samsung/smdk5250/tools/mkexynos_image.c
tools should be in tools/. there are already plenty of examples in there (see
tools/msxboot.c as the first example i found by reading tools/Makefile).
+int main(int argc, char **argv)
+{
...
+ unsigned char buffer[BUFSIZE] = {0};
this is an implicit memset() and from what i can see in the code, useless.
you read() the entire buffer, so there's no need to initialize it.
+ if (argc != 3) {
+ printf( %d Wrong number of arguments\n, argc);
this should tell the user how to use the tool.
fprintf(stderr, Usage: %s infile outfile\n, argv[0]);
+ if (ifd)
+ close(ifd);
this if() is wrong (0 is a valid fd) and useless (you already abort if ifd did
not succeed). just delete the if statement.
+ len = lseek(ifd, 0, SEEK_END);
+ lseek(ifd, 0, SEEK_SET);
lazy man's stat() :P. just use stat(). and change the type of len to
off_t.
+ count = (len CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
+
+ if (read(ifd, buffer, count) != count) {
count should be a ssize_t. although, this doesn't handle partial interrupted
reads, so i wonder if this could shouldn't just be changed to use stdio
fopen/fread. probably would be simpler that way too.
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
these if checks are wrong for the same reason mentioned above
+ unsigned long checksum = 0;
...
+ for (i = 0, checksum = 0; i CHECKSUM_OFFSET; i++)
+ checksum += buffer[i];
+ memcpy(buffer[CHECKSUM_OFFSET], checksum, sizeof(checksum));
pretty sure this fails if this tool is run on a big-endian machine, as well as
64bit vs 32bit. change the type of checksum to uint32_t, then use something
like:
put_unaligned_le32(checksum, buffer[CHECKSUM_OFFSET]);
+ if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
same issues as the read() mentioned above
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
same bad if() logic
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
same bad if() logic
-mike
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Re: [U-Boot] [PATCH v5 08/18] tegra: fdt: Add additional USB binding
On 01/24/2012 04:21 PM, Simon Glass wrote: This adds a property to indicate a port which can switch between host and device mode. ... diff --git a/doc/device-tree-bindings/usb/tegra-usb.txt b/doc/device-tree-bindings/usb/tegra-usb.txt ... +Optional properties: ... + - nvidia,has-legacy-mode : boolean indicates whether this controller can +operate in legacy mode (as APX 2500 / 2600). In legacy mode some +registers are accessed through the APB_MISC base address instead of +the USB controller. I was hoping to represent this as a different compatible value, in the same way as one of Tegra's I2C controllers is, eg. nvidia,tegra20-ehci and nvidia,tegra20-ehci-legacy. However, I suppose representing this using a property is OK too. Either way, can you please also push this patch to the Linux kernel (and the associated changes to tegra*.dtsi) in order to run it past the other Tegra maintainers before committing to it within U-Boot. Thanks. -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Porting YAFFS2 to U-boot
I am newbie in this. Anybody done it? Any lead is appreciated. Cheers, Bud Miljkovic -Original Message- From: Marek Vasut [mailto:marek.va...@gmail.com] Sent: Wednesday, 1 February 2012 11:58 p.m. To: Wolfgang Denk Cc: u-boot@lists.denx.de; Bud Miljkovic Subject: Re: [U-Boot] Can u-Boot Ran from RAM? Dear Marek Vasut, In message 20120201.09465.marek.va...@gmail.com you wrote: On Monday 30 January 2012 23:07:05 Bud Miljkovic wrote: While getting acquainted with possible u-Boot development issues, I read FAQ 14.2.1. Can U-Boot be configured such that it can be started in RAM? and was puzzled to learn that u-Boot cannot run from RAM. you misread it. the question is for people who have loaded u-boot, and then want to load another copy of u-boot into ram and then execute that directly. so the question is can u-boot be *started in ram* and the answer is no. The answer is yes if you know how to do it ;-) The answer is NO. You cannot load the _normal_ U-Boot image to RAM and start it. You must prepare a _special_ image which omits all the initializations that are normally included. You can on PXA ;-) This FAQ addresses the situation where people want to load and run their _normal_ images before burning these to flash. And this CANNOT be done like that. You're certainly right this is true for general case, but there are special cases where you can load u-boot from u-boot without any harm (PXA is the example). Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 10/18] tegra: usb: fdt: Add additional device tree definitions for USB ports
On 01/24/2012 04:21 PM, Simon Glass wrote: This adds clock references to the USB part of the device tree for U-Boot. The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there. The patch below does more than what's covered by this description... Signed-off-by: Simon Glass s...@chromium.org --- Changes in v5: - Add dr_mode property to control host/device/otg mode - Add nvidia,has-legacy-mode property per review comments - Change device tree comment style from // to /* */ arch/arm/dts/tegra20.dtsi |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index ec75747..b2e3a40 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -176,6 +176,9 @@ reg = 0xc500 0x4000; interrupts = 52 ; phy_type = utmi; + clocks = periph_clk 22; /* PERIPH_ID_USBD */ + dr_mode = otg; The dr_mode value is board-specific, so should be in tegra-seaboard.dts not tegra20.dtsi. For example, on true Seaboard, perhaps USB3 could operate in otg mode since it's an external port, whereas on Springbank, USB3 is hard-wired to a keyboard controller, so should be marked host mode only. Related, I assume that any port marked as otg needs to have a VBUS GPIO defined so that it can be turned off in device mode, or is VBUS controlled by some other mechanism in some cases? Given that, I /think/ you can't actually mark USB3 as otg or device on Seaboard since there's no VBUS GPIO. -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Porting YAFFS2 to U-boot
On Thursday 02 February 2012 16:40:45 Bud Miljkovic wrote: I am newbie in this. Anybody done it? Any lead is appreciated. please do not hijack threads. do not just pick a random e-mail and hit reply. start a new one from scratch. as for your question, check out the latest git. yaffs2 is already in u-boot and has been for some time. -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 18/18] tegra: fdt: Enable FDT support for Seaboard
On 01/24/2012 04:21 PM, Simon Glass wrote: This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present. Signed-off-by: Simon Glass s...@chromium.org Aside from the issues I've just mentioned in my recent emails, and from needing to update to the clock binding we discussed on the Linux mailing lists, the whole series is: Acked-by: Stephen Warren swar...@nvidia.com -- nvpublic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] da850evm: read mac address from I2C EEPROM on AM18x EVM
Dear Manjunath Hadli, In message 1328190138-5276-3-git-send-email-manjunath.ha...@ti.com you wrote: add support to read mac address for AM18x EVM manufactured from Spectrum digital which have mac address stored in I2C EEPROM manfactured by WINBOND. This patch reads mac address from I2C EEPROM and updates environment variable if not set. Introduced a config option CONFIG_MAC_ADDR_IN_EEPROM to where to look for the mac address. Signed-off-by: Manjunath Hadli manjunath.ha...@ti.com Cc: Tom Rini tr...@ti.com NAK. This has been discussed a thousand times before, so please look it up in the archives. The environment always has precedence. If there are several places to store tha MAC address, and the values don;t match, a warning must be issued. etc. While you are at it, the implementation of davinci_sync_env_enetaddr() should be cleaned up as well. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Fascinating, a totally parochial attitude. -- Spock, Metamorphosis, stardate 3219.8 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Porting YAFFS2 to U-boot
Bud Last time I looked, the yaffs code in u-boot is pretty old and I would recommend refreshing it. -- Charles On Friday 03 February 2012 10:40:45 Bud Miljkovic wrote: I am newbie in this. Anybody done it? Any lead is appreciated. Cheers, Bud Miljkovic -Original Message- From: Marek Vasut [mailto:marek.va...@gmail.com] Sent: Wednesday, 1 February 2012 11:58 p.m. To: Wolfgang Denk Cc: u-boot@lists.denx.de; Bud Miljkovic Subject: Re: [U-Boot] Can u-Boot Ran from RAM? Dear Marek Vasut, In message 20120201.09465.marek.va...@gmail.com you wrote: On Monday 30 January 2012 23:07:05 Bud Miljkovic wrote: While getting acquainted with possible u-Boot development issues, I read FAQ 14.2.1. Can U-Boot be configured such that it can be started in RAM? and was puzzled to learn that u-Boot cannot run from RAM. you misread it. the question is for people who have loaded u-boot, and then want to load another copy of u-boot into ram and then execute that directly. so the question is can u-boot be *started in ram* and the answer is no. The answer is yes if you know how to do it ;-) The answer is NO. You cannot load the _normal_ U-Boot image to RAM and start it. You must prepare a _special_ image which omits all the initializations that are normally included. You can on PXA ;-) This FAQ addresses the situation where people want to load and run their _normal_ images before burning these to flash. And this CANNOT be done like that. You're certainly right this is true for general case, but there are special cases where you can load u-boot from u-boot without any harm (PXA is the example). Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] doc: fix typos
From: Peter Meerwald p.meerw...@bct-electronic.com Signed-off-by: Peter Meerwald p.meerw...@bct-electronic.com --- doc/README.SPL |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/README.SPL b/doc/README.SPL index f01a8bd..0276953 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -42,8 +42,8 @@ The building of SPL images can be with: #define CONFIG_SPL -Because SPL images normally have a different text base, one have to be -configured by defining CONFIG_SPL_TEXT_BASE. The linker script have to be +Because SPL images normally have a different text base, one has to be +configured by defining CONFIG_SPL_TEXT_BASE. The linker script has to be defined with CONFIG_SPL_LDSCRIPT. To support generic U-Boot libraries and drivers in the SPL binary one can -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] beagle: fix typos
From: Peter Meerwald p.meerw...@bct-electronic.com
Signed-off-by: Peter Meerwald p.meerw...@bct-electronic.com
---
board/ti/beagle/beagle.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index 18bfaa8..c0a94a9 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -536,7 +536,7 @@ static const struct venc_regs venc_config_std_tv = {
* Configure Timings for DVI D
*/
static const struct panel_config dvid_cfg = {
- .timing_h = 0x0ff03f31, /* Horizantal timing */
+ .timing_h = 0x0ff03f31, /* Horizontal timing */
.timing_v = 0x01400504, /* Vertical timing */
.pol_freq = 0x7028, /* Pol Freq */
.divisor= 0x00010006, /* 72Mhz Pixel Clock */
@@ -548,7 +548,7 @@ static const struct panel_config dvid_cfg = {
};
static const struct panel_config dvid_cfg_xm = {
- .timing_h = 0x1a4024c9, /* Horizantal timing */
+ .timing_h = 0x1a4024c9, /* Horizontal timing */
.timing_v = 0x02c00509, /* Vertical timing */
.pol_freq = 0x7028, /* Pol Freq */
.divisor= 0x00010001, /* 96MHz Pixel Clock */
--
1.7.4.1
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[U-Boot] [PATCH] omap3: fix comment typos
From: Peter Meerwald p.meerw...@bct-electronic.com
Signed-off-by: Peter Meerwald p.meerw...@bct-electronic.com
---
arch/arm/cpu/armv7/omap3/board.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 871aa37..bdf676f 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -144,7 +144,7 @@ void secureworld_exit()
{
unsigned long i;
- /* configrue non-secure access control register */
+ /* configure non-secure access control register */
__asm__ __volatile__(mrc p15, 0, %0, c1, c1, 2:=r(i));
/* enabling co-processor CP10 and CP11 accesses in NS world */
__asm__ __volatile__(orr %0, %0, #0xC00:=r(i));
@@ -389,7 +389,7 @@ static void omap3_setup_aux_cr(void)
{
/* Workaround for Cortex-A8 errata: #454179 #430973
* Set IBE bit
-* Set Disable Brach Size Mispredicts bit
+* Set Disable Branch Size Mispredicts bit
* Workaround for erratum #621766
* Enable L1NEON bit
* ACR |= (IBE | DBSM | L1NEON) = ACR |= 0xE0
--
1.7.4.1
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[U-Boot] [PATCH] Blackfin: bfin_nand: mark local func static
This devready func is only used in this driver, so mark it static.
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
drivers/mtd/nand/bfin_nand.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c
index 3ee060f..c7ddbb2 100644
--- a/drivers/mtd/nand/bfin_nand.c
+++ b/drivers/mtd/nand/bfin_nand.c
@@ -73,7 +73,7 @@ static void bfin_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
SSYNC();
}
-int bfin_nfc_devready(struct mtd_info *mtd)
+static int bfin_nfc_devready(struct mtd_info *mtd)
{
pr_stamp();
return (bfin_read_NFC_STAT() NBUSY) ? 1 : 0;
--
1.7.8.4
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[U-Boot] [PATCH] tools: checkstack.pl from Linux added to tools
Added from Linux - commit 62aa2b537c6f5957afd98e29f96897419ed5ebab
Signed-off-by: Tom Rini tr...@ti.com
---
Makefile|5 ++
tools/checkstack.pl | 172 +++
2 files changed, 177 insertions(+), 0 deletions(-)
create mode 100755 tools/checkstack.pl
diff --git a/Makefile b/Makefile
index 36246b6..7931615 100644
--- a/Makefile
+++ b/Makefile
@@ -529,6 +529,11 @@ TAG_SUBDIRS += include
FIND := find
FINDFLAGS := -L
+checkstack:
+ $(CROSS_COMPILE)objdump -d $(obj)u-boot \
+ `$(FIND) $(obj) -name u-boot-spl -print` | \
+ perl $(src)tools/checkstack.pl $(ARCH)
+
tags ctags:
ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \
-name '*.[chS]' -print`
diff --git a/tools/checkstack.pl b/tools/checkstack.pl
new file mode 100755
index 000..17e3843
--- /dev/null
+++ b/tools/checkstack.pl
@@ -0,0 +1,172 @@
+#!/usr/bin/perl
+
+# Check the stack usage of functions
+#
+# Copyright Joern Engel jo...@lazybastard.org
+# Inspired by Linus Torvalds
+# Original idea maybe from Keith Owens
+# s390 port and big speedup by Arnd Bergmann a...@bergmann-dalldorf.de
+# Mips port by Juan Quintela quint...@mandrakesoft.com
+# IA64 port via Andreas Dilger
+# Arm port by Holger Schurig
+# sh64 port by Paul Mundt
+# Random bits by Matt Mackall m...@selenic.com
+# M68k port by Geert Uytterhoeven and Andreas Schwab
+# AVR32 port by Haavard Skinnemoen (Atmel)
+# PARISC port by Kyle McMartin k...@parisc-linux.org
+# sparc port by Martin Habets errandir_n...@mph.eclipse.co.uk
+#
+# Usage:
+# objdump -d vmlinux | scripts/checkstack.pl [arch]
+#
+# TODO : Port to all architectures (one regex per arch)
+
+use strict;
+
+# check for arch
+#
+# $re is used for two matches:
+# $ (whole re) matches the complete objdump line with the stack growth
+# $1 (first bracket) matches the size of the stack growth
+#
+# $dre is similar, but for dynamic stack redutions:
+# $ (whole re) matches the complete objdump line with the stack growth
+# $1 (first bracket) matches the dynamic amount of the stack growth
+#
+# use anything else and feel the pain ;)
+my (@stack, $re, $dre, $x, $xs);
+{
+ my $arch = shift;
+ if ($arch eq ) {
+ $arch = `uname -m`;
+ chomp($arch);
+ }
+
+ $x = [0-9a-f]; # hex character
+ $xs = [0-9a-f ]; # hex character or space
+ if ($arch eq 'arm') {
+ #c0008ffc: e24dd064sub sp, sp, #100; 0x64
+ $re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
+ } elsif ($arch eq 'avr32') {
+ #808a: 20 1d sub sp,4
+ #8ca8: fa cd 05 b0 sub sp,sp,1456
+ $re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
+ } elsif ($arch =~ /^i[3456]86$/) {
+ #c0105234: 81 ec ac 05 00 00 sub$0x5ac,%esp
+ $re = qr/^.*[as][du][db]\$(0x$x{1,8}),\%esp$/o;
+ $dre = qr/^.*[as][du][db](%.*),\%esp$/o;
+ } elsif ($arch eq 'x86_64') {
+ #2f60: 48 81 ec e8 05 00 00sub$0x5e8,%rsp
+ $re = qr/^.*[as][du][db]\$(0x$x{1,8}),\%rsp$/o;
+ $dre = qr/^.*[as][du][db](\%.*),\%rsp$/o;
+ } elsif ($arch eq 'ia64') {
+ #e44011fc: 01 0f fc 8c adds r12=-384,r12
+ $re = qr/.*adds.*r12=-(([0-9]{2}|[3-9])[0-9]{2}),r12/o;
+ } elsif ($arch eq 'm68k') {
+ #2b6c: 4e56 fb70 linkw %fp,#-1168
+ # 1df770: defc ffe4 addaw #-28,%sp
+ $re = qr/.*(?:linkw %fp,|addaw )#-([0-9]{1,4})(?:,%sp)?$/o;
+ } elsif ($arch eq 'mips64') {
+ #8800402c: 67bdfff0daddiu sp,sp,-16
+ $re = qr/.*daddiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o;
+ } elsif ($arch eq 'mips') {
+ #88003254: 27bdffe0addiu sp,sp,-32
+ $re = qr/.*addiu.*sp,sp,-(([0-9]{2}|[3-9])[0-9]{2})/o;
+ } elsif ($arch eq 'parisc' || $arch eq 'parisc64') {
+ $re = qr/.*ldo ($x{1,8})\(sp\),sp/o;
+ } elsif ($arch eq 'ppc') {
+ #c00029f4: 94 21 ff 30 stwur1,-208(r1)
+ $re = qr/.*stwu.*r1,-($x{1,8})\(r1\)/o;
+ } elsif ($arch eq 'ppc64') {
+ #XXX
+ $re = qr/.*stdu.*r1,-($x{1,8})\(r1\)/o;
+ } elsif ($arch eq 'powerpc') {
+ $re = qr/.*st[dw]u.*r1,-($x{1,8})\(r1\)/o;
+ } elsif ($arch =~ /^s390x?$/) {
+ # 11160: a7 fb ff 60 aghi %r15,-160
+ # or
+ # 100092: e3 f0 ff c8 ff 71 lay %r15,-56(%r15)
+ $re =
[U-Boot] [PATCH v4 3/5] net: phy: add support for Micrel's KSZ9021
Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable disable_giga
can be used to disable 1000baseTx.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
---
drivers/net/phy/micrel.c | 87 ++
include/micrel.h | 16
include/phy.h|1 +
3 files changed, 104 insertions(+), 0 deletions(-)
create mode 100644 include/micrel.h
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index d4e64f2..e3043df 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -20,6 +20,9 @@
* author Andy Fleming
*
*/
+#include config.h
+#include common.h
+#include micrel.h
#include phy.h
static struct phy_driver KSZ804_driver = {
@@ -42,10 +45,94 @@ static struct phy_driver KS8721_driver = {
.shutdown = genphy_shutdown,
};
+/* ksz9021 PHY Registers */
+#define MII_KSZ9021_EXTENDED_CTRL 0x0b
+#define MII_KSZ9021_EXTENDED_DATAW 0x0c
+#define MII_KSZ9021_EXTENDED_DATAR 0x0d
+#define MII_KSZ9021_PHY_CTL0x1f
+#define MIIM_KSZ9021_PHYCTL_1000 (1 6)
+#define MIIM_KSZ9021_PHYCTL_100(1 5)
+#define MIIM_KSZ9021_PHYCTL_10 (1 4)
+#define MIIM_KSZ9021_PHYCTL_DUPLEX (1 3)
+
+#define CTRL1000_PREFER_MASTER (1 10)
+#define CTRL1000_CONFIG_MASTER (1 11)
+#define CTRL1000_MANUAL_CONFIG (1 12)
+
+int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
+{
+ /* extended registers */
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
+ return phy_write(phydev, MDIO_DEVAD_NONE,
+ MII_KSZ9021_EXTENDED_DATAW, val);
+}
+
+int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
+{
+ /* extended registers */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
+ return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
+}
+
+/* Micrel ksz9021 */
+static int ksz9021_config(struct phy_device *phydev)
+{
+ unsigned ctrl1000 = 0;
+ const unsigned master = CTRL1000_PREFER_MASTER |
+ CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
+ unsigned features = phydev-drv-features;
+
+ if (getenv(disable_giga))
+ features = ~(SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full);
+ /* force master mode for 1000BaseT due to chip errata */
+ if (features SUPPORTED_1000baseT_Half)
+ ctrl1000 |= ADVERTISE_1000HALF | master;
+ if (features SUPPORTED_1000baseT_Full)
+ ctrl1000 |= ADVERTISE_1000FULL | master;
+ phydev-advertising = phydev-supported = features;
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
+ genphy_config_aneg(phydev);
+ genphy_restart_aneg(phydev);
+ return 0;
+}
+
+static int ksz9021_startup(struct phy_device *phydev)
+{
+ unsigned phy_ctl;
+ genphy_update_link(phydev);
+ phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_PHY_CTL);
+
+ if (phy_ctl MIIM_KSZ9021_PHYCTL_DUPLEX)
+ phydev-duplex = DUPLEX_FULL;
+ else
+ phydev-duplex = DUPLEX_HALF;
+
+ if (phy_ctl MIIM_KSZ9021_PHYCTL_1000)
+ phydev-speed = SPEED_1000;
+ else if (phy_ctl MIIM_KSZ9021_PHYCTL_100)
+ phydev-speed = SPEED_100;
+ else if (phy_ctl MIIM_KSZ9021_PHYCTL_10)
+ phydev-speed = SPEED_10;
+ return 0;
+}
+
+static struct phy_driver ksz9021_driver = {
+ .name = Micrel ksz9021,
+ .uid = 0x221610,
+ .mask = 0xf0,
+ .features = PHY_GBIT_FEATURES,
+ .config = ksz9021_config,
+ .startup = ksz9021_startup,
+ .shutdown = genphy_shutdown,
+};
+
int phy_micrel_init(void)
{
phy_register(KSZ804_driver);
phy_register(KS8721_driver);
+ phy_register(ksz9021_driver);
return 0;
}
diff --git a/include/micrel.h b/include/micrel.h
new file mode 100644
index 000..25e8a46
--- /dev/null
+++ b/include/micrel.h
@@ -0,0 +1,16 @@
+#ifndef _MICREL_H
+
+#define MII_KSZ9021_EXT_COMMON_CTRL0x100
+#define MII_KSZ9021_EXT_STRAP_STATUS 0x101
+#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE 0x102
+#define MII_KSZ9021_EXT_OP_STRAP_STATUS0x103
+#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW 0x104
+#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW 0x105
+#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
+#define MII_KSZ9021_EXT_ANALOG_TEST0x107
+
+struct phy_device;
+int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
+int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
+
+#endif
diff --git a/include/phy.h b/include/phy.h
[U-Boot] [PATCH v4 5/5] i.mx6q: mx6qsabrelite: Update the network configuration
Define CONFIG_PHY_MICREL, and
minimize the tx clock delay.
There is an issue with 1000 baseTx mode on early revs
of the SabreLite boards. The center tap pin 9 of the mag RJ45
USB combo was connected to the 3.3 filtered supply. Letting
this pin float solved the problem. Symptoms of the problem
were packets with many extra zeroes tacked on the end, and random
bit flips causing a high rate of CRC errors. 10/100 baseTx worked
fine on all revs. To disable 1000 baseTx for these boards, simply
define the environment variable disable_giga. ie.
setenv disable_giga 1
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
---
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 51 +++--
include/configs/mx6qsabrelite.h |2 +
2 files changed, 16 insertions(+), 37 deletions(-)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index a53b01f..2847539 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -29,9 +29,9 @@
#include asm/gpio.h
#include mmc.h
#include fsl_esdhc.h
+#include micrel.h
#include miiphy.h
#include netdev.h
-
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
@@ -193,53 +193,30 @@ int board_mmc_init(bd_t *bis)
}
#endif
-#define MII_1000BASET_CTRL 0x9
-#define MII_EXTENDED_CTRL 0xb
-#define MII_EXTENDED_DATAW 0xc
-
-int fecmxc_mii_postcall(int phy)
+int board_phy_config(struct phy_device *phydev)
{
- /* prefer master mode */
- miiphy_write(FEC, phy, MII_1000BASET_CTRL, 0x0f00);
-
/* min rx data delay */
- miiphy_write(FEC, phy, MII_EXTENDED_CTRL, 0x8105);
- miiphy_write(FEC, phy, MII_EXTENDED_DATAW, 0x);
-
- /* max rx/tx clock delay, min rx/tx control delay */
- miiphy_write(FEC, phy, MII_EXTENDED_CTRL, 0x8104);
- miiphy_write(FEC, phy, MII_EXTENDED_DATAW, 0xf0f0);
- miiphy_write(FEC, phy, MII_EXTENDED_CTRL, 0x104);
-
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+ /* min tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+ /* max rx/tx clock delay, min rx/tx control */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+ if (phydev-drv-config)
+ phydev-drv-config(phydev);
return 0;
}
int board_eth_init(bd_t *bis)
{
- struct eth_device *dev;
int ret;
-
setup_iomux_enet();
-
ret = cpu_eth_init(bis);
- if (ret) {
+ if (ret)
printf(FEC MXC: %s:failed\n, __func__);
- return ret;
- }
-
- dev = eth_get_dev_by_name(FEC);
- if (!dev) {
- printf(FEC MXC: Unable to get FEC device entry\n);
- return -EINVAL;
- }
-
- ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
- if (ret) {
- printf(FEC MXC: Unable to register FEC mii postcall\n);
- return ret;
- }
-
- return 0;
+ return ret;
}
int board_early_init_f(void)
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 2e9775a..47a1832 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -67,6 +67,8 @@
#defineCONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIMEFEC
#define CONFIG_FEC_MXC_PHYADDR 6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
--
1.7.5.4
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[U-Boot] [PATCH v4 4/5] net: phy: make board_phy_config responsible for calling drv-config
Boards may have things they want done before or after normal phy config.
Letting the boards call drv-config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
---
board/freescale/corenet_ds/eth_p4080.c |2 ++
board/freescale/mpc8544ds/mpc8544ds.c |2 ++
drivers/net/phy/phy.c |5 ++---
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index 1f00c14..b87b092 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -96,6 +96,8 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval)
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) defined(CONFIG_PHY_TERANETICS)
int board_phy_config(struct phy_device *phydev)
{
+ if (phydev-drv-config)
+ phydev-drv-config(phydev);
if (phydev-drv-uid == PHY_UID_TN2020) {
unsigned long timeout = 1 * 1000; /* 1 seconds */
enum srds_prtcl device;
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c
b/board/freescale/mpc8544ds/mpc8544ds.c
index 6fe8d39..24a1715 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -261,6 +261,8 @@ int board_phy_config(struct phy_device *phydev)
uint phyid;
struct mii_dev *bus = phydev-bus;
+ if (phydev-drv-config)
+ phydev-drv-config(phydev);
if (do_once)
return 0;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index eb55180..7d327f7 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -733,6 +733,8 @@ int phy_startup(struct phy_device *phydev)
static int __board_phy_config(struct phy_device *phydev)
{
+ if (phydev-drv-config)
+ return phydev-drv-config(phydev);
return 0;
}
@@ -741,9 +743,6 @@ int board_phy_config(struct phy_device *phydev)
int phy_config(struct phy_device *phydev)
{
- if (phydev-drv-config)
- phydev-drv-config(phydev);
-
/* Invoke an optional board-specific helper */
board_phy_config(phydev);
--
1.7.5.4
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[U-Boot] [PATCH v4 1/5] net: fec_mxc: add 1000 Mbps selection
Define CONFIG_FEC_QUIRK_ENET_MAC and add to
board files mx6qarm2 and mx6qsabrelite.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
Acked-by: Dirk Behme dirk.be...@de.bosch.com
---
drivers/net/fec_mxc.c | 21 +++--
drivers/net/fec_mxc.h |2 ++
include/configs/mx6qarm2.h |1 +
include/configs/mx6qsabrelite.h |1 +
4 files changed, 23 insertions(+), 2 deletions(-)
This patch series is against Stefano's u-boot-imx
Patches 2/3 and 5 have changes from version 3
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ed73353..7c42b87 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -379,13 +379,14 @@ static int fec_set_hwaddr(struct eth_device *dev)
static int fec_open(struct eth_device *edev)
{
struct fec_priv *fec = (struct fec_priv *)edev-priv;
+ int speed;
debug(fec_open: fec_open(dev)\n);
/* full-duplex, heartbeat disabled */
writel(1 2, fec-eth-x_cntrl);
fec-rbd_index = 0;
-#if defined(CONFIG_MX6Q)
+#ifdef CONFIG_FEC_QUIRK_ENET_MAC
/* Enable ENET HW endian SWAP */
writel(readl(fec-eth-ecntrl) | FEC_ECNTRL_DBSWAP,
fec-eth-ecntrl);
@@ -428,9 +429,25 @@ static int fec_open(struct eth_device *edev)
#endif
miiphy_wait_aneg(edev);
- miiphy_speed(edev-name, fec-phy_id);
+ speed = miiphy_speed(edev-name, fec-phy_id);
miiphy_duplex(edev-name, fec-phy_id);
+#ifdef CONFIG_FEC_QUIRK_ENET_MAC
+ {
+ u32 ecr = readl(fec-eth-ecntrl) ~FEC_ECNTRL_SPEED;
+ u32 rcr = (readl(fec-eth-r_cntrl)
+ ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
+ FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ if (speed == _1000BASET)
+ ecr |= FEC_ECNTRL_SPEED;
+ else if (speed != _100BASET)
+ rcr |= FEC_RCNTRL_RMII_10T;
+ writel(ecr, fec-eth-ecntrl);
+ writel(rcr, fec-eth-r_cntrl);
+ }
+#endif
+ debug(%s:Speed=%i\n, __func__, speed);
+
/*
* Enable SmartDMA receive task
*/
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 9825eab..af33d21 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -198,6 +198,7 @@ struct ethernet_regs {
#define FEC_RCNTRL_FCE 0x0020
#define FEC_RCNTRL_RGMII 0x0040
#define FEC_RCNTRL_RMII0x0100
+#define FEC_RCNTRL_RMII_10T0x0200
#define FEC_TCNTRL_GTS 0x0001
#define FEC_TCNTRL_HBC 0x0002
@@ -207,6 +208,7 @@ struct ethernet_regs {
#define FEC_ECNTRL_RESET 0x0001 /* reset the FEC */
#define FEC_ECNTRL_ETHER_EN0x0002 /* enable the FEC */
+#define FEC_ECNTRL_SPEED 0x0020
#define FEC_ECNTRL_DBSWAP 0x0100
#define FEC_X_WMRK_STRFWD 0x0100
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 0962d3c..495a32a 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -61,6 +61,7 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#defineCONFIG_FEC_MXC
+#define CONFIG_FEC_QUIRK_ENET_MAC
#defineCONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#defineCONFIG_FEC_XCV_TYPE RGMII
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index d650ee3..2e9775a 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -61,6 +61,7 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#defineCONFIG_FEC_MXC
+#define CONFIG_FEC_QUIRK_ENET_MAC
#defineCONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#defineCONFIG_FEC_XCV_TYPE RGMII
--
1.7.5.4
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[U-Boot] [PATCH v4 2/5] net: fec_mxc: add PHYLIB support
Surround non PHYLIB routines miiphy_restart_aneg
and miiphy_wait_aneg with ifndef CONFIG_PHYLIB.
When later PHYLIB is required it is easy to delete
the non-PHYLIB code. This separation idea
came from Andy Fleming.
fec_miiphy_read, and fec_miiphy_write changed to
fec_phy_read, and fec_phy_write with argument changes.
Deprecated miiphy_register is no longer used. Both
old and new PHYLIB code now use mdio_register.
Cleanup some debug prints.
Inline function fec_miiphy_fec_to_eth is no longer necessary.
Moved to the single call location.
Signed-off-by: Troy Kisky troy.ki...@boundarydevices.com
---
drivers/net/fec_mxc.c | 144
drivers/net/fec_mxc.h |5 ++
2 files changed, 101 insertions(+), 48 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 7c42b87..039e13b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -70,34 +70,15 @@ static void swap_packet(uint32_t *packet, int length)
#endif
/*
- * The i.MX28 has two ethernet interfaces, but they are not equal.
- * Only the first one can access the MDIO bus.
- */
-#ifdef CONFIG_MX28
-static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
-{
- return (struct ethernet_regs *)MXS_ENET0_BASE;
-}
-#else
-static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
-{
- return fec-eth;
-}
-#endif
-
-/*
* MII-interface related functions
*/
-static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
- uint16_t *retVal)
+static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
+ uint8_t regAddr)
{
- struct eth_device *edev = eth_get_dev_by_name(dev);
- struct fec_priv *fec = (struct fec_priv *)edev-priv;
- struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
-
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
+ int val;
/*
* reading from any PHY's register is done by properly
@@ -129,10 +110,10 @@ static int fec_miiphy_read(const char *dev, uint8_t
phyAddr, uint8_t regAddr,
/*
* it's now safe to read the PHY's register
*/
- *retVal = readl(eth-mii_data);
- debug(fec_miiphy_read: phy: %02x reg:%02x val:%#x\n, phyAddr,
- regAddr, *retVal);
- return 0;
+ val = (unsigned short)readl(eth-mii_data);
+ debug(%s: phy: %02x reg:%02x val:%#x\n, __func__, phyAddr,
+ regAddr, val);
+ return val;
}
static void fec_mii_setspeed(struct fec_priv *fec)
@@ -143,16 +124,12 @@ static void fec_mii_setspeed(struct fec_priv *fec)
*/
writelimx_get_fecclk() / 100) + 2) / 5) 1,
fec-eth-mii_speed);
- debug(fec_init: mii_speed %08x\n,
- readl(fec-eth-mii_speed));
+ debug(%s: mii_speed %08x\n, __func__, readl(fec-eth-mii_speed));
}
-static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
- uint16_t data)
-{
- struct eth_device *edev = eth_get_dev_by_name(dev);
- struct fec_priv *fec = (struct fec_priv *)edev-priv;
- struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
+static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
+ uint8_t regAddr, uint16_t data)
+{
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
@@ -178,15 +155,28 @@ static int fec_miiphy_write(const char *dev, uint8_t
phyAddr, uint8_t regAddr,
* clear MII interrupt bit
*/
writel(FEC_IEVENT_MII, eth-ievent);
- debug(fec_miiphy_write: phy: %02x reg:%02x val:%#x\n, phyAddr,
+ debug(%s: phy: %02x reg:%02x val:%#x\n, __func__, phyAddr,
regAddr, data);
return 0;
}
+int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
+{
+ return fec_mdio_read(bus-priv, phyAddr, regAddr);
+}
+
+int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
+ u16 data)
+{
+ return fec_mdio_write(bus-priv, phyAddr, regAddr, data);
+}
+
+#ifndef CONFIG_PHYLIB
static int miiphy_restart_aneg(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev-priv;
+ struct ethernet_regs *eth = fec-bus-priv;
int ret = 0;
/*
@@ -194,19 +184,18 @@ static int miiphy_restart_aneg(struct eth_device *dev)
* Reset PHY, then delay 300ns
*/
#ifdef CONFIG_MX27
- miiphy_write(dev-name, fec-phy_id, MII_DCOUNTER, 0x00FF);
+ fec_mdio_write(eth, fec-phy_id, MII_DCOUNTER, 0x00FF);
#endif
- miiphy_write(dev-name, fec-phy_id, MII_BMCR,
- BMCR_RESET);
+
Re: [U-Boot] Porting YAFFS2 to U-boot
I have a pile of changes to u-boot that make yaffs work w/mtdparts (I.e. ymount /partition looks through mtdparts to find start/end blocks, etc) that works in u-boot-2011.06), and want to refresh that for a current u-boot, but it's gonna take time to get it into acceptable shape for submission. If anyone wants the raw changes to get a head start I'm happy to pass them along... Splat-fingered from my iPhone On Feb 2, 2012, at 5:20 PM, Charles Manning mannin...@actrix.gen.nz wrote: Bud Last time I looked, the yaffs code in u-boot is pretty old and I would recommend refreshing it. -- Charles On Friday 03 February 2012 10:40:45 Bud Miljkovic wrote: I am newbie in this. Anybody done it? Any lead is appreciated. Cheers, Bud Miljkovic -Original Message- From: Marek Vasut [mailto:marek.va...@gmail.com] Sent: Wednesday, 1 February 2012 11:58 p.m. To: Wolfgang Denk Cc: u-boot@lists.denx.de; Bud Miljkovic Subject: Re: [U-Boot] Can u-Boot Ran from RAM? Dear Marek Vasut, In message 20120201.09465.marek.va...@gmail.com you wrote: On Monday 30 January 2012 23:07:05 Bud Miljkovic wrote: While getting acquainted with possible u-Boot development issues, I read FAQ 14.2.1. Can U-Boot be configured such that it can be started in RAM? and was puzzled to learn that u-Boot cannot run from RAM. you misread it. the question is for people who have loaded u-boot, and then want to load another copy of u-boot into ram and then execute that directly. so the question is can u-boot be *started in ram* and the answer is no. The answer is yes if you know how to do it ;-) The answer is NO. You cannot load the _normal_ U-Boot image to RAM and start it. You must prepare a _special_ image which omits all the initializations that are normally included. You can on PXA ;-) This FAQ addresses the situation where people want to load and run their _normal_ images before burning these to flash. And this CANNOT be done like that. You're certainly right this is true for general case, but there are special cases where you can load u-boot from u-boot without any harm (PXA is the example). Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] MX5:MX53: support for Freescale MX53LOCO
Hi Stefano, I have cloned yesterday http://git.denx.de/u-boot.git on to my local machine and from there selected the v2011.12-rc3 tag. Then I configured the mx53loco board and successfully build u-boot.imx, copied the image to a SD card and powered it up. What I then got on the serial port terminal was as follows: U-Boot 2011.12-00201-g137703b (Feb 03 2012 - 11:12:00) CPU: Freescale i.MX53 family rev2.1 at 800 MHz Reset cause: POR Board: MX53 LOCO DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial Net: At this point, having printed Net: the program hags. I must say that I am a newbie here but I was able to successfully build and launch the same u-boot.imx image on my i.MX53 Quick Start Board, having obtained the source tree via: wget ftp://ftp.denx.de/pub/u-boot/u-boot-2011.12.tar.bz2. As per instructions I also had to apply the following patches: * 0001-mx53loco-enable-ext-support.patch * 0002-mx53loco-use-part-1.patch * 0001-net-eth.c-fix-eth_write_hwaddr-to-use-dev-enetaddr-a.patch The patches were obtained via wget https://raw.github.com/RobertCNelson/Bootloader-Builder//aster/patches/ https://raw.github.com/RobertCNelson/Bootloader-Builder/aster/patches/ ... I also, applied the same patches on the my v2011.12-rc3 tag but the resulting build .imx image gave the same output (as above) Is it possible that I did not get the correct tag? Any other ideas? Cheers, Bud Miljkovic ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Porting YAFFS2 to U-boot
Dear Charles Manning, In message 201202031119.57323.mannin...@actrix.gen.nz you wrote: Last time I looked, the yaffs code in u-boot is pretty old and I would recommend refreshing it. Patches are welcome! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It seems intuitively obvious to me, which means that it might be wrong. -- Chris Torek ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] MX5:MX53: support for Freescale MX53LOCO
Bud, 2012/2/3 Bud Miljkovic bud_miljko...@trimble.com: Hi Stefano, I have cloned yesterday http://git.denx.de/u-boot.git on to my local machine and from there selected the v2011.12-rc3 tag. Then I configured the mx53loco board and successfully build u-boot.imx, copied the image to a SD card and powered it up. What I then got on the serial port terminal was as follows: U-Boot 2011.12-00201-g137703b (Feb 03 2012 - 11:12:00) CPU: Freescale i.MX53 family rev2.1 at 800 MHz Reset cause: POR Board: MX53 LOCO DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: At this point, having printed Net: the program hags. I have fixed this issue by a recent commit which is queened in u-boot-imx and you can refer to the patch here: http://patchwork.ozlabs.org/patch/138761/ Jason ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] MX5:MX53: support for Freescale MX53LOCO
On 03/02/2012 06:58, Jason Liu wrote: Hi Bud, I have cloned yesterday http://git.denx.de/u-boot.git on to my local machine and from there selected the v2011.12-rc3 tag. Then I configured the mx53loco board and successfully build u-boot.imx, copied the image to a SD card and powered it up. What I then got on the serial port terminal was as follows: I have fixed this issue by a recent commit which is queened in u-boot-imx and you can refer to the patch here: http://patchwork.ozlabs.org/patch/138761/ You can also clone from http://git.denx.de/u-boot-imx.git, Jason's patch was already merged. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM ld: .bss overlaps section .rel.dyn
Albert, Any suggestions? Thanks Amit Virdi On 2/1/12, Amit Virdi amitvi...@gmail.com wrote: Hi All, I'm in the process of updating platform support for spear series of SoC on the latest u-boot. I picked u-boot v2011.12. I tried compiling for different spear boards (spear 300, 310, 300 and spear600). In every compilation, I'm getting following errors: --- arm-linux-ld: section .bss [007263cc - 00728c5b] overlaps section .rel.dyn [007263cc - 0072a623] arm-linux-ld: u-boot: section .bss lma 0x7263cc overlaps previous sections make: *** [u-boot] Error 1 --- This is one case. Now if I apply some patches -all of them are either enhancing the features or are bug fixes - over the base line code, my code compiles *after* certain patch. None of these patches is changing any linker script. I drilled down to the last patch that made the code compile without error. Specifically, that commit is configuring Network support for SPEAr SoCs. Anyways, I did try to compare the map files generated for the good and the bad case but really couldn't conclude much!! Any pointers? Thanks Amit Virdi ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM ld: .bss overlaps section .rel.dyn
Adding Albert now... On 2/3/12, Amit Virdi amitvi...@gmail.com wrote: Albert, Any suggestions? Thanks Amit Virdi On 2/1/12, Amit Virdi amitvi...@gmail.com wrote: Hi All, I'm in the process of updating platform support for spear series of SoC on the latest u-boot. I picked u-boot v2011.12. I tried compiling for different spear boards (spear 300, 310, 300 and spear600). In every compilation, I'm getting following errors: --- arm-linux-ld: section .bss [007263cc - 00728c5b] overlaps section .rel.dyn [007263cc - 0072a623] arm-linux-ld: u-boot: section .bss lma 0x7263cc overlaps previous sections make: *** [u-boot] Error 1 --- This is one case. Now if I apply some patches -all of them are either enhancing the features or are bug fixes - over the base line code, my code compiles *after* certain patch. None of these patches is changing any linker script. I drilled down to the last patch that made the code compile without error. Specifically, that commit is configuring Network support for SPEAr SoCs. Anyways, I did try to compare the map files generated for the good and the bad case but really couldn't conclude much!! Any pointers? Thanks Amit Virdi ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] i.MX28: Fix ref_cpu clock setup
Hi, This patch fixes ref_cpu clock setup. This bug leads to a hanging board after rebooting from the Kernel, due to failing memory size detection: U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00) Freescale i.MX28 family I2C: ready DRAM: 0 Bytes The cause of the bug is register hw_clkctrl_frac0 being accessed as a 32-bit long, whereas the manual specifically states it can be accessed as bytes only. Applying this patch fixes this problem. Signed-off-by: Robert Delien (rob...@delien.nl) Hi, I was thinking of this and we might need to introduce either special accessor for this particular register or rework include/regs-common.h and introduce mx28_reg_8 (which I don't think is a good idea). So Robert, what do you think about introducing a special accessor in include/regs-clkctrl for FRAC0/1? This though introduces a problem with usage of _set, _clk and _tog accesses, which might need a little thinking through. Thanks for this patch, you really did a good share of research on this one. M From: Marek Vasut [marek.va...@gmail.com] Sent: 26 January 2012 19:32 To: Fabio Estevam Cc: Robert Deliën; u-boot@lists.denx.de Subject: Re: mx28 spl power cpu clock configuration Hi Robert, On 1/25/12, Marek Vasut marek.va...@gmail.com wrote: Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock gating - before disabling PLL bypass? This seems reasonable. Fabio, can you comment? Could you please post a patch with your proposed change so that we can test it? Hi Fabio, I bought a really crappy custom board a few days ago (some china-made crap) sporting mx287, but apparently I'm hitting similar issue you do here. When I swap power_init and mem_init though, the board boots fine, othervise it hangs. M ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: sh_eth: Remove unnecessary return
--- drivers/net/sh_eth.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 1bc44a8..8d3dac2 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -94,7 +94,6 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) if (port_info-tx_desc_cur = port_info-tx_desc_base + NUM_TX_DESC) port_info-tx_desc_cur = port_info-tx_desc_base; - return ret; err: return ret; } -- 1.7.7.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: sh_eth: Add support SH7734 Ethernet device
SH7734 has one channel ethernet device.
This support 10/100/1000Base, and RMII/MII/GMII.
And this has the same structure as SH7763.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 17 +-
drivers/net/sh_eth.h | 85 ++
2 files changed, 74 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8d3dac2..c1abe7c 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -59,7 +59,7 @@ int sh_eth_send(struct eth_device *dev, volatile void
*packet, int len)
}
/* packet must be a 4 byte boundary */
- if ((int)packet (4 - 1)) {
+ if ((int)packet 3) {
printf(SHETHER_NAME : %s: packet not 4 byte alligned\n,
__func__);
ret = -EFAULT;
goto err;
@@ -138,7 +138,7 @@ int sh_eth_recv(struct eth_device *dev)
static int sh_eth_reset(struct sh_eth_dev *eth)
{
int port = eth-port;
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
@@ -208,7 +208,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the tx descriptor list. Must use physical
addresses */
outl(ADDR_TO_PHY(port_info-tx_desc_base), TDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(ADDR_TO_PHY(port_info-tx_desc_base), TDFAR(port));
outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
outl(0x01, TDFFR(port));/* Last discriptor bit */
@@ -276,7 +276,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the rx descriptor list */
outl(ADDR_TO_PHY(port_info-rx_desc_base), RDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(ADDR_TO_PHY(port_info-rx_desc_base), RDFAR(port));
outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
outl(RDFFR_RDLF, RDFFR(port));
@@ -346,7 +346,8 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
struct eth_device *dev = port_info-dev;
struct phy_device *phydev;
- phydev = phy_connect(miiphy_get_dev_by_name(dev-name),
+ phydev = phy_connect(
+ miiphy_get_dev_by_name(dev-name),
port_info-phy_addr, dev, PHY_INTERFACE_MODE_MII);
port_info-phydev = phydev;
phy_config(phydev);
@@ -398,7 +399,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
#endif
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(TPAUSER_TPAUSE, TPAUSER(port));
#elif defined(CONFIG_CPU_SH7757)
outl(TPAUSER_UNLIMITED, TPAUSER(port));
@@ -418,7 +419,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
/* Set the transfer speed */
if (phy-speed == 100) {
printf(SHETHER_NAME : 100Base/);
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(GECMR_100B, GECMR(port));
#elif defined(CONFIG_CPU_SH7757)
outl(1, RTRATE(port));
@@ -427,7 +428,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
#endif
} else if (phy-speed == 10) {
printf(SHETHER_NAME : 10Base/);
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(GECMR_10B, GECMR(port));
#elif defined(CONFIG_CPU_SH7757)
outl(0, RTRATE(port));
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 27fde05..1f646e2 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -188,13 +188,51 @@ struct sh_eth_dev {
#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x01c8)
+
+#elif defined(CONFIG_CPU_SH7734)
+#define BASE_IO_ADDR 0xFEE0
+
+#define EDSR(port) (BASE_IO_ADDR)
+
+#define TDLAR(port)(BASE_IO_ADDR + 0x0010)
+#define TDFAR(port)(BASE_IO_ADDR + 0x0014)
+#define TDFXR(port)(BASE_IO_ADDR + 0x0018)
+#define TDFFR(port)(BASE_IO_ADDR + 0x001c)
+#define RDLAR(port)(BASE_IO_ADDR + 0x0030)
+#define RDFAR(port)(BASE_IO_ADDR + 0x0034)
+#define RDFXR(port)(BASE_IO_ADDR + 0x0038)
+#define RDFFR(port)(BASE_IO_ADDR + 0x003c)
+
+#define EDMR(port) (BASE_IO_ADDR + 0x0400)
+#define EDTRR(port)(BASE_IO_ADDR + 0x0408)
+#define EDRRR(port)(BASE_IO_ADDR + 0x0410)
+#define EESR(port) (BASE_IO_ADDR + 0x0428)
+#define EESIPR(port) (BASE_IO_ADDR + 0x0430)
+#define TRSCER(port) (BASE_IO_ADDR + 0x0438)
+#define
[U-Boot] [PATCH] sh: Add support for r0p7734 board
The r0p7734 board has SH7734, 128MB DDR2-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - 128MB DDR2-SDRAM - 32MB NOR Flash memory - Serial console (SCIF) - Ethernet (SH-Ether/SMSC) Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- MAINTAINERS |1 + board/renesas/r0p7734/Makefile| 40 +++ board/renesas/r0p7734/lowlevel_init.S | 606 + board/renesas/r0p7734/r0p7734.c | 78 + boards.cfg|1 + include/configs/r0p7734.h | 167 + 6 files changed, 893 insertions(+), 0 deletions(-) create mode 100644 board/renesas/r0p7734/Makefile create mode 100644 board/renesas/r0p7734/lowlevel_init.S create mode 100644 board/renesas/r0p7734/r0p7734.c create mode 100644 include/configs/r0p7734.h diff --git a/MAINTAINERS b/MAINTAINERS index 4bf12b5..44394a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1069,6 +1069,7 @@ Nobuhiro Iwamatsu iwama...@nigauri.org AP325RXASH7723 SHMIN SH7706 ECOVEC SH7724 + R0P7734 SH7734 Mark Jonas mark.jo...@de.bosch.com diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile new file mode 100644 index 000..b8c0353 --- /dev/null +++ b/board/renesas/r0p7734/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2011 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := r0p7734.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S new file mode 100644 index 000..1a7f1ac --- /dev/null +++ b/board/renesas/r0p7734/lowlevel_init.S @@ -0,0 +1,606 @@ +/* + * Copyright (C) 2011 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include config.h +#include version.h +#include asm/processor.h +#include asm/macro.h + +#include asm/processor.h + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + /* WDT */ + write32 WDTCSR_A, WDTCSR_D + + /* MMU */ + write32 MMUCR_A, MMUCR_D + + write32 FRQCR2_A, FRQCR2_D + write32 FRQCR0_A, FRQCR0_D + + write32 CS0CTRL_A, CS0CTRL_D + write32 CS1CTRL_A, CS1CTRL_D + write32 CS0CTRL2_A, CS0CTRL2_D + + write32 CSPWCR0_A, CSPWCR0_D + write32 CSPWCR1_A, CSPWCR1_D + write32 CS1GDST_A, CS1GDST_D + + # clock mode check + mov.l MODEMR, r1 + mov.l @r1, r0 + and #6, r0 /* Check 1 and 2 bit.*/ + cmp/eq #2, r0 /* 0x02 is 533Mhz mode */ + bt init_lbsc_533 + +init_lbsc_400: + + write32 CSWCR0_A, CSWCR0_D_400 + write32 CSWCR1_A, CSWCR1_D + + bra init_dbsc3_400_pad + nop + + .align 2 + +MODEMR:.long 0xFFCC0020 +WDTCSR_A: .long 0xFFCC0004 +WDTCSR_D: .long 0xA500 +MMUCR_A: .long 0xFF10 +MMUCR_D: .long
[U-Boot] [PATCH] net: sh_eth: Fix build warnings and whitespace for sh_eth
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 27 +--
1 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index c1abe7c..e29061c 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -60,7 +60,8 @@ int sh_eth_send(struct eth_device *dev, volatile void
*packet, int len)
/* packet must be a 4 byte boundary */
if ((int)packet 3) {
- printf(SHETHER_NAME : %s: packet not 4 byte alligned\n,
__func__);
+ printf(SHETHER_NAME
+ : %s: packet not 4 byte alligned\n , __func__);
ret = -EFAULT;
goto err;
}
@@ -141,6 +142,8 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
int ret = 0, i;
+ port = eth-port;
+
/* Start e-dmac transmitter and receiver */
outl(EDSR_ENALL, EDSR(port));
@@ -159,6 +162,8 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
return ret;
#else
+ port = eth-port;
+
outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
udelay(3000);
outl(inl(EDMR(port)) ~EDMR_SRST, EDMR(port));
@@ -564,8 +569,10 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
outl(inl(PIR(port)) | PIR_MMD, PIR(port));
@@ -574,8 +581,10 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
outl(inl(PIR(port)) ~PIR_MMD, PIR(port));
@@ -584,8 +593,10 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus
*bus)
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
if (v)
outl(inl(PIR(port)) | PIR_MDO, PIR(port));
@@ -597,8 +608,10 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus,
int v)
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
*v = (inl(PIR(port)) PIR_MDI) 3;
@@ -607,8 +620,10 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus,
int *v)
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
if (v)
outl(inl(PIR(port)) | PIR_MDC, PIR(port));
--
1.7.7.3
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[U-Boot] Skipping relocation RAM to RAM, esp. on i.MX6?
Hi,
on i.MX6 devices, e.g. ARM2 or SabreLite, the ROM boot loader copies the
U-Boot image from the boot device, e.g. the SD card, to the main memory.
This does mean that U-Boot is started in RAM.
With this, one might wonder why any relocation RAM - RAM is done anyway
and if this could be skipped?
Looking into the details shows that board_init_f() in
arch/arm/lib/board.c and relocate_code() in arch/arm/cpu/armv7/start.S
[1] are involved in this.
In board_init_f() the relocation destination address 'addr' is
calculated. This is basically at the end of the available RAM (- some
space for various stuff like TLB tables etc.). At SabreLite this results
in 0x4FF8D000.
By the boot loader, the U-Boot is loaded to
CONFIG_SYS_TEXT_BASE0x1780
This results in relocate_code() copying U-Boot from RAM 0x1780 to
RAM 0x4FF8D000.
Setting CONFIG_SYS_TEXT_BASE to the relocation destination address
0x4FF8D000 does avoid the (unnecessary?) copy by
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
in relocate_code().
But:
1) The resulting image still runs without the relocation
(CONFIG_SYS_TEXT_BASE 0x4FF8D000). But e.g. the U-Boot command line
doesn't work properly any more. Most probably this is because not only
the copy is skipped by the 'beq clear_bss', but the whole 'fix .rel.dyn
relocations' is skipped too.
2) It's hard to set CONFIG_SYS_TEXT_BASE at compile time to the
relocation address calculated at runtime in board_init_f() due to the
amount of #ifdef and runtime calculation done there. So finding a
generic approach which could easily defined in the config files to avoid
the relocation seems difficult.
I haven't tried it, but for (1) it might help to not jump to clear_bss,
but instead jumping to the 'fix .rel.dyn relocations' section. Just
avoiding the extra copy.
For (2) I don't have an idea how to solve this cleanly.
Do I have missed anything? Is there a clean way to skip the extra copy
from RAM - RAM in this case? Any idea or opinions?
Many thanks and best regards
Dirk
[1]
arch/arm/cpu/armv7/start.S:
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 - scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 - source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0]*/
stmia r1!, {r9-r10} /* copy to target address [r1]*/
cmp r0, r2 /* until source end address [r2]*/
blo copy_loop
#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 - Text base */
sub r9, r6, r0 /* r9 - relocation offset */
ldr r10, _dynsym_start_ofs /* r10 - sym table ofs */
add r10, r10, r0/* r10 - sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 - rel dyn start ofs */
add r2, r2, r0 /* r2 - rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs/* r3 - rel dyn end ofs */
add r3, r3, r0 /* r3 - rel dyn end in FLASH */
fixloop:
ldr r0, [r2]/* r0 - location to fix up, IN FLASH!
*/
add r0, r0, r9 /* r0 - location to fix up in RAM */
ldr r1, [r2, #4]
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 - symbol index in .dynsym */
add r1, r10, r1 /* r1 - address of symbol in table */
ldr r1, [r1, #4]/* r1 - symbol value */
add r1, r1, r9 /* r1 - relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
b clear_bss
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
[U-Boot] [PATCH] sh: i2c: Add support I2C controller of SH7734
Renesas SH7734 has two I2C interfaceis.
This supports these I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/i2c/Makefile|1 +
drivers/i2c/sh_sh7734_i2c.c | 468 +++
2 files changed, 469 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/sh_sh7734_i2c.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 504db03..506269d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
+COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c
new file mode 100644
index 000..6c514b4
--- /dev/null
+++ b/drivers/i2c/sh_sh7734_i2c.c
@@ -0,0 +1,468 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+
+struct sh_i2c {
+ u8 iccr1;
+ u8 iccr2;
+ u8 icmr;
+ u8 icier;
+ u8 icsr;
+ u8 sar;
+ u8 icdrt;
+ u8 icdrr;
+ u8 nf2cyc;
+ u8 __pad0;
+ u8 __pad1;
+};
+
+static struct sh_i2c *base;
+static u8 iccr1_cks, nf2cyc;
+
+/* ICCR1 */
+#define SH_I2C_ICCR1_ICE (1 7)
+#define SH_I2C_ICCR1_RCVD (1 6)
+#define SH_I2C_ICCR1_MST (1 5)
+#define SH_I2C_ICCR1_TRS (1 4)
+#define SH_I2C_ICCR1_MTRS \
+ (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
+
+/* ICCR1 */
+#define SH_I2C_ICCR2_BBSY (1 7)
+#define SH_I2C_ICCR2_SCP (1 6)
+#define SH_I2C_ICCR2_SDAO (1 5)
+#define SH_I2C_ICCR2_SDAOP (1 4)
+#define SH_I2C_ICCR2_SCLO (1 3)
+#define SH_I2C_ICCR2_IICRST(1 1)
+
+#define SH_I2C_ICIER_TIE (1 7)
+#define SH_I2C_ICIER_TEIE (1 6)
+#define SH_I2C_ICIER_RIE (1 5)
+#define SH_I2C_ICIER_NAKIE (1 4)
+#define SH_I2C_ICIER_STIE (1 3)
+#define SH_I2C_ICIER_ACKE (1 2)
+#define SH_I2C_ICIER_ACKBR (1 1)
+#define SH_I2C_ICIER_ACKBT (1 0)
+
+#define SH_I2C_ICSR_TDRE (1 7)
+#define SH_I2C_ICSR_TEND (1 6)
+#define SH_I2C_ICSR_RDRF (1 5)
+#define SH_I2C_ICSR_NACKF (1 4)
+#define SH_I2C_ICSR_STOP (1 3)
+#define SH_I2C_ICSR_ALOVE (1 2)
+#define SH_I2C_ICSR_AAS(1 1)
+#define SH_I2C_ICSR_ADZ(1 0)
+
+#define IRQ_WAIT 1000
+
+
+static void sh_i2c_send_stop(struct sh_i2c *base)
+{
+ writeb(readb(base-iccr2) ~(SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP),
+ base-iccr2);
+}
+
+static int check_stop(struct sh_i2c *base)
+{
+ int i, ret = 1;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_STOP readb(base-icsr)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ writeb(readb(base-icsr) ~SH_I2C_ICSR_STOP, base-icsr);
+
+ return ret;
+}
+
+static int check_tend(struct sh_i2c *base, int stop)
+{
+ int i, ret = 1;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_TEND readb(base-icsr)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ if (stop) {
+ u8 data;
+
+ writeb(readb(base-icsr) ~SH_I2C_ICSR_STOP, base-icsr);
+
+ sh_i2c_send_stop(base);
+ }
+
+ writeb(readb(base-icsr) ~SH_I2C_ICSR_TEND, base-icsr);
+
+ return ret;
+}
+
+static int check_tdre(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_TDRE readb(base-icsr))
+ return 0;
+ udelay(10);
+ }
+
+ return 1;
+}
+
+static int check_rdrf(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_RDRF readb(base-icsr))
+ return 0;
+ udelay(10);
+ }
+
+ return 1;
+}
+
+static int check_bbsy(struct sh_i2c *base)
+{
+
[U-Boot] [PATCH] sh: r0p7734: Add support I2C and set MAC address
r0p7734 board stores away MAC address in EEPROM.
This sets an MAC address to reading, environment variable
from an EEPROM by supporting I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/renesas/r0p7734/r0p7734.c | 19 ++-
include/configs/r0p7734.h | 16
2 files changed, 34 insertions(+), 1 deletions(-)
diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c
index 80f4329..656b9ee 100644
--- a/board/renesas/r0p7734/r0p7734.c
+++ b/board/renesas/r0p7734/r0p7734.c
@@ -24,6 +24,7 @@
#include common.h
#include asm/io.h
#include asm/processor.h
+#include i2c.h
#include netdev.h
DECLARE_GLOBAL_DATA_PTR;
@@ -50,11 +51,28 @@ int checkboard(void)
int board_init(void)
{
+ u8 mac[6];
+ char env_mac[17];
+ int i;
+
#if defined(CONFIG_SH_ETHER)
u32 r = readl(MSTPSR1);
if (r MSTPSR1_GETHER)
writel((r ~MSTPSR1_GETHER), MSTPCR1);
#endif
+
+ /* Read MAC address */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 0 */
+
+ i2c_read(0x50, 0x10, 0, mac, 6);
+
+ /* Set MAC address */
+ printf(%02X:%02X:%02X:%02X:%02X:%02X\n,
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ sprintf(env_mac, %02X:%02X:%02X:%02X:%02X:%02X,
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
return 0;
}
@@ -75,4 +93,3 @@ int board_eth_init(bd_t *bis)
return rc;
}
#endif
-
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index d73cc4d..22c1ef7 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -34,6 +34,7 @@
#define CONFIG_400MHZ_MODE 1
/* #define CONFIG_533MHZ_MODE 1 */
+#define BOARD_LATE_INIT1
#define CONFIG_SYS_TEXT_BASE 0x8FFC
#define CONFIG_CMD_FLASH
@@ -53,6 +54,21 @@
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_SH7734_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MULTI_BUS1
+#define CONFIG_SYS_MAX_I2C_BUS 2
+#define CONFIG_SYS_I2C_MODULE 0
+#define CONFIG_SYS_I2C_SPEED10 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE0x50
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK 5
+#define CONFIG_SH_I2C_BASE0 0xFFC7
+#define CONFIG_SH_I2C_BASE1 0xFFC71000
+
/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
--
1.7.7.3
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