> Hi, > > This patch fixes ref_cpu clock setup. This bug leads to a hanging board > after rebooting from the Kernel, due to failing memory size detection: > U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00) > > Freescale i.MX28 family > I2C: ready > DRAM: 0 Bytes > > The cause of the bug is register hw_clkctrl_frac0 being accessed as > a 32-bit long, whereas the manual specifically states it can be accessed > as bytes only. > Applying this patch fixes this problem. > > Signed-off-by: Robert Delien (rob...@delien.nl)
Hi, I was thinking of this and we might need to introduce either special accessor for this particular register or rework include/regs-common.h and introduce mx28_reg_8 (which I don't think is a good idea). So Robert, what do you think about introducing a special accessor in include/regs-clkctrl for FRAC0/1? This though introduces a problem with usage of _set, _clk and _tog accesses, which might need a little thinking through. Thanks for this patch, you really did a good share of research on this one. M > > ________________________________________ > From: Marek Vasut [marek.va...@gmail.com] > Sent: 26 January 2012 19:32 > To: Fabio Estevam > Cc: Robert Deliën; u-boot@lists.denx.de > Subject: Re: mx28 spl power cpu clock configuration > > > Hi Robert, > > > > On 1/25/12, Marek Vasut <marek.va...@gmail.com> wrote: > > >> Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock > > >> gating - before disabling PLL bypass? > > > > > > This seems reasonable. Fabio, can you comment? > > > > Could you please post a patch with your proposed change so that we can > > test it? > > Hi Fabio, > > I bought a really crappy custom board a few days ago (some china-made crap) > sporting mx287, but apparently I'm hitting similar issue you do here. > > When I swap power_init and mem_init though, the board boots fine, othervise > it hangs. > > M _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot