[U-Boot] [PATCH] arm: omap3: cm-t35: minor comment and printf change

[Igor Grinberg]

Fix the comment to reflect the actual function call time.
Change the printf message to look nicer in the context it might be printed.

Signed-off-by: Igor Grinberg 
---
 board/cm_t35/cm_t35.c |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c
index 995dd41..6a090e0 100644
--- a/board/cm_t35/cm_t35.c
+++ b/board/cm_t35/cm_t35.c
@@ -74,7 +74,7 @@ static u32 gpmc_nand_config[GPMC_MAX_REG] = {
 
 /*
  * Routine: board_init
- * Description: Early hardware init.
+ * Description: hardware init.
  */
 int board_init(void)
 {
@@ -438,7 +438,7 @@ int board_eth_init(bd_t *bis)
 
rc1 = handle_mac_address();
if (rc1)
-   printf("CM-T3x: No MAC address found\n");
+   printf("No MAC address found! ");
 
rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
if (rc1 > 0)
-- 
1.7.3.4

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[U-Boot] [PATCH 1/1] tegra: seaboard: Initialize multiple USB controllers at once

[Jim Lin]

From: Jim Lin 

Add support for command line "usb reset" or "usb start" to initialize
, "usb stop" to stop multiple USB controllers at once.
Other commands like "usb tree" also support multiple controllers.

New added definitions in header file are:
CONFIG_USB_INIT_MULTI
CONFIG_USB_MAX_CONTROLLER_COUNT

Signed-off-by: Jim Lin 
---
 arch/arm/cpu/armv7/tegra2/usb.c|   15 +++
 arch/arm/include/asm/arch-tegra2/usb.h |4 +
 common/cmd_usb.c   |   10 ++
 common/usb.c   |  108 ++
 common/usb_hub.c   |4 +
 drivers/usb/host/ehci-hcd.c|  192 
 drivers/usb/host/ehci-tegra.c  |   17 +++-
 drivers/usb/host/ehci.h|5 +
 include/configs/seaboard.h |2 +
 include/usb.h  |   12 ++
 10 files changed, 368 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c
index c80de7f..3d2cfb9 100644
--- a/arch/arm/cpu/armv7/tegra2/usb.c
+++ b/arch/arm/cpu/armv7/tegra2/usb.c
@@ -352,7 +352,11 @@ int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 
*hcor)

if (portnum >= port_count)
return -1;
+#ifdef CONFIG_USB_INIT_MULTI
+   tegrausb_stop_port(portnum);
+#else
tegrausb_stop_port();
+#endif
set_host_mode(&port[portnum]);

usbctlr = port[portnum].reg;
@@ -362,6 +366,16 @@ int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 
*hcor)
return 0;
 }

+#ifdef CONFIG_USB_INIT_MULTI
+int tegrausb_stop_port(unsigned portnum)
+{
+   struct usb_ctlr *usbctlr;
+
+   if (portnum >= port_count)
+   return -1;
+
+   usbctlr = port[portnum].reg;
+#else
 int tegrausb_stop_port(void)
 {
struct usb_ctlr *usbctlr;
@@ -370,6 +384,7 @@ int tegrausb_stop_port(void)
return -1;

usbctlr = port[port_current].reg;
+#endif

/* Stop controller */
writel(0, &usbctlr->usb_cmd);
diff --git a/arch/arm/include/asm/arch-tegra2/usb.h 
b/arch/arm/include/asm/arch-tegra2/usb.h
index 638033b..119d7b4 100644
--- a/arch/arm/include/asm/arch-tegra2/usb.h
+++ b/arch/arm/include/asm/arch-tegra2/usb.h
@@ -247,6 +247,10 @@ int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 
*hcor);
  *
  * @return 0 if ok, -1 if no port was active
  */
+#ifdef CONFIG_USB_INIT_MULTI
+int tegrausb_stop_port(unsigned portnum);
+#else
 int tegrausb_stop_port(void);
+#endif

 #endif /* _TEGRA_USB_H_ */
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index 9eba271..4c01a78 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -553,7 +553,17 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
}
if (strncmp(argv[1], "tree", 4) == 0) {
printf("\nDevice Tree:\n");
+#ifdef CONFIG_USB_INIT_MULTI
+   for (i = 0; i < USB_MAX_DEVICE; i++) {
+   dev = usb_get_dev_index(i);
+   if (dev == NULL)
+   break;
+   if (dev->parent == NULL)
+   usb_show_tree(dev);
+   }
+#else
usb_show_tree(usb_get_dev_index(0));
+#endif
return 0;
}
if (strncmp(argv[1], "inf", 3) == 0) {
diff --git a/common/usb.c b/common/usb.c
index 1ec30bc..b4275c5 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -81,6 +81,86 @@ char usb_started; /* flag for the started/stopped USB status 
*/
  */
 static void usb_scan_devices(void);

+#ifdef CONFIG_USB_INIT_MULTI
+/***
+ * Init USB Device
+ */
+
+int usb_init(void)
+{
+   void *ctrl;
+   int i;
+   struct usb_device *dev;
+
+   running = 0;
+   dev_index = 0;
+   asynch_allowed = 1;
+   usb_hub_reset();
+
+   /* first make all devices unknown */
+   for (i = 0; i < USB_MAX_DEVICE; i++) {
+   memset(&usb_dev[i], 0, sizeof(struct usb_device));
+   usb_dev[i].devnum = -1;
+   }
+
+   /* init low_level USB */
+   printf("USB:   ");
+   for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+   /* init low_level USB */
+   ctrl = usb_lowlevel_init(i);
+   /*
+* if lowlevel init is OK, scan the bus for devices
+* i.e. search HUBs and configure them
+*/
+   if (ctrl) {
+   running = 1;
+
+   printf("scanning bus for devices... ");
+   dev = usb_alloc_new_device(ctrl);
+   /*
+* device 0 is always present
+* (root hub, so let it analyze)
+*/
+   if (dev)
+   usb_new_device(dev);
+   }
+   }
+
+   if (running) {
+

[U-Boot] [RFC v2 1/3] imx-common/cmd_resetmode.c: add imx resetmode command

[Troy Kisky]

This is useful for forcing the ROM's
usb downloader to activate upon a watchdog reset.
Or, you can boot from either SD Card.

Currently, support added for MX53 and MX6Q
Signed-off-by: Troy Kisky 

Note: MX53 support untested.
---
 arch/arm/cpu/armv7/imx-common/Makefile|4 +-
 arch/arm/cpu/armv7/imx-common/cmd_resetmode.c |  152 +
 arch/arm/cpu/armv7/mx5/soc.c  |   31 +
 arch/arm/cpu/armv7/mx6/soc.c  |   36 ++
 arch/arm/include/asm/arch-mx5/imx-regs.h  |   18 +++
 arch/arm/include/asm/arch-mx6/imx-regs.h  |   21 
 arch/arm/include/asm/imx-common/resetmode.h   |   36 ++
 7 files changed, 297 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/imx-common/cmd_resetmode.c
 create mode 100644 arch/arm/include/asm/imx-common/resetmode.h

diff --git a/arch/arm/cpu/armv7/imx-common/Makefile 
b/arch/arm/cpu/armv7/imx-common/Makefile
index e5ff375..aed8262 100644
--- a/arch/arm/cpu/armv7/imx-common/Makefile
+++ b/arch/arm/cpu/armv7/imx-common/Makefile
@@ -27,7 +27,9 @@ include $(TOPDIR)/config.mk
 
 LIB = $(obj)libimx-common.o
 
-COBJS  = timer.o cpu.o speed.o
+COBJS-y= timer.o cpu.o speed.o
+COBJS-$(CONFIG_CMD_RESETMODE) += cmd_resetmode.o
+COBJS  := $(sort $(COBJS-y))
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/imx-common/cmd_resetmode.c 
b/arch/arm/cpu/armv7/imx-common/cmd_resetmode.c
new file mode 100644
index 000..d1c50e1
--- /dev/null
+++ b/arch/arm/cpu/armv7/imx-common/cmd_resetmode.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+const struct reset_mode *modes[2];
+
+const struct reset_mode *search_modes(char *arg)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(modes); i++) {
+   const struct reset_mode *p = modes[i];
+   if (p) {
+   while (p->name) {
+   if (!strcmp(p->name, arg))
+   return p;
+   p++;
+   }
+   }
+   }
+   return NULL;
+}
+
+int create_usage(char *dest)
+{
+   int i;
+   int size = 0;
+
+   for (i = 0; i < ARRAY_SIZE(modes); i++) {
+   const struct reset_mode *p = modes[i];
+   if (p) {
+   while (p->name) {
+   int len = strlen(p->name);
+   if (dest) {
+   memcpy(dest, p->name, len);
+   dest += len;
+   *dest++ = '|';
+   }
+   size += len + 1;
+   p++;
+   }
+   }
+   }
+   if (dest)
+   dest[-1] = 0;
+   return size;
+}
+
+int do_resetmode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   const struct reset_mode *p;
+
+   if (argc < 2)
+   return CMD_RET_USAGE;
+   p = search_modes(argv[1]);
+   if (!p)
+   return CMD_RET_USAGE;
+   reset_mode_apply(p->cfg_val);
+   return 0;
+}
+
+U_BOOT_CMD(
+   resetmode, 2, 0, do_resetmode,
+   NULL,
+   "");
+
+void add_board_resetmodes(const struct reset_mode *p)
+{
+   int size;
+   char *dest;
+
+   if (__u_boot_cmd_resetmode.usage) {
+   free(__u_boot_cmd_resetmode.usage);
+   __u_boot_cmd_resetmode.usage = NULL;
+   }
+
+   modes[0] = p;
+   modes[1] = soc_reset_modes;
+   size = create_usage(NULL);
+   dest = malloc(size);
+   if (dest) {
+   create_usage(dest);
+   __u_boot_cmd_resetmode.usage = dest;
+   }
+}
+
+int do_resetmode_cmd(char *arg)
+{
+   const struct reset_mode *p;
+
+   p = search_modes(arg);
+   if (!p) {
+   printf("%s not found\n", arg);
+   return CMD_RET_FAILURE;
+   }
+   reset_mode_apply(p->cfg_val);

[U-Boot] [RFC v2 2/3] mx6qsabrelite: add resetmode support

[Troy Kisky]

This allows a watchdog reset to start the ROM's
usb downloader, or boot from an sdcard.

Signed-off-by: Troy Kisky 

squash sabrelite
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   14 ++
 include/configs/mx6qsabrelite.h   |3 +++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 29cbfed..ae2dc95 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -434,10 +435,23 @@ static void preboot_keys(void)
 }
 #endif
 
+#ifdef CONFIG_CMD_RESETMODE
+static const struct reset_mode board_reset_modes[] = {
+   /* 4 bit bus width */
+   {"mmc0",MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+   {"mmc1",MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+   {NULL,  0},
+};
+#endif
+
 int misc_init_r(void)
 {
 #ifdef CONFIG_PREBOOT
preboot_keys();
 #endif
+
+#ifdef CONFIG_CMD_RESETMODE
+   add_board_resetmodes(board_reset_modes);
+#endif
return 0;
 }
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index feabc05..5165843 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -111,6 +111,9 @@
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
 
+/* Miscellaneous commands */
+#define CONFIG_CMD_RESETMODE
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX 1
-- 
1.7.5.4

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[U-Boot] [RFC v2 3/3] mx53evk: add resetmode support

[Troy Kisky]

This allows a watchdog reset to start the ROM's
usb/serial downloader, or boot from an sdcard.

Signed-off-by: Troy Kisky 

Compile tested only, I don't have a mx53evk.
---
 board/freescale/mx53evk/mx53evk.c |   13 +
 include/configs/mx53evk.h |3 +++
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx53evk/mx53evk.c 
b/board/freescale/mx53evk/mx53evk.c
index 8a6e31d..48499d6 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -367,11 +368,23 @@ int board_init(void)
return 0;
 }
 
+#ifdef CONFIG_CMD_RESETMODE
+static const struct reset_mode board_reset_modes[] = {
+   /* 4 bit bus width */
+   {"mmc0",MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+   {"mmc1",MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+   {NULL,  0},
+};
+#endif
+
 int board_late_init(void)
 {
setup_i2c(1);
power_init();
 
+#ifdef CONFIG_CMD_RESETMODE
+   add_board_resetmodes(board_reset_modes);
+#endif
return 0;
 }
 
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index a77e5b2..7be469c 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -90,6 +90,9 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DATE
 
+/* Miscellaneous commands */
+#define CONFIG_CMD_RESETMODE
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX  1
-- 
1.7.5.4

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Re: [U-Boot] [PATCH v2 0/19] tegra: Add display driver and LCD support for Seaboard

[Stephen Warren]

On 06/13/2012 05:03 PM, Stephen Warren wrote:
> On 06/13/2012 04:57 PM, Stephen Warren wrote:
>> On 06/13/2012 10:19 AM, Simon Glass wrote:
>>> This series adds support for the Tegra2x's display peripheral. This
>>> supports the LCD display on Seaboard and we use this to enable console
>>> output in U-Boot on the LCD.
>>
>> Simon,
>>
>> This series doesn't apply to u-boot-tegra/master cleanly; there are a
>> couple trivial conflicts in arch/arm/cpu/armv7/tegra2/Makefile to
>> resolve, but I had to apply the final patch completely by hand.
>>
>> When I run the resultant binary, I see the LCD backlight turn on, but
>> the image on the LCD is wrong; it starts completely black without any
>> text showing, then slowly fills in to white/gray with many horizontal
>> and vertical black lines; I guess the LCD timing is incorrect - are
>> there multiple different LCD models? Note that I am using a real
>> Seaboard not a Springbank for this test.
> 
> Oh, false alarm on this second point - the LCD is screwed up after using
> nvflash to flash the device, but when power-cycling it rather than just
> resetting it, the LCD works fine. I guess this means the driver is not
> initializing something that nvflash changed, and relying on a power-on
> default. I suppose it might not be worth fixing that given it works from
> cold power on.

Oops, there is a problem - executing "reset" in U-Boot, or "reboot" from
the kernel (one without any display support at least; mainline Linux)
will get into the "bad LCD" state too. So, I guess there is something
that needs to be fixed.

Sorry for the back-to-back emails.
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Re: [U-Boot] [PATCH v2 0/19] tegra: Add display driver and LCD support for Seaboard

[Stephen Warren]

On 06/13/2012 04:57 PM, Stephen Warren wrote:
> On 06/13/2012 10:19 AM, Simon Glass wrote:
>> This series adds support for the Tegra2x's display peripheral. This
>> supports the LCD display on Seaboard and we use this to enable console
>> output in U-Boot on the LCD.
> 
> Simon,
> 
> This series doesn't apply to u-boot-tegra/master cleanly; there are a
> couple trivial conflicts in arch/arm/cpu/armv7/tegra2/Makefile to
> resolve, but I had to apply the final patch completely by hand.
> 
> When I run the resultant binary, I see the LCD backlight turn on, but
> the image on the LCD is wrong; it starts completely black without any
> text showing, then slowly fills in to white/gray with many horizontal
> and vertical black lines; I guess the LCD timing is incorrect - are
> there multiple different LCD models? Note that I am using a real
> Seaboard not a Springbank for this test.

Oh, false alarm on this second point - the LCD is screwed up after using
nvflash to flash the device, but when power-cycling it rather than just
resetting it, the LCD works fine. I guess this means the driver is not
initializing something that nvflash changed, and relying on a power-on
default. I suppose it might not be worth fixing that given it works from
cold power on.
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Re: [U-Boot] [PATCH v2 0/19] tegra: Add display driver and LCD support for Seaboard

[Stephen Warren]

On 06/13/2012 10:19 AM, Simon Glass wrote:
> This series adds support for the Tegra2x's display peripheral. This
> supports the LCD display on Seaboard and we use this to enable console
> output in U-Boot on the LCD.

Simon,

This series doesn't apply to u-boot-tegra/master cleanly; there are a
couple trivial conflicts in arch/arm/cpu/armv7/tegra2/Makefile to
resolve, but I had to apply the final patch completely by hand.

When I run the resultant binary, I see the LCD backlight turn on, but
the image on the LCD is wrong; it starts completely black without any
text showing, then slowly fills in to white/gray with many horizontal
and vertical black lines; I guess the LCD timing is incorrect - are
there multiple different LCD models? Note that I am using a real
Seaboard not a Springbank for this test.
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[U-Boot] [PATCH] env_onenand: set ONENAND_MAX_ENV_SIZE to CONFIG_ENV_SIZE

[David du Colombier]

This fix prevents env_import() CRC to fail when CONFIG_ENV_SIZE
is not equal to 4096 bytes
It also prevents mtd->read and mtd->write to be incomplete when
the environment is larger than 4096 bytes.

Signed-off-by: David du Colombier <0in...@gmail.com>
---
 common/env_onenand.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/common/env_onenand.c b/common/env_onenand.c
index 7197ab6..da35071 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -39,7 +39,7 @@
 
 char *env_name_spec = "OneNAND";
 
-#define ONENAND_MAX_ENV_SIZE   4096
+#define ONENAND_MAX_ENV_SIZE   CONFIG_ENV_SIZE
 #define ONENAND_ENV_SIZE(mtd)  (ONENAND_MAX_ENV_SIZE - ENV_HEADER_SIZE)
 
 DECLARE_GLOBAL_DATA_PTR;
-- 
1.7.6.5

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Re: [U-Boot] [PATCH 1/3] BOOT: Fix unused variable issue when enabling bootz support

[Marek Vasut]

Dear Stephen Warren,

> From: Stephen Warren 
> 
> cmd_bootm.c: In function 'do_bootz':
> cmd_bootm.c:1590:9: warning: variable 'iflag' set but not used
> [-Wunused-but-set-variable]

It can be applied directly too ...

Acked-by: Marek Vasut 

> Cc: Marek Vasut 
> Cc: Wolfgang Denk 
> Signed-off-by: Stephen Warren 
> ---
> I think this is best taken through the Tegra tree, since it's needed to
> avoid introducing warnings when enabling CONFIG_CMD_BOOTZ, which the next
> patch enables, and we don't want MAKEALL -s tegra2 to suddenly start
> giving warnings.
> ---
>  common/cmd_bootm.c |3 +--
>  1 files changed, 1 insertions(+), 2 deletions(-)
> 
> diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
> index 5685232..45e726a 100644
> --- a/common/cmd_bootm.c
> +++ b/common/cmd_bootm.c
> @@ -1587,7 +1587,6 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag,
> int argc,
> 
>  static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> argv[]) {
> - ulong   iflag;
>   bootm_headers_t images;
> 
>   if (bootz_start(cmdtp, flag, argc, argv, &images))
> @@ -1598,7 +1597,7 @@ static int do_bootz(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[]) * overwrite all exception vector code, so we
> cannot easily
>* recover from any failures any more...
>*/
> - iflag = disable_interrupts();
> + disable_interrupts();
> 
>  #if defined(CONFIG_CMD_USB)
>   /*

Best regards,
Marek Vasut
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[U-Boot] [PATCH 1/3] BOOT: Fix unused variable issue when enabling bootz support

[Stephen Warren]

From: Stephen Warren 

cmd_bootm.c: In function 'do_bootz':
cmd_bootm.c:1590:9: warning: variable 'iflag' set but not used 
[-Wunused-but-set-variable]

Cc: Marek Vasut 
Cc: Wolfgang Denk 
Signed-off-by: Stephen Warren 
---
I think this is best taken through the Tegra tree, since it's needed to
avoid introducing warnings when enabling CONFIG_CMD_BOOTZ, which the next
patch enables, and we don't want MAKEALL -s tegra2 to suddenly start
giving warnings.
---
 common/cmd_bootm.c |3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 5685232..45e726a 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -1587,7 +1587,6 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int 
argc,
 
 static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-   ulong   iflag;
bootm_headers_t images;
 
if (bootz_start(cmdtp, flag, argc, argv, &images))
@@ -1598,7 +1597,7 @@ static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 * overwrite all exception vector code, so we cannot easily
 * recover from any failures any more...
 */
-   iflag = disable_interrupts();
+   disable_interrupts();
 
 #if defined(CONFIG_CMD_USB)
/*
-- 
1.7.0.4

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[U-Boot] [PATCH 2/3] tegra: enable bootz command

[Stephen Warren]

From: Stephen Warren 

bootz is just like bootm, except that it can boot a raw zImage, without
requiring it to be wrapped inside a uImage.

Signed-off-by: Stephen Warren 
---
 include/configs/tegra2-common.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 8393901..74f1140 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -195,4 +195,5 @@
 #define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_ENTERRCM
+#define CONFIG_CMD_BOOTZ
 #endif /* __TEGRA2_COMMON_H */
-- 
1.7.0.4

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[U-Boot] [PATCH 3/3] tegra: define fdt_load/fdt_high variables

[Stephen Warren]

From: Stephen Warren 

These variables act like loadaddr, but for a device tree image. Defining
them in the environment allows boot scripts to be identical on Tegra20 and
Tegra30, which have different memory base addresses, and hence need
different values for these variables.

Signed-off-by: Stephen Warren 
---
 include/configs/tegra2-common-post.h |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/configs/tegra2-common-post.h 
b/include/configs/tegra2-common-post.h
index 80d9c35..c21fc28 100644
--- a/include/configs/tegra2-common-post.h
+++ b/include/configs/tegra2-common-post.h
@@ -142,6 +142,8 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA2_DEVICE_SETTINGS \
+   "fdt_load=0x0100\0" \
+   "fdt_high=0110\0" \
BOOTCMDS_COMMON
 
 #endif /* __TEGRA2_COMMON_POST_H */
-- 
1.7.0.4

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[U-Boot] [PATCH] hawkboard/omapl-138: Add support for generating ais image for hawkboard

[Sughosh Ganu]

Parameters used for configuring certain SoC peripherals are parsed
from the cfg file and appended as part of the ais image's header. The
u-boot-spl.ais generated is flashed separately to the nand, so do not
delete the file after generation of u-boot.ais.

Signed-off-by: Sughosh Ganu 
---
 .gitignore|3 +++
 Makefile  |5 +++--
 board/davinci/da8xxevm/hawkboard-ais-nand.cfg |4 
 include/configs/hawkboard.h   |1 +
 4 files changed, 11 insertions(+), 2 deletions(-)
 create mode 100644 board/davinci/da8xxevm/hawkboard-ais-nand.cfg

diff --git a/.gitignore b/.gitignore
index 0f32fd8..d8a1893 100644
--- a/.gitignore
+++ b/.gitignore
@@ -75,3 +75,6 @@ cscope.*
 /onenand_ipl/onenand-ipl*
 /onenand_ipl/board/*/onenand*
 /onenand_ipl/board/*/*.S
+
+# spl ais files
+/spl/*.ais
diff --git a/Makefile b/Makefile
index 0197239..8ac0530 100644
--- a/Makefile
+++ b/Makefile
@@ -441,7 +441,8 @@ $(obj)u-boot.ubl:   $(obj)spl/u-boot-spl.bin 
$(obj)u-boot.bin
rm $(obj)spl/u-boot-spl-pad.bin
 
 $(obj)u-boot.ais:   $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-   $(obj)tools/mkimage -s -n /dev/null -T aisimage \
+   $(obj)tools/mkimage -s -n $(if 
$(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
+   -T aisimage \
-e $(CONFIG_SPL_TEXT_BASE) \
-d $(obj)spl/u-boot-spl.bin \
$(obj)spl/u-boot-spl.ais
@@ -450,7 +451,6 @@ $(obj)u-boot.ais:   $(obj)spl/u-boot-spl.bin 
$(obj)u-boot.bin
$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
$(obj)u-boot.ais
-   rm $(obj)spl/u-boot-spl{,-pad}.ais
 
 $(obj)u-boot.sb:   $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
@@ -783,6 +783,7 @@ clobber:tidy
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l 
-print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l 
-print | xargs rm -f
@rm -f $(obj)dts/*.tmp
+   @rm -f $(obj)spl/u-boot-spl{,-pad}.ais
 
 mrproper \
 distclean: clobber unconfig
diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg 
b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg
new file mode 100644
index 000..76282de
--- /dev/null
+++ b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg
@@ -0,0 +1,4 @@
+#  PLL0CFG0PLL0CFG1
+PLL0   0x00180001  0x0205
+#  PLL1CFG0PLL1CFG1DRPYC1R SDCRSDTIMR1 
SDTIMR2 SDRCR   CLK2XSRC
+DDR2   0x15010001  0x0002  0x0043  0x00134632  
0x26492a09  0x7d13c722  0x0249  0x
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 6d2d4fb..5fa1273 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -43,6 +43,7 @@
 #define CONFIG_SYS_HZ  1000
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_AIS_CONFIG_FILE 
"board/$(BOARDDIR)/hawkboard-ais-nand.cfg"
 
 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (  \
DAVINCI_SYSCFG_SUSPSRC_EMAC |   \
-- 
1.7.5.4

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Re: [U-Boot] mx53loco build fails with CONFIG_VIDEO disabled

[Fabio Estevam]

On Wed, Jun 13, 2012 at 2:53 PM, Vikram Narayanan  wrote:

>> Anyway, when patches for IPU flow into mainline, is there a good reason
>> to not enable CONFIG_VIDEO for mx53loco ?
>
>
> Though this would be helpful for headless boards, I'm not the right guy.
> Fabio can give a better picture here.

I like the idea of keeping CONFIG_VIDEO enabled by default for
mx53loco as it is currently.

Other boards like vision2, mx51evk do the same thing.

It is also a good idea to be able to deselect CONFIG_VIDEO and not
break the build and Vikram intends to submit a patch for fixing this.

Regards,

Fabio Estevam
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Re: [U-Boot] mx53loco build fails with CONFIG_VIDEO disabled

[Fabio Estevam]

On Wed, Jun 13, 2012 at 2:20 PM, Stefano Babic  wrote:
> On 13/06/2012 19:00, Vikram Narayanan wrote:
>> Hello,
>>
>> mx53loco build fails when CONFIG_VIDEO and its friends disabled.
>> I can send a patch fixing this.
>>
>
> But CONFIG_VIDEO is *not* set in mx53loco.h mainline. Do you mean you
> are testing Fabio's patches ?
>
> Fabio, can you give me an overview about your IPU patches ? I have seen
> several patches during my vacation, but it is not clear to me the
> status. In patchwork, most of them (but not all) are assigned to
> Anatolji. Can you help me to sync myself with the current status ?

Sure, mx51evk and mx53loco patches were already accepted by Anatolij
and are in mainline.

I have also submitted a patch series for adding framebuffer for
mx6qsabrelite. These were not applied yet and I need to rework at
least the last one of the series.

Regards,

Fabio Estevam
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Re: [U-Boot] mx53loco build fails with CONFIG_VIDEO disabled

[Vikram Narayanan]

On 6/13/2012 10:50 PM, Stefano Babic wrote:

On 13/06/2012 19:00, Vikram Narayanan wrote:

Hello,

mx53loco build fails when CONFIG_VIDEO and its friends disabled.
I can send a patch fixing this.



But CONFIG_VIDEO is *not* set in mx53loco.h mainline. Do you mean you
are testing Fabio's patches ?


With this (fedab338f3459315cb69627fcf46032ec8df1753) it is already in 
the master.



Fabio, can you give me an overview about your IPU patches ? I have seen
several patches during my vacation, but it is not clear to me the
status. In patchwork, most of them (but not all) are assigned to
Anatolji. Can you help me to sync myself with the current status ?


I _really_ don't like ifdef -ing a lot of stuff.


Nobody likes it ;-)


Instead I'd feel to
have a separate file in the directory which does this LCD init and FB
init call, and let the makefile handle the conditional compilation.


A way we use in the past to have different compilation of the same board
with different features is to use a separate entry into boards.cfg, for
example see imx31_phycore, or also magnesium and imx27lite, or...

Anyway, when patches for IPU flow into mainline, is there a good reason
to not enable CONFIG_VIDEO for mx53loco ?


Though this would be helpful for headless boards, I'm not the right guy. 
Fabio can give a better picture here.


Regards,
Vikram


Best regards,
Stefano


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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Vikram Narayanan]

Hello Marek,

On 6/13/2012 10:45 PM, Marek Vasut wrote:

Dear Vikram Narayanan,


Hello Marek,

On 6/13/2012 5:57 PM, Marek Vasut wrote:

Dear Vikram Narayanan,


If in case this is valid according to the latest datasheet, ignore this
patch.

--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
bits 4 and 5 read-only and the value is always set as zero.
So write '0' to these bits instead of writing '1'.


I'm acking this as writing 0 to read-only bits is the only rightous thing
to do. btw. how did you find this? Good catch, praise on you :-)

:
:)

In the middle of writing a imximage.cfg file for a custom mx6 board.


So it did manifest somehow?


Still in progress. :)

Regards,
Vikram
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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Marek Vasut]

Dear Vikram Narayanan,

> Hello Marek,
> 
> On 6/13/2012 5:57 PM, Marek Vasut wrote:
> > Dear Vikram Narayanan,
> > 
> >> If in case this is valid according to the latest datasheet, ignore this
> >> patch.
> >> 
> >> --
> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> >> bits 4 and 5 read-only and the value is always set as zero.
> >> So write '0' to these bits instead of writing '1'.
> > 
> > I'm acking this as writing 0 to read-only bits is the only rightous thing
> > to do. btw. how did you find this? Good catch, praise on you :-)
> :
> :)
> 
> In the middle of writing a imximage.cfg file for a custom mx6 board.

So it did manifest somehow?

> Regards,
> Vikram
> 
> > Acked-by: Marek Vasut
> > 
> >> Signed-off-by: Vikram Narayanan
> >> Cc: Jason Liu
> >> Cc: Dirk Behme
> >> ---
> >> 
> >>   board/freescale/mx6qarm2/imximage.cfg  |2 +-
> >>   board/freescale/mx6qsabrelite/imximage.cfg |2 +-
> >>   2 files changed, 2 insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/board/freescale/mx6qarm2/imximage.cfg
> >> b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
> >> --- a/board/freescale/mx6qarm2/imximage.cfg
> >> +++ b/board/freescale/mx6qarm2/imximage.cfg
> >> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0FC3
> >> 
> >>   DATA 4 0x020c4080 0x03FF
> >>   
> >>   # enable AXI cache for VDOA/VPU/IPU
> >> 
> >> -DATA 4 0x020e0010 0xF0FF
> >> +DATA 4 0x020e0010 0xF0CF
> >> 
> >>   # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
> >>   DATA 4 0x020e0018 0x007F007F
> >>   DATA 4 0x020e001c 0x007F007F
> >> 
> >> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg
> >> b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab
> >> 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg
> >> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
> >> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0FC3
> >> 
> >>   DATA 4 0x020c4080 0x03FF
> >>   
> >>   # enable AXI cache for VDOA/VPU/IPU
> >> 
> >> -DATA 4 0x020e0010 0xF0FF
> >> +DATA 4 0x020e0010 0xF0CF
> >> 
> >>   # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
> >>   DATA 4 0x020e0018 0x007F007F
> >>   DATA 4 0x020e001c 0x007F007F
> > 
> > Best regards,
> > Marek Vasut

Best regards,
Marek Vasut
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Re: [U-Boot] mx53loco build fails with CONFIG_VIDEO disabled

[Stefano Babic]

On 13/06/2012 19:00, Vikram Narayanan wrote:
> Hello,
> 
> mx53loco build fails when CONFIG_VIDEO and its friends disabled.
> I can send a patch fixing this.
> 

But CONFIG_VIDEO is *not* set in mx53loco.h mainline. Do you mean you
are testing Fabio's patches ?

Fabio, can you give me an overview about your IPU patches ? I have seen
several patches during my vacation, but it is not clear to me the
status. In patchwork, most of them (but not all) are assigned to
Anatolji. Can you help me to sync myself with the current status ?

> I _really_ don't like ifdef -ing a lot of stuff.

Nobody likes it ;-)

> Instead I'd feel to
> have a separate file in the directory which does this LCD init and FB
> init call, and let the makefile handle the conditional compilation.

A way we use in the past to have different compilation of the same board
with different features is to use a separate entry into boards.cfg, for
example see imx31_phycore, or also magnesium and imx27lite, or...

Anyway, when patches for IPU flow into mainline, is there a good reason
to not enable CONFIG_VIDEO for mx53loco ?

Best regards,
Stefano

-- 
=
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] mx53loco build fails with CONFIG_VIDEO disabled

[Fabio Estevam]

On Wed, Jun 13, 2012 at 2:00 PM, Vikram Narayanan  wrote:
> Hello,
>
> mx53loco build fails when CONFIG_VIDEO and its friends disabled.
> I can send a patch fixing this.
>
> I _really_ don't like ifdef -ing a lot of stuff. Instead I'd feel to have a
> separate file in the directory which does this LCD init and FB init call,
> and let the makefile handle the conditional compilation.
>
> @Fabio:
> As you've pushed this stuff, I'd like to have your opinions on splitting
> this into a separate file.

I don't have a strong opinion on this: either ifdef or a new file is
fine with me.

Thanks,

Fabio Estevam
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[U-Boot] mx53loco build fails with CONFIG_VIDEO disabled

[Vikram Narayanan]

Hello,

mx53loco build fails when CONFIG_VIDEO and its friends disabled.
I can send a patch fixing this.

I _really_ don't like ifdef -ing a lot of stuff. Instead I'd feel to 
have a separate file in the directory which does this LCD init and FB 
init call, and let the makefile handle the conditional compilation.


@Fabio:
As you've pushed this stuff, I'd like to have your opinions on splitting 
this into a separate file.


Regards,
Vikram
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[U-Boot] [PATCH v2 03/19] fdt: Add function to look up a phandle's register address

[Simon Glass]

This is a commonly-used requirement, so add a function to support it
easily.

Signed-off-by: Simon Glass 
---

 include/fdtdec.h |   13 +
 lib/fdtdec.c |   11 +++
 2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index fab577e..d7bef6c 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -276,6 +276,19 @@ const char *fdtdec_get_compatible(enum fdt_compat_id id);
 int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name);
 
 /**
+ * Look up a phandle and follow it to its node. Then return the register
+ * address of that node as a pointer. This can be used to access the
+ * peripheral directly.
+ *
+ * @param blob FDT blob
+ * @param node node to examine
+ * @param prop_namename of property to find
+ * @return pointer to node's register address
+ */
+void *fdtdec_lookup_phandle_reg(const void *blob, int node,
+   const char *prop_name);
+
+/**
  * Look up a property in a node and return its contents in an integer
  * array of given length. The property must have at least enough data for
  * the array (4*count bytes). It may have more, but this will be ignored.
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 61056f1..8185d8f 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -347,6 +347,17 @@ int fdtdec_lookup_phandle(const void *blob, int node, 
const char *prop_name)
return lookup;
 }
 
+void *fdtdec_lookup_phandle_reg(const void *blob, int node,
+   const char *prop_name)
+{
+   int lookup;
+
+   lookup = fdtdec_lookup_phandle(blob, node, prop_name);
+   if (lookup < 0)
+   return NULL;
+   return (void *)fdtdec_get_addr(blob, lookup, "reg");
+}
+
 /**
  * Look up a property in a node and check that it has a minimum length.
  *
-- 
1.7.7.3

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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Vikram Narayanan]

Hello Marek,

On 6/13/2012 5:57 PM, Marek Vasut wrote:

Dear Vikram Narayanan,


If in case this is valid according to the latest datasheet, ignore this
patch.

--
According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
bits 4 and 5 read-only and the value is always set as zero.
So write '0' to these bits instead of writing '1'.


I'm acking this as writing 0 to read-only bits is the only rightous thing to do.
btw. how did you find this? Good catch, praise on you :-)


:)
In the middle of writing a imximage.cfg file for a custom mx6 board.

Regards,
Vikram



Acked-by: Marek Vasut


Signed-off-by: Vikram Narayanan
Cc: Jason Liu
Cc: Dirk Behme
---
  board/freescale/mx6qarm2/imximage.cfg  |2 +-
  board/freescale/mx6qsabrelite/imximage.cfg |2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mx6qarm2/imximage.cfg
b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0FC3
  DATA 4 0x020c4080 0x03FF

  # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF0FF
+DATA 4 0x020e0010 0xF0CF
  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
  DATA 4 0x020e0018 0x007F007F
  DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabrelite/imximage.cfg
b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644
--- a/board/freescale/mx6qsabrelite/imximage.cfg
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0FC3
  DATA 4 0x020c4080 0x03FF

  # enable AXI cache for VDOA/VPU/IPU
-DATA 4 0x020e0010 0xF0FF
+DATA 4 0x020e0010 0xF0CF
  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
  DATA 4 0x020e0018 0x007F007F
  DATA 4 0x020e001c 0x007F007F


Best regards,
Marek Vasut


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Re: [U-Boot] [PATCH v2] tx25: Use generic gpio_* calls

[Vikram Narayanan]

On 6/13/2012 1:22 PM, Stefano Babic wrote:

On 12/06/2012 18:37, Vikram Narayanan wrote:

Changes from v1:
Used appropriate gpio_* lib calls.

---
Instead of manipulating gpio registers directly, use the calls
from the gpio library.


Changelog must go after the "---" line and commit message before. They
are swapped. Apart of that..


Sorry for the mix up of commit message and the change log.
Will send a v3 for this.

BTW, did someone test this on tx25?
@John: Any comments from your side?

Thanks,
Vikram
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Re: [U-Boot] [PATCH 1/2] patman: Change the location of patman config file

[Vikram Narayanan]

Hello Wolfgang,

On 5/30/2012 11:04 AM, Simon Glass wrote:



On Wed, May 23, 2012 at 11:58 AM, Vikram Narayanan mailto:vikram...@gmail.com>> wrote:

Move the config file from ~/.config/patman to ~/.patman as it is
more appropriate to have it there. Update the same in the README.

Signed-off-by: Vikram Narayanan mailto:vikram...@gmail.com>>
Cc: Simon Glass mailto:s...@chromium.org>>
Cc: Wolfgang Denk mailto:w...@denx.de>>


Acked-by: Simon Glass mailto:s...@chromium.org>>


Can you please consider this patch series? Both are acked by Simon.
If you have any issues in taking this in, please let me know.

Thanks,
Vikram



---
  tools/patman/README  |2 +-
  tools/patman/settings.py |2 +-
  2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/patman/README b/tools/patman/README
index 7ba9e80..1af8665 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -68,7 +68,7 @@ How to configure it
  For most cases patman will locate and use the file 'doc/git-mailrc' in
  your U-Boot directory. This contains most of the aliases you will
need.

-To add your own, create a file ~/.config/patman directory like this:
+To add your own, create a file ~/.patman like this:

 
  # patman alias file
diff --git a/tools/patman/settings.py b/tools/patman/settings.py
index 049c709..f980071 100644
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
@@ -69,7 +69,7 @@ def Setup(config_fname=''):
"""
 settings = ConfigParser.SafeConfigParser()
 if config_fname == '':
-config_fname = '%s/.config/patman' % os.getenv('HOME')
+config_fname = '%s/.patman' % os.getenv('HOME')
 if config_fname:
 settings.read(config_fname)

--
1.7.4.1





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[U-Boot] [PATCH v2 01/19] Add gpio_request() to asm-generic header

[Simon Glass]

This function should also be part of the GPIO API, so add it.

Signed-off-by: Simon Glass 
---

 include/asm-generic/gpio.h |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index c19e16c..23c9649 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -94,4 +94,13 @@ int gpio_get_value(unsigned gpio);
  */
 int gpio_set_value(unsigned gpio, int value);
 
+/**
+ * Request a gpio. This should be called before any of the other functions
+ * are used on this gpio.
+ *
+ * @param gp   GPIO number
+ * @param labelUser label for this GPIO
+ * @return 0 if ok, -1 on error
+ */
+int gpio_request(unsigned gpio, const char *label);
 #endif /* _ASM_GENERIC_GPIO_H_ */
-- 
1.7.7.3

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[U-Boot] [PATCH v2 0/19] tegra: Add display driver and LCD support for Seaboard

[Simon Glass]

This series adds support for the Tegra2x's display peripheral. This
supports the LCD display on Seaboard and we use this to enable console
output in U-Boot on the LCD.

Configuration is via the device tree. Proposed bindings are included
in this series.

I looked at the message "[RFC 4/4] drm: Add NVIDIA Tegra support" on
device-tree-discuss. There does not seem to be any conclusion for now.

While I agree EDID is convenient for machines I would prefer to provide
a user-friendly way of selecting LCD settings as well, with EDID more
as a fallback and auto-detection when available.

To improve performance two optimisations are offered:

1. The LCD frame buffer is cached, with the cache being flushed after
each newline sent to putc(), and in a few other situations. This
dramatically increases performance (around 10x). This requires a few
additions to the ARM cache support.

2. The console supports scrolling in steps of more than 1 line. This
speeds up scrolling output considerably, particularly commands like
'printenv' which display a lot of output. This requires a new CONFIG
and a change to the console_scrollup() function.

Changes in v2:
- Add new patch to use const in pinmux_config_pingroup/table()
- Add nvidia prefix to device tree properties
- Align tegra display using new CONFIG_LCD_ALIGNMENT feature
- Put the LCD cache flush logic into lcd_putc() instead of lcd_puts()
- Update LCD driver to deal with new fdt bindings
- Update seaboard LCD definitions for new fdt binding
- Use a more generic config CONFIG_LCD_ALIGNMENT for lcd alignment
- Use const where possible in funcmux

Mayuresh Kulkarni (1):
  tegra: Enable display/lcd support on Seaboard

Simon Glass (17):
  Add gpio_request() to asm-generic header
  fdt: Add debugging to fdtdec_get_int/addr()
  fdt: Add function to look up a phandle's register address
  fdt: Add header guard to fdtdec.h
  tegra: Use const for pinmux_config_pingroup/table()
  tegra: Add display support to funcmux
  tegra: fdt: Add LCD definitions for Tegra
  tegra: Add support for PWFM
  tegra: Add LCD driver
  tegra: Add LCD support to Nvidia boards
  arm: Add control over cachability of memory regions
  lcd: Add CONFIG_LCD_ALIGNMENT to select frame buffer alignment
  lcd: Add support for flushing LCD fb from dcache after update
  tegra: Align LCD frame buffer to section boundary
  tegra: Support control of cache settings for LCD
  tegra: fdt: Add LCD definitions for Seaboard
  lcd: Add CONSOLE_SCROLL_LINES option to speed console

Wei Ni (1):
  tegra: Add SOC support for display/lcd

 README  |   16 +
 arch/arm/cpu/armv7/cache_v7.c   |   11 +
 arch/arm/cpu/armv7/tegra2/Makefile  |1 +
 arch/arm/cpu/armv7/tegra2/display.c |  271 +++
 arch/arm/cpu/armv7/tegra2/funcmux.c |   39 ++
 arch/arm/cpu/armv7/tegra2/pinmux.c  |4 +-
 arch/arm/cpu/armv7/tegra2/pwfm.c|   40 ++
 arch/arm/dts/tegra20.dtsi   |   25 +
 arch/arm/include/asm/arch-tegra2/dc.h   |  544 +++
 arch/arm/include/asm/arch-tegra2/display.h  |  133 ++
 arch/arm/include/asm/arch-tegra2/pinmux.h   |4 +-
 arch/arm/include/asm/arch-tegra2/pwfm.h |   54 +++
 arch/arm/include/asm/system.h   |   30 ++
 arch/arm/lib/cache-cp15.c   |   62 +++-
 board/nvidia/common/board.c |   21 +-
 board/nvidia/dts/tegra2-seaboard.dts|   21 +
 common/cmd_echo.c   |3 +-
 common/lcd.c|   84 +++-
 doc/device-tree-bindings/video/nvidia-video.txt |   88 
 drivers/video/Makefile  |1 +
 drivers/video/tegra.c   |  392 
 include/asm-generic/gpio.h  |9 +
 include/configs/seaboard.h  |   12 +-
 include/configs/tegra2-common.h |3 +
 include/fdtdec.h|   17 +
 include/lcd.h   |   11 +
 lib/fdtdec.c|   34 ++-
 27 files changed, 1891 insertions(+), 39 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
 create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/display.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h
 create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt
 create mode 100644 drivers/video/tegra.c

-- 
1.7.7.3

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[U-Boot] [PATCH v2 18/19] lcd: Add CONSOLE_SCROLL_LINES option to speed console

[Simon Glass]

When the cursor position gets to the end of the LCD console we normally
scroll by one line. This adds an option to increase that value.

Console scrolling is often slow, and if a large amount of output is
being sent, increasing this option to 10 or so will speed things up
considerably.

Signed-off-by: Simon Glass 
---

 README   |6 ++
 common/lcd.c |   15 +--
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/README b/README
index ccdddbf..cb2c6cf 100644
--- a/README
+++ b/README
@@ -1407,6 +1407,12 @@ The following options need to be configured:
here, since it is cheaper to change data cache settings on
a per-section basis.
 
+   CONSOLE_SCROLL_LINES
+
+   When the console need to be scrolled, this is the number of
+   lines to scroll by. It defaults to 1. Increasing this makes
+   the console jump but can help speed up operation when scrolling
+   is slow.
 
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 
diff --git a/common/lcd.c b/common/lcd.c
index 758f158..b4e0853 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -134,12 +134,23 @@ void lcd_set_flush_dcache(int flush)
 
 static void console_scrollup (void)
 {
+   int rows = 1;
+
+#ifdef CONSOLE_SCROLL_LINES
+   rows = CONSOLE_SCROLL_LINES;
+#endif
/* Copy up rows ignoring the first one */
-   memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
+   memcpy(CONSOLE_ROW_FIRST,
+  lcd_console_address + CONSOLE_ROW_SIZE * rows,
+  CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows);
 
/* Clear the last one */
-   memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
+   memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows,
+   COLOR_MASK(lcd_color_bg),
+  CONSOLE_ROW_SIZE * rows);
+
lcd_sync();
+   console_row -= rows;
 }
 
 /*--*/
-- 
1.7.7.3

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[U-Boot] [PATCH v2 15/19] tegra: Align LCD frame buffer to section boundary

[Simon Glass]

For tegra we want to enable the cache for the LCD. This is easier if
we can avoid using L2 page tages, so align the LCD to a section
boundary.

Signed-off-by: Simon Glass 
---
Changes in v2:
- Align tegra display using new CONFIG_LCD_ALIGNMENT feature

 include/configs/tegra2-common.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 068ce88..0420098 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -45,6 +45,9 @@
 
 #define CONFIG_ARCH_CPU_INIT   /* Fire up the A9 core */
 
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT   MMU_SECTION_SIZE
+
 #include/* get chip and board defs */
 
 /*
-- 
1.7.7.3

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[U-Boot] [PATCH v2 16/19] tegra: Support control of cache settings for LCD

[Simon Glass]

Add support for selecting the required cache mode for the LCD:
off, write-through or write-back.

Signed-off-by: Simon Glass 
---

 drivers/video/tegra.c |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 12518b2..15e10f7 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -175,6 +175,15 @@ void lcd_ctrl_init(void *lcdbase)
return;
}
 
+   /* For write-through or cache off, change the LCD memory region */
+   if (!(config.cache_type & FDT_LCD_CACHE_WRITE_BACK))
+   mmu_set_region_dcache(config.frame_buffer, size,
+   config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH ?
+   DCACHE_WRITETHROUGH : DCACHE_OFF);
+
+   /* Enable flushing after LCD writes if requested */
+   lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
+
debug("LCD frame buffer at %p\n", lcd_base);
 }
 
-- 
1.7.7.3

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[U-Boot] [PATCH v2 06/19] tegra: Add display support to funcmux

[Simon Glass]

Add support for a default pin mapping for display1.

Signed-off-by: Simon Glass 
---
Changes in v2:
- Use const where possible in funcmux

 arch/arm/cpu/armv7/tegra2/funcmux.c |   39 +++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c 
b/arch/arm/cpu/armv7/tegra2/funcmux.c
index 0ef7753..9a339cd 100644
--- a/arch/arm/cpu/armv7/tegra2/funcmux.c
+++ b/arch/arm/cpu/armv7/tegra2/funcmux.c
@@ -25,6 +25,31 @@
 #include 
 #include 
 
+/*
+ * The PINMUX macro is used to set up pinmux tables.
+ */
+#define PINMUX(grp, mux, pupd, tri)   \
+   {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+
+static const struct pingroup_config disp1_default[] = {
+   PINMUX(LDI,   DISPA,  NORMAL,NORMAL),
+   PINMUX(LHP0,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LHP1,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LHP2,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LHS,   DISPA,  NORMAL,NORMAL),
+   PINMUX(LM0,   RSVD4,  NORMAL,NORMAL),
+   PINMUX(LPP,   DISPA,  NORMAL,NORMAL),
+   PINMUX(LPW0,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LPW1,  RSVD4,  NORMAL,TRISTATE),
+   PINMUX(LPW2,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LSC0,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LSPI,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LVP1,  DISPA,  NORMAL,NORMAL),
+   PINMUX(LVS,   DISPA,  NORMAL,NORMAL),
+   PINMUX(SLXD,  SPDIF,  NORMAL,NORMAL),
+};
+
+
 int funcmux_select(enum periph_id id, int config)
 {
int bad_config = config != FUNCMUX_DEFAULT;
@@ -185,6 +210,20 @@ int funcmux_select(enum periph_id id, int config)
break;
}
 
+   case PERIPH_ID_DISP1:
+   if (config == FUNCMUX_DEFAULT) {
+   int i;
+
+   for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
+   pinmux_set_func(i, PMUX_FUNC_DISPA);
+   pinmux_tristate_disable(i);
+   pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
+   }
+   pinmux_config_table(disp1_default,
+   ARRAY_SIZE(disp1_default));
+   }
+   break;
+
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
-- 
1.7.7.3

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[U-Boot] [PATCH v2 10/19] tegra: Add LCD driver

[Simon Glass]

This driver supports driving a single LCD and providing a U-Boot console
on it.

Signed-off-by: Simon Glass 
---
Changes in v2:
- Update LCD driver to deal with new fdt bindings

 drivers/video/Makefile |1 +
 drivers/video/tegra.c  |  383 
 include/fdtdec.h   |1 +
 lib/fdtdec.c   |1 +
 4 files changed, 386 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/tegra.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 4fad20d..d7518c4 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -46,6 +46,7 @@ COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o videomodes.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o
 COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 
 COBJS  := $(sort $(COBJS-y))
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
new file mode 100644
index 000..12518b2
--- /dev/null
+++ b/drivers/video/tegra.c
@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* These are the stages we go throuh in enabling the LCD */
+enum stage_t {
+   STAGE_START,
+   STAGE_LVDS,
+   STAGE_BACKLIGHT_VDD,
+   STAGE_PWFM,
+   STAGE_BACKLIGHT_EN,
+   STAGE_DONE,
+};
+
+static enum stage_t stage; /* Current stage we are at */
+static unsigned long timer_next; /* Time we can move onto next stage */
+static struct fdt_lcd config;  /* Our LCD config, set up in handle_stage() */
+
+enum {
+   /* Maximum LCD size we support */
+   LCD_MAX_WIDTH   = 1366,
+   LCD_MAX_HEIGHT  = 768,
+   LCD_MAX_LOG2_BPP= 4,/* 2^4 = 16 bpp */
+};
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+void *lcd_base;/* Start of framebuffer memory  */
+void *lcd_console_address; /* Start of console buffer  */
+
+short console_col;
+short console_row;
+
+vidinfo_t panel_info = {
+   /* Insert a value here so that we don't end up in the BSS */
+   .vl_col = -1,
+};
+
+char lcd_cursor_enabled;
+
+ushort lcd_cursor_width;
+ushort lcd_cursor_height;
+
+#ifndef CONFIG_OF_CONTROL
+#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support"
+#endif
+
+void lcd_cursor_size(ushort width, ushort height)
+{
+   lcd_cursor_width = width;
+   lcd_cursor_height = height;
+}
+
+void lcd_toggle_cursor(void)
+{
+   ushort x, y;
+   uchar *dest;
+   ushort row;
+
+   x = console_col * lcd_cursor_width;
+   y = console_row * lcd_cursor_height;
+   dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) /
+   8);
+
+   for (row = 0; row < lcd_cursor_height; ++row, dest += lcd_line_length) {
+   ushort *d = (ushort *)dest;
+   ushort color;
+   int i;
+
+   for (i = 0; i < lcd_cursor_width; ++i) {
+   color = *d;
+   color ^= lcd_color_fg;
+   *d = color;
+   ++d;
+   }
+   }
+}
+
+void lcd_cursor_on(void)
+{
+   lcd_cursor_enabled = 1;
+   lcd_toggle_cursor();
+}
+void lcd_cursor_off(void)
+{
+   lcd_cursor_enabled = 0;
+   lcd_toggle_cursor();
+}
+
+char lcd_is_cursor_enabled(void)
+{
+   return lcd_cursor_enabled;
+}
+
+static void update_panel_size(struct fdt_lcd *config)
+{
+   panel_info.vl_col = config->width;
+   panel_info.vl_row = config->height;
+   panel_info.vl_bpix = config->log2_bpp;
+}
+
+/*
+ *  Main init function called by lcd driver.
+ *  Inits and then prints test pattern if required.
+ */
+
+void lcd_ctrl_init(void *lcdbase)
+{
+   int line_length, size;
+
+   /*
+* The framebuffer address should be specified in the device tree.
+* This FDT value should be the same as the one defined in Linux kernel;
+* otherwise, i

[U-Boot] [PATCH v2 04/19] fdt: Add header guard to fdtdec.h

[Simon Glass]

This makes it easier to include this header from other headers.

Signed-off-by: Simon Glass 
---

 include/fdtdec.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d7bef6c..627d077 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -19,6 +19,8 @@
  * MA 02111-1307 USA
  */
 
+#ifndef __fdtdec_h
+#define __fdtdec_h
 
 /*
  * This file contains convenience functions for decoding useful and
@@ -395,3 +397,4 @@ int fdtdec_get_byte_array(const void *blob, int node, const 
char *prop_name,
  */
 const u8 *fdtdec_locate_byte_array(const void *blob, int node,
 const char *prop_name, int count);
+#endif
-- 
1.7.7.3

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[U-Boot] [PATCH v2 17/19] tegra: fdt: Add LCD definitions for Seaboard

[Simon Glass]

The Seaboard has a 1366x768 16bpp LCD. The backlight is controlled
by one of the PWMs.

Signed-off-by: Simon Glass 
---
Changes in v2:
- Update seaboard LCD definitions for new fdt binding

 board/nvidia/dts/tegra2-seaboard.dts |   21 +
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/board/nvidia/dts/tegra2-seaboard.dts 
b/board/nvidia/dts/tegra2-seaboard.dts
index 3352539..3b16f84 100644
--- a/board/nvidia/dts/tegra2-seaboard.dts
+++ b/board/nvidia/dts/tegra2-seaboard.dts
@@ -153,4 +153,25 @@
0x1f04008a>;
linux,fn-keymap = <0x05040002>;
};
+
+   display@0x5420 {
+   nvidia,pwfm = <&pwfm2>;
+   nvidia,frame-buffer = <0x2f68>;
+   nvidia,backlight-enable-gpios = <&gpio 28 0>;   /* PD4 */
+   nvidia,lvds-shutdown-gpios = <&gpio 10 0>;  /* PB2 */
+   nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+   nvidia,panel-vdd-gpios = <&gpio 22 0>;  /* PC6 */
+   nvidia,panel-timings = <4 203 17 15>;
+
+   lcd {
+   compatible = "nvidia,lcd";
+   nvidia,width = <1366>;
+   nvidia,height = <768>;
+   nvidia,bits-per-pixel = <16>;
+   nvidia,pixel-clock = <7060>;
+
+   nvidia,horiz-timing = <11 58 58 58>;
+   nvidia,vert-timing = <1 4 4 4>;
+   };
+   };
 };
-- 
1.7.7.3

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[U-Boot] [PATCH v2 14/19] lcd: Add support for flushing LCD fb from dcache after update

[Simon Glass]

This provides an option for the LCD to flush the dcache after each update
(puts, scroll or clear).

Signed-off-by: Simon Glass 
---
Changes in v2:
- Put the LCD cache flush logic into lcd_putc() instead of lcd_puts()

 common/cmd_echo.c |3 ++-
 common/lcd.c  |   45 ++---
 include/lcd.h |8 
 3 files changed, 48 insertions(+), 8 deletions(-)

diff --git a/common/cmd_echo.c b/common/cmd_echo.c
index 43a6da5..12efbab 100644
--- a/common/cmd_echo.c
+++ b/common/cmd_echo.c
@@ -44,8 +44,9 @@ int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
}
}
 
+   /* Use puts() so that the LCD sees it as a new line */
if (putnl)
-   putc('\n');
+   puts("\n");
 
return 0;
 }
diff --git a/common/lcd.c b/common/lcd.c
index c915a49..758f158 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -97,6 +97,9 @@ static void lcd_setbgcolor (int color);
 
 char lcd_is_enabled = 0;
 
+static char lcd_flush_dcache;  /* 1 to flush dcache after each lcd update */
+
+
 #ifdef NOT_USED_SO_FAR
 static void lcd_getcolreg (ushort regno,
ushort *red, ushort *green, ushort *blue);
@@ -105,6 +108,28 @@ static int lcd_getfgcolor (void);
 
 //
 
+/* Flush LCD activity to the caches */
+void lcd_sync(void)
+{
+   /*
+* flush_dcache_range() is declared in common.h but it seems that some
+* architectures do not actually implement it. Is there a way to find
+* out whether it exists? For now, ARM is safe.
+*/
+#ifdef CONFIG_ARM
+   int line_length;
+
+   if (lcd_flush_dcache)
+   flush_dcache_range((u32)lcd_base,
+   (u32)(lcd_base + lcd_get_size(&line_length)));
+#endif
+}
+
+void lcd_set_flush_dcache(int flush)
+{
+   lcd_flush_dcache = (flush != 0);
+}
+
 /*--*/
 
 static void console_scrollup (void)
@@ -114,6 +139,7 @@ static void console_scrollup (void)
 
/* Clear the last one */
memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
+   lcd_sync();
 }
 
 /*--*/
@@ -144,6 +170,8 @@ static inline void console_newline (void)
/* Scroll everything up */
console_scrollup () ;
--console_row;
+   } else {
+   lcd_sync();
}
 }
 
@@ -369,13 +397,6 @@ int drv_lcd_init (void)
 }
 
 /*--*/
-static
-int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
-   lcd_clear();
-   return 0;
-}
-
 void lcd_clear(void)
 {
 #if LCD_BPP == LCD_MONOCHROME
@@ -417,6 +438,14 @@ void lcd_clear(void)
 
console_col = 0;
console_row = 0;
+   lcd_sync();
+}
+
+static int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc,
+   char *const argv[])
+{
+   lcd_clear();
+   return 0;
 }
 
 U_BOOT_CMD(
@@ -611,6 +640,7 @@ void bitmap_plot (int x, int y)
}
 
WATCHDOG_RESET();
+   lcd_sync();
 }
 #endif /* CONFIG_LCD_LOGO */
 
@@ -809,6 +839,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
break;
};
 
+   lcd_sync();
return (0);
 }
 #endif
diff --git a/include/lcd.h b/include/lcd.h
index 5016d6b..7c2dae2 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -56,6 +56,14 @@ extern void lcd_initcolregs (void);
 /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
 extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
 
+/**
+ * Set whether we need to flush the dcache when changing the LCD image. This
+ * defaults to off.
+ *
+ * @param flushnon-zero to flush cache after update, 0 to skip
+ */
+void lcd_set_flush_dcache(int flush);
+
 #if defined CONFIG_MPC823
 /*
  * LCD controller stucture for MPC823 CPU
-- 
1.7.7.3

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[U-Boot] [PATCH v2 13/19] lcd: Add CONFIG_LCD_ALIGNMENT to select frame buffer alignment

[Simon Glass]

The normal alignment is PAGE_SIZE, but if this is defined, we can support
other alignments.

The motivation for this change is to make the display section-aligned on
ARM so that we can easily turn off data caching for the frame buffer region
without resorting to level 2 page tables.

Signed-off-by: Simon Glass 
---
Changes in v2:
- Use a more generic config CONFIG_LCD_ALIGNMENT for lcd alignment

 README|   10 ++
 common/lcd.c  |   24 +++-
 include/lcd.h |3 +++
 3 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/README b/README
index 67dc444..ccdddbf 100644
--- a/README
+++ b/README
@@ -1398,6 +1398,16 @@ The following options need to be configured:
Normally display is black on white background; define
CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
 
+
+   CONFIG_LCD_ALIGNMENT
+
+   Normally the LCD is page-aligned (tyically 4KB). If this is
+   defined then the LCD will be aligned to this value instead.
+   For ARM it is sometimes useful to use MMU_SECTION_SIZE
+   here, since it is cheaper to change data cache settings on
+   a per-section basis.
+
+
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 
If this option is set, the environment is checked for
diff --git a/common/lcd.c b/common/lcd.c
index bf1a6a9..c915a49 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -35,6 +35,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_ARM
+#include 
+#endif
 #if defined(CONFIG_POST)
 #include 
 #endif
@@ -72,6 +75,10 @@
 # endif
 #endif
 
+#ifndef CONFIG_LCD_ALIGNMENT
+#define CONFIG_LCD_ALIGNMENT PAGE_SIZE
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 ulong lcd_setmem (ulong addr);
@@ -330,6 +337,12 @@ static void test_pattern (void)
 /* ** GENERIC Initialization Routines  */
 //
 
+int lcd_get_size(int *line_length)
+{
+   *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+   return *line_length * panel_info.vl_row;
+}
+
 int drv_lcd_init (void)
 {
struct stdio_dev lcddev;
@@ -337,7 +350,7 @@ int drv_lcd_init (void)
 
lcd_base = (void *)(gd->fb_base);
 
-   lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
+   lcd_get_size(&lcd_line_length);
 
lcd_init (lcd_base);/* LCD initialization */
 
@@ -449,15 +462,16 @@ static int lcd_init (void *lcdbase)
 ulong lcd_setmem (ulong addr)
 {
ulong size;
-   int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
+   int line_length;
 
debug ("LCD panel info: %d x %d, %d bit/pix\n",
panel_info.vl_col, panel_info.vl_row, NBITS 
(panel_info.vl_bpix) );
 
-   size = line_length * panel_info.vl_row;
+   size = lcd_get_size(&line_length);
 
-   /* Round up to nearest full page */
-   size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+   /* Round up to nearest full page, or MMU section if defined */
+   size = ALIGN(size, CONFIG_LCD_ALIGNMENT);
+   addr = ALIGN(addr - CONFIG_LCD_ALIGNMENT + 1, CONFIG_LCD_ALIGNMENT);
 
/* Allocate pages for the frame buffer. */
addr -= size;
diff --git a/include/lcd.h b/include/lcd.h
index 3d9ef16..5016d6b 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -281,6 +281,9 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y);
 /* Allow boards to customize the information displayed */
 void lcd_show_board_info(void);
 
+/* Return the size of the LCD frame buffer, and the line length */
+int lcd_get_size(int *line_length);
+
 //
 /* ** BITMAP DISPLAY SUPPORT   */
 //
-- 
1.7.7.3

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[U-Boot] [PATCH v2 05/19] tegra: Use const for pinmux_config_pingroup/table()

[Simon Glass]

These two functions don't actually modify their arguments so add a const
keyword.

Signed-off-by: Simon Glass 
---
Changes in v2:
- Add new patch to use const in pinmux_config_pingroup/table()

 arch/arm/cpu/armv7/tegra2/pinmux.c|4 ++--
 arch/arm/include/asm/arch-tegra2/pinmux.h |4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/tegra2/pinmux.c 
b/arch/arm/cpu/armv7/tegra2/pinmux.c
index b053f90..bf6d40d 100644
--- a/arch/arm/cpu/armv7/tegra2/pinmux.c
+++ b/arch/arm/cpu/armv7/tegra2/pinmux.c
@@ -554,7 +554,7 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func 
func)
writel(reg, muxctl);
 }
 
-void pinmux_config_pingroup(struct pingroup_config *config)
+void pinmux_config_pingroup(const struct pingroup_config *config)
 {
enum pmux_pingrp pin = config->pingroup;
 
@@ -563,7 +563,7 @@ void pinmux_config_pingroup(struct pingroup_config *config)
pinmux_set_tristate(pin, config->tristate);
 }
 
-void pinmux_config_table(struct pingroup_config *config, int len)
+void pinmux_config_table(const struct pingroup_config *config, int len)
 {
int i;
 
diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h 
b/arch/arm/include/asm/arch-tegra2/pinmux.h
index 469d742..13ee790 100644
--- a/arch/arm/include/asm/arch-tegra2/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra2/pinmux.h
@@ -339,7 +339,7 @@ void pinmux_set_pullupdown(enum pmux_pingrp pin, enum 
pmux_pull pupd);
 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
 
 /* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
+void pinmux_config_pingroup(const struct pingroup_config *config);
 
 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
 
@@ -349,6 +349,6 @@ void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
  * @param config   List of config items
  * @param len  Number of config items in list
  */
-void pinmux_config_table(struct pingroup_config *config, int len);
+void pinmux_config_table(const struct pingroup_config *config, int len);
 
 #endif /* PINMUX_H */
-- 
1.7.7.3

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[U-Boot] [PATCH v2 12/19] arm: Add control over cachability of memory regions

[Simon Glass]

Add support for adjusting the cachability of an L1 section by updating
the MMU. The mmu_set_region_dcache() function allows drivers to make
these changes after the MMU is set up.

It is implemented only for ARMv7 at present.

This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.

Signed-off-by: Simon Glass 
---

 arch/arm/cpu/armv7/cache_v7.c |   11 +++
 arch/arm/include/asm/system.h |   30 
 arch/arm/lib/cache-cp15.c |   62 +---
 3 files changed, 92 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 1b4e808..5f6d039 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -297,6 +297,12 @@ void arm_init_before_mmu(void)
v7_inval_tlb();
 }
 
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+   flush_dcache_range(start, stop);
+   v7_inval_tlb();
+}
+
 /*
  * Flush range from all levels of d-cache/unified-cache used:
  * Affects the range [start, start + size - 1]
@@ -329,6 +335,11 @@ void arm_init_before_mmu(void)
 void  flush_cache(unsigned long start, unsigned long size)
 {
 }
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2b28a26..f52a4fc 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -75,6 +75,36 @@ static inline void set_cr(unsigned int val)
isb();
 }
 
+/* options available for data cache on each page */
+enum dcache_option {
+   DCACHE_OFF,
+   DCACHE_WRITETHROUGH,
+   DCACHE_WRITEBACK,
+};
+
+/* Size of an MMU section */
+enum {
+   MMU_SECTION_SHIFT   = 20,
+   MMU_SECTION_SIZE= 1 << MMU_SECTION_SHIFT,
+};
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param startstart address of memory region to change
+ * \param size size of memory region to change
+ * \param option   dcache option to select
+ */
+void mmu_set_region_dcache(u32 start, int size, enum dcache_option option);
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param startstart address of update in page table
+ * \param stop stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e6c3eae..facb1a7 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -26,12 +26,6 @@
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define CACHE_SETUP0x1a
-#else
-#define CACHE_SETUP0x1e
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void __arm_init_before_mmu(void)
@@ -50,9 +44,52 @@ static void cp_delay (void)
asm volatile("" : : : "memory");
 }
 
-static inline void dram_bank_mmu_setup(int bank)
+void set_section_dcache(int section, enum dcache_option option)
 {
+   u32 value = section << MMU_SECTION_SHIFT | (3 << 10);
u32 *page_table = (u32 *)gd->tlb_addr;
+
+   switch (option) {
+   case DCACHE_WRITETHROUGH:
+   value |= 0x1a;
+   break;
+
+   case DCACHE_WRITEBACK:
+   value |= 0x1e;
+   break;
+
+   case DCACHE_OFF:
+   value |= 0x12;
+   break;
+   }
+
+   page_table[section] = value;
+}
+
+void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+   debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+   __attribute__((weak, alias("__mmu_page_table_flush")));
+
+void mmu_set_region_dcache(u32 start, int size, enum dcache_option option)
+{
+   u32 *page_table = (u32 *)gd->tlb_addr;
+   u32 upto, end;
+
+   end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+   start = start >> MMU_SECTION_SHIFT;
+   debug("mmu_set_region_dcache start=%x, size=%x, option=%d\n",
+ start, size, option);
+   for (upto = start; upto < end; upto++)
+   set_section_dcache(upto, option);
+   mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+}
+
+static inline void dram_bank_mmu_setup(int bank)
+{
bd_t *bd = gd->bd;
int i;
 
@@ -60,21 +97,24 @@ static inline void dram_bank_mmu_setup(int bank)
for (i = bd->bi_dram[bank].start >> 20;
 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
 i++) {
-   page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+   set_section_dc

[U-Boot] [PATCH v2 09/19] tegra: Add SOC support for display/lcd

[Simon Glass]

From: Wei Ni 

Add support for the LCD peripheral at the Tegra2 SOC level. A separate
LCD driver will use this functionality to configure the display.

Mayuresh Kulkarni:
- changes to remove bitfields and clean up for submission

Simon Glass:
- simplify code, move clock control into here, clean-up

Signed-off-by: Mayuresh Kulkarni 
Signed-off-by: Simon Glass 
---

 arch/arm/cpu/armv7/tegra2/Makefile |2 +-
 arch/arm/cpu/armv7/tegra2/display.c|  271 ++
 arch/arm/include/asm/arch-tegra2/dc.h  |  544 
 arch/arm/include/asm/arch-tegra2/display.h |  133 +++
 4 files changed, 949 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/display.h

diff --git a/arch/arm/cpu/armv7/tegra2/Makefile 
b/arch/arm/cpu/armv7/tegra2/Makefile
index 9779e9e..413f8c9 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -39,7 +39,7 @@ COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
-COBJS-$(CONFIG_VIDEO_TEGRA) += pwfm.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += display.o pwfm.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/tegra2/display.c 
b/arch/arm/cpu/armv7/tegra2/display.c
new file mode 100644
index 000..f4f4c85
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/display.c
@@ -0,0 +1,271 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
+{
+   unsigned h_dda, v_dda;
+   unsigned long val;
+
+   val = readl(&dc->cmd.disp_win_header);
+   val |= WINDOW_A_SELECT;
+   writel(val, &dc->cmd.disp_win_header);
+
+   writel(win->fmt, &dc->win.color_depth);
+
+   val = readl(&dc->win.byte_swap);
+   val |= BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT;
+   writel(val, &dc->win.byte_swap);
+
+   val = win->out_x << H_POSITION_SHIFT;
+   val |= win->out_y << V_POSITION_SHIFT;
+   writel(val, &dc->win.pos);
+
+   val = win->out_w << H_SIZE_SHIFT;
+   val |= win->out_h << V_SIZE_SHIFT;
+   writel(val, &dc->win.size);
+
+   val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
+   val |= win->h << V_PRESCALED_SIZE_SHIFT;
+   writel(val, &dc->win.prescaled_size);
+
+   writel(0, &dc->win.h_initial_dda);
+   writel(0, &dc->win.v_initial_dda);
+
+   h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
+   v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
+
+   val = h_dda << H_DDA_INC_SHIFT;
+   val |= v_dda << V_DDA_INC_SHIFT;
+   writel(val, &dc->win.dda_increment);
+
+   writel(win->stride, &dc->win.line_stride);
+   writel(0, &dc->win.buf_stride);
+
+   val = WIN_ENABLE;
+   if (win->bpp < 24)
+   val |= COLOR_EXPAND;
+   writel(val, &dc->win.win_opt);
+
+   writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
+   writel(win->x, &dc->winbuf.addr_h_offset);
+   writel(win->y, &dc->winbuf.addr_v_offset);
+
+   writel(0xff00, &dc->win.blend_nokey);
+   writel(0xff00, &dc->win.blend_1win);
+
+   val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
+   val |= GENERAL_UPDATE | WIN_A_UPDATE;
+   writel(val, &dc->cmd.state_ctrl);
+}
+
+static void write_pair(struct fdt_lcd *config, int item, u32 *reg)
+{
+   writel(config->horiz_timing[item] |
+   (config->vert_timing[item] << 16), reg);
+}
+
+static int update_display_mode(struct dc_disp_reg *disp,
+   struct fdt_lcd *config)
+{
+   unsigned long val;
+   unsigned long rate;
+   unsigned long div;
+
+   writel(0x0, &disp->disp_timing_opt);
+   write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
+   write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
+   write_pai

[U-Boot] [PATCH v2 11/19] tegra: Add LCD support to Nvidia boards

[Simon Glass]

Add calls to the LCD driver from Nvidia board code.

Signed-off-by: Simon Glass 
---

 board/nvidia/common/board.c |   21 -
 1 files changed, 20 insertions(+), 1 deletions(-)

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 2e22133..791 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -29,6 +29,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -87,6 +88,9 @@ int board_init(void)
 {
__maybe_unused int err;
 
+#ifdef CONFIG_VIDEO_TEGRA2
+   tegra_lcd_check_next_stage(gd->blob, 0);
+#endif
/* Do clocks and UART first so that printf() works */
clock_init();
clock_verify();
@@ -122,6 +126,9 @@ int board_init(void)
pin_mux_usb();
board_usb_init(gd->fdt_blob);
 #endif
+#if defined(CONFIG_VIDEO_TEGRA)
+   tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
 
 #ifdef CONFIG_TEGRA2_LP0
/* prepare the WB code to LP0 location */
@@ -142,6 +149,18 @@ int board_early_init_f(void)
 #else
gpio_config_uart();
 #endif
-   return 0;
+#if defined(CONFIG_VIDEO_TEGRA)
+   tegra_lcd_early_init(gd->fdt_blob);
+#endif
+return 0;
 }
 #endif /* EARLY_INIT */
+
+int board_late_init(void)
+{
+#ifdef CONFIG_VIDEO_TEGRA
+   /* Make sure we finish initing the LCD */
+   tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+   return 0;
+}
-- 
1.7.7.3

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[U-Boot] [PATCH v2 08/19] tegra: Add support for PWFM

[Simon Glass]

The pulse width/frequency modulation peripheral supports generating
a repeating pulse. It is useful for controlling LCD brightness.

Signed-off-by: Simon Glass 
---

 arch/arm/cpu/armv7/tegra2/Makefile  |1 +
 arch/arm/cpu/armv7/tegra2/pwfm.c|   40 +++
 arch/arm/include/asm/arch-tegra2/pwfm.h |   54 +++
 3 files changed, 95 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h

diff --git a/arch/arm/cpu/armv7/tegra2/Makefile 
b/arch/arm/cpu/armv7/tegra2/Makefile
index 08c4137..9779e9e 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += pwfm.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/tegra2/pwfm.c b/arch/arm/cpu/armv7/tegra2/pwfm.c
new file mode 100644
index 000..cdb0cbe
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/pwfm.c
@@ -0,0 +1,40 @@
+/*
+ * Tegra2 pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+
+void pwfm_enable(struct pwfm_ctlr *pwfm, int rate, int pulse_width,
+   int freq_divider)
+{
+   u32 reg;
+
+   /* TODO: Can we use clock_adjust_periph_pll_div() here? */
+   clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+
+   reg = PWFM_ENABLE_MASK;
+   reg |= pulse_width << PWFM_WIDTH_SHIFT;
+   reg |= freq_divider << PWFM_DIVIDER_SHIFT;
+   writel(reg, &pwfm->control);
+}
diff --git a/arch/arm/include/asm/arch-tegra2/pwfm.h 
b/arch/arm/include/asm/arch-tegra2/pwfm.h
new file mode 100644
index 000..69e2edd
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/pwfm.h
@@ -0,0 +1,54 @@
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWFM_H
+#define __ASM_ARCH_TEGRA_PWFM_H
+
+/* This is a single PWFM channel */
+struct pwfm_ctlr {
+   uint control;   /* Control register */
+};
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWFM_ENABLE_SHIFT  31
+#define PWFM_ENABLE_MASK   (0x1 << PWFM_ENABLE_SHIFT)
+
+#define PWFM_WIDTH_SHIFT   16
+#define PWFM_WIDTH_MASK(0x7FFF << PWFM_WIDTH_SHIFT)
+
+#define PWFM_DIVIDER_SHIFT 0
+#define PWFM_DIVIDER_MASK  (0x1FFF << PWFM_DIVIDER_SHIFT)
+
+/**
+ * Program the PWFM with the given parameters.
+ *
+ * @param pwfm Pointer to PWFM register
+ * @param rate Clock rate to use for PWFM
+ * @param pulse_width  high pulse width: 0=always low, 1=1/256 pulse high,
+ * n = n/256 pulse high
+ * @param freq_divider frequency divider value (1 to use rate as is)
+ */
+void pwfm_enable(struct pwfm_ctlr *pwfm, int rate, int pulse_width,
+   int freq_divider);
+
+#endif /* __ASM_ARCH_TEGRA_PWFM_H */
-- 
1.7.7.3

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[U-Boot] [PATCH v2 02/19] fdt: Add debugging to fdtdec_get_int/addr()

[Simon Glass]

The new debugging shows the value of integers and addresses read
from the device tree.

Signed-off-by: Simon Glass 
---

 lib/fdtdec.c |   22 --
 1 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index cc09e06..61056f1 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -80,11 +80,16 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node,
const fdt_addr_t *cell;
int len;
 
-   debug("get_addr: %s\n", prop_name);
+   debug("%s: %s\n", __func__, prop_name);
cell = fdt_getprop(blob, node, prop_name, &len);
if (cell && (len == sizeof(fdt_addr_t) ||
-   len == sizeof(fdt_addr_t) * 2))
-   return fdt_addr_to_cpu(*cell);
+   len == sizeof(fdt_addr_t) * 2)) {
+   fdt_addr_t addr = fdt_addr_to_cpu(*cell);
+
+   debug("%p\n", (void *)addr);
+   return addr;
+   }
+   debug("(not found)\n");
return FDT_ADDR_T_NONE;
 }
 
@@ -94,10 +99,15 @@ s32 fdtdec_get_int(const void *blob, int node, const char 
*prop_name,
const s32 *cell;
int len;
 
-   debug("get_size: %s\n", prop_name);
+   debug("%s: %s: ", __func__, prop_name);
cell = fdt_getprop(blob, node, prop_name, &len);
-   if (cell && len >= sizeof(s32))
-   return fdt32_to_cpu(cell[0]);
+   if (cell && len >= sizeof(s32)) {
+   s32 val = fdt32_to_cpu(cell[0]);
+
+   debug("%#x (%d)\n", val, val);
+   return val;
+   }
+   debug("(not found)\n");
return default_val;
 }
 
-- 
1.7.7.3

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[U-Boot] [PATCH v2 19/19] tegra: Enable display/lcd support on Seaboard

[Simon Glass]

From: Mayuresh Kulkarni 

Enable the Seaboard's 16-bit LCD and use it as the console.

Signed-off-by: Mayuresh Kulkarni 
Signed-off-by: Simon Glass 
---

 include/configs/seaboard.h |   12 ++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 1d1176a..ed87bbe 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -62,6 +62,7 @@
 #define CONFIG_SYS_BOARD_ODMDATA   0x300d8011 /* lp1, 1GB */
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT /* Make sure LCD init is complete */
 
 /* SPI */
 #define CONFIG_TEGRA2_SPI
@@ -111,6 +112,13 @@
 
 #undef TEGRA2_DEVICE_SETTINGS
 #define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
-   "stdout=serial\0" \
-   "stderr=serial\0"
+   "stdout=serial,lcd\0" \
+   "stderr=serial,lcd\0"
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPPLCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONSOLE_SCROLL_LINES   10
 #endif /* __CONFIG_H */
-- 
1.7.7.3

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[U-Boot] [PATCH v2 07/19] tegra: fdt: Add LCD definitions for Tegra

[Simon Glass]

Add LCD definitions and also a proposed binding for LCD displays.

The PWFM is in progress on the device-tree-discuss list, so only a
very basic binding is offered here.

I am not sure if it is better to have the lcd within the display
controller as with i2c/spi, or a separate node. From a hardware point
of view the LCD is certainly connected to the display controller, so
perhaps this version makes most sense. We could have a stand-alone
top-level lcd node with a phandle pointing to the display controller,
but these doesn't seem to be an obvious advantage to that approach.

Signed-off-by: Simon Glass 
---
Changes in v2:
- Add nvidia prefix to device tree properties

 arch/arm/dts/tegra20.dtsi   |   25 +++
 doc/device-tree-bindings/video/nvidia-video.txt |   88 +++
 2 files changed, 113 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index f95be58..4e59e9b 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -204,4 +204,29 @@
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x0078>;
};
+
+   pwfm0: pwm@7000a000 {
+   compatible = "nvidia,tegra20-pwfm";
+   reg = <0x7000a000 0x4>;
+   };
+
+   pwfm1: pwm@7000a010 {
+   compatible = "nvidia,tegra20-pwfm";
+   reg = <0x7000a010 0x4>;
+   };
+
+   pwfm2: pwm@7000a020 {
+   compatible = "nvidia,tegra20-pwfm";
+   reg = <0x7000a020 0x4>;
+   };
+
+   pwfm3: pwm@7000a030 {
+   compatible = "nvidia,tegra20-pwfm";
+   reg = <0x7000a030 0x4>;
+   };
+
+   display1: display@0x5420 {
+   compatible = "nvidia,tegra20-display";
+   reg = <0x5420 0x4>;
+   };
 };
diff --git a/doc/device-tree-bindings/video/nvidia-video.txt 
b/doc/device-tree-bindings/video/nvidia-video.txt
new file mode 100644
index 000..2e1b999
--- /dev/null
+++ b/doc/device-tree-bindings/video/nvidia-video.txt
@@ -0,0 +1,88 @@
+LCD Display
+---
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot)
+
+The device node for a display device is as described in the document
+"Open Firmware Recommended Practice : Universal Serial Bus" with the
+following modifications and additions :
+
+Required properties :
+ - compatible : Should be "nvidia,tegra20-display"
+ - nvidia,pwfm: phandle of PWFM to use for backlight
+
+Note: This is just a phande and provides no information, nor a backlight
+node. The PWM is still under discussion I think:
+   http://patchwork.ozlabs.org/patch/132386/
+
+We don't support any parameters as yet - the setting is hard-coded.
+
+ - nvidia,width: width of display in pixels
+ - nvidia,height: height of display in pixels
+ - nvidia,bits-per-pixel: number of bits per pixel (depth)
+ - nvidia,pixel-clock : Pixel clock in Hz
+ - nvidia,horiz-timing; horizontal timing: ref_to_sync, sync_width. back_porch,
+   front_porch
+ - nvidia,vert-timing; vertical timing: ref_to_sync, sync_width. back_porch,
+   front_porch
+
+This node should sit inside its controller.
+
+
+Nvidia Tegra2x Display Controller
+-
+
+The device node for a NAND flash controller is as described in the document
+"Open Firmware Recommended Practice : Universal Serial Bus" with the
+following modifications and additions :
+
+Required properties:
+ - compatible: should be "tegra20-display"
+ - panel-timings: 4 cells containing required timings in ms:
+   * delay between panel_vdd-rise and data-rise
+   * delay between data-rise and backlight_vdd-rise
+   * delay between backlight_vdd and pwm-rise
+   * delay between pwm-rise and backlight_en-rise
+
+(should we use us here, or perhaps call it panel-timings-ms?)
+
+Optional properties:
+ - nvidia,frame-buffer: address of frame buffer (if omitted it will be
+   calculated)
+   - This may be useful to share an address between U-Boot and Linux and
+   avoid boot-time corruption / flicker
+
+Optional GPIO properies all have (phandle, GPIO number, flags):
+ - nvidia,backlight-enable-gpios: backlight enable GPIO
+ - nvidia,lvds-shutdown-gpios: LVDS power shutdown GPIO
+ - nvidia,backlight-vdd-gpios: backlight power GPIO
+ - nvidia,panel-vdd-gpios: panel power GPIO
+
+(Perhap use polariy bit so that lvds-shutdown becomes lvds-enable?)
+
+I have put these into the display controller since I don't think they are
+generic enough to go in the lcd node.
+
+Example:
+
+display@0x5420 {
+   nvidia,pwfm = <&pwfm2>;
+   nvidia,frame-buffer = <0x2f68>;
+   nvidia,backlight-enable-gpios = <&gpio 28 0>;   /* PD4 */
+   nvidia,lvds-shutdown-gpios = <&gpio 10 0>;  /* PB2 */
+   nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+   nvidia

Re: [U-Boot] [PATCH] powerpc/CoreNet: add tool to support pbl image build.

[Tabi Timur-B04825]

On Jun 12, 2012, at 7:54 PM, "Wood Scott-B07421"  wrote:

> 
> You mean to replace this tool?  There are other PBL things that may need
> to be done, such as reconfiguring the SPI speed so it doesn't take
> forever to read out the rest of the PBL image.

My tool builds and RCW image. I could change it so that it also understands the 
PBL language, but that's not trivial. For now, it would be easy to add a 
feature to only embed the PBL binary into the RCW binary. 


> 
> -Scott

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[U-Boot] [PATCH v2] omap4: Use a smaller M,N couple for IVA DPLL

[Sebastien Jan]

This reduced M,N couple corresponds to the advised value from
TI HW team.

Tested on 4460 Pandaboard, it also provides peripheral clocks
closer to the advised values.

Signed-off-by: Sebastien Jan 
---
 arch/arm/cpu/armv7/omap4/clocks.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap4/clocks.c 
b/arch/arm/cpu/armv7/omap4/clocks.c
index c568951..1d92e66 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -146,7 +146,7 @@ static const struct dpll_params 
iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
{727, 14, -1, -1, 4, 7, -1, -1},/* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1},/* 26 MHz   */
{931, 26, -1, -1, 4, 7, -1, -1},/* 27 MHz   */
-   {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
+   {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
 };
 
 /* ABE M & N values with sys_clk as source */
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] omap4: Use a smaller M,N couple for IVA DPLL

[Jan, Sebastien]

On Wed, Jun 13, 2012 at 5:03 PM, Tom Rini  wrote:

> On 06/13/2012 12:30 AM, Jan, Sebastien wrote:
> > Hi Tom,
> >
> > On Tue, Jun 12, 2012 at 7:41 PM, Tom Rini  > > wrote:
> >
> > On Tue, Jun 12, 2012 at 12:34 AM, Sebastien Jan  > > wrote:
> > > Signed-off-by: Sebastien Jan mailto:s-...@ti.com>>
> >
> > Please explain what / why you are changing things here (based on
> docs,
> > testing, ?).  Thanks!
> >
> >
> > Sure, sorry for missing that. The reduced M,N couple in this patch
> > corresponds to the advised value from our HW team. It tested with it,
> > and it also provides peripheral clocks closer to the advised values.
>
> Thanks.  Can you please submit a v2 with that explanation in the commit
> message?
>

Yes, will do
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Re: [U-Boot] [PATCH] omap4: Use a smaller M,N couple for IVA DPLL

[Jan, Sebastien]

Hi Tom,

On Tue, Jun 12, 2012 at 7:41 PM, Tom Rini  wrote:

> On Tue, Jun 12, 2012 at 12:34 AM, Sebastien Jan  wrote:
> > Signed-off-by: Sebastien Jan 
>
> Please explain what / why you are changing things here (based on docs,
> testing, ?).  Thanks!
>

Sure, sorry for missing that. The reduced M,N couple in this patch
corresponds to the advised value from our HW team. It tested with it, and
it also provides peripheral clocks closer to the advised values.

Regards,
Seb
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Re: [U-Boot] [PATCH] omap4: Use a smaller M,N couple for IVA DPLL

[Tom Rini]

On 06/13/2012 12:30 AM, Jan, Sebastien wrote:
> Hi Tom,
> 
> On Tue, Jun 12, 2012 at 7:41 PM, Tom Rini  > wrote:
> 
> On Tue, Jun 12, 2012 at 12:34 AM, Sebastien Jan  > wrote:
> > Signed-off-by: Sebastien Jan mailto:s-...@ti.com>>
> 
> Please explain what / why you are changing things here (based on docs,
> testing, ?).  Thanks!
> 
> 
> Sure, sorry for missing that. The reduced M,N couple in this patch
> corresponds to the advised value from our HW team. It tested with it,
> and it also provides peripheral clocks closer to the advised values.

Thanks.  Can you please submit a v2 with that explanation in the commit
message?

-- 
Tom
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Re: [U-Boot] [PATCH] integrator: break out common config

[Linus Walleij]

On Tue, May 22, 2012 at 10:53 PM, Linus Walleij
 wrote:

> The configuration that is common for all Integrator boards may
> just as well be stored in a common include file as per pattern
> from other boards. This eases maintenance quite a bit.
>
> Signed-off-by: Linus Walleij 

Albert, is this patch OK?

It's available here in patchwork:
http://patchwork.ozlabs.org/patch/160740/

Yours,
Linus Walleij
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[U-Boot] [PATCH v2 06/14] arm/km: enable BOCO2 FPGA download support

[Holger Brunck]

From: Valentin Longchamp 

This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.

This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1
   for the end of the FPGA configuration (with a timeout)
3) reset the FPGA
4) finally remove the access to its config EEPROM from the FPGA so that
   the CPU can update the FPGA configuration when the kernel is running

The boards with a PCIe FPGA but without BOCO2 still are supported.

The config option name is CONFIG_KM_FPGA_CONFIG

Signed-off-by: Valentin Longchamp 
Signed-off-by: Holger Brunck 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 board/keymile/common/common.h  |6 +
 board/keymile/km_arm/Makefile  |4 +
 board/keymile/km_arm/fpga_config.c |  212 
 board/keymile/km_arm/km_arm.c  |   21 +++-
 boards.cfg |2 +-
 include/configs/km/km_arm.h|3 +
 include/configs/km_kirkwood.h  |8 +-
 7 files changed, 246 insertions(+), 10 deletions(-)
 create mode 100644 board/keymile/km_arm/fpga_config.c

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 49225b8..c58e565 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -131,6 +131,12 @@ int ext_switch_reg_write(const char *devname, u8 phy_addr, 
u8 port,
 int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
u8 reg, u16 *data);
 
+
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
 int set_km_env(void);
 int fdt_set_node_and_value(void *blob,
char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index 06079e9..bd824e2 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB  = $(obj)lib$(BOARD).o
 
 COBJS  := $(BOARD).o ../common/common.o ../common/ivm.o
 
+ifdef CONFIG_KM_FPGA_CONFIG
+COBJS  += fpga_config.o
+endif
+
 ifdef CONFIG_KM_MANAGED_SW_ADDR
 COBJS  += managed_switch.o
 endif
diff --git a/board/keymile/km_arm/fpga_config.c 
b/board/keymile/km_arm/fpga_config.c
new file mode 100644
index 000..4356b9a
--- /dev/null
+++ b/board/keymile/km_arm/fpga_config.c
@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longch...@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include 
+#include 
+#include 
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN39
+
+#define BOCO_ADDR  0x10
+
+#define ID_REG 0x00
+#define BOCO2_ID   0x5b
+
+static int check_boco2(void)
+{
+   int ret;
+   u8 id;
+
+   ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
+   if (ret) {
+   printf("%s: error reading the BOCO id !!\n", __func__);
+   return ret;
+   }
+
+   return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+   int ret;
+   u8 regval;
+
+   /* give access to the EEPROM from FPGA */
+   ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
+   if (ret) {
+   printf("%s: error reading the BOCO @%#x !!\n",
+   __func__, reg);
+   return ret;
+   }
+   regval &= ~flags;
+   ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
+   if (ret) {
+   printf("%s: error writing the BOCO @%#x !!\n",
+   __func__, reg);
+   return ret;
+   }
+
+   return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+   int ret;
+   u8 regval;
+
+   /* give access to the EEPROM from FPGA */
+   ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
+   if (ret) {
+   printf("%s: error reading the BOCO @%#x !!\n",
+   __func__, reg);
+   return ret;
+   }
+   regval |= flags;
+   ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
+   if (ret) {
+   printf

[U-Boot] [PATCH v2 05/14] arm/km: correct init of 88e6352 switch in the reset_phy function

[Holger Brunck]

From: Valentin Longchamp 

This is achieved thanks to the support read/write regs for the external
88e6352 switch. The functions for this are added into an own file
managed_switch.c. This is compiled if the define CONFIG_KM_MANAGED_SW_ADDR
was set in the board setup. This define specifies the phy address.

Signed-off-by: Valentin Longchamp 
Signed-off-by: Holger Brunck 
cc: Gerlando Falauto 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 board/keymile/common/common.h |6 +
 board/keymile/km_arm/Makefile |4 +
 board/keymile/km_arm/km_arm.c |   26 +-
 board/keymile/km_arm/managed_switch.c |  166 +
 include/configs/km_kirkwood.h |   13 +++
 5 files changed, 214 insertions(+), 1 deletions(-)
 create mode 100644 board/keymile/km_arm/managed_switch.c

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index 6c1f640..49225b8 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -125,6 +125,12 @@ struct bfticu_iomap {
 int ethernet_present(void);
 int ivm_read_eeprom(void);
 
+
+int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
+   u8 reg, u16 data);
+int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
+   u8 reg, u16 *data);
+
 int set_km_env(void);
 int fdt_set_node_and_value(void *blob,
char *nodename,
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index aa51255..06079e9 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -31,6 +31,10 @@ LIB  = $(obj)lib$(BOARD).o
 
 COBJS  := $(BOARD).o ../common/common.o ../common/ivm.o
 
+ifdef CONFIG_KM_MANAGED_SW_ADDR
+COBJS  += managed_switch.o
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 89fcab3..66b82d0 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -9,6 +9,9 @@
  * (C) Copyright 2010
  * Heiko Schocher, DENX Software Engineering, h...@denx.de.
  *
+ * (C) Copyright 2011, 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longch...@keymile.com
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -36,6 +39,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -351,7 +355,27 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#elif !defined(CONFIG_KM_PIGGY4_88E6352)
+#elif defined(CONFIG_KM_PIGGY4_88E6352)
+
+#if defined(CONFIG_KM_MANAGED_SW_ADDR)
+void reset_phy(void)
+{
+   char *name = "egiga0";
+
+   if (miiphy_set_current_dev(name))
+   return;
+
+   /* enable autoneg on port 0 phy */
+   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 0, 0, 0x3300);
+
+   /* egress broadcast franes on all macs, with forwarding */
+   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 16, 4, 0x000f);
+   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 20, 4, 0x000f);
+   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 21, 4, 0x000f);
+}
+#endif
+
+#else
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {
diff --git a/board/keymile/km_arm/managed_switch.c 
b/board/keymile/km_arm/managed_switch.c
new file mode 100644
index 000..482c18d
--- /dev/null
+++ b/board/keymile/km_arm/managed_switch.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longch...@keymile.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include 
+#include 
+#include 
+
+#define SMI_HDR((0x8 | 0x1) << 12)
+#define SMI_BUSY_MASK  (0x8000)
+#define SMIRD_OP   (0x2 << 10)
+#define SMIWR_OP   (0x1 << 10)
+#define SMI_MASK   0x1f
+#define PORT_SHIFT 5
+
+#define COMMAND_REG0
+#define DATA_REG   1
+
+static int ext_switch_wait_rdy(const char *devname, u8 phy_addr)
+{
+   u16 command;
+   u32 timeout = 100;
+   int ret;
+
+   /* wait till the SMI is not busy */
+   do {
+   /* read co

[U-Boot] [PATCH v2 13/14] arm/km: add implementation for read_dip_switch

[Holger Brunck]

From: Thomas Herzmann 

Add a function to read the dip_switch on kmcoge5un. If the
switch is set the actual_bank is set to 0 and this SW is
booted.

Signed-off-by: Thomas Herzmann 
Signed-off-by: Holger Brunck 
cc: Valentin Longchamp 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 board/keymile/km_arm/km_arm.c |   14 +-
 include/configs/km_kirkwood.h |3 ---
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 1348186..7e8bdfe 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -290,12 +290,24 @@ int board_init(void)
 
 int board_late_init(void)
 {
+#if defined(CONFIG_KMCOGE5UN)
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE  43
+   u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+   /* if pin 1 do full erase */
+   if (dip_switch != 0) {
+   /* start bootloader */
+   puts("DIP:   Enabled\n");
+   setenv("actual_bank", "0");
+   }
+#endif
+
 #if defined(CONFIG_KM_FPGA_CONFIG)
wait_for_fpga_config();
fpga_reset();
toggle_eeprom_spi_bus();
 #endif
-
return 0;
 }
 
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index b29e1a6..c42d0cb 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -184,8 +184,5 @@
 #undef  CONFIG_KIRKWOOD_PCIE_INIT
 #endif
 
-#ifndef CONFIG_KM_FPGA_CONFIG
-#undef  BOARD_LATE_INIT
-#endif
 
 #endif /* _CONFIG_KM_KIRKWOOD */
-- 
1.7.1

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[U-Boot] [PATCH v2 03/14] arm/km: convert mgcoge3un target to km_kirkwood

[Holger Brunck]

Use the generic header km_kirkwood.h and get rid of the
board specific header.

Signed-off-by: Holger Brunck 
Signed-off-by: Valentin Longchamp 
cc: Prafulla Wadaskar 
---
changes for v2:
   - rebased because of changes in other patches

 board/keymile/km_arm/km_arm.c |9 ++--
 boards.cfg|2 +-
 include/configs/km_kirkwood.h |   46 +
 include/configs/mgcoge3un.h   |   87 -
 4 files changed, 51 insertions(+), 93 deletions(-)
 delete mode 100644 include/configs/mgcoge3un.h

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index b1e4178..09a9538 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -114,7 +114,7 @@ u32 kwmpp_config[] = {
0
 };
 
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
 /*
  * Wait for startup OK from mgcoge3ne
  */
@@ -134,8 +134,7 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
-   defined(CONFIG_KM_PIGGY4_88E6352))
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
 /*
  * All boards with PIGGY4 connected via a simple switch have ethernet always
  * present.
@@ -203,7 +202,7 @@ int misc_init_r(void)
printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
gd->bd->bi_arch_number = mach_type;
}
-#if defined(CONFIG_MGCOGE3UN)
+#if defined(CONFIG_KM_MGCOGE3UN)
char *wait_for_ne;
wait_for_ne = getenv("waitforne");
if (wait_for_ne != NULL) {
@@ -318,7 +317,7 @@ void dram_init_banksize(void)
}
 }
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
 
 #definePHY_LED_SEL 0x18
 #define PHY_LED0_LINK  (0x5)
diff --git a/boards.cfg b/boards.cfg
index 6b3ca89..47d384e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -141,7 +141,7 @@ dns325   arm arm926ejs   -  
 d-link
 km_kirkwood  arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
 km_kirkwood_pci  arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD_PCI,KM_RECONFIG_XLX
 kmnusa   arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_NUSA
-mgcoge3unarm arm926ejs   km_arm  
keymilekirkwood
+mgcoge3unarm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_MGCOGE3UN
 kmcoge5unarm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_COGE5UN
 portl2   arm arm926ejs   km_arm  
keymilekirkwood
 inetspace_v2 arm arm926ejs   netspace_v2 LaCie 
 kirkwood   lacie_kw:INETSPACE_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index d839a02..f5b9d27 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -58,6 +58,20 @@
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
 
+/* KM_MGCOGE3UN */
+#elif defined(CONFIG_KM_MGCOGE3UN)
+#define CONFIG_IDENT_STRING"\nKeymile COGE3UN"
+#define CONFIG_HOSTNAMEmgcoge3un
+#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG \
+   $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_KM_BOARD_EXTRA_ENV  "waitforne=true\0"
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6061
+
+/* KMCOGE5UN */
 #elif defined(CONFIG_KM_COGE5UN)
 #define CONFIG_IDENT_STRING"\nKeymile COGE5UN"
 #define KM_IVM_BUS "pca9547:70:9"  /* I2C2 (Mux-Port 1)*/
@@ -111,7 +125,39 @@
 
 #endif
 
+#ifdef CONFIG_KM_PIGGY4_88E6061
+/*
+ * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * an Marvell 88E6061 simple switch.
+ * In this case we have to change the default settings for the
+ * ethernet phy connected to the kirkwood.
+ * In this case 100MB full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE  ( \
+   MVGBE_FORCE_LINK_PASS   | \
+   MVGBE_DIS_AUTO_NEG_FOR_DUPLX| \
+   MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL| \
+   MVGBE_ADV_NO_FLOW_CTRL  | \
+   MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+   MVGBE_FORCE_BP_MODE_NO_JAM  | \
+   (1 << 9) /* Reserved bit has to be 1 */ | \
+   MVGBE_DO_NOT_FORCE_LINK_FAIL| \
+   MVGBE_DIS_AUTO_NEG_SPEED_GMII   | \
+   MVGBE_DTE_ADV_0 | \
+   MVGBE_MIIPHY_MAC_MODE   | \
+

[U-Boot] [PATCH v2 09/14] arm/km: add support for external switch configuration

[Holger Brunck]

From: Valentin Longchamp 

This can be used if we do not want to use an EEPROM for the
configuration.

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 board/keymile/common/common.h |7 --
 board/keymile/km_arm/managed_switch.c |  169 +++--
 board/keymile/km_arm/managed_switch.h |   99 +++
 3 files changed, 258 insertions(+), 17 deletions(-)
 create mode 100644 board/keymile/km_arm/managed_switch.h

diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index c58e565..e9abfcd 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -125,13 +125,6 @@ struct bfticu_iomap {
 int ethernet_present(void);
 int ivm_read_eeprom(void);
 
-
-int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
-   u8 reg, u16 data);
-int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
-   u8 reg, u16 *data);
-
-
 int trigger_fpga_config(void);
 int wait_for_fpga_config(void);
 int fpga_reset(void);
diff --git a/board/keymile/km_arm/managed_switch.c 
b/board/keymile/km_arm/managed_switch.c
index 482c18d..3b022cd 100644
--- a/board/keymile/km_arm/managed_switch.c
+++ b/board/keymile/km_arm/managed_switch.c
@@ -25,15 +25,43 @@
 #include 
 #include 
 
-#define SMI_HDR((0x8 | 0x1) << 12)
-#define SMI_BUSY_MASK  (0x8000)
-#define SMIRD_OP   (0x2 << 10)
-#define SMIWR_OP   (0x1 << 10)
-#define SMI_MASK   0x1f
-#define PORT_SHIFT 5
+#include "managed_switch.h"
 
-#define COMMAND_REG0
-#define DATA_REG   1
+#if defined(CONFIG_KM_NUSA)
+struct switch_reg sw_conf[] = {
+   /* port 0, PIGY4, autoneg */
+   { PORT(0), PORT_PHY, NO_SPEED_FOR },
+   { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+   { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+   FULL_DUPLEX },
+   { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+   /* port 1, unused */
+   { PORT(1), PORT_CTRL, PORT_DIS },
+   { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
+   { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+   /* port 2, unused */
+   { PORT(2), PORT_CTRL, PORT_DIS },
+   { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+   { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+   /* port 3, unused */
+   { PORT(3), PORT_CTRL, PORT_DIS },
+   { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
+   { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+   /* port 4, ICNEV, SerDes, SGMII */
+   { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+   { PORT(4), PORT_PHY, SPEED_1000_FOR },
+   { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+   { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
+   { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+   /* port 5, CPU_RGMII */
+   { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
+   FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
+   FULL_DPX_FOR | SPEED_1000_FOR },
+   { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+   /* port 6, unused, this port has no phy */
+   { PORT(6), PORT_CTRL, PORT_DIS },
+};
+#endif
 
 static int ext_switch_wait_rdy(const char *devname, u8 phy_addr)
 {
@@ -59,7 +87,7 @@ static int ext_switch_wait_rdy(const char *devname, u8 
phy_addr)
return 0;
 }
 
-int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
+static int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 port,
u8 reg, u16 *data)
 {
int ret;
@@ -85,7 +113,7 @@ int ext_switch_reg_read(const char *devname, u8 phy_addr, u8 
port,
return ret;
 }
 
-int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
+static int ext_switch_reg_write(const char *devname, u8 phy_addr, u8 port,
u8 reg, u16 data)
 {
int ret;
@@ -114,6 +142,127 @@ int ext_switch_reg_write(const char *devname, u8 
phy_addr, u8 port,
return 0;
 }
 
+static int ppu_enable(const char *devname, u8 phy_addr)
+{
+   int i, ret = 0;
+   u16 reg;
+
+   ret = ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
+   if (ret) {
+   printf("%s: Error reading global ctrl reg\n", __func__);
+   return ret;
+   }
+
+   reg |= PPU_ENABLE;
+
+   ret = ext_switch_reg_write(devname, phy_addr, GLOBAL, GLOBAL_CTRL, reg);
+   if (ret) {
+   printf("%s: Error writing global ctrl reg\n", __func__);
+   return ret;
+   }
+
+   for (i = 0; i < 1000; i++) {
+   ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_STATUS,
+   ®);
+   if ((reg & 0xc000) == 0xc000)
+   return 0;
+   udelay(1000);
+   }
+
+   return -ETIMEDOUT;
+}
+
+static int ppu_disable(const char *devname, u8 phy_addr)
+{
+   int i, ret = 0;
+   u16 reg;
+
+   ret = ext_switch_reg_read(devname, phy_addr, GLOBAL, GLOBAL_CTRL, ®);
+   if (ret) {
+  

[U-Boot] [PATCH v2 04/14] arm/km: remove portl2.h and use km_kirkwood instead

[Holger Brunck]

The additional headerfile is unneeded here, we can use the generic
km_kirkwood.h instead. And we can use the better config option
KM_PIGGY4_88E6061 for the specific features for boards with this
design in km_arm.c.

Signed-off-by: Holger Brunck 
Signed-off-by: Valentin Longchamp 
cc: Prafulla Wadaskar 
---
changes for v2: -simply rebased

 board/keymile/km_arm/km_arm.c |2 +-
 boards.cfg|2 +-
 include/configs/km_kirkwood.h |8 
 include/configs/portl2.h  |   85 -
 4 files changed, 10 insertions(+), 87 deletions(-)
 delete mode 100644 include/configs/portl2.h

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 09a9538..89fcab3 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -317,7 +317,7 @@ void dram_init_banksize(void)
}
 }
 
-#if (defined(CONFIG_KM_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
 
 #definePHY_LED_SEL 0x18
 #define PHY_LED0_LINK  (0x5)
diff --git a/boards.cfg b/boards.cfg
index 47d384e..3b63167 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -143,7 +143,7 @@ km_kirkwood_pci  arm arm926ejs   km_arm 
 keymile
 kmnusa   arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_NUSA
 mgcoge3unarm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_MGCOGE3UN
 kmcoge5unarm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_COGE5UN
-portl2   arm arm926ejs   km_arm  
keymilekirkwood
+portl2   arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_PORTL2
 inetspace_v2 arm arm926ejs   netspace_v2 LaCie 
 kirkwood   lacie_kw:INETSPACE_V2
 net2big_v2   arm arm926ejs   net2big_v2  LaCie 
 kirkwood   lacie_kw:NET2BIG_V2
 netspace_max_v2  arm arm926ejs   netspace_v2 LaCie 
 kirkwood   lacie_kw:NETSPACE_MAX_V2
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index f5b9d27..44a3e7a 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -83,6 +83,14 @@
 #define CONFIG_HOSTNAMEkmcoge5un
 #define CONFIG_KM_DISABLE_PCIE
 #define CONFIG_KM_PIGGY4_88E6352
+
+/* KM_PORTL2 */
+#elif defined(CONFIG_KM_PORTL2)
+#define CONFIG_IDENT_STRING"\nKeymile Port-L2"
+#define CONFIG_HOSTNAMEportl2
+#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_PIGGY4_88E6061
+
 #else
 #error ("Board unsupported")
 #endif
diff --git a/include/configs/portl2.h b/include/configs/portl2.h
deleted file mode 100644
index e436cfe..000
--- a/include/configs/portl2.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor 
- * Prafulla Wadaskar 
- *
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, s...@denx.de.
- *
- * (C) Copyright 2010-2011
- * Holger Brunck, Keymile GmbH Hannover, holger.bru...@keymile.com.
- * Valentin Longchamp, Keymile AG Bern, valentin.longch...@keymile.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* for linking errors see
- * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
-
-#ifndef _CONFIG_PORTL2_H
-#define _CONFIG_PORTL2_H
-
-/* include common defines/options for all arm based Keymile boards */
-#include "km/km_arm.h"
-
-/*
- * Version number information
- */
-#define CONFIG_IDENT_STRING"\nKeymile Port-L2"
-#define CONFIG_HOSTNAMEportl2
-#define CONFIG_PORTL2
-
-#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
-/*
- * Note: This is only valid for HW > P1A if you got an outdated P1A
- *   use KM_ENV_BUS  "pca9544a:70:a"
- */
-#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
-
-/*
- * portl2 has a fixed link to the XMPP backplane
- * with 100MB full duplex and autoneg off, for thi

[U-Boot] [PATCH v2 14/14] arm/km: remove calls to kw_gpio_* in board_early_init_f

[Holger Brunck]

These functions tried to access two static tables before relocation
(board_early_init_f is executed before relocation). But these static
tables lie in the bss section which is not valid before relocation.
These accesses then overwrote some parts of u-boot binary before it was
relocated. For the kmnusa build, this results in a corrupted important
env variable (bootcmd) but it may be that some other parts of the u-boot
binary are corrupted.

This patch solves this problem by moving all the kw_gpio_* calls to
board_init, which should be early enough in the boot sequence. The only
calls that could not be moved is the one for the SOFT (bitbang) I2C, and
they have been replaced by a direct access to the GPIO dataout Control
register to set the two GPIOs as output.


Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
---
changes for v2:
  - fix comment syntax
  - rebase

 board/keymile/km_arm/km_arm.c |   43 ++--
 include/configs/km/km_arm.h   |1 +
 2 files changed, 29 insertions(+), 15 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 7e8bdfe..7169fd1 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -248,38 +248,51 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
+#if defined(CONFIG_SOFT_I2C)
u32 tmp;
 
+   /* set the 2 bitbang i2c pins as output gpios */
+   tmp = readl(KW_GPIO0_BASE + 4);
+   writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
+#endif
+
kirkwood_mpp_conf(kwmpp_config, NULL);
+   return 0;
+}
 
+int board_init(void)
+{
/*
-* The FLASH_GPIO_PIN switches between using a
+* arch number of board
+*/
+   gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
+
+   /* address of boot parameters */
+   gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+   /*
+* The KM_FLASH_GPIO_PIN switches between using a
 * NAND or a SPI FLASH. Set this pin on start
 * to NAND mode.
 */
-   tmp = readl(KW_GPIO0_BASE);
-   writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-   tmp = readl(KW_GPIO0_BASE + 4);
-   writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
+   kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+   kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 
 #if defined(CONFIG_SOFT_I2C)
-   /* init the GPIO for I2C Bitbang driver */
+   /*
+* Reinit the GPIO for I2C Bitbang driver so that the now
+* available gpio framework is consistent. The calls to
+* direction output in are not necessary, they are already done in
+* board_early_init_f
+*/
kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
-   kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
-   kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
 #endif
+
 #if defined(CONFIG_SYS_EEPROM_WREN)
kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 #endif
-   return 0;
-}
-
-int board_init(void)
-{
-   /* address of boot parameters */
-   gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
 #if defined(CONFIG_KM_FPGA_CONFIG)
trigger_fpga_config();
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index 5fbb590..8a6b345 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -192,6 +192,7 @@ int get_sda(void);
 int get_scl(void);
 #define KM_KIRKWOOD_SDA_PIN8
 #define KM_KIRKWOOD_SCL_PIN9
+#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300
 #define KM_KIRKWOOD_ENV_WP 38
 
 #define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
-- 
1.7.1

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[U-Boot] [PATCH v2 08/14] arm/km: redefine piggy 4 reg names to avoid conflicts

[Holger Brunck]

From: Valentin Longchamp 

Some very similar #defines for reg addresses are used in a later patch
(managed_switch support for km_arm).

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 board/keymile/km_arm/km_arm.c |   22 +++---
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 5c9ba8f..d9cd4a0 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -332,13 +332,13 @@ void dram_init_banksize(void)
 
 #if (defined(CONFIG_KM_PIGGY4_88E6061))
 
-#definePHY_LED_SEL 0x18
-#define PHY_LED0_LINK  (0x5)
-#define PHY_LED1_ACT   (0x8<<4)
-#define PHY_LED2_INT   (0xe<<8)
-#definePHY_SPEC_CTRL   0x1c
+#definePHY_LED_SEL_REG 0x18
+#define PHY_LED0_LINK  (0x5)
+#define PHY_LED1_ACT   (0x8<<4)
+#define PHY_LED2_INT   (0xe<<8)
+#definePHY_SPEC_CTRL_REG   0x1c
 #define PHY_RGMII_CLK_STABLE   (0x1<<10)
-#define PHY_CLSA   (0x1<<1)
+#define PHY_CLSA   (0x1<<1)
 
 /* Configure and enable MV88E3018 PHY */
 void reset_phy(void)
@@ -350,15 +350,15 @@ void reset_phy(void)
return;
 
/* RGMII clk transition on data stable */
-   if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0)
+   if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
printf("Error reading PHY spec ctrl reg\n");
-   if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
-   reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
+   if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+   reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
printf("Error writing PHY spec ctrl reg\n");
 
/* leds setup */
-   if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
-   PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
+   if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+   PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
printf("Error writing PHY LED reg\n");
 
/* reset the phy */
-- 
1.7.1

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[U-Boot] [PATCH v2 12/14] arm/km: support the 2 PCIe fpga resets

[Holger Brunck]

From: Valentin Longchamp 

The PCIe FPGAs now have to support 2 resets: one for the non traffic
affecting part (PCIe) and one for the traffic affecting part.

When the FPGA is not reconfigured, we only reset the PCIe part.

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 board/keymile/km_arm/fpga_config.c |   13 +
 1 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/board/keymile/km_arm/fpga_config.c 
b/board/keymile/km_arm/fpga_config.c
index 8ac6393..fcc5fe6 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -99,7 +99,7 @@ static int boco_set_bits(u8 reg, u8 flags)
 #define FPGA_INIT_B0x10
 #define FPGA_DONE  0x20
 
-static int fpga_done()
+static int fpga_done(void)
 {
int ret = 0;
u8 regval;
@@ -206,25 +206,30 @@ int wait_for_fpga_config(void)
 }
 
 #define PRST1  0x4
-#define BRIDGE_RST 0x4
+#define PCIE_RST   0x10
+#define TRAFFIC_RST0x04
 
 int fpga_reset(void)
 {
int ret = 0;
+   u8 resets;
 
if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */
return 0;
}
 
-   ret = boco_clear_bits(PRST1, BRIDGE_RST);
+   /* if we have skipped, we only want to reset the PCIe part */
+   resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+   ret = boco_clear_bits(PRST1, resets);
if (ret)
return ret;
 
/* small delay for the pulse */
udelay(10);
 
-   ret = boco_set_bits(PRST1, BRIDGE_RST);
+   ret = boco_set_bits(PRST1, resets);
if (ret)
return ret;
 
-- 
1.7.1

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[U-Boot] [PATCH v2 11/14] arm/km: skip FPGA config when already configured

[Holger Brunck]

From: Valentin Longchamp 

In order to be able to perform board resets without interrupting the
traffic, the configuration of an already properly configured FPGA is
skipped.

This is because some PCIe FPGAs embed some other function that must
continue to work over reset.

It is then the responsibility of the application to trigger a
reconfiguration when needed. This is done by lowering the FPGA_INIT_B
pin for delaying the configuration to u-boot @ next reboot, and then
lower the FPGA_PROGRAM_B signal.

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
---
changes for v2:
   - nothing

 board/keymile/km_arm/fpga_config.c |   41 +++-
 1 files changed, 40 insertions(+), 1 deletions(-)

diff --git a/board/keymile/km_arm/fpga_config.c 
b/board/keymile/km_arm/fpga_config.c
index 4356b9a..8ac6393 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -96,12 +96,43 @@ static int boco_set_bits(u8 reg, u8 flags)
 #define SPI_REG0x06
 #define CFG_EEPROM 0x02
 #define FPGA_PROG  0x04
+#define FPGA_INIT_B0x10
 #define FPGA_DONE  0x20
 
+static int fpga_done()
+{
+   int ret = 0;
+   u8 regval;
+
+   /* this is only supported with the boco2 design */
+   if (!check_boco2())
+   return 0;
+
+   ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1);
+   if (ret) {
+   printf("%s: error reading the BOCO @%#x !!\n",
+   __func__, SPI_REG);
+   return 0;
+   }
+
+   return regval & FPGA_DONE ? 1 : 0;
+}
+
+int skip;
+
 int trigger_fpga_config(void)
 {
int ret = 0;
 
+   /* if the FPGA is already configured, we do not want to
+* reconfigure it */
+   skip = 0;
+   if (fpga_done()) {
+   printf("PCIe FPGA config: skipped\n");
+   skip = 1;
+   return 0;
+   }
+
if (check_boco2()) {
/* we have a BOCO2, this has to be triggered here */
 
@@ -111,7 +142,7 @@ int trigger_fpga_config(void)
return ret;
 
/* trigger the config start */
-   ret = boco_clear_bits(SPI_REG, FPGA_PROG);
+   ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
if (ret)
return ret;
 
@@ -123,6 +154,11 @@ int trigger_fpga_config(void)
if (ret)
return ret;
 
+   /* finally, raise INIT_B to remove the config delay */
+   ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
+   if (ret)
+   return ret;
+
} else {
/* we do it the old way, with the gpio pin */
kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
@@ -141,6 +177,9 @@ int wait_for_fpga_config(void)
u8 spictrl;
u32 timeout = 2;
 
+   if (skip)
+   return 0;
+
if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */
return 0;
-- 
1.7.1

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[U-Boot] [PATCH v2 10/14] arm/km: enable external switch configuration for kmnusa

[Holger Brunck]

From: Valentin Longchamp 

The configuration EEPROM should be removed for P1B.

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 board/keymile/km_arm/km_arm.c |   11 +--
 board/keymile/km_arm/managed_switch.c |3 ++-
 board/keymile/km_arm/managed_switch.h |7 +++
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index d9cd4a0..1348186 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -44,6 +44,7 @@
 #include 
 
 #include "../common/common.h"
+#include "managed_switch.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -374,13 +375,11 @@ void reset_phy(void)
if (miiphy_set_current_dev(name))
return;
 
-   /* enable autoneg on port 0 phy */
-   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 0, 0, 0x3300);
+#if defined(CONFIG_KM_NUSA)
+   ext_switch_program(name, CONFIG_KM_MANAGED_SW_ADDR);
+#endif
 
-   /* egress broadcast franes on all macs, with forwarding */
-   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 16, 4, 0x000f);
-   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 20, 4, 0x000f);
-   ext_switch_reg_write(name, CONFIG_KM_MANAGED_SW_ADDR, 21, 4, 0x000f);
+   ext_switch_reset(name, CONFIG_KM_MANAGED_SW_ADDR);
 }
 #endif
 
diff --git a/board/keymile/km_arm/managed_switch.c 
b/board/keymile/km_arm/managed_switch.c
index 3b022cd..a776f1d 100644
--- a/board/keymile/km_arm/managed_switch.c
+++ b/board/keymile/km_arm/managed_switch.c
@@ -32,9 +32,10 @@ struct switch_reg sw_conf[] = {
/* port 0, PIGY4, autoneg */
{ PORT(0), PORT_PHY, NO_SPEED_FOR },
{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+   { PHY(0), PHY_1000_CTRL, NO_ADV },
+   { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
FULL_DUPLEX },
-   { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
/* port 1, unused */
{ PORT(1), PORT_CTRL, PORT_DIS },
{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
diff --git a/board/keymile/km_arm/managed_switch.h 
b/board/keymile/km_arm/managed_switch.h
index c0dcf82..d5b938a 100644
--- a/board/keymile/km_arm/managed_switch.h
+++ b/board/keymile/km_arm/managed_switch.h
@@ -51,6 +51,7 @@
 
 #define PHY_CTRL   0x00
 #define PHY_100_MBPS   0x2000
+#define PHY_1_GBPS 0x0040
 #define AUTONEG_EN 0x1000
 #define AUTONEG_RST0x0200
 #define FULL_DUPLEX0x0100
@@ -62,6 +63,12 @@
 #define SPEC_PWR_DOWN  0x0004
 #define AUTO_MDIX_EN   0x0060
 
+#define PHY_1000_CTRL  0x9
+
+#define NO_ADV 0x
+#define ADV_1000_FDPX  0x0200
+#define ADV_1000_HDPX  0x0100
+
 /* PORT or MAC registers */
 #define PORT(itf)  (itf+0x10)
 
-- 
1.7.1

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[U-Boot] [PATCH v2 01/14] arm/km: add kmnusa board support

[Holger Brunck]

This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.

Some other details:
 - IVM EEPROM is at adress: pca9547:70:9
 - PCI is enabled
 - PIGGY4 is connected via MV88E6352 simple switch. There is no phy
   between the simple switch and the kirkwood.

Signed-off-by: Holger Brunck 
Signed-off-by: Valentin Longchamp 
cc: Prafulla Wadaskar 
---
changes for v2:
  - rename 128M16-1.cfg to kwbimage_128M16_1.cfg

 MAINTAINERS|1 +
 board/keymile/km_arm/km_arm.c  |9 +-
 board/keymile/km_arm/kwbimage_128M16_1.cfg |  296 
 boards.cfg |1 +
 include/configs/km/km_arm.h|   44 -
 include/configs/km_kirkwood.h  |   67 ++-
 6 files changed, 394 insertions(+), 24 deletions(-)
 create mode 100644 board/keymile/km_arm/kwbimage_128M16_1.cfg

diff --git a/MAINTAINERS b/MAINTAINERS
index 0445539..aa11268 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -738,6 +738,7 @@ Sergey Lapin 
 Valentin Longchamp 
 
km_kirkwood ARM926EJS (Kirkwood SoC)
+   kmnusa  ARM926EJS (Kirkwood SoC)
mgcoge3un   ARM926EJS (Kirkwood SoC)
portl2  ARM926EJS (Kirkwood SoC)
 
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index cb3402b..421ee5a 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -134,10 +134,11 @@ int startup_allowed(void)
 }
 #endif
 
-#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
+#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
+   defined(CONFIG_KM_PIGGY4_88E6352))
 /*
- * These two boards have always ethernet present. Its connected to the mv
- * switch.
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
  */
 int ethernet_present(void)
 {
@@ -351,7 +352,7 @@ void reset_phy(void)
/* reset the phy */
miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
-#else
+#elif !defined(CONFIG_KM_PIGGY4_88E6352)
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
 {
diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg 
b/board/keymile/km_arm/kwbimage_128M16_1.cfg
new file mode 100644
index 000..3e1237b
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -0,0 +1,296 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.big...@keymile.com
+# Norbert Mayer, Keymile AG, norbert.ma...@keymile.com
+# Deepak Patel, XENTECH Limited, deepak.pa...@xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+#   MT47H256M8EB-3IT:C
+#   MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM  spi # Boot from SPI flash
+
+DATA 0xFFD1 0x0111 # MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_MOSI (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0:   0, MPPSel8 GPIO[8] CPU_SDA bitbanged
+# bit 7-4:   0, MPPSel9  GPIO[9] CPU_SCL bitbanged
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x1100 # MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 11-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+

[U-Boot] [PATCH v2 00/14] updates for Keymile Marvell boards

[Holger Brunck]

Updated after some comments on the Mailing list.

>From the previous version was removed and send as standalone patch:
[PATCH 03/20] arm/kirkwood: protect the ENV_SPI
see:
http://lists.denx.de/pipermail/u-boot/2012-June/126140.html

And this four were squshed to one:
[PATCH 01/20] arm/km: enable spi claim bus
[PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
[PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release
[PATCH 19/20] arm/km: remove spi toggle command
see:
http://lists.denx.de/pipermail/u-boot/2012-June/126139.html

Additionaly 
[PATCH 17/20] arm/km: fix testpin detection for kmcoge5un
was squashed to kmcoge5un board support, which makes logically
sense.

cc: Holger Brunck 
cc: Valentin Longchamp 
cc: Prafulla Wadaskar 

Holger Brunck (6):
  arm/km: add kmnusa board support
  arm/km: add kmcoge5un board support
  arm/km: convert mgcoge3un target to km_kirkwood
  arm/km: remove portl2.h and use km_kirkwood instead
  arm/km: cleanup km_kirkwood boards
  arm/km: remove calls to kw_gpio_* in board_early_init_f

Thomas Herzmann (1):
  arm/km: add implementation for read_dip_switch

Valentin Longchamp (7):
  arm/km: correct init of 88e6352 switch in the reset_phy function
  arm/km: enable BOCO2 FPGA download support
  arm/km: redefine piggy 4 reg names to avoid conflicts
  arm/km: add support for external switch configuration
  arm/km: enable external switch configuration for kmnusa
  arm/km: skip FPGA config when already configured
  arm/km: support the 2 PCIe fpga resets

 MAINTAINERS|2 +
 board/keymile/common/common.h  |5 +
 board/keymile/km_arm/Makefile  |8 +
 board/keymile/km_arm/fpga_config.c |  256 ++
 board/keymile/km_arm/km_arm.c  |  127 ---
 board/keymile/km_arm/kwbimage_128M16_1.cfg |  296 ++
 board/keymile/km_arm/kwbimage_256M8_1.cfg  |  296 ++
 board/keymile/km_arm/managed_switch.c  |  316 
 board/keymile/km_arm/managed_switch.h  |  106 ++
 boards.cfg |   10 +-
 include/configs/km/km_arm.h|   48 -
 include/configs/km_kirkwood.h  |  154 +--
 include/configs/mgcoge3un.h|   87 
 include/configs/portl2.h   |   85 
 14 files changed, 1565 insertions(+), 231 deletions(-)
 create mode 100644 board/keymile/km_arm/fpga_config.c
 create mode 100644 board/keymile/km_arm/kwbimage_128M16_1.cfg
 create mode 100644 board/keymile/km_arm/kwbimage_256M8_1.cfg
 create mode 100644 board/keymile/km_arm/managed_switch.c
 create mode 100644 board/keymile/km_arm/managed_switch.h
 delete mode 100644 include/configs/mgcoge3un.h
 delete mode 100644 include/configs/portl2.h

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[U-Boot] [PATCH v2 07/14] arm/km: cleanup km_kirkwood boards

[Holger Brunck]

Remove config options from boards.cfg and simply add one switch
per board and differ afterwards in km_kirkwood.h between the features.
More boards are upcoming and therefore it's easier to have this
at one place.

Signed-off-by: Holger Brunck 
Signed-off-by: Valentin Longchamp 
cc: Prafulla Wadaskar 
---
changes for v2:
  - nothing

 boards.cfg|4 ++--
 include/configs/km_kirkwood.h |7 ++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index da52a49..71630ba 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -138,8 +138,8 @@ enbw_cmc arm arm926ejs   
enbw_cmcenbw
 calimain arm arm926ejs   calimain
omicrondavinci
 pogo_e02 arm arm926ejs   -   
cloudengines   kirkwood
 dns325   arm arm926ejs   -   
d-link kirkwood
-km_kirkwood  arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD,KM_DISABLE_PCI
-km_kirkwood_pci  arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD_PCI,KM_FPGA_CONFIG
+km_kirkwood  arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD
+km_kirkwood_pci  arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_KIRKWOOD_PCI
 kmnusa   arm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_NUSA
 mgcoge3unarm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_MGCOGE3UN
 kmcoge5unarm arm926ejs   km_arm  
keymilekirkwoodkm_kirkwood:KM_COGE5UN
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index be0da83..b29e1a6 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -37,15 +37,20 @@
 #ifndef _CONFIG_KM_KIRKWOOD_H
 #define _CONFIG_KM_KIRKWOOD_H
 
+/* KM_KIRKWOOD */
 #if defined(CONFIG_KM_KIRKWOOD)
 #define CONFIG_IDENT_STRING"\nKeymile Kirkwood"
 #define CONFIG_HOSTNAMEkm_kirkwood
-#undef  CONFIG_KIRKWOOD_PCIE_INIT
+#define CONFIG_KM_DISABLE_PCIE
 #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+
+/* KM_KIRKWOOD_PCI */
 #elif defined(CONFIG_KM_KIRKWOOD_PCI)
 #define CONFIG_IDENT_STRING"\nKeymile Kirkwood PCI"
 #define CONFIG_HOSTNAMEkm_kirkwood_pci
 #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_FPGA_CONFIG
+
 /* KM_NUSA */
 #elif defined(CONFIG_KM_NUSA)
 #define KM_IVM_BUS "pca9547:70:9"  /* I2C2 (Mux-Port 1)*/
-- 
1.7.1

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[U-Boot] [PATCH v2 02/14] arm/km: add kmcoge5un board support

[Holger Brunck]

For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch without a
phy inbetween, this needs a new configuration for the mvgbe driver.
The testpin was inverted compared to other km_kirkwood boards, this
is the reason we need the change in post_hotkeys_pressed.

Signed-off-by: Holger Brunck 
Signed-off-by: Valentin Longchamp 
cc: Prafulla Wadaskar 

Signed-off-by: Thomas Herzmann 
Signed-off-by: Holger Brunck 
---
changes for v2:
 - rename KMCOGE5UN to KM_COGE5UN
 - rename 256M8-1.cfg -> kwbimage_256M8_1.cfg
 - squash 17/20 arm/km: fix testpin detection for kmcoge5un into this
   commit because it should come with the board support patch

 MAINTAINERS   |1 +
 board/keymile/km_arm/km_arm.c |4 +
 board/keymile/km_arm/kwbimage_256M8_1.cfg |  296 +
 boards.cfg|1 +
 include/configs/km_kirkwood.h |   16 ++-
 5 files changed, 316 insertions(+), 2 deletions(-)
 create mode 100644 board/keymile/km_arm/kwbimage_256M8_1.cfg

diff --git a/MAINTAINERS b/MAINTAINERS
index aa11268..ef57cd6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -740,6 +740,7 @@ Valentin Longchamp 
km_kirkwood ARM926EJS (Kirkwood SoC)
kmnusa  ARM926EJS (Kirkwood SoC)
mgcoge3un   ARM926EJS (Kirkwood SoC)
+   kmcoge5un   ARM926EJS (Kirkwood SoC)
portl2  ARM926EJS (Kirkwood SoC)
 
 Nishanth Menon 
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 421ee5a..b1e4178 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -457,7 +457,11 @@ int get_scl(void)
 
 int post_hotkeys_pressed(void)
 {
+#if defined(CONFIG_KMCOGE5UN)
+   return kw_gpio_get_value(KM_POST_EN_L);
+#else
return !kw_gpio_get_value(KM_POST_EN_L);
+#endif
 }
 
 ulong post_word_load(void)
diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg 
b/board/keymile/km_arm/kwbimage_256M8_1.cfg
new file mode 100644
index 000..3e1237b
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -0,0 +1,296 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.big...@keymile.com
+# Norbert Mayer, Keymile AG, norbert.ma...@keymile.com
+# Deepak Patel, XENTECH Limited, deepak.pa...@xentech.co.uk
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+#   MT47H256M8EB-3IT:C
+#   MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM  spi # Boot from SPI flash
+
+DATA 0xFFD1 0x0111 # MPP Control 0 Register
+# bit 3-0:   2, MPPSel0  SPI_CSn  (1=NF_IO[2])
+# bit 7-4:   2, MPPSel1  SPI_MOSI (1=NF_IO[3])
+# bit 12-8:  2, MPPSel2  SPI_SCK  (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3  SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4  NF_IO[6]
+# bit 23-20: 1, MPPSel5  NF_IO[7]
+# bit 27-24: 1, MPPSel6  SYSRST_O
+# bit 31-28: 0, MPPSel7  GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0:   0, MPPSel8 GPIO[8] CPU_SDA bitbanged
+# bit 7-4:   0, MPPSel9  GPIO[9] CPU_SCL bitbanged
+# bit 12-8:  3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x1100 # MPP Control 2 Register
+# bit 3-0:   0, MPPSel16 GPIO[16]
+# bit 7-4:   0, MPPSel17 not connected
+# bit 11-8:  1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+# bit 2-0:   3, Reserved
+# bit 5

Re: [U-Boot] [PATCH 2/7] common lcd: simplify #ifdefs

[Nikita Kiryanov]

On 06/08/2012 03:52 PM, Anatolij Gustschin wrote:
> Hi,
>
> On Thu, 24 May 2012 14:42:39 +0300
> Igor Grinberg  wrote:
>
>> From: Nikita Kiryanov
>>
>> Simplify #ifdefs by slightly changing the order of operations
>>
>> Signed-off-by: Nikita Kiryanov
>> Signed-off-by: Igor Grinberg
>> ---
>>   common/lcd.c |   20 
>>   1 files changed, 8 insertions(+), 12 deletions(-)
>>
>> diff --git a/common/lcd.c b/common/lcd.c
>> index 506a138..3b2f25f 100644
>> --- a/common/lcd.c
>> +++ b/common/lcd.c
>> @@ -525,20 +525,18 @@ void bitmap_plot(int x, int y)
>>fb   = (uchar *)(lcd_base + y * lcd_line_length + x);
>>
>>if (NBITS(panel_info.vl_bpix)<  12) {
>> -  /* Leave room for default color map */
>> +  /* Leave room for default color map
>> +   * default case: generic system with no cmap (most likely 
16bpp)
>> +   * We set cmap to the source palette, so no change is done.
>> +   * This avoids even more ifdefs in the next stanza
>> +   */
>> +  cmap = bmp_logo_palette;
>>   #if defined(CONFIG_CPU_PXA)
>>cmap = (ushort *) fbi->palette;
>>   #elif defined(CONFIG_MPC823)
>>cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET * 
sizeof(ushort)]);
>>   #elif defined(CONFIG_ATMEL_LCD)
>>cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
>> -#else
>> -  /*
>> -   * default case: generic system with no cmap (most likely 
16bpp)
>> -   * We set cmap to the source palette, so no change is done.
>> -   * This avoids even more ifdef in the next stanza
>> -   */
>> -  cmap = bmp_logo_palette;
>>   #endif
>>
>>WATCHDOG_RESET();
>> @@ -680,14 +678,12 @@ int lcd_display_bitmap(ulong bmp_image, int x, 
int y)

>>for (i = 0; i<  colors; ++i) {
>>bmp_color_table_entry_t cte = bmp->color_table[i];
>>   #if !defined(CONFIG_ATMEL_LCD)
>> -  ushort colreg =
>> +  *cmap =
>>( ((cte.red)<<  8)&  0xf800) |
>>( ((cte.green)<<  3)&  0x07e0) |
>>( ((cte.blue)>>  3)&  0x001f) ;
>>   #ifdef CONFIG_SYS_INVERT_COLORS
>> -  *cmap = 0x - colreg;
>> -#else
>> -  *cmap = colreg;
>> +  *cmap = 0x - *cmap;
>>   #endif
>>   #if defined(CONFIG_MPC823)
>>cmap--;
>
> Sorry, but I do not like this change. We should not try to simplify it
> this way. Better would be to just reduce all this color map setting code
> to something like:
>
>  for (i = 0; i<  ARRAY_SIZE(bmp_logo_palette); ++i) {
>  bmp_color_table_entry_t cte = bmp->color_table[i];
>  lcd_setcolreg(i, cte.red, cte.green, cte.blue);
>  }
>
> and fix lcd_setcolreg() functions of the drivers if/where needed.
>
> Thanks,
>
> Anatolij

This does sound like the way to go, but having looked at the different
versions of lcd_setcolreg I am unsure of how to consolidate the code in
lcd_display_bitmap (and bitmap_plot in patch 3) with the
implementations I see in the drivers.

For one, they shift the color values in a different way than the code
in common/lcd, and I'm not sure who I should listen to, what's in the
drivers or common/lcd...
Also, I see that lcd_setcolreg is used in lcd_clear, where it sets
console colors. This raises the question can/should the treatment of
bmp color map values be similar to that of console color values?

I'd appreciate some guidance on these issues.

Thanks,
Nikita
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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Marek Vasut]

Dear Liu Hui-R64343,

> Hi, Marek,
> 
> >-Original Message-
> >From: Marek Vasut [mailto:ma...@denx.de]
> >Sent: Wednesday, June 13, 2012 8:25 PM
> >To: u-boot@lists.denx.de
> >Cc: Liu Hui-R64343; Dirk Behme
> >Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
> >imximage.cfg
> >
> >Dear Liu Hui-R64343,
> >
> >[...]
> >
> >> >> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> >> >> >> bits
> >> >> >> 4 and 5 read-only and the value is always set as zero.
> >> >> >> So write '0' to these bits instead of writing '1'.
> >> >> >
> >> >> >Jason, Fabio: What do you think? You should be the datasheet
> >> >> >'masters' ;)
> >> >> 
> >> >> Yes, according to the RM,
> >> >> 5
> >> >> Reserved
> >> >> This read-only field is reserved and always has the value 0.
> >> >> 4
> >> >> Reserved
> >> >> This read-only field is reserved and always has the value 0.
> >> >> 
> >> >> So, write 1 should have no effect.
> >> >
> >> >I really dislike how "write 1 should have no effect" sounds. Can you
> >> >please check with HW people?
> >> 
> >> Since this is read-only bit, if you write 1 to it, it will have no
> >> effect.
> >
> >For how long do you work with hardware? Did it never occur to you that
> >when you wrote 1 to an "reserved" bit, it either did something you didn't
> >expect or you had to rework it later because the new CPU has that bit for
> >something else?
> >
> >> Yes, to avoid the confusion, for example to do the read-back check, I
> >> agree with not writing '1' to the read-only bit.
> >
> >Please, ask the hardware people about this.
> 
> Yes, I will and back to you.

Thanks!

btw. sorry, I didn't meant to offend you.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Liu Hui-R64343]

Hi, Marek,

>-Original Message-
>From: Marek Vasut [mailto:ma...@denx.de]
>Sent: Wednesday, June 13, 2012 8:25 PM
>To: u-boot@lists.denx.de
>Cc: Liu Hui-R64343; Dirk Behme
>Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
>imximage.cfg
>
>Dear Liu Hui-R64343,
>
>[...]
>
>> >> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
>> >> >> bits
>> >> >> 4 and 5 read-only and the value is always set as zero.
>> >> >> So write '0' to these bits instead of writing '1'.
>> >> >
>> >> >Jason, Fabio: What do you think? You should be the datasheet
>> >> >'masters' ;)
>> >>
>> >> Yes, according to the RM,
>> >> 5
>> >> Reserved
>> >> This read-only field is reserved and always has the value 0.
>> >> 4
>> >> Reserved
>> >> This read-only field is reserved and always has the value 0.
>> >>
>> >> So, write 1 should have no effect.
>> >
>> >I really dislike how "write 1 should have no effect" sounds. Can you
>> >please check with HW people?
>>
>> Since this is read-only bit, if you write 1 to it, it will have no effect.
>
>For how long do you work with hardware? Did it never occur to you that
>when you wrote 1 to an "reserved" bit, it either did something you didn't
>expect or you had to rework it later because the new CPU has that bit for
>something else?
>
>> Yes, to avoid the confusion, for example to do the read-back check, I
>> agree with not writing '1' to the read-only bit.
>
>Please, ask the hardware people about this.

Yes, I will and back to you.

>
>> >[..]
>> >
>> >Best regards,
>> >Marek Vasut
>
>Best regards,
>Marek Vasut


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[U-Boot] [PATCH] arm/kirkwood: protect the ENV_SPI #defines

[Holger Brunck]

From: Valentin Longchamp 

So that they can be redefined by some boards specific values.

Signed-off-by: Valentin Longchamp 
Signed-off-by: Holger Brunck 
cc: Prafulla Wadaskar 
---
Hi Prafulla,
here is the only common kirkwood related change from our patch serie,
as discussed on the ml.

 arch/arm/include/asm/arch-kirkwood/config.h |   12 +---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-kirkwood/config.h 
b/arch/arm/include/asm/arch-kirkwood/config.h
index 91164eb..a9499b7 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -82,9 +82,15 @@
 #ifdef CONFIG_CMD_SF
 #define CONFIG_HARD_SPI1
 #define CONFIG_KIRKWOOD_SPI1
-#define CONFIG_ENV_SPI_BUS 0
-#define CONFIG_ENV_SPI_CS  0
-#define CONFIG_ENV_SPI_MAX_HZ  5000/*50Mhz */
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS 0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ 5000
+#endif
 #endif
 
 /*
-- 
1.7.1

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[U-Boot] [PATCH] arm/km: use spi claim bus to switch between SPI and NAND

[Holger Brunck]

From: Valentin Longchamp 

We overwrite these weak functions from the kirkwood spi code to
use our own method to be able to switch between the SPI NOR and
the NAND flash. This is needed e.g. to update the u-boot. The former
command do_spi_toggle can therefore be removed. And the usage of
this command is removed from the u-boot update command in the
u-boot environment.

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
---
Hi Prafulla,
this is now a standalone patch. This patch was already posted, but is now a 
rebase
of the following three patches from 
http://lists.denx.de/pipermail/u-boot/2012-June/125864.html
[PATCH 01/20] arm/km: enable spi claim bus
[PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
[PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release
[PATCH 19/20] arm/km: remove spi toggle command
This makes the patch much more logical and easier to understand. 

Updates for the remaining patch serie will follow.
Regards

 board/keymile/km_arm/km_arm.c |   44 ++--
 include/configs/km/km_arm.h   |9 +--
 2 files changed, 13 insertions(+), 40 deletions(-)

diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index ed12b5c..cb3402b 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -284,48 +285,17 @@ int board_init(void)
return 0;
 }
 
-#if defined(CONFIG_CMD_SF)
-int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int board_spi_claim_bus(struct spi_slave *slave)
 {
-   u32 tmp;
-   if (argc < 2)
-   return cmd_usage(cmdtp);
-
-   if ((strcmp(argv[1], "off") == 0)) {
-   printf("SPI FLASH disabled, NAND enabled\n");
-   /* Multi-Purpose Pins Functionality configuration */
-   kwmpp_config[0] = MPP0_NF_IO2;
-   kwmpp_config[1] = MPP1_NF_IO3;
-   kwmpp_config[2] = MPP2_NF_IO4;
-   kwmpp_config[3] = MPP3_NF_IO5;
-
-   kirkwood_mpp_conf(kwmpp_config, NULL);
-   tmp = readl(KW_GPIO0_BASE);
-   writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
-   } else if ((strcmp(argv[1], "on") == 0)) {
-   printf("SPI FLASH enabled, NAND disabled\n");
-   /* Multi-Purpose Pins Functionality configuration */
-   kwmpp_config[0] = MPP0_SPI_SCn;
-   kwmpp_config[1] = MPP1_SPI_MOSI;
-   kwmpp_config[2] = MPP2_SPI_SCK;
-   kwmpp_config[3] = MPP3_SPI_MISO;
-
-   kirkwood_mpp_conf(kwmpp_config, NULL);
-   tmp = readl(KW_GPIO0_BASE);
-   writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
-   } else {
-   return cmd_usage(cmdtp);
-   }
+   kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
 
return 0;
 }
 
-U_BOOT_CMD(
-   spitoggle,  2,  0,  do_spi_toggle,
-   "En-/disable SPI FLASH access",
-   " - Enable (on) or disable (off) SPI FLASH access\n"
-   );
-#endif
+void board_spi_release_bus(struct spi_slave *slave)
+{
+   kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+}
 
 int dram_init(void)
 {
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
index eb60d29..4626e65 100644
--- a/include/configs/km/km_arm.h
+++ b/include/configs/km/km_arm.h
@@ -227,7 +227,11 @@ int get_scl(void);
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 
+/* SPI bus claim MPP configuration */
+#define CONFIG_SYS_KW_SPI_MPP  0x0
+
 #define FLASH_GPIO_PIN 0x0001
+#define KM_FLASH_GPIO_PIN  16
 
 #define MTDIDS_DEFAULT "nand0=orion_nand"
 /* test-only: partitioning needs some tuning, this is just for tests */
@@ -237,9 +241,8 @@ int get_scl(void);
 
 #defineCONFIG_KM_UPDATE_UBOOT  
\
"update="   \
-   "spi on;sf probe 0;sf erase 0 +${filesize};"\
-   "sf write ${load_addr_r} 0 ${filesize};"\
-   "spi off\0"
+   "sf probe 0;sf erase 0 +${filesize};"   \
+   "sf write ${load_addr_r} 0 ${filesize};\0"
 
 /*
  * Default environment variables
-- 
1.7.1

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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Marek Vasut]

Dear Vikram Narayanan,

> If in case this is valid according to the latest datasheet, ignore this
> patch.
> 
> --
> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has
> bits 4 and 5 read-only and the value is always set as zero.
> So write '0' to these bits instead of writing '1'.

I'm acking this as writing 0 to read-only bits is the only rightous thing to 
do. 
btw. how did you find this? Good catch, praise on you :-)

Acked-by: Marek Vasut 

> Signed-off-by: Vikram Narayanan 
> Cc: Jason Liu 
> Cc: Dirk Behme 
> ---
>  board/freescale/mx6qarm2/imximage.cfg  |2 +-
>  board/freescale/mx6qsabrelite/imximage.cfg |2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/freescale/mx6qarm2/imximage.cfg
> b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644
> --- a/board/freescale/mx6qarm2/imximage.cfg
> +++ b/board/freescale/mx6qarm2/imximage.cfg
> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0FC3
>  DATA 4 0x020c4080 0x03FF
> 
>  # enable AXI cache for VDOA/VPU/IPU
> -DATA 4 0x020e0010 0xF0FF
> +DATA 4 0x020e0010 0xF0CF
>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>  DATA 4 0x020e0018 0x007F007F
>  DATA 4 0x020e001c 0x007F007F
> diff --git a/board/freescale/mx6qsabrelite/imximage.cfg
> b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644
> --- a/board/freescale/mx6qsabrelite/imximage.cfg
> +++ b/board/freescale/mx6qsabrelite/imximage.cfg
> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0FC3
>  DATA 4 0x020c4080 0x03FF
> 
>  # enable AXI cache for VDOA/VPU/IPU
> -DATA 4 0x020e0010 0xF0FF
> +DATA 4 0x020e0010 0xF0CF
>  # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
>  DATA 4 0x020e0018 0x007F007F
>  DATA 4 0x020e001c 0x007F007F

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Marek Vasut]

Dear Liu Hui-R64343,

[...]

> >> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits
> >> >> 4 and 5 read-only and the value is always set as zero.
> >> >> So write '0' to these bits instead of writing '1'.
> >> >
> >> >Jason, Fabio: What do you think? You should be the datasheet
> >> >'masters' ;)
> >> 
> >> Yes, according to the RM,
> >> 5
> >> Reserved
> >> This read-only field is reserved and always has the value 0.
> >> 4
> >> Reserved
> >> This read-only field is reserved and always has the value 0.
> >> 
> >> So, write 1 should have no effect.
> >
> >I really dislike how "write 1 should have no effect" sounds. Can you
> >please check with HW people?
> 
> Since this is read-only bit, if you write 1 to it, it will have no effect.

For how long do you work with hardware? Did it never occur to you that when you 
wrote 1 to an "reserved" bit, it either did something you didn't expect or you 
had to rework it later because the new CPU has that bit for something else?

> Yes, to avoid the confusion, for example to do the read-back check, I agree
> with not writing '1' to the read-only bit.

Please, ask the hardware people about this.

> >[..]
> >
> >Best regards,
> >Marek Vasut

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 12/17] lcd: Add support for flushing LCD fb from dcache after update

[Simon Glass]

Hi Mike,

On Sat, Jan 14, 2012 at 6:16 PM, Mike Frysinger  wrote:

> On Saturday 14 January 2012 20:57:25 Simon Glass wrote:
> > On Sat, Jan 14, 2012 at 5:42 PM, Mike Frysinger wrote:
> > > On Saturday 14 January 2012 19:47:24 Simon Glass wrote:
> > >> --- a/common/cmd_echo.c
> > >> +++ b/common/cmd_echo.c
> > >> @@ -44,8 +44,9 @@ int do_echo(cmd_tbl_t *cmdtp, int flag, int argc,
> char
> > >> * const argv[]) }
> > >>   }
> > >>
> > >> + /* Use puts() so that the LCD sees it as a new line */
> > >>   if (putnl)
> > >> - putc('\n');
> > >> + puts("\n");
> > >>
> > >>   return 0;
> > >>  }
> > >
> > > this sounds like a hack for a broken LCD core and so the fix should be
> > > somewhere in there
> >
> > Well it's actually that I don't want to flush after every character
> > (it slows things down a lot)
>
> right, but ...
>
> > so puts is a good place to look
>
> most puts() that i've seen are simple loops that call putc()
>
> > I suppose we could flush after every newline we see in lcd_putc().
>
> that would be the right way to go i think
>

Yes indeed, will fix.


> -mike
>

Regards,
Simon
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Re: [U-Boot] [PATCH 11/17] lcd: Add CONFIG_ALIGN_LCD_TO_SECTION to align lcd for MMU

[Simon Glass]

Hi Mike,

On Sat, Jan 14, 2012 at 5:38 PM, Mike Frysinger  wrote:

> On Saturday 14 January 2012 19:47:23 Simon Glass wrote:
> > We want to make the display section-aligned on ARM so that we can easily
> > turn off data caching for this.
> >
> > Is this useful for other architectures? We could perhaps generalise it by
> > adding the ability to specify the alignment size, but at least for ARM
> > it is easier to have it be an architecture feature set by the MMU's
> > system.h header.
>
> seems like a generally useful thing, but the exact alignment is a bit
> hackish.
> so perhaps the CONFIG knob should instead be the size you want to align
> things
> to ?
>

OK I will do that.


> -mike
>

Regards,
Simon
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Re: [U-Boot] [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching

[Holger Brunck]

On 06/12/2012 12:29 PM, Holger Brunck wrote:
> On 06/12/2012 11:32 AM, Prafulla Wadaskar wrote:
>>
>>
>>> -Original Message-
>>> From: Holger Brunck [mailto:holger.bru...@keymile.com]
>>> Sent: 12 June 2012 14:08
>>> To: Prafulla Wadaskar
>>> Cc: Valentin Longchamp; prafu...@mavell.com; u-boot@lists.denx.de;
>>> Gerlando Falauto
>>> Subject: Re: [PATCH 02/20] arm/km: use correct kw_gpio function for
>>> NAND/SPI switching
>>>
>>> On 06/12/2012 06:39 AM, Prafulla Wadaskar wrote:


> -Original Message-
> From: Valentin Longchamp [mailto:valentin.longch...@keymile.com]
> Sent: 07 June 2012 15:37
> To: prafu...@mavell.com
> Cc: Valentin Longchamp; holger.bru...@keymile.com; u-
> b...@lists.denx.de; Gerlando Falauto; Prafulla Wadaskar
> Subject: [PATCH 02/20] arm/km: use correct kw_gpio function for
> NAND/SPI switching
>
> This used to be done with registers direct access, which is not
>>> clear
> and optimal.
>
> Signed-off-by: Valentin Longchamp 
> Signed-off-by: Holger Brunck 
> cc: Gerlando Falauto 
> cc: Prafulla Wadaskar 
> ---
>  board/keymile/km_arm/km_arm.c |   53 +
>>> ---
> 
>  include/configs/km/km_arm.h   |1 +
>  2 files changed, 29 insertions(+), 25 deletions(-)
>
> diff --git a/board/keymile/km_arm/km_arm.c
> b/board/keymile/km_arm/km_arm.c
> index ed12b5c..e4ae1fb 100644
> --- a/board/keymile/km_arm/km_arm.c
> +++ b/board/keymile/km_arm/km_arm.c
> @@ -247,15 +247,12 @@ int board_early_init_f(void)
>   kirkwood_mpp_conf(kwmpp_config, NULL);
>
>   /*
> -  * The FLASH_GPIO_PIN switches between using a
> +  * The KM_FLASH_GPIO_PIN switches between using a
>* NAND or a SPI FLASH. Set this pin on start
>* to NAND mode.
>*/
> - tmp = readl(KW_GPIO0_BASE);
> - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
> - tmp = readl(KW_GPIO0_BASE + 4);
> - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
> -
> + kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
> + kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
>  #if defined(CONFIG_SOFT_I2C)
>   /* init the GPIO for I2C Bitbang driver */
>   kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
> @@ -284,35 +281,41 @@ int board_init(void)
>   return 0;
>  }
>
> +int km_hw_spi_bus_claim(int on)
> +{
> + int gpio_value = !on;
> +
> + if (on) {
> + kwmpp_config[0] = MPP0_SPI_SCn;
> + kwmpp_config[1] = MPP1_SPI_MOSI;
> + kwmpp_config[2] = MPP2_SPI_SCK;
> + kwmpp_config[3] = MPP3_SPI_MISO;
> + } else {
> + kwmpp_config[0] = MPP0_NF_IO2;
> + kwmpp_config[1] = MPP1_NF_IO3;
> + kwmpp_config[2] = MPP2_NF_IO4;
> + kwmpp_config[3] = MPP3_NF_IO5;
> + }

 NACK...

>>>
>>> Could you please be a bit more verbose. Why do you NACK this? This
>>> code is only
>>> related to our boards...
>>
>> Dear Holger
>> We have already patches for Kirkwood-spi in place that address this.
>> So we have to use this framework.
>>
>> Ref: http://lists.denx.de/pipermail/u-boot/2012-June/125574.html
>>
> 
> ok I see what you mean. We make use of it later on:
> [PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release
> I'll squash this one together with 02/20 then it is more clear.
> 

ok  I'll send an update of the SPI feature update soon as a standalone patch.
I'll squash

[PATCH 01/20] arm/km: enable spi claim bus
[PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching
[PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release
[PATCH 19/20] arm/km: remove spi toggle command

into it and then it is much more clear what the patch does.

Updates with your inputs of the remaining patches will also follow.

Regards
Holger
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Re: [U-Boot] [PATCH 04/17] tegra: Add display support to funcmux

[Simon Glass]

Hi Mike,

On Sat, Jan 14, 2012 at 5:36 PM, Mike Frysinger  wrote:

> On Saturday 14 January 2012 19:47:16 Simon Glass wrote:
> > --- a/arch/arm/cpu/armv7/tegra2/funcmux.c
> > +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c
> >
> > +struct pingroup_config disp1_default[] = {
>
> const ?  although it looks like we need to fix pinmux_config_table() first
> ...
> -mike
>

done

(With everything except NAND on Tegra in I am trying to get back to this
now.)

Regards,
Simon
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Re: [U-Boot] [PATCH 1/3] imx25: Move MXC_GPIO_PORT_TO_NUM to imx-regs.h

[Fabio Estevam]

On Mon, Jun 11, 2012 at 12:02 PM, Vikram Narayanan  wrote:

>> Also, this macro is useful not only for mx25, and it would be nice to
>> let it avaible for the other i.MX SoCs as well.
>
>
> Agree. But I guess u-boot doesn't have a common folder where this can be put
> up something like plat-mxc. So, I should think where to place this macro to
> avoid duplicates in many header files. Any pointers?

Yes, a common folder would help indeed.

Copying Stefano, so that he could provide us some suggestion on this.

Thanks,

Fabio Estevam
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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Liu Hui-R64343]

Hi, Marek,

>-Original Message-
>From: Marek Vasut [mailto:ma...@denx.de]
>Sent: Wednesday, June 13, 2012 7:18 PM
>To: u-boot@lists.denx.de
>Cc: Liu Hui-R64343; Dirk Behme; Fabio Estevam
>Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
>imximage.cfg
>
>Dear Liu Hui-R64343,
>
>> >-Original Message-
>> >From: Dirk Behme [mailto:dirk.be...@de.bosch.com]
>> >Sent: Tuesday, June 12, 2012 11:05 PM
>> >To: Fabio Estevam; Liu Hui-R64343
>> >Cc: Vikram Narayanan; u-boot@lists.denx.de
>> >Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
>> >imximage.cfg
>> >
>> >On 12.06.2012 16:50, Vikram Narayanan wrote:
>> >> If in case this is valid according to the latest datasheet, ignore
>> >> this patch.
>> >>
>> >> --
>> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits
>> >> 4 and 5 read-only and the value is always set as zero.
>> >> So write '0' to these bits instead of writing '1'.
>> >
>> >Jason, Fabio: What do you think? You should be the datasheet
>> >'masters' ;)
>>
>> Yes, according to the RM,
>> 5
>> Reserved
>> This read-only field is reserved and always has the value 0.
>> 4
>> Reserved
>> This read-only field is reserved and always has the value 0.
>>
>> So, write 1 should have no effect.
>
>I really dislike how "write 1 should have no effect" sounds. Can you please
>check with HW people?

Since this is read-only bit, if you write 1 to it, it will have no effect.

Yes, to avoid the confusion, for example to do the read-back check, I agree
with not writing '1' to the read-only bit. 

>
>[..]
>
>Best regards,
>Marek Vasut


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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Fabio Estevam]

On Wed, Jun 13, 2012 at 8:18 AM, Marek Vasut  wrote:

>
> I really dislike how "write 1 should have no effect" sounds. Can you please
> check with HW people?

I agree.

Jason, please check this with the design team.

Vikram's patch look correct.

Regards,

Fabio Estevam
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Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg

[Marek Vasut]

Dear Liu Hui-R64343,

> >-Original Message-
> >From: Dirk Behme [mailto:dirk.be...@de.bosch.com]
> >Sent: Tuesday, June 12, 2012 11:05 PM
> >To: Fabio Estevam; Liu Hui-R64343
> >Cc: Vikram Narayanan; u-boot@lists.denx.de
> >Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in
> >imximage.cfg
> >
> >On 12.06.2012 16:50, Vikram Narayanan wrote:
> >> If in case this is valid according to the latest datasheet, ignore this
> >> patch.
> >> 
> >> --
> >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4
> >> and 5 read-only and the value is always set as zero.
> >> So write '0' to these bits instead of writing '1'.
> >
> >Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
> 
> Yes, according to the RM,
> 5
> Reserved
> This read-only field is reserved and always has the value 0.
> 4
> Reserved
> This read-only field is reserved and always has the value 0.
> 
> So, write 1 should have no effect.

I really dislike how "write 1 should have no effect" sounds. Can you please 
check with HW people?

[..]

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2 0/7] feature additions and fixes for da850/omap-l138

[Sughosh Ganu]

On Thu Jun 07, 2012 at 03:25:27PM +0530, Prabhakar Lad wrote:
> From: Lad, Prabhakar 
> 
> This series adds MMC/SD, NAND and NOR SPL support
> for Logic PD's DA850/OMAP-L138 EVM. This series
> also fixes some issues found on the EVM during
> testing. The patches are sent in a series as these
> patches need to be applied in the order they are sent.
> 
> Changes for v2:
> 1: Fixed comments from Tom to remove unused macro
>and add comment.
> 2: Fixed comments from Christian to move GPIO pins
>to board file and add a check to perform initializations
>only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined.
> 
> Lad, Prabhakar (5):
>   da850/omap-l138: Add MMC support for DA850/OMAP-L138
>   da850/omap-l138: Add support to read u-boot image from MMC/SD
>   da850/omap-l138: Fix NAND flash timings
>   da850/omap-l138: Add support for NAND SPL
>   da850/omap-l138: add support for direct NOR boot mode
> 
> Rajashekhara, Sudhakar (2):
>   da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM
>   da850/omap-l138: Make MMC and NOR support mutually exclusive
> 
>  arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c   |   11 +++
>  arch/arm/cpu/arm926ejs/davinci/spl.c|   27 +--
>  arch/arm/include/asm/arch-davinci/hardware.h|1 +
>  arch/arm/include/asm/arch-davinci/pinmux_defs.h |3 +
>  board/davinci/da8xxevm/da850evm.c   |   54 +--
>  boards.cfg  |1 +
>  drivers/mmc/Makefile|4 +
>  drivers/mmc/spl_mmc_load.c  |   62 
>  include/configs/da850evm.h  |   86 
> +--
>  include/mmc.h   |2 +
>  10 files changed, 233 insertions(+), 18 deletions(-)
>  create mode 100644 drivers/mmc/spl_mmc_load.c

 Tested on hawkboard. Boots up fine.

 Tested-by: Sughosh Ganu 

-sughosh
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Re: [U-Boot] [PATCH 6/8] mx28evk: fix board config include guardian macro name

[Stefano Babic]

On 13/05/2012 01:40, Otavio Salvador wrote:
> Signed-off-by: Otavio Salvador 
> ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic
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Re: [U-Boot] [PATCH 5/8] m28evk: fix board config include guardian macro name

[Stefano Babic]

On 13/05/2012 01:40, Otavio Salvador wrote:
> Signed-off-by: Otavio Salvador 
> ---
>  include/configs/m28evk.h |6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
> index ebf7e39..c1ae996 100644

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 2/3] m28evk: drop duplicated definition of CONFIG_OF_LIBFDT

[Stefano Babic]

On 15/05/2012 22:59, Otavio Salvador wrote:
> Signed-off-by: Otavio Salvador 
> Cc: Marek Vasut 
> Cc: Stefano Babic 
> Cc: Wolfgang Denk 
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 3/8] mx28evk: ensure command definition is in alphabetic order

[Stefano Babic]

On 13/05/2012 01:40, Otavio Salvador wrote:
> Signed-off-by: Otavio Salvador 
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 1/8] MX28: Fix a typo in mx28_reg_8 macro

[Stefano Babic]

On 11/05/2012 17:37, Otavio Salvador wrote:
> The macro mistakenly referred to 32bit struct instead of 8bit one.
> 
> Signed-off-by: Otavio Salvador 
> Cc: Fabio Estevam 
> Cc: Marek Vasut 
> ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

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Re: [U-Boot] [PATCH 1/8] m28evk: use same notation to alloc the 128kB stack

[Stefano Babic]

On 13/05/2012 01:40, Otavio Salvador wrote:
> Signed-off-by: Otavio Salvador 
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH v2] tx25: Use generic gpio_* calls

[Stefano Babic]

On 12/06/2012 18:37, Vikram Narayanan wrote:
> Changes from v1:
> Used appropriate gpio_* lib calls.
> 
> ---
> Instead of manipulating gpio registers directly, use the calls
> from the gpio library.

Changelog must go after the "---" line and commit message before. They
are swapped. Apart of that..

> 
> Signed-off-by: Vikram Narayanan 
> Cc: Fabio Estevam 
> Cc: John Rigby 
> Cc: Stefano Babic 
> ---
>  board/karo/tx25/tx25.c |   25 +
>  1 files changed, 9 insertions(+), 16 deletions(-)
> 
> diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c
> index 2a29943..ff2de38 100644
> --- a/board/karo/tx25/tx25.c
> +++ b/board/karo/tx25/tx25.c
> @@ -34,14 +34,13 @@
>  DECLARE_GLOBAL_DATA_PTR;
>  
>  #ifdef CONFIG_FEC_MXC
> +#define GPIO_FEC_RESET_B MXC_GPIO_PORT_TO_NUM(4, 7)
> +#define GPIO_FEC_ENABLE_BMXC_GPIO_PORT_TO_NUM(4, 9)
>  void tx25_fec_init(void)
>  {
>   struct iomuxc_mux_ctl *muxctl;
>   struct iomuxc_pad_ctl *padctl;
> - u32 val;
>   u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
> - struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
> - struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
>   u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
>  
>   debug("tx25_fec_init\n");
> @@ -66,18 +65,15 @@ void tx25_fec_init(void)
>   writel(0x0, &padctl->pad_d11);
>  
>   /* drop PHY power and assert reset (low) */
> - val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9));
> - writel(val, &gpio4->gpio_dr);
> - val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9);
> - writel(val, &gpio4->gpio_dir);
> + gpio_direction_output(GPIO_FEC_RESET_B, 0);
> + gpio_direction_output(GPIO_FEC_ENABLE_B, 0);
>  
>   mdelay(5);
>  
>   debug("resetting phy\n");
>  
>   /* turn on PHY power leaving reset asserted */
> - val = readl(&gpio4->gpio_dr) | 1 << 9;
> - writel(val, &gpio4->gpio_dr);
> + gpio_direction_output(GPIO_FEC_ENABLE_B, 1);
>  
>   mdelay(10);
>  
> @@ -107,19 +103,16 @@ void tx25_fec_init(void)
>   /*
>* set each to 1 and make each an output
>*/
> - val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12);
> - writel(val, &gpio3->gpio_dr);
> - val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12);
> - writel(val, &gpio3->gpio_dir);
> + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 10), 1);
> + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 11), 1);
> + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 12), 1);
>  
>   mdelay(22); /* this value came from RedBoot */
>  
>   /*
>* deassert PHY reset
>*/
> - val = readl(&gpio4->gpio_dr) | 1 << 7;
> - writel(val, &gpio4->gpio_dr);
> - writel(val, &gpio4->gpio_dr);
> + gpio_set_value(GPIO_FEC_RESET_B, 1);
>  
>   mdelay(5);
>  

Acked-by: Stefano Babic 

Best regards,
Stefano Babic

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