[U-Boot] [PATCH 7/8] net: zynq_gem: Calculate clock dividers dynamically
From: Soren Brinkmann soren.brinkm...@xilinx.com
Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/slcr.c | 13 -
arch/arm/include/asm/arch-zynq/sys_proto.h | 2 +-
drivers/net/zynq_gem.c | 17 +++--
3 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 6710d92..d7c1882 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -8,6 +8,7 @@
#include asm/io.h
#include malloc.h
#include asm/arch/hardware.h
+#include asm/arch/clk.h
#define SLCR_LOCK_MAGIC0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
@@ -50,8 +51,10 @@ void zynq_slcr_cpu_reset(void)
}
/* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk)
+void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
+ int ret;
+
zynq_slcr_unlock();
if (gem_id 1) {
@@ -59,14 +62,14 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk)
goto out;
}
+ ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
+ if (ret)
+ goto out;
+
if (gem_id) {
- /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
- writel(clk, slcr_base-gem1_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
writel(1, slcr_base-gem1_rclk_ctrl);
} else {
- /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
- writel(clk, slcr_base-gem0_clk_ctrl);
/* Configure GEM_RCLK_CTRL */
writel(1, slcr_base-gem0_rclk_ctrl);
}
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h
b/arch/arm/include/asm/arch-zynq/sys_proto.h
index a485d79..0a2ba05 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -10,7 +10,7 @@
extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
-extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 53b7c6f..f4c5134 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -90,6 +90,11 @@
#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x0800
#define ZYNQ_GEM_TXBUF_UNDERRUN0x1000
+/* Clock frequencies for different speeds */
+#define ZYNQ_GEM_FREQUENCY_10 250UL
+#define ZYNQ_GEM_FREQUENCY_100 2500UL
+#define ZYNQ_GEM_FREQUENCY_100012500UL
+
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* Network Control reg */
@@ -270,7 +275,8 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
{
- u32 i, clk = 0;
+ u32 i;
+ unsigned long clk_rate = 0;
struct phy_device *phydev;
const u32 stat_size = (sizeof(struct zynq_gem_regs) -
offsetof(struct zynq_gem_regs, stat)) / 4;
@@ -343,23 +349,22 @@ static int zynq_gem_init(struct eth_device *dev, bd_t *
bis)
case SPEED_1000:
writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
regs-nwcfg);
- clk = (1 20) | (8 8) | (0 4) | (1 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
clrsetbits_le32(regs-nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
- clk = (5 20) | (8 8) | (0 4) | (1 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
case SPEED_10:
- /* FIXME untested */
- clk = (5 20) | (8 8) | (0 4) | (1 0);
+ clk_rate = ZYNQ_GEM_FREQUENCY_10;
break;
}
/* Change the rclk and clk only not using EMIO interface */
if (!priv-emio)
zynq_slcr_gem_clk_setup(dev-iobase !=
- ZYNQ_GEM_BASEADDR0, clk);
+ ZYNQ_GEM_BASEADDR0, clk_rate);
setbits_le32(regs-nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
--
1.8.2.3
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Re: [U-Boot] [PATCH imx6dl] Enable SION Bit for GPIO16 when ALT2 mode is selected
On Wed, Jan 22, 2014 at 5:19 AM, Markus Niebel list-09_u-b...@tqsc.de wrote: IOMUX_CONFIG_SION is used everywhere for I2C dedicated pins - partly hard coded for mx6q - so yes, should be used fro enet_clk, too Yes, looks good. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] config: trats: trats2: extend dfu_alt_info by env update settings
This change allows updating environment stored on MMC by dfu or thor.
New setting:
- params.bin mmc 0x38 0x8
File params.bin can be generated by: tools/mkenvimage.
e.g. ./mkenvimage -s 4096 -o params.bin env_text_file
Every new env variable in text file should start with a new line.
Sample env text file:
- board/samsung/common/dfu_sample_env.txt
Requirements:
- file name: params.bin
- file size: 4096 Bytes - the same as CONFIG_ENV_SIZE.
Other size will cause CRC miscalculation at boot.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
CC: Piotr Wilczek p.wilc...@samsung.com
CC: Lukasz Majewski l.majew...@samsung.com
---
board/samsung/common/dfu_sample_env.txt |9 +
include/configs/trats.h |3 ++-
include/configs/trats2.h|3 ++-
3 files changed, 13 insertions(+), 2 deletions(-)
create mode 100644 board/samsung/common/dfu_sample_env.txt
diff --git a/board/samsung/common/dfu_sample_env.txt
b/board/samsung/common/dfu_sample_env.txt
new file mode 100644
index 000..d6ee8a2
--- /dev/null
+++ b/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype}
rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
diff --git a/include/configs/trats.h b/include/configs/trats.h
index fdd8b46..d09f7c7 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -147,7 +147,8 @@
PARTS_BOOT part 0 2; \
PARTS_ROOT part 0 5; \
PARTS_DATA part 0 6; \
- PARTS_UMS part 0 7\0
+ PARTS_UMS part 0 7; \
+ params.bin mmc 0x38 0x8\0
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 83633b0..31c52f1 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -178,7 +178,8 @@
PARTS_BOOT part 0 2; \
PARTS_ROOT part 0 5; \
PARTS_DATA part 0 6; \
- PARTS_UMS part 0 7\0
+ PARTS_UMS part 0 7; \
+ params.bin mmc 0x38 0x8\0
#define CONFIG_EXTRA_ENV_SETTINGS \
bootk= \
--
1.7.9.5
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[U-Boot] [RFC PATCH 1/2] common: Add new clk command
Command provides just dump subcommand for showing clock
frequencies in a soc.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
README | 1 +
common/Makefile | 1 +
common/cmd_clk.c | 51
include/clk.h| 6 ++
include/config_cmd_all.h | 1 +
5 files changed, 60 insertions(+)
create mode 100644 common/cmd_clk.c
create mode 100644 include/clk.h
diff --git a/README b/README
index aea82be..0087649 100644
--- a/README
+++ b/README
@@ -887,6 +887,7 @@ The following options need to be configured:
CONFIG_CMD_BSP * Board specific commands
CONFIG_CMD_BOOTD bootd
CONFIG_CMD_CACHE* icache, dcache
+ CONFIG_CMD_CLK * clock command support
CONFIG_CMD_CONSOLEconinfo
CONFIG_CMD_CRC32* crc32
CONFIG_CMD_DATE * support for RTC, date/time...
diff --git a/common/Makefile b/common/Makefile
index d12cba5..a000e7d 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
obj-$(CONFIG_CMD_CACHE) += cmd_cache.o
obj-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
+obj-$(CONFIG_CMD_CLK) += cmd_clk.o
obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
diff --git a/common/cmd_clk.c b/common/cmd_clk.c
new file mode 100644
index 000..6d3d46a
--- /dev/null
+++ b/common/cmd_clk.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include command.h
+#include clk.h
+
+int __weak soc_clk_dump(void)
+{
+ puts(Not implemented\n);
+ return 1;
+}
+
+static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ return soc_clk_dump();
+}
+
+static cmd_tbl_t cmd_clk_sub[] = {
+ U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, , ),
+};
+
+static int do_clk(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc 2)
+ return CMD_RET_USAGE;
+
+ /* Strip off leading 'clk' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], cmd_clk_sub[0], ARRAY_SIZE(cmd_clk_sub));
+
+ if (c)
+ return c-cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char clk_help_text[] =
+ dump - Print clock frequencies;
+#endif
+
+U_BOOT_CMD(clk, 2, 1, do_clk, CLK sub-system, clk_help_text);
diff --git a/include/clk.h b/include/clk.h
new file mode 100644
index 000..df4570c
--- /dev/null
+++ b/include/clk.h
@@ -0,0 +1,6 @@
+#ifndef _CLK_H_
+#define _CLK_H_
+
+int soc_clk_dump(void);
+
+#endif /* _CLK_H_ */
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index d847069..3e8983f 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -23,6 +23,7 @@
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
+#define CONFIG_CMD_CLK /* Clock support*/
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DATE/* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP/* DHCP Support */
--
1.8.2.3
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[U-Boot] [RFC PATCH 2/2] zynq: Implement dump clock command
From: Soren Brinkmann soren.brinkm...@xilinx.com
Enable and implement dump clock command which shows
soc frequencies.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
On the top of Zynq clk patches I have sent.
All paches available for testing here
git://git.denx.de/u-boot-microblaze.git
xnext/clk-cmd branch.
For example:
zynq-uboot clk dump
clk frequency
armpll 133320
ddrpll 106656
iopll 0
cpu_6or4x 0
cpu_3or2x 0
cpu_2x 0
cpu_1x 0
ddr_2x 35552
ddr_3x 53328
dci10158730
lqspi 19998
smc
pcap 19998
gem02500
gem11667
fclk05000
fclk15000
fclk25000
fclk35000
sdio05000
sdio15000
uart05000
uart15000
spi015873016
spi115873016
usb0_aper 0
usb1_aper 0
gem0_aper 0
gem1_aper 0
sdio0_aper 0
sdio1_aper 0
spi0_aper 0
spi1_aper 0
can0_aper 0
can1_aper 0
i2c0_aper 0
i2c1_aper 0
uart0_aper 0
uart1_aper 0
gpio_aper 0
lqspi_aper 0
smc_aper 0
dbg_trc
dbg_apb
arch/arm/cpu/armv7/zynq/clk.c | 21 +
include/configs/zynq-common.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c
index ea7a677..6a759a1 100644
--- a/arch/arm/cpu/armv7/zynq/clk.c
+++ b/arch/arm/cpu/armv7/zynq/clk.c
@@ -6,6 +6,7 @@
*/
#include common.h
#include errno.h
+#include clk.h
#include asm/io.h
#include asm/arch/hardware.h
#include asm/arch/clk.h
@@ -641,3 +642,23 @@ const char *zynq_clk_get_name(enum zynq_clk clk)
{
return clks[clk].name;
}
+
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+ int i;
+
+ printf(clk\t\tfrequency\n);
+ for (i = 0; i clk_max; i++) {
+ const char *name = zynq_clk_get_name(i);
+ if (name)
+ printf(%10s%20lu\n, name, zynq_clk_get_rate(i));
+ }
+
+ return 0;
+}
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 9666f88..52f1c66 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -164,6 +164,7 @@
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
+#define CONFIG_CMD_CLK
#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
--
1.8.2.3
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Re: [U-Boot] [PATCH] config: trats: trats2: extend dfu_alt_info by env update settings
CC
On 01/22/2014 12:02 PM, Przemyslaw Marczak wrote:
This change allows updating environment stored on MMC by dfu or thor.
New setting:
- params.bin mmc 0x38 0x8
File params.bin can be generated by: tools/mkenvimage.
e.g. ./mkenvimage -s 4096 -o params.bin env_text_file
Every new env variable in text file should start with a new line.
Sample env text file:
- board/samsung/common/dfu_sample_env.txt
Requirements:
- file name: params.bin
- file size: 4096 Bytes - the same as CONFIG_ENV_SIZE.
Other size will cause CRC miscalculation at boot.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
CC: Piotr Wilczek p.wilc...@samsung.com
CC: Lukasz Majewski l.majew...@samsung.com
---
board/samsung/common/dfu_sample_env.txt |9 +
include/configs/trats.h |3 ++-
include/configs/trats2.h|3 ++-
3 files changed, 13 insertions(+), 2 deletions(-)
create mode 100644 board/samsung/common/dfu_sample_env.txt
diff --git a/board/samsung/common/dfu_sample_env.txt
b/board/samsung/common/dfu_sample_env.txt
new file mode 100644
index 000..d6ee8a2
--- /dev/null
+++ b/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype}
rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
diff --git a/include/configs/trats.h b/include/configs/trats.h
index fdd8b46..d09f7c7 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -147,7 +147,8 @@
PARTS_BOOT part 0 2; \
PARTS_ROOT part 0 5; \
PARTS_DATA part 0 6; \
- PARTS_UMS part 0 7\0
+ PARTS_UMS part 0 7; \
+ params.bin mmc 0x38 0x8\0
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 83633b0..31c52f1 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -178,7 +178,8 @@
PARTS_BOOT part 0 2; \
PARTS_ROOT part 0 5; \
PARTS_DATA part 0 6; \
- PARTS_UMS part 0 7\0
+ PARTS_UMS part 0 7; \
+ params.bin mmc 0x38 0x8\0
#define CONFIG_EXTRA_ENV_SETTINGS \
bootk= \
Thank you,
--
Przemyslaw Marczak
Samsung RD Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH] config: trats: trats2: extend dfu_alt_info by env update settings
Hi Przemyslaw,
This change allows updating environment stored on MMC by dfu or thor.
New setting:
- params.bin mmc 0x38 0x8
File params.bin can be generated by: tools/mkenvimage.
e.g. ./mkenvimage -s 4096 -o params.bin env_text_file
Every new env variable in text file should start with a new line.
Sample env text file:
- board/samsung/common/dfu_sample_env.txt
Requirements:
- file name: params.bin
- file size: 4096 Bytes - the same as CONFIG_ENV_SIZE.
Other size will cause CRC miscalculation at boot.
Acked-by: Lukasz Majewski l.majew...@samsung.com
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
CC: Piotr Wilczek p.wilc...@samsung.com
CC: Lukasz Majewski l.majew...@samsung.com
---
board/samsung/common/dfu_sample_env.txt |9 +
include/configs/trats.h |3 ++-
include/configs/trats2.h|3 ++-
3 files changed, 13 insertions(+), 2 deletions(-)
create mode 100644 board/samsung/common/dfu_sample_env.txt
diff --git a/board/samsung/common/dfu_sample_env.txt
b/board/samsung/common/dfu_sample_env.txt new file mode 100644
index 000..d6ee8a2
--- /dev/null
+++ b/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart}
${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4 +loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart}
0x40007FC0 uImage +mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0
2 diff --git a/include/configs/trats.h b/include/configs/trats.h
index fdd8b46..d09f7c7 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -147,7 +147,8 @@
PARTS_BOOT part 0 2; \
PARTS_ROOT part 0 5; \
PARTS_DATA part 0 6; \
- PARTS_UMS part 0 7\0
+ PARTS_UMS part 0 7; \
+ params.bin mmc 0x38 0x8\0
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 83633b0..31c52f1 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -178,7 +178,8 @@
PARTS_BOOT part 0 2; \
PARTS_ROOT part 0 5; \
PARTS_DATA part 0 6; \
- PARTS_UMS part 0 7\0
+ PARTS_UMS part 0 7; \
+ params.bin mmc 0x38 0x8\0
#define CONFIG_EXTRA_ENV_SETTINGS \
bootk= \
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH 1/3 V3] esdhc: Workaround for card can't be detected on T4240QDS
Hi Haijun, On Jan 10, 2014, at 7:52 AM, Haijun Zhang wrote: Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for V3: - Define quirk in board specific file instead of code in driver changes for V2: - Add the judgement condition for this broken card drivers/mmc/fsl_esdhc.c| 4 include/configs/T4240QDS.h | 5 + 2 files changed, 9 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e522a70..2ee93cd 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -548,6 +548,10 @@ static int esdhc_getcd(struct mmc *mmc) struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg-esdhc_base; int timeout = 1000; +#ifdef CONFIG_ESDHC_DETECT_QUIRK + if (CONFIG_ESDHC_DETECT_QUIRK) + return 1; +#endif while (!(esdhc_read32(regs-prsstat) PRSSTAT_CINS) --timeout) udelay(1000); diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index c96df54..0e0b346 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG50x55 +#define QIXIS_MUX_SDHC 2 #define QIXIS_BASE_PHYS (0xfull | QIXIS_BASE) #define CONFIG_SYS_CSPR3_EXT (0xf) @@ -466,6 +468,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_ESDHC_DETECT_QUIRK \ + (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) QIXIS_MUX_SDHC) || \ + IS_SVR_REV(get_svr(), 1, 0)) #endif #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -- 1.8.4.1 Acked-by: Pantelis Antoniou pa...@antoniou-consulting.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3 V3] esdhc: Detecting 8 bit width before mmc initialization
Hi Haijun, On Jan 10, 2014, at 7:52 AM, Haijun Zhang wrote: The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for V3: - Define quirk in board specific file instead of code in driver changes for V2: - No changes drivers/mmc/fsl_esdhc.c| 5 + include/configs/T4240QDS.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 2ee93cd..72ca109 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -644,6 +644,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (caps ESDHC_HOSTCAPBLT_HSS) mmc-host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; +#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK + if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) + mmc-host_caps = ~MMC_MODE_8BIT; +#endif + mmc-f_min = 40; mmc-f_max = MIN(gd-arch.sdhc_clk, 5200); diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 0e0b346..275a7a8 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BRDCFG5 0x55 #define QIXIS_MUX_SDHC2 +#define QIXIS_MUX_SDHC_WIDTH81 #define QIXIS_BASE_PHYS (0xfull | QIXIS_BASE) #define CONFIG_SYS_CSPR3_EXT (0xf) @@ -471,6 +472,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ESDHC_DETECT_QUIRK \ (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) QIXIS_MUX_SDHC) || \ IS_SVR_REV(get_svr(), 1, 0)) +#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ + (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) QIXIS_MUX_SDHC_WIDTH8)) #endif #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -- 1.8.4.1 Acked-by: Pantelis Antoniou pa...@antoniou-consulting.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3 V3] eSDHC: Calculate envaddr accroding to the address format
Hi Haijun,
On Jan 10, 2014, at 7:52 AM, Haijun Zhang wrote:
On BSC9131, BSC9132, P1010 : For High Capacity SD Cards ( 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.
If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
changes for V3:
- Define quirk in SOC specific file instead of code in driver
changes for V2:
- Use 0xu instead of UINT_MAX
arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
board/freescale/common/sdhc_boot.c| 29 +
2 files changed, 32 insertions(+)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 15affdc..e8bd76a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -152,6 +152,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV0x10
+#define CONFIG_ESDHC_HC_BLK_ADDR
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_P1011)
@@ -552,6 +553,7 @@
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_BSC9132)
#define CONFIG_MAX_CPUS 2
@@ -575,6 +577,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV0x11
+#define CONFIG_ESDHC_HC_BLK_ADDR
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#define CONFIG_E6500
diff --git a/board/freescale/common/sdhc_boot.c
b/board/freescale/common/sdhc_boot.c
index f6e2b2b..022f38b 100644
--- a/board/freescale/common/sdhc_boot.c
+++ b/board/freescale/common/sdhc_boot.c
@@ -16,6 +16,8 @@
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
+#define ESDHC_DEFAULT_ENVADDR0x400
+
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
@@ -39,6 +41,33 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32
*env_addr)
/* Get the code size from offset 0x48 */
code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+#ifdef CONFIG_ESDHC_HC_BLK_ADDR
+ /*
+ * On soc BSC9131, BSC9132:
+ * In High Capacity SD Cards ( 2 GBytes), the 32-bit source address and
+ * code length of these soc specify the memory address in block address
+ * format. Block length is fixed to 512 bytes as per the SD High
+ * Capacity specification.
+ */
+ u64 tmp;
+
+ if (mmc-high_capacity) {
+ tmp = (u64)code_offset * blklen;
+ tmp += code_len * blklen;
+ } else
+ tmp = code_offset + code_len;
+
+ if ((tmp + CONFIG_ENV_SIZE mmc-capacity) ||
+ (tmp 0xU))
+ *env_addr = ESDHC_DEFAULT_ENVADDR;
+ else
+ *env_addr = tmp;
+
+ free(tmp_buf);
+
+ return 0;
+#endif
+
*env_addr = code_offset + code_len;
free(tmp_buf);
--
1.8.4.1
Acked-by: Pantelis Antoniou pa...@antoniou-consulting.com
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Re: [U-Boot] [PATCH 1/3 V3] esdhc: Workaround for card can't be detected on T4240QDS
Hi York, On Jan 22, 2014, at 12:01 AM, York Sun wrote: Pantelis, On 01/09/2014 09:52 PM, Haijun Zhang wrote: Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for V3: - Define quirk in board specific file instead of code in driver changes for V2: - Add the judgement condition for this broken card I think this set of patches are in your backyard. If you ack them, I can apply them to mpc85xx. Go ahead please. http://patchwork.ozlabs.org/patch/309168/ http://patchwork.ozlabs.org/patch/309167/ http://patchwork.ozlabs.org/patch/309170/ York Regards -- Pantelis ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 1/2] common: Add new clk command
Hi Michal,
On 22/01/2014 12:02, Michal Simek wrote:
Command provides just dump subcommand for showing clock frequencies
in a soc.
i.MXes has already an own command for this functionality - see command
clocks in arch/arm. However, I like that we can have a common
command for all SOCs.
Signed-off-by: Michal Simek michal.si...@xilinx.com ---
README | 1 + common/Makefile | 1 +
common/cmd_clk.c | 51
include/clk.h
| 6 ++ include/config_cmd_all.h | 1 + 5 files changed, 60
insertions(+) create mode 100644 common/cmd_clk.c create mode
100644 include/clk.h
diff --git a/README b/README index aea82be..0087649 100644 ---
a/README +++ b/README @@ -887,6 +887,7 @@ The following options
need to be configured: CONFIG_CMD_BSP * Board specific commands
CONFIG_CMD_BOOTDbootd CONFIG_CMD_CACHE* icache, dcache +
CONFIG_CMD_CLK* clock command support CONFIG_CMD_CONSOLE
coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for
RTC, date/time... diff --git a/common/Makefile b/common/Makefile
index d12cba5..a000e7d 100644 --- a/common/Makefile +++
b/common/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) +=
cmd_bootldr.o obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
obj-$(CONFIG_CMD_CACHE) += cmd_cache.o obj-$(CONFIG_CMD_CBFS) +=
cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o
obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff
--git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644
index 000..6d3d46a --- /dev/null +++ b/common/cmd_clk.c @@ -0,0
+1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + *
SPDX-License-Identifier: GPL-2.0+ + */ +#include common.h
+#include command.h +#include clk.h + +int __weak
soc_clk_dump(void) +{ + puts(Not implemented\n); +return 1; +}
+ +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, +
char *const argv[]) +{ + return soc_clk_dump(); +} + +static
cmd_tbl_t cmd_clk_sub[] = { + U_BOOT_CMD_MKENT(dump, 1, 1,
do_clk_dump, , ), +}; +
Do you plan to extend the list with new functionalities ? IMHO we
should do it when we really need, that is when we will need at least a
second subcommand.
Best regards,
Stefano Babic
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Re: [U-Boot] [RFC PATCH 1/2] common: Add new clk command
Hi Stefano,
On 01/22/2014 01:46 PM, Stefano Babic wrote:
Hi Michal,
On 22/01/2014 12:02, Michal Simek wrote:
Command provides just dump subcommand for showing clock frequencies
in a soc.
i.MXes has already an own command for this functionality - see command
clocks in arch/arm. However, I like that we can have a common
command for all SOCs.
Ah good to know. It seems to me better to have clock like command name
and then subcommand. Unification will be good to have.
Signed-off-by: Michal Simek michal.si...@xilinx.com ---
README | 1 + common/Makefile | 1 +
common/cmd_clk.c | 51
include/clk.h
| 6 ++ include/config_cmd_all.h | 1 + 5 files changed, 60
insertions(+) create mode 100644 common/cmd_clk.c create mode
100644 include/clk.h
diff --git a/README b/README index aea82be..0087649 100644 ---
a/README +++ b/README @@ -887,6 +887,7 @@ The following options
need to be configured: CONFIG_CMD_BSP* Board specific
commands
CONFIG_CMD_BOOTD bootd CONFIG_CMD_CACHE* icache, dcache +
CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE
coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for
RTC, date/time... diff --git a/common/Makefile b/common/Makefile
index d12cba5..a000e7d 100644 --- a/common/Makefile +++
b/common/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_CMD_BOOTLDR) +=
cmd_bootldr.o obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
obj-$(CONFIG_CMD_CACHE) += cmd_cache.o obj-$(CONFIG_CMD_CBFS) +=
cmd_cbfs.o +obj-$(CONFIG_CMD_CLK) += cmd_clk.o
obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o diff
--git a/common/cmd_clk.c b/common/cmd_clk.c new file mode 100644
index 000..6d3d46a --- /dev/null +++ b/common/cmd_clk.c @@ -0,0
+1,51 @@ +/* + * Copyright (C) 2013 Xilinx, Inc. + * + *
SPDX-License-Identifier: GPL-2.0+ + */ +#include common.h
+#include command.h +#include clk.h + +int __weak
soc_clk_dump(void) +{ + puts(Not implemented\n); +return 1; +}
+ +static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, +
char *const argv[]) +{ + return soc_clk_dump(); +} + +static
cmd_tbl_t cmd_clk_sub[] = { +U_BOOT_CMD_MKENT(dump, 1, 1,
do_clk_dump, , ), +}; +
Do you plan to extend the list with new functionalities ? IMHO we
should do it when we really need, that is when we will need at least a
second subcommand.
I tried to write it as generic as possible and currently we don't need
any special clock functionality but it can happen in future.
Will be great if we can add all the clock handling to the one command,
Currently we just use clock dump.
Thanks,
Michal
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[U-Boot] [PATCH] mx6sl: Adjust fdt_addr to avoid address overlapping
From: Fabio Estevam fabio.este...@freescale.com Similarly as it was done on commit 6584a1b526 (ARM: mx6: Change the FDT loading address to avoid overlaping), we need to adjust the fdt_addr in order to be able to boot FSL 3.10 kernel. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- include/configs/mx6slevk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index b29f78c..db5607c 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -81,7 +81,7 @@ fdt_high=0x\0 \ initrd_high=0x\0 \ fdt_file=imx6sl-evk.dtb\0 \ - fdt_addr=0x8100\0 \ + fdt_addr=0x8800\0 \ boot_fdt=try\0 \ ip_dyn=yes\0 \ mmcdev=0\0 \ -- 1.8.1.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mx6sl: Adjust fdt_addr to avoid address overlapping
On Wed, Jan 22, 2014 at 12:23 PM, Fabio Estevam feste...@gmail.com wrote: From: Fabio Estevam fabio.este...@freescale.com Similarly as it was done on commit 6584a1b526 (ARM: mx6: Change the FDT loading address to avoid overlaping), we need to adjust the fdt_addr in order to be able to boot FSL 3.10 kernel. Signed-off-by: Fabio Estevam fabio.este...@freescale.com Good catch, I missed this one :) Acked-by: Otavio Salvador ota...@ossystems.com.br -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://code.ossystems.com.br Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 0/8] arm: add runtime envs describing build
This patchset adds runtime variables for Samsung boards that describe build configuration (arch, soc, board, vendor). Additionally, more envs describing platform (soc and board revision) are added to Samsung common code. For boards Trats and Trats2, based on the added envs, 'fdtfile' env is set and dual kernel boot is enabled: - with separated DTB if the DTB file is loaded successfully; - with DTB apppended to uImage if DTB file is not found; This is neccesssary for backward compatibilty. THis patchset depends on the patchset: [PATCH v6 00/11] Introduce Samsung misc file and LCD menu. http://patchwork.ozlabs.org/patch/313186/ ... http://patchwork.ozlabs.org/patch/313192/ Changes for V2: - rebased against current u-boot0samsung branch Piotr Wilczek (8): arm:exynos: add cpu revision arm:s5pc110: add cpu revision board:samsung:common: set envs with board unified information board:samsung:goni: add env variables describing platform board:samsung:universal: add env variables describing platform board:samsung:trats: add env variables describing platform board:samsung:trats2: add env variables describing platform board:samsung:trats/trats2: enable boot with appended and separated DTB arch/arm/include/asm/arch-exynos/cpu.h |8 ++-- arch/arm/include/asm/arch-s5pc1xx/cpu.h |7 +++ board/samsung/common/misc.c | 24 board/samsung/goni/goni.c| 17 + board/samsung/trats/trats.c |3 +++ board/samsung/trats2/trats2.c|3 +++ board/samsung/universal_c210/universal.c |3 +++ include/configs/s5p_goni.h |6 ++ include/configs/s5pc210_universal.h |3 +++ include/configs/trats.h | 12 +--- include/configs/trats2.h | 12 +--- include/samsung/misc.h | 12 12 files changed, 98 insertions(+), 12 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 1/8] arm:exynos: add cpu revision
This patch enables to read cpu revision on Exynos CPU.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for V2:
- none
arch/arm/include/asm/arch-exynos/cpu.h |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 573f755..bccce63 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -185,9 +185,11 @@ static inline int s5p_get_cpu_rev(void)
static inline void s5p_set_cpu_id(void)
{
- unsigned int pro_id = (readl(EXYNOS4_PRO_ID) 0x00FFF000) 12;
+ unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+ unsigned int cpu_id = (pro_id 0x00FFF000) 12;
+ unsigned int cpu_rev = pro_id 0x00FF;
- switch (pro_id) {
+ switch (cpu_id) {
case 0x200:
/* Exynos4210 EVT0 */
s5p_cpu_id = 0x4210;
@@ -196,10 +198,12 @@ static inline void s5p_set_cpu_id(void)
case 0x210:
/* Exynos4210 EVT1 */
s5p_cpu_id = 0x4210;
+ s5p_cpu_rev = cpu_rev;
break;
case 0x412:
/* Exynos4412 */
s5p_cpu_id = 0x4412;
+ s5p_cpu_rev = cpu_rev;
break;
case 0x520:
/* Exynos5250 */
--
1.7.9.5
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[U-Boot] [PATCH V2 3/8] board:samsung:common: set envs with board unified information
This patch sets envs that describe board information.
The following envs are set: soc_id, soc_rev, board_rev.
Based on this information, if CONFIG_OF_LIBFDT is enabled,
the 'fdtfile' env is set as:
fdtfile=${soc_family}${soc_id}-${board}.dtb
The generated envs are intenionally not saved to persistent storage.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6 00/11] Introduce Samsung misc file and LCD menu
board/samsung/common/misc.c | 24
include/samsung/misc.h | 12
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 643f957..eb15739 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -21,6 +21,30 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void)
+{
+ char info[64];
+
+ snprintf(info, ARRAY_SIZE(info), %d.%d, s5p_cpu_rev 0x0f,
+(s5p_cpu_rev 0xf0) 0x04);
+ setenv(soc_rev, info);
+
+ snprintf(info, ARRAY_SIZE(info), %x, s5p_cpu_id);
+ setenv(soc_id, info);
+
+#ifdef CONFIG_REVISION_TAG
+ snprintf(info, ARRAY_SIZE(info), %x, get_board_rev());
+ setenv(board_rev, info);
+#endif
+#ifdef CONFIG_OF_LIBFDT
+ snprintf(info, ARRAY_SIZE(info), %s%x-%s.dtb,
+CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD);
+ setenv(fdtfile, info);
+#endif
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
#ifdef CONFIG_LCD_MENU
static int power_key_pressed(u32 reg)
{
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
index 1a6d47f..ede6c15 100644
--- a/include/samsung/misc.h
+++ b/include/samsung/misc.h
@@ -1,6 +1,14 @@
#ifndef __SAMSUNG_MISC_COMMON_H__
#define __SAMSUNG_MISC_COMMON_H__
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void);
+#endif
+
#ifdef CONFIG_LCD_MENU
enum {
BOOT_MODE_INFO,
@@ -10,10 +18,6 @@ enum {
BOOT_MODE_EXIT,
};
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void);
-#endif
-
void keys_init(void);
void check_boot_mode(void);
#endif /* CONFIG_LCD_MENU */
--
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[U-Boot] [PATCH V2 4/8] board:samsung:goni: add env variables describing platform
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Mateusz Zalega m.zal...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6 00/11] Introduce Samsung misc file and LCD menu
board/samsung/goni/goni.c | 17 +
include/configs/s5p_goni.h |6 ++
2 files changed, 23 insertions(+)
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 366f648..61b9ece 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -13,10 +13,17 @@
#include usb/s3c_udc.h
#include asm/arch/cpu.h
#include power/max8998_pmic.h
+#include samsung/misc.h
+
DECLARE_GLOBAL_DATA_PTR;
static struct s5pc110_gpio *s5pc110_gpio;
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
int board_init(void)
{
/* Set Initial global variables */
@@ -173,3 +180,13 @@ struct s3c_plat_otg_data s5pc110_otg_data = {
.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
};
#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+ return 0;
+}
+#endif
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 4cdf937..991c43e 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -34,6 +34,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
@@ -113,8 +114,13 @@
#define CONFIG_UBIFS_OPTIONrootflags=bulk_read,no_chk_data_crc
+#define CONFIG_MISC_COMMON
+#define CONFIG_MISC_INIT_R
+
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_UPDATEB \
updatek= \
--
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[U-Boot] [PATCH V2 6/8] board:samsung:trats: add env variables describing platform
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6 00/11] Introduce Samsung misc file and LCD menu
board/samsung/trats/trats.c |3 +++
include/configs/trats.h |3 +++
2 files changed, 6 insertions(+)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index c6664e7..b725505 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -791,6 +791,9 @@ void init_panel_info(vidinfo_t *vid)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
#ifdef CONFIG_LCD_MENU
keys_init();
check_boot_mode();
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 1de971c..18b4e2f 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -149,6 +149,9 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
#define CONFIG_EXTRA_ENV_SETTINGS \
bootk= \
run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0 \
--
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[U-Boot] [PATCH V2 7/8] board:samsung:trats2: add env variables describing platform
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6 00/11] Introduce Samsung misc file and LCD menu
board/samsung/trats2/trats2.c |3 +++
include/configs/trats2.h |3 +++
2 files changed, 6 insertions(+)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 62e7fd2..c17c24d 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -616,6 +616,9 @@ void init_panel_info(vidinfo_t *vid)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
#ifdef CONFIG_LCD_MENU
keys_init();
check_boot_mode();
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index c48e3f5..7daa445 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -150,6 +150,9 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
/* Tizen - partitions definitions */
#define PARTS_CSA csa
#define PARTS_BOOT boot
--
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[U-Boot] [PATCH V2 2/8] arm:s5pc110: add cpu revision
This patch adds s5p_cpu_rev.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Changes for V2:
- none
arch/arm/include/asm/arch-s5pc1xx/cpu.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
index 4fc5a0c..5ae5c87 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -51,10 +51,17 @@
#include asm/io.h
/* CPU detection macros */
extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+ return s5p_cpu_rev;
+}
static inline void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl(S5PC100_PRO_ID);
+ s5p_cpu_rev = s5p_cpu_id 0x00FF;
s5p_cpu_id = 0xC000 | ((s5p_cpu_id 0x00FFF000) 12);
}
--
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[U-Boot] [PATCH V2 5/8] board:samsung:universal: add env variables describing platform
This patch adds variables describing platform (soc, board, vendor)
to default environment.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Przemyslaw Marczak p.marc...@samsung.com
---
Changes for V2:
- rebased on patchset [PATCH v6 00/11] Introduce Samsung misc file and LCD menu
board/samsung/universal_c210/universal.c |3 +++
include/configs/s5pc210_universal.h |3 +++
2 files changed, 6 insertions(+)
diff --git a/board/samsung/universal_c210/universal.c
b/board/samsung/universal_c210/universal.c
index 98b387f..5ce74b7 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -516,6 +516,9 @@ int board_init(void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
#ifdef CONFIG_LCD_MENU
keys_init();
check_boot_mode();
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index bfb044b..67921e9 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -124,6 +124,9 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
#define CONFIG_EXTRA_ENV_SETTINGS \
updateb= \
onenand erase 0x0 0x10; \
--
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[U-Boot] [PATCH V2 8/8] board:samsung:trats/trats2: enable boot with appended and separated DTB
This patch modifies envs to enable dual kernel boot
- with separated DTB if the DTB file is loaded successfully;
- with DTB apppended to uImage if DTB file is not found;
This is neccesssary for backward compatibilty.
Signed-off-by: Piotr Wilczek p.wilc...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
Changes for V2:
- squashed separated patches for Trats and Trats2 inito one
include/configs/trats.h |9 ++---
include/configs/trats2.h |9 ++---
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 18b4e2f..7bd1584 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -154,7 +154,11 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
bootk= \
- run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0 \
+ run loaduimage; \
+ if run loaddtb; then \
+ bootm 0x40007FC0 - ${fdtaddr}; \
+ fi; \
+ bootm 0x40007FC0;\0 \
updatemmc= \
mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200; \
mmc boot 0 1 1 0\0 \
@@ -177,7 +181,7 @@
mmcboot= \
setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} \
${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; \
- run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0 \
+ run bootk\0 \
bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0 \
boottrace=setenv opts initcall_debug; run bootcmd\0 \
mmcoops=mmc read 0 0x4000 0x40 8; md 0x4000 0x400\0 \
@@ -216,7 +220,6 @@
setenv spl_imgaddr; \
setenv spl_addr_tmp;\0 \
fdtaddr=4080\0 \
- fdtfile=exynos4210-trats.dtb\0
/* Miscellaneous configurable options */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 7daa445..28270fe 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -180,7 +180,11 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
bootk= \
- run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0 \
+ run loaduimage; \
+ if run loaddtb; then \
+ bootm 0x40007FC0 - ${fdtaddr}; \
+ fi; \
+ bootm 0x40007FC0;\0 \
updatemmc= \
mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200; \
mmc boot 0 1 1 0\0 \
@@ -194,7 +198,7 @@
mmcboot= \
setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} \
${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; \
- run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0 \
+ run bootk\0 \
bootchart=set opts init=/sbin/bootchartd; run bootcmd\0 \
boottrace=setenv opts initcall_debug; run bootcmd\0 \
verify=n\0 \
@@ -235,7 +239,6 @@
setenv spl_imgaddr; \
setenv spl_addr_tmp;\0 \
fdtaddr=4080\0 \
- fdtfile=exynos4412-trats2.dtb\0
/*
* Miscellaneous configurable options
--
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Re: [U-Boot] [PATCH v2] designware_i2c: Enhance DesignWare I2C driver address support
Thanks Alexey. Hi Heiko, I believe this patch should be good for apply. Would need your help then. :) Thanks Chin Liang On Wed, 2014-01-15 at 15:51 +, Alexey Brodkin wrote: On Wed, 2014-01-15 at 09:45 -0600, Chin Liang See wrote: Changes for v2 - Removed the function check_params() Ok, so you decided to not add assert check instead. I think it's ok - it's not a requirement. Others don't do it as well so let's leave it as it is. Acked-by: Alexey Brodkin abrod...@synopsys.com Regards, Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request u-boot-mpc85xx
On Tue, Jan 21, 2014 at 03:07:40PM -0800, York Sun wrote: Tom, The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b: Prepare v2014.01 (2014-01-20 17:52:59 -0500) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to e222b1f36fedb0363dbc21e0add7dc3848bae553: powerpc/mpc85xx:Increase binary size for P, B T series boards. (2014-01-21 14:06:30 -0800) Po Liu (2): powerpc:mpc85xx: Add ifc nand boot support for TPL/SPL powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL Prabhakar Kushwaha (2): powerpc:Rename CONFIG_PBLRCW_CONFIG CONFIG_SYS_FSL_PBL_PBI powerpc/mpc85xx:Increase binary size for P, B T series boards. Priyanka Jain (1): powerpc/t1040qds: Update DDR initialization related settings Ramneek Mehresh (1): powerpc/83xx: Add support for get_svr() for 83xx devices Shengzhou Liu (4): powerpc/t2080qds: some update for t2080qds powerpc/85xx: update erratum a006379 t2080qds/ddr: update ddr parameters net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90f York Sun (2): powerpc/mpc85xx: Fix a typo in workaround message for DDR erratum A003474 powerpc/mpc85xx: Revise workaround for DDR-A003 Makefile|4 +- README |9 ++ arch/powerpc/cpu/mpc83xx/start.S|5 + arch/powerpc/cpu/mpc85xx/cmd_errata.c |2 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 15 +-- arch/powerpc/include/asm/fsl_errata.h |6 +- board/freescale/c29xpcie/Makefile | 15 +++ board/freescale/c29xpcie/README | 12 +-- board/freescale/c29xpcie/cpld.c |2 + board/freescale/c29xpcie/spl.c | 77 +++ board/freescale/c29xpcie/spl_minimal.c | 63 board/freescale/c29xpcie/tlb.c | 13 ++- board/freescale/p1010rdb/README.P1010RDB-PA | 12 +-- board/freescale/p1010rdb/README.P1010RDB-PB |4 +- board/freescale/p1023rds/README |4 +- board/freescale/p1_p2_rdb/README| 12 +-- board/freescale/p2041rdb/README | 12 +-- board/freescale/t1040qds/README | 12 +-- board/freescale/t1040qds/ddr.h | 22 +++-- board/freescale/t104xrdb/README | 12 +-- board/freescale/t2080qds/ddr.c | 12 +-- board/freescale/t2080qds/ddr.h | 65 + board/freescale/t2080qds/eth_t2080qds.c | 12 ++- board/freescale/t2080qds/t2080qds.c | 66 +++-- boards.cfg | 67 ++--- doc/README.SPL |1 + doc/README.b4860qds | 12 +-- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 69 +- drivers/mtd/nand/fsl_ifc_spl.c | 31 -- drivers/net/fm/init.c | 53 +- drivers/net/fm/t2080.c | 10 +- include/configs/B4860QDS.h | 12 +-- include/configs/BSC9131RDB.h|6 +- include/configs/BSC9132QDS.h| 17 ++-- include/configs/C29XPCIE.h | 138 +-- include/configs/P1010RDB.h | 16 ++-- include/configs/P1022DS.h | 12 +-- include/configs/P1023RDB.h |8 +- include/configs/P1023RDS.h | 12 +-- include/configs/P1_P2_RDB.h | 14 +-- include/configs/P2020DS.h | 10 +- include/configs/P2041RDB.h | 21 ++-- include/configs/T1040QDS.h | 26 ++--- include/configs/T1040RDB.h | 16 ++-- include/configs/T1042RDB_PI.h | 16 ++-- include/configs/T2080QDS.h | 20 ++-- include/configs/T4240EMU.h |4 +- include/configs/T4240QDS.h | 18 ++-- include/configs/corenet_ds.h| 30 +++--- include/configs/km/kmp204x-common.h |4 +- include/configs/p1_p2_rdb_pc.h | 12 +-- include/configs/p1_twr.h|8 +- include/configs/t4qds.h |2 +- spl/Makefile|1 + 54 files changed, 742 insertions(+), 392 deletions(-) create mode 100644 board/freescale/c29xpcie/spl.c create mode 100644 board/freescale/c29xpcie/spl_minimal.c Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, SF code optimized stuff and few fixes. -- Thanks! Jagan. The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b: Prepare v2014.01 (2014-01-20 17:52:59 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to b53c0ea9adb7b72f4e3074d382598b6b3d9c5037: sf: Update bank configuration (2014-01-21 23:08:28 +0530) Jagannadha Sutradharudu Teki (5): sf: ops: Squash the malloc+memset combo sf: Optimize flash features code sf: Use mode_bits for dual_flash connection doc: SPI: Update the dual_flash info sf: Update bank configuration Marek Vasut (3): sf: Squash the malloc+memset combo sf: Fix entries for S25FL256S_256K and S25FL512S_256K sf: Add S25FL128S_256K IDs doc/SPI/README.dual-flash | 5 +- doc/SPI/README.sf-features| 124 ++ drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 1 - drivers/mtd/spi/sf_ops.c | 16 ++-- drivers/mtd/spi/sf_params.c | 171 +- drivers/mtd/spi/sf_probe.c| 104 - include/spi.h | 42 --- include/spi_flash.h | 24 +++--- 9 files changed, 299 insertions(+), 192 deletions(-) create mode 100644 doc/SPI/README.sf-features ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] net/designware: make driver compatible with data cache
From: Alexey Brodkin alexey.brod...@synopsys.com
Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:
* Flush Tx/Rx buffer descriptors their modification
* Invalidate Tx/Rx buffer descriptors before reading its values
* Flush cache for data passed from CPU to GMAC
* Invalidate cache for data passed from GMAC to CPU
Signed-off-by: Alexey Brodkin abrod...@synopsys.com
Cc: Joe Hershberger joe.hershber...@ni.com
Cc: Vipin Kumar vipin.ku...@st.com
Cc: Stefan Roese s...@denx.de
Cc: Mischa Jonker mjon...@synopsys.com
Cc: Shiraz Hashim shiraz.has...@st.com
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Cc: Amit Virdi amit.vi...@st.com
Cc: Sonic Zhang sonic.zh...@analog.com
Compared to v2:
1. Removed trailing white space
---
drivers/net/designware.c | 53 +---
1 file changed, 50 insertions(+), 3 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 22155b4..c0c8659 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -51,6 +51,11 @@ static void tx_descs_init(struct eth_device *dev)
/* Correcting the last pointer of the chain */
desc_p-dmamac_next = desc_table_p[0];
+ /* Flush all Tx buffer descriptors at once */
+ flush_dcache_range((unsigned int)priv-tx_mac_descrtable,
+ (unsigned int)priv-tx_mac_descrtable +
+ sizeof(priv-tx_mac_descrtable));
+
writel((ulong)desc_table_p[0], dma_p-txdesclistaddr);
}
@@ -63,6 +68,15 @@ static void rx_descs_init(struct eth_device *dev)
struct dmamacdescr *desc_p;
u32 idx;
+ /* Before passing buffers to GMAC we need to make sure zeros
+* written there right after priv structure allocation were
+* flushed into RAM.
+* Otherwise there's a chance to get some of them flushed in RAM when
+* GMAC is already pushing data to RAM via DMA. This way incoming from
+* GMAC data will be corrupted. */
+ flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
+ RX_TOTAL_BUFSIZE);
+
for (idx = 0; idx CONFIG_RX_DESCR_NUM; idx++) {
desc_p = desc_table_p[idx];
desc_p-dmamac_addr = rxbuffs[idx * CONFIG_ETH_BUFSIZE];
@@ -78,6 +92,11 @@ static void rx_descs_init(struct eth_device *dev)
/* Correcting the last pointer of the chain */
desc_p-dmamac_next = desc_table_p[0];
+ /* Flush all Rx buffer descriptors at once */
+ flush_dcache_range((unsigned int)priv-rx_mac_descrtable,
+ (unsigned int)priv-rx_mac_descrtable +
+ sizeof(priv-rx_mac_descrtable));
+
writel((ulong)desc_table_p[0], dma_p-rxdesclistaddr);
}
@@ -197,6 +216,11 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
u32 desc_num = priv-tx_currdescnum;
struct dmamacdescr *desc_p = priv-tx_mac_descrtable[desc_num];
+ /* Invalidate only status field for the following check */
+ invalidate_dcache_range((unsigned long)desc_p-txrx_status,
+ (unsigned long)desc_p-txrx_status +
+ sizeof(desc_p-txrx_status));
+
/* Check if the descriptor is owned by CPU */
if (desc_p-txrx_status DESC_TXSTS_OWNBYDMA) {
printf(CPU not owner of tx frame\n);
@@ -205,6 +229,10 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
memcpy((void *)desc_p-dmamac_addr, packet, length);
+ /* Flush data to be sent */
+ flush_dcache_range((unsigned long)desc_p-dmamac_addr,
+ (unsigned long)desc_p-dmamac_addr + length);
+
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p-txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
desc_p-dmamac_cntl |= (length DESC_TXCTRL_SIZE1SHFT) \
@@ -220,6 +248,10 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
desc_p-txrx_status = DESC_TXSTS_OWNBYDMA;
#endif
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)desc_p,
+ (unsigned long)desc_p + sizeof(struct dmamacdescr));
+
/* Test the wrap-around condition. */
if (++desc_num = CONFIG_TX_DESCR_NUM)
desc_num = 0;
@@ -235,18 +267,28 @@ static int dw_eth_send(struct eth_device *dev, void
*packet, int length)
static int dw_eth_recv(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev-priv;
- u32 desc_num = priv-rx_currdescnum;
+ u32 status, desc_num = priv-rx_currdescnum;
struct dmamacdescr *desc_p = priv-rx_mac_descrtable[desc_num];
-
- u32 status = desc_p-txrx_status;
int length = 0;
+ /* Invalidate entire buffer descriptor */
+ invalidate_dcache_range((unsigned long)desc_p,
+
Re: [U-Boot] [PATCH v3] net/designware: make driver compatible with data cache
Hi Alexey, On 22.01.2014 17:49, Alexey Brodkin wrote: From: Alexey Brodkin alexey.brod...@synopsys.com Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Flush Tx/Rx buffer descriptors their modification * Invalidate Tx/Rx buffer descriptors before reading its values * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU Signed-off-by: Alexey Brodkin abrod...@synopsys.com A small nitpicking comment below. Cc: Joe Hershberger joe.hershber...@ni.com Cc: Vipin Kumar vipin.ku...@st.com Cc: Stefan Roese s...@denx.de Cc: Mischa Jonker mjon...@synopsys.com Cc: Shiraz Hashim shiraz.has...@st.com Cc: Albert ARIBAUD albert.u.b...@aribaud.net Cc: Amit Virdi amit.vi...@st.com Cc: Sonic Zhang sonic.zh...@analog.com Compared to v2: 1. Removed trailing white space --- drivers/net/designware.c | 53 +--- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 22155b4..c0c8659 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -51,6 +51,11 @@ static void tx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p-dmamac_next = desc_table_p[0]; + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv-tx_mac_descrtable, + (unsigned int)priv-tx_mac_descrtable + + sizeof(priv-tx_mac_descrtable)); + writel((ulong)desc_table_p[0], dma_p-txdesclistaddr); } @@ -63,6 +68,15 @@ static void rx_descs_init(struct eth_device *dev) struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros +* written there right after priv structure allocation were +* flushed into RAM. +* Otherwise there's a chance to get some of them flushed in RAM when +* GMAC is already pushing data to RAM via DMA. This way incoming from +* GMAC data will be corrupted. */ Please use this recommended multi-line comment style: /* * Before ... * ... * * ... will be corrupted. */ Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] net/designware - switch driver to phylib usage
With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
* Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
* Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
* Support of custom phy initialization is now done with existing
board_phy_config.
Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.
For example:
* CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
* CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used
I believe there's no need now in doc/README.designware_eth because
user only needs to instantiate the driver with designware_initialize
whose prototype exists in include/netdev.h.
Prerequisites are:
1) http://patchwork.ozlabs.org/patch/313326/
2) http://patchwork.ozlabs.org/patch/309764/
Signed-off-by: Alexey Brodkin abrod...@synopsys.com
Cc: Joe Hershberger joe.hershber...@ni.com
Cc: Vipin Kumar vipin.ku...@st.com
Cc: Stefan Roese s...@denx.de
Cc: Mischa Jonker mjon...@synopsys.com
Cc: Shiraz Hashim shiraz.has...@st.com
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Cc: Amit Virdi amit.vi...@st.com
Cc: Sonic Zhang sonic.zh...@analog.com
Compared to v1:
1. Removed trailing white space
2. Mentioned prerequisites
---
board/bf609-ezkit/bf609-ezkit.c | 4 +-
board/spear/spear300/spear300.c | 3 +-
board/spear/spear310/spear310.c | 3 +-
board/spear/spear320/spear320.c | 3 +-
board/spear/spear600/spear600.c | 3 +-
board/spear/x600/x600.c | 25 +--
doc/README.designware_eth | 25 ---
drivers/net/designware.c| 460 +---
drivers/net/designware.h| 18 +-
include/configs/bf609-ezkit.h | 3 +-
include/configs/spear-common.h | 4 +-
include/configs/spear6xx_evb.h | 3 +
include/netdev.h| 2 +-
13 files changed, 177 insertions(+), 379 deletions(-)
delete mode 100644 doc/README.designware_eth
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
index cfc64fe..43a4330 100644
--- a/board/bf609-ezkit/bf609-ezkit.c
+++ b/board/bf609-ezkit/bf609-ezkit.c
@@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis)
if (CONFIG_DW_PORTS 1) {
static const unsigned short pins[] = P_RMII0;
if (!peripheral_request_list(pins, emac0))
- ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
+ ret += designware_initialize(EMAC0_MACCFG, 0);
}
if (CONFIG_DW_PORTS 2) {
static const unsigned short pins[] = P_RMII1;
if (!peripheral_request_list(pins, emac1))
- ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
+ ret += designware_initialize(EMAC1_MACCFG, 0);
}
return ret;
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index e25aba2..6b6bd9f 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
- interface) = 0)
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) = 0)
ret++;
#endif
return ret;
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 70f9aa1..a4c6a8e 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
- interface) = 0)
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) = 0)
ret++;
#endif
#if defined(CONFIG_MACB)
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index f6b1fdd..ab732a7 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII;
- if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
- interface) = 0)
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) = 0)
ret++;
#endif
#if defined(CONFIG_MACB)
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index e996a0e..8472002 100644
---
Re: [U-Boot] [PATCH v3] net/designware: make driver compatible with data cache
Hello Alexey, In general, a very nice, clean patch. + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)desc_p, +(unsigned long)desc_p + sizeof(struct dmamacdescr)); + If I remember correctly, there is some bit that tells you if the DMA descriptor is owned by CPU or by GMAC. What if the descriptor size is smaller than the cache line size of the CPU? How do you prevent the CPU from overwriting adiacent DMA descriptors that may be owned by the GMAC? As far as I can remember, in Linux they solve this by mapping the descriptors (not the packet buffers, these are always cacheline aligned) in uncached memory, but we cannot do that in u-boot as the MMU is still disabled. OTOH, as we may not need to have the performance benefits of the CPU and GMAC concurrently accessing the descriptor table, we may be able to work around it by handing off multiple descriptors at once from GMAC to CPU and vice versa (maybe depending on cache line size?). I remember that a similar patch (that looked a lot uglier BTW) solved it by doing uncached accesses to the descriptors, but that would require using arch-specific accessor macro's (and I'm not sure if all architectures support an 'uncached access' attribute/flag with load/store instructions). Mischa ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] net/designware: make driver compatible with data cache
Hi Mischa, On Wed, 2014-01-22 at 17:10 +, Mischa Jonker wrote: Hello Alexey, In general, a very nice, clean patch. + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + sizeof(struct dmamacdescr)); + If I remember correctly, there is some bit that tells you if the DMA descriptor is owned by CPU or by GMAC. What if the descriptor size is smaller than the cache line size of the CPU? How do you prevent the CPU from overwriting adiacent DMA descriptors that may be owned by the GMAC? Well, good point. It might happen with long cache line easily. As far as I can remember, in Linux they solve this by mapping the descriptors (not the packet buffers, these are always cacheline aligned) in uncached memory, but we cannot do that in u-boot as the MMU is still disabled. OTOH, as we may not need to have the performance benefits of the CPU and GMAC concurrently accessing the descriptor table, we may be able to work around it by handing off multiple descriptors at once from GMAC to CPU and vice versa (maybe depending on cache line size?). Frankly I don't see a point in trying to process few descriptors at once. The only true failure safe scenario I may think of - CPU waits until all descriptors are processed by GMAC and then CPU processes all Tx or Rx descriptors. In this case CPU won't corrupt the next descriptor used currently by CPU. But this approach will kill benefits of multiple buffers - operation will become synchronous as if we have only 1 buffer for Tx and one for Rx. Which might be a resolution but with penalty of speed/time (which we don't want). I remember that a similar patch (that looked a lot uglier BTW) solved it by doing uncached accesses to the descriptors, but that would require using arch-specific accessor macro's (and I'm not sure if all architectures support an 'uncached access' attribute/flag with load/store instructions). Word/byte-aligned uncached access is sweet but not universal - how many arches have it? As a summary - this problem is very generic (I saw other places like DW MMC driver which use similar approach - flushing/invalidating buffer descriptors) and without true uncached access (be it with means of MMU or specific accessors without MMU) it's not clear how to act completely fail-safe. Might be we need just to add compile-time warning for cases when cache line is longer than one unit of interest (buffer descriptor in our case) so people at least will be informed and suggest to disable D$ for starters. -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx
Tom, The following changes since commit e222b1f36fedb0363dbc21e0add7dc3848bae553: powerpc/mpc85xx:Increase binary size for P, B T series boards. (2014-01-21 14:06:30 -0800) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to f28bea0003536976ebe2fb299cfc140702fec489: eSDHC: Calculate envaddr accroding to the address format (2014-01-22 08:56:44 -0800) Haijun.Zhang (3): esdhc: Workaround for card can't be detected on T4240QDS esdhc: Detecting 8 bit width before mmc initialization eSDHC: Calculate envaddr accroding to the address format arch/powerpc/include/asm/config_mpc85xx.h |3 +++ board/freescale/common/sdhc_boot.c| 29 + drivers/mmc/fsl_esdhc.c |9 + include/configs/T4240QDS.h|8 4 files changed, 49 insertions(+) Thanks, York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/7] zynq: Fix incorrect header name
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote: Zynq common configuration is placed in zynq-common.h not zynq_common.h. Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq_zc70x.h | 2 +- include/configs/zynq_zed.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 673660e..de0e241 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -2,7 +2,7 @@ * (C) Copyright 2013 Xilinx, Inc. * * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards - * See zynq_common.h for Zynq common configs + * See zynq-common.h for Zynq common configs * * SPDX-License-Identifier:GPL-2.0+ */ diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 412dede..274140c 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -2,7 +2,7 @@ * (C) Copyright 2013 Xilinx, Inc. * * Configuration for Zynq Evaluation and Development Board - ZedBoard - * See zynq_common.h for Zynq common configs + * See zynq-common.h for Zynq common configs * * SPDX-License-Identifier:GPL-2.0+ */ -- Acked-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] zynq: Do not explicitely enable icache
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote: icache is already enabled by default. Signed-off-by: Michal Simek michal.si...@xilinx.com --- board/xilinx/zynq/board.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index a5b9bde..08932a2 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -55,8 +55,6 @@ int board_init(void) } #endif - icache_enable(); - #ifdef CONFIG_FPGA fpga_init(); fpga_add(fpga_xilinx, fpga); -- 1.8.2.3 Acked-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] zynq: Enable dcache support
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote:
Enable dcache.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 9af340e..c771759 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -46,3 +46,11 @@ void reset_cpu(ulong addr)
while (1)
;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
--
1.8.2.3
Acked-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
--
Jagan.
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Re: [U-Boot] [PATCH 7/7] zynq: Move bootmode to headers
On Wed, Jan 22, 2014 at 2:53 PM, Michal Simek michal.si...@xilinx.com wrote:
These numbers will be reused by SPL.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/include/asm/arch-zynq/hardware.h | 6 ++
board/xilinx/zynq/board.c | 6 --
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index cd69677..1fe0448 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -21,6 +21,12 @@
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK 0xF
+#define ZYNQ_BM_NOR0x2
+#define ZYNQ_BM_SD 0x5
+#define ZYNQ_BM_JTAG 0x0
+
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 27aeaa4..82595fb 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -12,12 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Bootmode setting values */
-#define ZYNQ_BM_MASK 0x0F
-#define ZYNQ_BM_NOR0x02
-#define ZYNQ_BM_SD 0x05
-#define ZYNQ_BM_JTAG 0x0
-
#ifdef CONFIG_FPGA
Xilinx_desc fpga;
--
1.8.2.3
Acked-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
--
Jagan.
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Re: [U-Boot] how to get u-boot code with arm64: core support
Hi Bhupesh, U-boot doesn't have ARM trusted firmware support as of now. U-boot for ARMv8 starts in EL3, whereas UEFI starts in EL2 as trusted firmware itself is working in EL3. Since the ATF software doesn't really care whether it is loading uefi or u-boot and since it wants to load non-secure images as EL2 or EL1 (https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/user-guide.md See section Normal World Software Execution), why would we want to assume u-boot starts in EL3 mode by default? If we want to support EL3 execution for convenience to those that don't have ATF setup, that might make sense, but then shouldn't initial EL3 execution and subsequent switching levels be debug CONFIG options? Thanks. Regards, Darwin Rambo -- View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v15-00-10-arm64-patch-tp167751p172079.html Sent from the U-Boot mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 1/2] common: Add new clk command
On Wed, Jan 22, 2014 at 12:02 +0100, Michal Simek wrote:
--- /dev/null
+++ b/common/cmd_clk.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include common.h
+#include command.h
+#include clk.h
+
+int __weak soc_clk_dump(void)
+{
+ puts(Not implemented\n);
+ return 1;
+}
+
+static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+char *const argv[])
+{
+ return soc_clk_dump();
+}
Is there a specific reason to not pass on the remaining (not yet
consumed) command line arguments? Future implementations may
want to take a clock item's name, or a clock group's name, or
options related to the format or verbosity of the dump, et al.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de
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[U-Boot] [PATCH 5/6] ARM: tegra: MASK_BITS_ no longer needs specific values
From: Stephen Warren swar...@nvidia.com
Since all code that sets or interprets MASK_BITS_* now uses the enums
to define/compare the values, there is no need for MASK_BITS_* to have
a specific integer value. In fact, having a specific integer value may
encourage people to hard-code those values, or interpret the values in
incorrect ways.
As such, remove the logic that assigns a specific value to the enum
values in order to make it completely clear that it's just an enum, not
something that directly represents some integer value.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/include/asm/arch-tegra/clock.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index cb89bd91f40c..357d9c592b55 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -30,7 +30,7 @@ enum clock_osc_freq {
* them all together and pretends they're all 31:28.
*/
enum {
- MASK_BITS_31_30 = 2,/* num of bits used to specify clock source */
+ MASK_BITS_31_30,/* num of bits used to specify clock source */
MASK_BITS_31_29,
MASK_BITS_31_28,
};
--
1.8.1.5
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[U-Boot] [PATCH 6/6] ARM: tegra: implement MASK_BITS_31_29
From: Tom Warren twarren.nvi...@gmail.com
Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.
Signed-off-by: Tom Warren twar...@nvidia.com
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra-common/clock.c | 22 ++
arch/arm/include/asm/arch-tegra/clk_rst.h | 3 +++
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
index 96b705f2f6a4..33bb19084b8c 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id,
int source,
/* work out the source clock and set it */
if (source 0)
return -1;
- if (mux_bits == MASK_BITS_31_28) {
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
- source OUT_CLK_SOURCE_31_28_SHIFT);
- } else {
+
+ switch (mux_bits) {
+ case MASK_BITS_31_30:
clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
source OUT_CLK_SOURCE_31_30_SHIFT);
+ break;
+
+ case MASK_BITS_31_29:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+ source OUT_CLK_SOURCE_31_29_SHIFT);
+ break;
+
+ case MASK_BITS_31_28:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+ source OUT_CLK_SOURCE_31_28_SHIFT);
+ break;
+
+ default:
+ return -1;
}
+
udelay(2);
return 0;
}
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 9f81237d2865..f07b83d26af4 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -236,6 +236,9 @@ enum {
#define OUT_CLK_SOURCE_31_30_SHIFT 30
#define OUT_CLK_SOURCE_31_30_MASK (3U OUT_CLK_SOURCE_31_30_SHIFT)
+#define OUT_CLK_SOURCE_31_29_SHIFT 29
+#define OUT_CLK_SOURCE_31_29_MASK (7U OUT_CLK_SOURCE_31_29_SHIFT)
+
/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
#define OUT_CLK_SOURCE_31_28_SHIFT 28
#define OUT_CLK_SOURCE_31_28_MASK (15U OUT_CLK_SOURCE_31_28_SHIFT)
--
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[U-Boot] [PATCH] ARM: tegra: don't exceed AVP limits when configuring PLLP
From: Jimmy Zhang jimmzh...@nvidia.com
Based on the Tegra114 TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.
The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured
Signed-off-by: Jimmy Zhang jimmzh...@nvidia.com
[swarren, significantly refactored the changes, so that AVP only runs on
clk_m for the short duration that PLLP is being reconfigured. Fixed
Tegra30 too]
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/arm720t/tegra114/cpu.c | 12
arch/arm/cpu/arm720t/tegra30/cpu.c| 12
arch/arm/cpu/tegra-common/clock.c | 15 +++
arch/arm/cpu/tegra114-common/clock.c | 27 +++
arch/arm/cpu/tegra30-common/clock.c | 30 ++
arch/arm/include/asm/arch-tegra/clk_rst.h | 7 +++
arch/arm/include/asm/arch-tegra/clock.h | 2 ++
7 files changed, 81 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c
b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 7a1747a3beb8..042942f61dd4 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -126,18 +126,6 @@ void t114_init_clocks(void)
/* Set active CPU cluster to G */
clrbits_le32(flow-cluster_control, 1);
- /*
-* Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-* at 108 MHz. This is glitch free as only the source is changed, no
-* special precaution needed.
-*/
- val = (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
- (SCLK_SYS_STATE_RUN SCLK_SYS_STATE_SHIFT);
- writel(val, clkrst-crc_sclk_brst_pol);
-
writel(SUPER_SCLK_ENB_MASK, clkrst-crc_super_sclk_div);
debug(Setting up PLLX\n);
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c
b/arch/arm/cpu/arm720t/tegra30/cpu.c
index e16235748449..3c50844c12be 100644
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -84,18 +84,6 @@ void t30_init_clocks(void)
/* Set active CPU cluster to G */
clrbits_le32(flow-cluster_control, 1 0);
- /*
-* Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-* at 108 MHz. This is glitch free as only the source is changed, no
-* special precaution needed.
-*/
- val = (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
- (SCLK_SYS_STATE_RUN SCLK_SYS_STATE_SHIFT);
- writel(val, clkrst-crc_sclk_brst_pol);
-
writel(SUPER_SCLK_ENB_MASK, clkrst-crc_super_sclk_div);
val = (0 CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
index 33bb19084b8c..488721cf4de3 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -575,3 +575,18 @@ void clock_init(void)
/* Do any special system timer/TSC setup */
arch_timer_init();
}
+
+void set_avp_clock_to(u32 src)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 val;
+
+ val = (src SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+ (src SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+ (src SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+ (src SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+ (SCLK_SYS_STATE_RUN SCLK_SYS_STATE_SHIFT);
+ writel(val, clkrst-crc_sclk_brst_pol);
+ udelay(3);
+}
diff --git a/arch/arm/cpu/tegra114-common/clock.c
b/arch/arm/cpu/tegra114-common/clock.c
index 3bede71a7a1f..14d1d99cfe49 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -603,6 +603,19 @@ void clock_early_init(void)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /*
+* Based on the Tegra TRM, the system clock (which is the AVP clock) can
+* run up to 275MHz. On power on, the default sytem clock source is set
+* to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
+* 408MHz which is beyond system clock's upper limit.
+*
+* The fix is to set the system clock to CLK_M before
[U-Boot] [PATCH 3/6] ARM: tegra: rename OUT_CLK_SOURCE_*
From: Stephen Warren swar...@nvidia.com
OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to
more completely describe exactly what they represent, without having to
go look up the definitions.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra-common/clock.c | 16
arch/arm/include/asm/arch-tegra/clk_rst.h | 9 +
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
index 268fb912b502..d9f2c767d5d1 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id,
unsigned source,
value = readl(reg);
- value = ~OUT_CLK_SOURCE_MASK;
- value |= source OUT_CLK_SOURCE_SHIFT;
+ value = ~OUT_CLK_SOURCE_31_30_MASK;
+ value |= source OUT_CLK_SOURCE_31_30_SHIFT;
value = ~OUT_CLK_DIVISOR_MASK;
value |= divisor OUT_CLK_DIVISOR_SHIFT;
@@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned
source)
{
u32 *reg = get_periph_source_reg(periph_id);
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source OUT_CLK_SOURCE_SHIFT);
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+ source OUT_CLK_SOURCE_31_30_SHIFT);
}
/**
@@ -305,11 +305,11 @@ static int adjust_periph_pll(enum periph_id periph_id,
int source,
if (source 0)
return -1;
if (mux_bits == 4) {
- clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
- source OUT_CLK_SOURCE4_SHIFT);
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+ source OUT_CLK_SOURCE_31_28_SHIFT);
} else {
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source OUT_CLK_SOURCE_SHIFT);
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+ source OUT_CLK_SOURCE_31_30_SHIFT);
}
udelay(2);
return 0;
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h
b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 074b3bca0b4f..9f81237d2865 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -233,11 +233,12 @@ enum {
#define OUT_CLK_DIVISOR_SHIFT 0
#define OUT_CLK_DIVISOR_MASK (0x OUT_CLK_DIVISOR_SHIFT)
-#define OUT_CLK_SOURCE_SHIFT 30
-#define OUT_CLK_SOURCE_MASK(3U OUT_CLK_SOURCE_SHIFT)
+#define OUT_CLK_SOURCE_31_30_SHIFT 30
+#define OUT_CLK_SOURCE_31_30_MASK (3U OUT_CLK_SOURCE_31_30_SHIFT)
-#define OUT_CLK_SOURCE4_SHIFT 28
-#define OUT_CLK_SOURCE4_MASK (15U OUT_CLK_SOURCE4_SHIFT)
+/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
+#define OUT_CLK_SOURCE_31_28_SHIFT 28
+#define OUT_CLK_SOURCE_31_28_MASK (15U OUT_CLK_SOURCE_31_28_SHIFT)
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
#define SCLK_SYS_STATE_SHIFT28U
--
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[U-Boot] [PATCH 2/6] ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28
From: Stephen Warren swar...@nvidia.com
The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.
Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits about the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:29 and 29; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra114-common/clock.c| 2 +-
arch/arm/cpu/tegra30-common/clock.c | 2 +-
arch/arm/include/asm/arch-tegra/clock.h | 11 ++-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/clock.c
b/arch/arm/cpu/tegra114-common/clock.c
index 47612e12d262..3bede71a7a1f 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -103,7 +103,7 @@ static enum clock_id
clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ),CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_29_28}
+ MASK_BITS_31_28}
};
/*
diff --git a/arch/arm/cpu/tegra30-common/clock.c
b/arch/arm/cpu/tegra30-common/clock.c
index 89c3529c885b..33528702185e 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -102,7 +102,7 @@ static enum clock_id
clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_29_28}
+ MASK_BITS_31_28}
};
/*
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index 052c0208b18a..cb89bd91f40c 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,10 +20,19 @@ enum clock_osc_freq {
CLOCK_OSC_FREQ_COUNT,
};
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:29 and 29; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
enum {
MASK_BITS_31_30 = 2,/* num of bits used to specify clock source */
MASK_BITS_31_29,
- MASK_BITS_29_28,
+ MASK_BITS_31_28,
};
#include asm/arch/clock-tables.h
--
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[U-Boot] [PATCH 4/6] ARM: tegra: use MASK_BITS_* macros everywhere
From: Stephen Warren swar...@nvidia.com
Not all code that set or interpreted mux_bits was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.
Replace the integer constants with the equivalent macro definitions so
that everything is nicely tied together.
Note that I'm not convinced all the code was using the correct integer
constants, and hence I'm not convinced that all the code is now using
the desired macros. However, this change is a purely mechanical
replacement and should have no functional change. Fixing any bugs will
come later, separately.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra-common/clock.c | 2 +-
arch/arm/cpu/tegra20-common/clock.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
index d9f2c767d5d1..96b705f2f6a4 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -304,7 +304,7 @@ static int adjust_periph_pll(enum periph_id periph_id, int
source,
/* work out the source clock and set it */
if (source 0)
return -1;
- if (mux_bits == 4) {
+ if (mux_bits == MASK_BITS_31_28) {
clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
source OUT_CLK_SOURCE_31_28_SHIFT);
} else {
diff --git a/arch/arm/cpu/tegra20-common/clock.c
b/arch/arm/cpu/tegra20-common/clock.c
index 34124f9bbac3..0c4f5fb288a0 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -412,9 +412,9 @@ int get_periph_clock_source(enum periph_id periph_id,
* with its 16-bit divisor
*/
if (type == CLOCK_TYPE_PCXTS)
- *mux_bits = 4;
+ *mux_bits = MASK_BITS_31_28;
else
- *mux_bits = 2;
+ *mux_bits = MASK_BITS_31_30;
if (type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
--
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[U-Boot] [PATCH] ARM: tegra: amend pmc.h for Tegra114+
From: Stephen Warren swar...@nvidia.com
Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.
The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.
There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/arm720t/tegra114/cpu.c | 4 ++--
arch/arm/include/asm/arch-tegra/pmc.h | 8 ++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c
b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 51ecff794fb7..7a1747a3beb8 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -219,8 +219,8 @@ static int is_clamp_enabled(u32 mask)
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
- /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
- reg = readl(pmc-pmc_pwrgate_timer_on);
+ /* Get clamp status. */
+ reg = readl(pmc-pmc_clamp_status);
return (reg mask) == mask;
}
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h
b/arch/arm/include/asm/arch-tegra/pmc.h
index ba22236ee3b7..80a6aebc5fd3 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010,2011,2014
* NVIDIA Corporation www.nvidia.com
*
* SPDX-License-Identifier:GPL-2.0+
@@ -21,7 +21,11 @@ struct pmc_ctlr {
uint pmc_dpd_sample;/* _DPD_PADS_SAMPLE_0, offset 20 */
uint pmc_dpd_enable;/* _DPD_PADS_ENABLE_0, offset 24 */
uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
- uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
+ uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 28 */
+#else
+ uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */
+#endif
uint pmc_pwrgate_toggle;/* _PWRGATE_TOGGLE_0, offset 30 */
uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
uint pmc_pwrgate_status;/* _PWRGATE_STATUS_0, offset 38 */
--
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[U-Boot] [PATCH v2] mx6: Distinguish mx6dual from mx6quad
From: Fabio Estevam fabio.este...@freescale.com
Currently when we boot a mx6dual U-boot reports that it is a mx6quad.
Report it as MX6D instead:
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
Tested-by: Otavio Salvador ota...@ossystems.com.br
---
Changes since v1:
- Fix mx5 build error (Otavio)
arch/arm/cpu/armv7/mx6/soc.c | 14 +++---
arch/arm/imx-common/cpu.c | 2 ++
arch/arm/include/asm/arch-mx5/sys_proto.h | 1 +
arch/arm/include/asm/arch-mx6/sys_proto.h | 1 +
4 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0208cba..9acd8c9 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -41,14 +41,19 @@ u32 get_cpu_rev(void)
if (type != MXC_CPU_MX6SL) {
reg = readl(anatop-digprog);
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ u32 cfg = readl(scu-config) 3;
type = ((reg 16) 0xff);
if (type == MXC_CPU_MX6DL) {
- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
- u32 cfg = readl(scu-config) 3;
-
if (!cfg)
type = MXC_CPU_MX6SOLO;
}
+
+ if (type == MXC_CPU_MX6Q) {
+ if (cfg == 1)
+ type = MXC_CPU_MX6D;
+ }
+
}
reg = 0xff;/* mx6 silicon revision */
return (type 12) | (reg + 0x10);
@@ -62,6 +67,9 @@ u32 __weak get_board_rev(void)
if (type == MXC_CPU_MX6SOLO)
cpurev = (MXC_CPU_MX6DL) 12 | (cpurev 0xFFF);
+ if (type == MXC_CPU_MX6D)
+ cpurev = (MXC_CPU_MX6Q) 12 | (cpurev 0xFFF);
+
return cpurev;
}
#endif
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 9231649..a77c4de 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
switch (imxtype) {
case MXC_CPU_MX6Q:
return 6Q;/* Quad-core version of the mx6 */
+ case MXC_CPU_MX6D:
+ return 6D;/* Dual-core version of the mx6 */
case MXC_CPU_MX6DL:
return 6DL; /* Dual Lite version of the mx6 */
case MXC_CPU_MX6SOLO:
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h
b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 9949ad1..7dacc4c 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -14,6 +14,7 @@
#define MXC_CPU_MX6DL 0x61
#define MXC_CPU_MX6SOLO0x62
#define MXC_CPU_MX6Q 0x63
+#define MXC_CPU_MX6D 0x64
#define is_soc_rev(rev)((get_cpu_rev() 0xFF) - rev)
u32 get_cpu_rev(void);
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h
b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 17125a6..eda779e 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -16,6 +16,7 @@
#define MXC_CPU_MX6DL 0x61
#define MXC_CPU_MX6SOLO0x62
#define MXC_CPU_MX6Q 0x63
+#define MXC_CPU_MX6D 0x64
#define is_soc_rev(rev)((get_cpu_rev() 0xFF) - rev)
u32 get_cpu_rev(void);
--
1.8.1.2
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[U-Boot] [PATCH 1/6] ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum
From: Tom Warren twarren.nvi...@gmail.com
The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.
Signed-off-by: Tom Warren twar...@nvidia.com
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra114-common/clock.c| 6 --
arch/arm/cpu/tegra30-common/clock.c | 6 --
arch/arm/include/asm/arch-tegra/clock.h | 6 ++
3 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/clock.c
b/arch/arm/cpu/tegra114-common/clock.c
index 5c4305a418cc..47612e12d262 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -61,12 +61,6 @@ enum {
CLOCK_MAX_MUX = 8 /* number of source options for each clock */
};
-enum {
- MASK_BITS_31_30 = 2,/* num of bits used to specify clock source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
diff --git a/arch/arm/cpu/tegra30-common/clock.c
b/arch/arm/cpu/tegra30-common/clock.c
index 74bd22be1aeb..89c3529c885b 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -60,12 +60,6 @@ enum {
CLOCK_MAX_MUX = 8 /* number of source options for each clock */
};
-enum {
- MASK_BITS_31_30 = 2,/* num of bits used to specify clock source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index e7d0fd45ee1d..052c0208b18a 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,6 +20,12 @@ enum clock_osc_freq {
CLOCK_OSC_FREQ_COUNT,
};
+enum {
+ MASK_BITS_31_30 = 2,/* num of bits used to specify clock source */
+ MASK_BITS_31_29,
+ MASK_BITS_29_28,
+};
+
#include asm/arch/clock-tables.h
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
--
1.8.1.5
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Re: [U-Boot] [PATCH 5/5] NAND: DaVinci: allow forced disable of subpage writes
On Mon, 2014-01-20 at 17:10 -0500, Murali Karicheri wrote: This patch introduces a configurable mechanism to disable subpage writes in the DaVinci NAND driver. Signed-off-by: Vitaly Andrianov vita...@ti.com Signed-off-by: Murali Karicheri m-kariche...@ti.com --- drivers/mtd/nand/davinci_nand.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 5b17d7b..75b03a7 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -609,6 +609,9 @@ void davinci_nand_init(struct nand_chip *nand) #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand-bbt_options |= NAND_BBT_USE_FLASH; #endif +#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE + nand-options |= NAND_NO_SUBPAGE_WRITE; +#endif #ifdef CONFIG_SYS_NAND_HW_ECC nand-ecc.mode = NAND_ECC_HW; nand-ecc.size = 512; Why does it need to be configurable? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum
Stephen,
On Wed, Jan 22, 2014 at 1:20 PM, Stephen Warren swar...@wwwdotorg.orgwrote:
From: Tom Warren twarren.nvi...@gmail.com
The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.
Signed-off-by: Tom Warren twar...@nvidia.com
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren swar...@nvidia.com
---
arch/arm/cpu/tegra114-common/clock.c| 6 --
arch/arm/cpu/tegra30-common/clock.c | 6 --
arch/arm/include/asm/arch-tegra/clock.h | 6 ++
3 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/tegra114-common/clock.c
b/arch/arm/cpu/tegra114-common/clock.c
index 5c4305a418cc..47612e12d262 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -61,12 +61,6 @@ enum {
CLOCK_MAX_MUX = 8 /* number of source options for each clock
*/
};
-enum {
- MASK_BITS_31_30 = 2,/* num of bits used to specify clock
source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
diff --git a/arch/arm/cpu/tegra30-common/clock.c
b/arch/arm/cpu/tegra30-common/clock.c
index 74bd22be1aeb..89c3529c885b 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -60,12 +60,6 @@ enum {
CLOCK_MAX_MUX = 8 /* number of source options for each clock
*/
};
-enum {
- MASK_BITS_31_30 = 2,/* num of bits used to specify clock
source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index e7d0fd45ee1d..052c0208b18a 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,6 +20,12 @@ enum clock_osc_freq {
CLOCK_OSC_FREQ_COUNT,
};
+enum {
+ MASK_BITS_31_30 = 2,/* num of bits used to specify clock
source */
+ MASK_BITS_31_29,
+ MASK_BITS_29_28,
+};
+
#include asm/arch/clock-tables.h
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
--
1.8.1.5
Thanks for doing these patches - nice job. LGTM.
Applies cleanly to u-boot-tegra/next after applying Alban's 2 patches, your
other 3 patches, and then this series of 6. Building all now, I'll test
later.
Tom
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Re: [U-Boot] [PATCH 1/6] ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum
On 01/22/2014 02:35 PM, Tom Warren wrote: ... Thanks for doing these patches - nice job. LGTM. Applies cleanly to u-boot-tegra/next after applying Alban's 2 patches, your other 3 patches, and then this series of 6. Building all now, I'll test later. Great! Just FYI, I tested MMC and DHCP (USB net) boot on all of Springbank, Cardhu, Dalmore, Venice2 with these patches, your Tegra124 series, plus the other pxe/extlinux/... stuff I've been working on all applied. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum
On Wed, Jan 22, 2014 at 2:54 PM, Stephen Warren swar...@wwwdotorg.orgwrote: On 01/22/2014 02:35 PM, Tom Warren wrote: ... Thanks for doing these patches - nice job. LGTM. Applies cleanly to u-boot-tegra/next after applying Alban's 2 patches, your other 3 patches, and then this series of 6. Building all now, I'll test later. Great! Just FYI, I tested MMC and DHCP (USB net) boot on all of Springbank, Cardhu, Dalmore, Venice2 with these patches, your Tegra124 series, plus the other pxe/extlinux/... stuff I've been working on all applied. Great - I'd assumed you'd been thorough in your testing! I'd like to have someone else ACK these patches before I commit them to u-boot-tegra/next. The only one of the 11 pending Tegra patches I mentioned that's got an Acked-by is Alban's pullid patch. Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] serial: sh: Add Support R7S72100 of rmobile
The R7S72100 has same IP as serial with SH.
This adds support R7S72100 to serial_sh.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/serial/serial_sh.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index f5e9854..612e113 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -203,7 +203,7 @@ struct uart_port {
# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
# endif
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7269)
+#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_R7S72100)
# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
@@ -213,6 +213,7 @@ struct uart_port {
# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_CPU_SH7619)
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
--
1.8.5
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[U-Boot] [PATCH 1/3] net: sh-eth: Add support R7S72100 of rmobile
The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 10 ---
drivers/net/sh_eth.h | 81 +---
2 files changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 5e132f2..0cb963f 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -148,7 +148,7 @@ int sh_eth_recv(struct eth_device *dev)
static int sh_eth_reset(struct sh_eth_dev *eth)
{
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
@@ -218,7 +218,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the tx descriptor list. Must use physical
addresses */
sh_eth_write(eth, ADDR_TO_PHY(port_info-tx_desc_base), TDLAR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info-tx_desc_base), TDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
@@ -288,7 +288,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the rx descriptor list */
sh_eth_write(eth, ADDR_TO_PHY(port_info-rx_desc_base), RDLAR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info-rx_desc_base), RDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
sh_eth_write(eth, RDFFR_RDLF, RDFFR);
@@ -384,7 +384,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
sh_eth_write(eth, 0, TFTR);
sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
sh_eth_write(eth, RMCR_RST, RMCR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, 0, RPADIR);
#endif
sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
@@ -403,6 +403,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, 0, PIPR);
+#endif
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, APR_AP, APR);
sh_eth_write(eth, MPR_MP, MPR);
sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 331c07c..0925759 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -230,6 +230,61 @@ static const u16
sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMII_MII] = 0x0790,
};
+#if defined(SH_ETH_TYPE_RZ)
+static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
+ [EDSR] = 0x,
+ [EDMR] = 0x0400,
+ [EDTRR] = 0x0408,
+ [EDRRR] = 0x0410,
+ [EESR] = 0x0428,
+ [EESIPR]= 0x0430,
+ [TDLAR] = 0x0010,
+ [TDFAR] = 0x0014,
+ [TDFXR] = 0x0018,
+ [TDFFR] = 0x001c,
+ [RDLAR] = 0x0030,
+ [RDFAR] = 0x0034,
+ [RDFXR] = 0x0038,
+ [RDFFR] = 0x003c,
+ [TRSCER]= 0x0438,
+ [RMFCR] = 0x0440,
+ [TFTR] = 0x0448,
+ [FDR] = 0x0450,
+ [RMCR] = 0x0458,
+ [RPADIR]= 0x0460,
+ [FCFTR] = 0x0468,
+ [CSMR] = 0x04E4,
+
+ [ECMR] = 0x0500,
+ [ECSR] = 0x0510,
+ [ECSIPR]= 0x0518,
+ [PSR] = 0x0528,
+ [PIPR] = 0x052c,
+ [RFLR] = 0x0508,
+ [APR] = 0x0554,
+ [MPR] = 0x0558,
+ [PFTCR] = 0x055c,
+ [PFRCR] = 0x0560,
+ [TPAUSER] = 0x0564,
+ [GECMR] = 0x05b0,
+ [BCULR] = 0x05b4,
+ [MAHR] = 0x05c0,
+ [MALR] = 0x05c8,
+ [TROCR] = 0x0700,
+ [CDCR] = 0x0708,
+ [LCCR] = 0x0710,
+ [CEFCR] = 0x0740,
+ [FRECR] = 0x0748,
+ [TSFRCR]= 0x0750,
+ [TLFRCR]= 0x0758,
+ [RFCR] = 0x0760,
+ [CERCR] = 0x0768,
+ [CEECR] = 0x0770,
+ [MAFCR] = 0x0778,
+ [RMII_MII] = 0x0790,
+};
+#endif
+
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100,
[RFLR] = 0x0108,
@@ -306,13 +361,16 @@ static const u16
sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
+#elif defined(CONFIG_R7S72100)
+#define SH_ETH_TYPE_RZ
+#define BASE_IO_ADDR 0xE8203000
#endif
/*
* Register's bits
* Copy from Linux driver source code
*/
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
/* EDSR */
enum EDSR_BIT {
[U-Boot] [PATCH 2/3] net: sh-eth: Fix coding style
This fixes checkpatch's warning.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 35 ++-
drivers/net/sh_eth.h | 9 -
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 0cb963f..81e8ddb 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -67,7 +67,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
/* packet must be a 4 byte boundary */
if ((int)packet 3) {
- printf(SHETHER_NAME : %s: packet not 4 byte alligned\n,
__func__);
+ printf(SHETHER_NAME : %s: packet not 4 byte alligned\n
+ , __func__);
ret = -EFAULT;
goto err;
}
@@ -156,7 +157,7 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
/* Perform a software reset and wait for it to complete */
sh_eth_write(eth, EDMR_SRST, EDMR);
- for (i = 0; i TIMEOUT_CNT ; i++) {
+ for (i = 0; i TIMEOUT_CNT; i++) {
if (!(sh_eth_read(eth, EDMR) EDMR_SRST))
break;
udelay(1000);
@@ -523,41 +524,41 @@ void sh_eth_halt(struct eth_device *dev)
int sh_eth_initialize(bd_t *bd)
{
-int ret = 0;
+ int ret = 0;
struct sh_eth_dev *eth = NULL;
-struct eth_device *dev = NULL;
+ struct eth_device *dev = NULL;
-eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
+ eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
printf(SHETHER_NAME : %s: malloc failed\n, __func__);
ret = -ENOMEM;
goto err;
}
-dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev) {
printf(SHETHER_NAME : %s: malloc failed\n, __func__);
ret = -ENOMEM;
goto err;
}
-memset(dev, 0, sizeof(struct eth_device));
-memset(eth, 0, sizeof(struct sh_eth_dev));
+ memset(dev, 0, sizeof(struct eth_device));
+ memset(eth, 0, sizeof(struct sh_eth_dev));
eth-port = CONFIG_SH_ETHER_USE_PORT;
eth-port_info[eth-port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
-dev-priv = (void *)eth;
-dev-iobase = 0;
-dev-init = sh_eth_init;
-dev-halt = sh_eth_halt;
-dev-send = sh_eth_send;
-dev-recv = sh_eth_recv;
-eth-port_info[eth-port].dev = dev;
+ dev-priv = (void *)eth;
+ dev-iobase = 0;
+ dev-init = sh_eth_init;
+ dev-halt = sh_eth_halt;
+ dev-send = sh_eth_send;
+ dev-recv = sh_eth_recv;
+ eth-port_info[eth-port].dev = dev;
sprintf(dev-name, SHETHER_NAME);
-/* Register Device to EtherNet subsystem */
-eth_register(dev);
+ /* Register Device to EtherNet subsystem */
+ eth_register(dev);
bb_miiphy_buses[0].priv = eth;
miiphy_register(dev-name, bb_miiphy_read, bb_miiphy_write);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 0925759..2909659 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -452,7 +452,6 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
/* EESR */
enum EESR_BIT {
-
#if defined(SH_ETH_TYPE_ETHER)
EESR_TWB = 0x4000,
#else
@@ -560,8 +559,8 @@ enum RECV_RST_BIT { RMCR_RST = 0x01, };
/* ECMR */
enum FELIC_MODE_BIT {
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
- ECMR_TRCCM=0x0400, ECMR_RCSC= 0x0080, ECMR_DPAD= 0x0020,
- ECMR_RZPF = 0x0010,
+ ECMR_TRCCM = 0x0400, ECMR_RCSC = 0x0080,
+ ECMR_DPAD = 0x0020, ECMR_RZPF = 0x0010,
#endif
ECMR_ZPF = 0x0008, ECMR_PFR = 0x0004, ECMR_RXF = 0x0002,
ECMR_TXF = 0x0001, ECMR_MCT = 0x2000, ECMR_PRCEF = 0x1000,
@@ -577,8 +576,8 @@ enum FELIC_MODE_BIT {
};
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
-#define ECMR_CHG_DM(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR |
ECMR_RXF | \
- ECMR_TXF | ECMR_MCT)
+#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
+ ECMR_RXF | ECMR_TXF | ECMR_MCT)
#elif defined(SH_ETH_TYPE_ETHER)
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
--
1.8.5
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[U-Boot] [PATCH 3/3] net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLF
'r' of rESR_RTLF is a mistake of E.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 2909659..d0d9aaa 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -476,7 +476,7 @@ enum EESR_BIT {
EESR_CD = 0x0200, EESR_RTO = 0x0100,
EESR_RMAF = 0x0080, EESR_CEEF = 0x0040,
EESR_CELF = 0x0020, EESR_RRF = 0x0010,
- rESR_RTLF = 0x0008, EESR_RTSF = 0x0004,
+ EESR_RTLF = 0x0008, EESR_RTSF = 0x0004,
EESR_PRE = 0x0002, EESR_CERF = 0x0001,
};
--
1.8.5
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Re: [U-Boot] [PATCH 3/8] Tegra124: Add SPL/AVP (arm720t) cpu files
On 10/08/2013 02:13 AM, Thierry Reding wrote: On Tue, Oct 08, 2013 at 12:42:53AM +0200, Tom Warren wrote: This provides SPL support for T124 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. +#if defined(CONFIG_TEGRA124) + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + /* Disable IDDQ */ + reg = readl(clkrst-crc_pllx_misc3); + reg = ~PLLX_IDDQ_MASK; + writel(reg, clkrst-crc_pllx_misc3); + udelay(2); + debug(%s: IDDQ: PLLX IDDQ = 0x%08X\n, __func__, + readl(clkrst-crc_pllx_misc3)); +#endif /* T124 */ Perhaps this should be moved to a separate function that can be provided as a dummy for non-Tegra124? (I'm working on finalizing this patch for submission now) I think it's fine for the core driver to know about the different SoCs. A simple ifdef like this is quite manageable. If the code starts to get unmanageable, or does a lot of things that aren't common across chips, we can always split it out into the SoC-specific files. +void pmic_enable_cpu_vdd(void); This doesn't seem to exist until patch 8. Perhaps this should really be an weak function so that it always exists but can still be overwritten by individual boards? The build of these files isn't enabled until the last patch anyway, so it's all perfectly bisectable. I'm not included to do anything to fix this unless you feel strongly.. I'll fix up all the other issues you mentioned. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: tegra: don't exceed AVP limits when configuring PLLP
On 01/22/2014 01:21 PM, Stephen Warren wrote: From: Jimmy Zhang jimmzh...@nvidia.com Based on the Tegra114 TRM, the system clock (which is the AVP clock) can run up to 275MHz. On power on, the default sytem clock source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 408MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP, and then switch back to PLLP_OUT4, which has an appropriate divider configured, after PLLP has been configured Signed-off-by: Jimmy Zhang jimmzh...@nvidia.com [swarren, significantly refactored the changes, so that AVP only runs on clk_m for the short duration that PLLP is being reconfigured. Fixed Tegra30 too] I think I need to revise this one patch; while going through the Tegra124 patches, I found function adjust_pllp_out_freqs(), which really should be used by this patch. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] File system API: Read file size without reading file contents
Hi All, I would like to read a configuration file from an ext4 disk partition in u-boot and parse its contents. In order to malloc a buffer of sufficient size to read the entire file contents, I would need to know the file size before actually reading it. As far as I understand, the current struct fstype_info API does not allow me to do that (other than parsing the ls output). While the read function does in fact return the file size, it does so only after the file was already read into memory. Lower level functions for ext4 such as ext4fs_open() do however provide this information before reading the file contents. Unless there is something that I have missed, how would you feel about me adding a .size function to the struct fstype_info API to expose this information on the top-level API? Thanks, Frank ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v15 07/10] arm64: core support
On Tue, 2014-01-14 at 09:52 +0800, FengHua wrote: hi bhupesh, Hi David, In reference to my mail above, I see that the transition to EL2 (from EL3) which occurs very early in start.S needs to be changed on lines of the ARMv7 code, i.e. the EL2 transition should happen just before Linux is booted up by the u-boot. The reason for the same is that a no of ARM IPs like GIC, SMMU and TZPC/TZASC need to be configured to allow non-secure accesses from Linux world (which runs in EL1 mode). Adding the assembly code for all such IPs in 'setup_el3' function in start.S, will bloat the start.S and also increase the chances of a bug in the assembly code. Hence, I would like to propose a strategy to shift from EL3 to EL2 to some point in u-boot code after the C Run Time has been initialized (similar to present ARMv7 u-boot code). If you are ok with the same, I can try to send out some RFC patches rebased against your latest v16 code-base. Please let me know. Regards, Bhupesh Actually, patch v16 did exception level switch in the way as you said. please review the code. Both master and slaves switch to el2(el1) just before jumping to linux kernel. BTW,if any good conception please feel free to patch it. How would you handle running U-Boot under a secure firmware, or under a hypervisor? Why not take the Linux approach of running most code in EL1, with exception handlers pointing at code to handle special situations (such as returning to EL2 before OS entry)? As for bloating start.S, could leaving EL3 be done in early C code rather than in early asm or late C code? Or, bundle U-Boot with a tiny insecure firmware that provides the minimum functionality needed with similar APIs that would be used with real secure firmware. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v15 07/10] arm64: core support
On 14-01-22 04:29 PM, Scott Wood-2 [via U-Boot] wrote: On Tue, 2014-01-14 at 09:52 +0800, FengHua wrote: hi bhupesh, Hi David, In reference to my mail above, I see that the transition to EL2 (from EL3) which occurs very early in start.S needs to be changed on lines of the ARMv7 code, i.e. the EL2 transition should happen just before Linux is booted up by the u-boot. The reason for the same is that a no of ARM IPs like GIC, SMMU and TZPC/TZASC need to be configured to allow non-secure accesses from Linux world (which runs in EL1 mode). Adding the assembly code for all such IPs in 'setup_el3' function in start.S, will bloat the start.S and also increase the chances of a bug in the assembly code. Hence, I would like to propose a strategy to shift from EL3 to EL2 to some point in u-boot code after the C Run Time has been initialized (similar to present ARMv7 u-boot code). If you are ok with the same, I can try to send out some RFC patches rebased against your latest v16 code-base. Please let me know. Regards, Bhupesh Actually, patch v16 did exception level switch in the way as you said. please review the code. Both master and slaves switch to el2(el1) just before jumping to linux kernel. BTW,if any good conception please feel free to patch it. How would you handle running U-Boot under a secure firmware, or under a hypervisor? Why not take the Linux approach of running most code in EL1, with exception handlers pointing at code to handle special situations (such as returning to EL2 before OS entry)? As for bloating start.S, could leaving EL3 be done in early C code rather than in early asm or late C code? Or, bundle U-Boot with a tiny insecure firmware that provides the minimum functionality needed with similar APIs that would be used with real secure firmware. Hi Scott, Why is any EL3 code in u-boot at all? That's not the ARM ATF approach I believe but I'm not an expert in this. Please see http://lists.denx.de/pipermail/u-boot/2014-January/171581.html and (https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/user-guide.md See section Normal World Software Execution) Thanks. Darwin -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ If you reply to this email, your message will be added to the discussion below: http://u-boot.10912.n7.nabble.com/PATCH-v15-00-10-arm64-patch-tp167751p172101.html To unsubscribe from [PATCH v15 00/10] arm64 patch, visit http://u-boot.10912.n7.nabble.com/template/NamlServlet.jtp?macro=unsubscribe_by_codenode=167751code=ZHJhbWJvQGJyb2FkY29tLmNvbXwxNjc3NTF8LTQ0Nzc3MTIxNQ== -- View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v15-00-10-arm64-patch-tp167751p172102.html Sent from the U-Boot mailing list archive at Nabble.com.___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3 V3] esdhc: Workaround for card can't be detected on T4240QDS
Many thanks. Pantelis and York How about below patch? http://patchwork.ozlabs.org/patch/283002/ It's about esdhc, but is in york's backyard. Regards Haijun On 01/22/2014 08:01 PM, Pantelis Antoniou wrote: Hi York, On Jan 22, 2014, at 12:01 AM, York Sun wrote: Pantelis, On 01/09/2014 09:52 PM, Haijun Zhang wrote: Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- changes for V3: - Define quirk in board specific file instead of code in driver changes for V2: - Add the judgement condition for this broken card I think this set of patches are in your backyard. If you ack them, I can apply them to mpc85xx. Go ahead please. http://patchwork.ozlabs.org/patch/309168/ http://patchwork.ozlabs.org/patch/309167/ http://patchwork.ozlabs.org/patch/309170/ York Regards -- Pantelis ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] How to perform a secure boot on ARM Linux
+Tom Hi, On 20 January 2014 11:47, Marek Vasut ma...@denx.de wrote: On Monday, January 20, 2014 at 01:40:52 PM, rakesh ranjan wrote: Hi, I have a beagle board and want to create a u-boot that verifies the kernel and rootfs before booting it. Any pointers on how it can be achieved will be appreciated. Rakesh See doc/uImage.FIT/verified-boot.txt and doc/uImage.FIT/signature.txt in the source tree . Final suggestion - also see this post: https://plus.google.com/103658573279088224166/posts/NDgYtMnmAge The actual patches did not make it into the release, but hopefully next time. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] File system API: Read file size without reading file contents
+Stephen Hi Frank, On 22 January 2014 16:01, Frank Bormann fborm...@yahoo.com wrote: Hi All, I would like to read a configuration file from an ext4 disk partition in u-boot and parse its contents. In order to malloc a buffer of sufficient size to read the entire file contents, I would need to know the file size before actually reading it. As far as I understand, the current struct fstype_info API does not allow me to do that (other than parsing the ls output). While the read function does in fact return the file size, it does so only after the file was already read into memory. Lower level functions for ext4 such as ext4fs_open() do however provide this information before reading the file contents. Unless there is something that I have missed, how would you feel about me adding a .size function to the struct fstype_info API to expose this information on the top-level API? Perhaps .filesize, but this sounds reasonable to me. Regards, Simon Thanks, Frank ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] imx6: ensure AHB clock is 132MHz in low freq boot mode
For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and i.MX6SL EVK board.
Reviewed-by: Fabio Estevam fabio.este...@freescale.com
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/cpu/armv7/mx6/soc.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 0208cba..33a2939 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -177,10 +177,30 @@ static void imx_set_wdog_powerdown(bool enable)
writew(enable, wdog2-wmcr);
}
+static void set_ahb_rate(u32 val)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg, div;
+
+ div = get_periph_clk() / val - 1;
+ reg = readl(mxc_ccm-cbcdr);
+
+ writel((reg (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
+ (div MXC_CCM_CBCDR_AHB_PODF_OFFSET), mxc_ccm-cbcdr);
+}
+
int arch_cpu_init(void)
{
init_aips();
+ /*
+* When low freq boot is enabled, ROM will not set AHB
+* freq, so we need to ensure AHB freq is 132MHz in such
+* scenario.
+*/
+ if (mxc_get_clock(MXC_ARM_CLK) == 39600)
+ set_ahb_rate(13200);
+
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
--
1.7.9.5
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[U-Boot] [PATCH 2/2] imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failure
Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2),
it will cause warm reset fail, need to clear this MMDC_CHx_MASK field
to make sure all the i.MX6 series SOCs reset function work. Otherwise,
uboot reset command will fail, tested on i.MX6SL EVK board with TO1.2.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/cpu/armv7/mx6/soc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 33a2939..2b162c2 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -189,10 +189,21 @@ static void set_ahb_rate(u32 val)
(div MXC_CCM_CBCDR_AHB_PODF_OFFSET), mxc_ccm-cbcdr);
}
+static void clear_mmdc_ch_mask()
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* Clear MMDC channel mask */
+ writel(0, mxc_ccm-ccdr);
+}
+
int arch_cpu_init(void)
{
init_aips();
+ /* Need to clear MMDC_CHx_MASK to make warm reset work. */
+ clear_mmdc_ch_mask();
+
/*
* When low freq boot is enabled, ROM will not set AHB
* freq, so we need to ensure AHB freq is 132MHz in such
--
1.7.9.5
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[U-Boot] U-boot for 64bit ARMv8
Hi, experts: I found ARMv8/Exceptions.S only created a 8 items vector table. But based on ARMv8 Arch Ref Manual, it should create 16 items in a vector table: Current Exception level with SP_EL0 : 4 items Current Exception level with SP_Elx : 4 items EL immediately lower than target_EL is using AARCH64 : 4 items EL immediately lower than target_EL is using AARCH32 : 4 items Are current 8 items enough? Or will patch it in the future? Best wishes, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Warnings on arm64 build
Hello aarch64 experts,
Since commit 3865ceb (vexpress/armv7: Fix incorrect ethernet controller),
I have many warning messages when I compile vexpress board.
smc9.c: In function ‘poll4int’:
smc9.h:252:25: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
#define SMC_inw(a,r) (*((volatile word *)((a)-iobase+(r
^
smc9.c:242:18: note: in expansion of macro ‘SMC_inw’
word old_bank = SMC_inw (dev, BSR_REG);
^
smc9.h:261:28: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
#define SMC_outw(a,d,r) (*((volatile word *)((a)-iobase+(r))) = d)
^
smc9.h:747:33: note: in expansion of macro ‘SMC_outw’
#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
Best Regards
Masahiro Yamada
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Re: [U-Boot] how to get u-boot code with arm64: core support
Hi Darwin, -Original Message- From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On Behalf Of drambo Sent: Thursday, January 23, 2014 12:32 AM To: u-boot@lists.denx.de Subject: Re: [U-Boot] how to get u-boot code with arm64: core support Hi Bhupesh, U-boot doesn't have ARM trusted firmware support as of now. U-boot for ARMv8 starts in EL3, whereas UEFI starts in EL2 as trusted firmware itself is working in EL3. Since the ATF software doesn't really care whether it is loading uefi or u-boot and since it wants to load non-secure images as EL2 or EL1 (https://github.com/ARM-software/arm-trusted- firmware/blob/master/docs/user-guide.md See section Normal World Software Execution), why would we want to assume u-boot starts in EL3 mode by default? If we want to support EL3 execution for convenience to those that don't have ATF setup, that might make sense, but then shouldn't initial EL3 execution and subsequent switching levels be debug CONFIG options? Thanks. In the past I remember using u-boot as the bare-metal s/w to debug a Silicon without any BootROM/firmware code running before the same on ARM 32-bit architectures. The ATF is presently tested only for UEFI and UEFI comes up in EL2 while the ATF itself is running in EL3. I don't know what would be the popular vote on this, but personally I feel that the u-boot for ARMv8 should also be launched by the ATF (similar to UEFI) and should start execution in EL2 so that it can launch a hypervisor (running in EL2) or Linux (running in EL1). But this might hurt the popular premise that u-boot can be used as a bare-metal s/w to debug a silicon without additional firmware components. Perhaps u-boot experts can guide us on this ! Regards, Bhupesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Warnings on arm64 build
Hi Mashiro,
-Original Message-
From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
On Behalf Of Masahiro Yamada
Sent: Thursday, January 23, 2014 12:38 PM
To: u-boot@lists.denx.de
Subject: [U-Boot] Warnings on arm64 build
Hello aarch64 experts,
Since commit 3865ceb (vexpress/armv7: Fix incorrect ethernet controller),
I have many warning messages when I compile vexpress board.
smc9.c: In function 'poll4int':
smc9.h:252:25: warning: cast to pointer from integer of different
size [-Wint-to-pointer-cast] #define SMC_inw(a,r) (*((volatile word
*)((a)-iobase+(r
^
smc9.c:242:18: note: in expansion of macro 'SMC_inw'
word old_bank = SMC_inw (dev, BSR_REG);
^
smc9.h:261:28: warning: cast to pointer from integer of different
size [-Wint-to-pointer-cast] #define SMC_outw(a,d,r) (*((volatile word
*)((a)-iobase+(r))) = d)
^
smc9.h:747:33: note: in expansion of macro 'SMC_outw'
#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
These are issues with the SMSC91c111 driver highlighted when trying to compile
for ARM64.
I can try to fix the same, but will need some time to do the same, plus I don't
have additional
platforms to test the same.
Regards,
Bhupesh
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Re: [U-Boot] [RFC PATCH 1/2] common: Add new clk command
On 01/22/2014 08:44 PM, Gerhard Sittig wrote:
On Wed, Jan 22, 2014 at 12:02 +0100, Michal Simek wrote:
--- /dev/null
+++ b/common/cmd_clk.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include common.h
+#include command.h
+#include clk.h
+
+int __weak soc_clk_dump(void)
+{
+puts(Not implemented\n);
+return 1;
+}
+
+static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+return soc_clk_dump();
+}
Is there a specific reason to not pass on the remaining (not yet
consumed) command line arguments? Future implementations may
want to take a clock item's name, or a clock group's name, or
options related to the format or verbosity of the dump, et al.
Only one reason is that I don't need it for my zynq implementation.
If this is necessary there is no problem to pass them because
it is internal API. Also I prefer to pass just arguments
which I need.
I have looked at i.MXes cases and they do in general what
my zynq implementation. They can just include clk.h and
change do_mx6_showclocks to soc_clk_dump.
Thanks,
Michal
--
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
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Re: [U-Boot] how to get u-boot code with arm64: core support
Hi, bhupesh and drambo: I think current uboot ARMv8's start.S could handle EL2/EL1 case. I have tested it on FVP model, let arm trusted firmware boot u-boot.bin. It seemed ok. The command I used is: ./Foundation_v8 --cores=4 --no-secure-memory --no-gicv3 --data=./bl1.bin@0x0 --nsdata=./u-boot.bin@0x0800 I changed CONFIG_SYS_TEXT_BASE = 0x0800 (because ARM trusted firmware will search non-secure firmware entry point at this addr). Best wishes, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] blackfin: Change SMC dcplb entry flag to cover 16M address region
From: Sonic Zhang sonic.zh...@analog.com Signed-off-by: Sonic Zhang sonic.zh...@analog.com --- arch/blackfin/lib/board.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 392d72d..facbc7a 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -142,7 +142,8 @@ void init_cplbtables(void) ++i; #if defined(__ADSPBF60x__) icplb_add(0x0, 0x0); - dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY | + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID); ++i; #endif -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] blackfin: init bss early
From: Bob Liu lliu...@gmail.com Signed-off-by: Bob Liu lliu...@gmail.com Signed-off-by: Sonic Zhang sonic.zh...@analog.com --- arch/blackfin/cpu/start.S |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index 90b4d1a..b7c1c3a 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -195,6 +195,7 @@ ENTRY(_start) call _memcpy_ASM; #endif +.Lnorelocate: /* Initialize BSS section ... we know that memset() does not * use the BSS, so it is safe to call here. The bootrom LDR * takes care of clearing things for us. @@ -207,7 +208,6 @@ ENTRY(_start) r2.h = __bss_len; call _memset; -.Lnorelocate: /* Setup the actual stack in external memory */ sp.h = HI(CONFIG_STACKBASE); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc: Enabled quirk SDHCI_QUIRK_BROKEN_R1B
From: Siva Durga Prasad Paladugu siva.durga.palad...@xilinx.com As per the below commit mmc: sdhci: add the quirk for broken r1b response (sha1: 3a6383207be3f71b39004e64464a6e99290b16fa) need to add quirk SDHCI_QUIRK_BROKEN_R1B, when the response type is R1b. Signed-off-by: Siva Durga Prasad Paladugu siva...@xilinx.com Signed-off-by: Michal Simek michal.si...@xilinx.com Acked-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- drivers/mmc/zynq_sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 610bef5..72a272f 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -23,7 +23,8 @@ int zynq_sdhci_init(u32 regbase) host-name = zynq_sdhci; host-ioaddr = (void *)regbase; - host-quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD; + host-quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD | + SDHCI_QUIRK_BROKEN_R1B; host-version = sdhci_readw(host, SDHCI_HOST_VERSION); host-host_caps = MMC_MODE_HC; -- 1.8.2.3 pgpSgth1NLYSR.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fpga: zynq: Correct fpga load when buf is not aligned
From: Novasys Ingenierie xil...@novasys-ingenierie.com
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.
A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.
Signed-off-by: Stany MARCEL smar...@novasys-ingenierie.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/fpga/zynqpl.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 1effbad..15900c9 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -187,6 +187,16 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t
bsize)
if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+ /*
+* This might be dangerous but permits to flash if
+* ARCH_DMA_MINALIGN is greater than header size
+*/
+ if (new_buf buf_start) {
+ debug(%s: Aligned buffer is after buffer start\n,
+ __func__);
+ new_buf -= ARCH_DMA_MINALIGN;
+ }
+
printf(%s: Align buffer at %x to %x(swap %d)\n, __func__,
(u32)buf_start, (u32)new_buf, swap);
--
1.8.2.3
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[U-Boot] [PATCH] blackfin: Initialize the EMAC VLAN with proper default value
From: Aaron Wu aaron...@analog.com EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in the kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot. Signed-off-by: Aaron Wu aaron...@analog.com Signed-off-by: Sonic Zhang sonic.zh...@analog.com --- arch/blackfin/include/asm/mach-common/bits/emac.h |3 +++ drivers/net/bfin_mac.c|2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h index 7a43bbb..4c9bc9d 100644 --- a/arch/blackfin/include/asm/mach-common/bits/emac.h +++ b/arch/blackfin/include/asm/mach-common/bits/emac.h @@ -217,4 +217,7 @@ #defineTX_GE1024_CNT 0x0020 /* 1024-Max-Byte TX Frames Sent */ #defineTX_ABORT_CNT0x0040 /* TX Frames Aborted */ +/*default value for EMAC_VLANx reg*/ +#define EMAC_VLANX_DEF_VAL 0x + #endif diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 0ffd59d..42e208c 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -259,6 +259,8 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) *opmode = 0; bfin_write_EMAC_MMC_CTL(RSTC | CROLL); + bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL); + bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL); /* Initialize the TX DMA channel registers */ bfin_write_DMA2_X_COUNT(0); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] i2c: zynq: Support for 0-length register address
From: Michael Burr michael.b...@logicpd.com
Fixed bug with alen == 0 in 'i2c_write', 'i2c_read'
Further minor corrections:
- Write 'address' register before 'data' register.
- Write 'transfer_size' register before 'address' register.
Signed-off-by: Michael Burr michael.b...@logicpd.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Fix incorrect rebase
Changes in v1:
- Based on original thread from Michael Burr
http://lists.denx.de/pipermail/u-boot/2013-October/165060.html
- MS rebase on latestgreatest
drivers/i2c/zynq_i2c.c | 42 +++---
1 file changed, 23 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index 70a9aea..11ef0f8 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -189,20 +189,22 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8
dev, uint addr,
* Temporarily disable restart (by clearing hold)
* It doesn't seem to work.
*/
- clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_RW |
- ZYNQ_I2C_CONTROL_HOLD);
+ clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_HOLD);
writel(0xFF, zynq_i2c-interrupt_status);
- while (alen--)
- writel(addr (8*alen), zynq_i2c-data);
- writel(dev, zynq_i2c-address);
+ if (alen) {
+ clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_RW);
+ writel(dev, zynq_i2c-address);
+ while (alen--)
+ writel(addr (8 * alen), zynq_i2c-data);
- /* Wait for the address to be sent */
- if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
- /* Release the bus */
- clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_HOLD);
- return -ETIMEDOUT;
+ /* Wait for the address to be sent */
+ if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+ /* Release the bus */
+ clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_HOLD);
+ return -ETIMEDOUT;
+ }
+ debug(Device acked address\n);
}
- debug(Device acked address\n);
setbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_CLR_FIFO |
ZYNQ_I2C_CONTROL_RW);
@@ -247,17 +249,19 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8
dev, uint addr,
ZYNQ_I2C_CONTROL_HOLD);
clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_RW);
writel(0xFF, zynq_i2c-interrupt_status);
- while (alen--)
- writel(addr (8*alen), zynq_i2c-data);
- /* Start the tranfer */
writel(dev, zynq_i2c-address);
- if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
- /* Release the bus */
- clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_HOLD);
- return -ETIMEDOUT;
+ if (alen) {
+ while (alen--)
+ writel(addr (8 * alen), zynq_i2c-data);
+ /* Start the tranfer */
+ if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+ /* Release the bus */
+ clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_HOLD);
+ return -ETIMEDOUT;
+ }
+ debug(Device acked address\n);
}
- debug(Device acked address\n);
while (length--) {
writel(*(cur_data++), zynq_i2c-data);
if (readl(zynq_i2c-transfer_size) == ZYNQ_I2C_FIFO_DEPTH) {
--
1.8.2.3
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[U-Boot] [PATCH v2 2/2] i2c: zynq: Add support for the second i2c controller
From: Michael Burr michael.b...@logicpd.com
Initialize the second i2c controller.
Signed-off-by: Michael Burr michael.b...@logicpd.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2: None
Changes in v1:
- Based on original thread from Michael Burr
http://lists.denx.de/pipermail/u-boot/2013-October/165017.html
Heiko did some changes in this mainline patch
i2c, zynq: convert zynq i2c driver to new multibus/multiadapter framework
(sha1: 0bdffe71fddeaa46768a39305797e4512dee0f15)
- MS rebase on latestgreatest
drivers/i2c/zynq_i2c.c| 44 ++-
include/configs/zynq-common.h | 6 +++---
2 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index 11ef0f8..f1f6513 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -64,19 +64,21 @@ struct zynq_i2c_registers {
#define ZYNQ_I2C_FIFO_DEPTH16
#define ZYNQ_I2C_TRANSFERT_SIZE_MAX255 /* Controller transfer limit */
-#if defined(CONFIG_ZYNQ_I2C0)
-# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0
-#else
-# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1
-#endif
-
-static struct zynq_i2c_registers *zynq_i2c =
- (struct zynq_i2c_registers *)ZYNQ_I2C_BASE;
+static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap)
+{
+ return adap-hwadapnr ?
+ /* Zynq PS I2C1 */
+ (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 :
+ /* Zynq PS I2C0 */
+ (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0;
+}
/* I2C init called by cmd_i2c when doing 'i2c reset'. */
static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed,
int slaveadd)
{
+ struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
+
/* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
writel((16 ZYNQ_I2C_CONTROL_DIV_B_SHIFT) |
(2 ZYNQ_I2C_CONTROL_DIV_A_SHIFT), zynq_i2c-control);
@@ -87,7 +89,7 @@ static void zynq_i2c_init(struct i2c_adapter *adap, int
requested_speed,
}
#ifdef DEBUG
-static void zynq_i2c_debug_status(void)
+static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c)
{
int int_status;
int status;
@@ -129,7 +131,7 @@ static void zynq_i2c_debug_status(void)
#endif
/* Wait for an interrupt */
-static u32 zynq_i2c_wait(u32 mask)
+static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
{
int timeout, int_status;
@@ -140,7 +142,7 @@ static u32 zynq_i2c_wait(u32 mask)
break;
}
#ifdef DEBUG
- zynq_i2c_debug_status();
+ zynq_i2c_debug_status(zynq_i2c));
#endif
/* Clear interrupt status flags */
writel(int_status mask, zynq_i2c-interrupt_status);
@@ -154,6 +156,8 @@ static u32 zynq_i2c_wait(u32 mask)
*/
static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
+ struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
+
/* Attempt to read a byte */
setbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_CLR_FIFO |
ZYNQ_I2C_CONTROL_RW);
@@ -162,7 +166,7 @@ static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev)
writel(dev, zynq_i2c-address);
writel(1, zynq_i2c-transfer_size);
- return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+ return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
ZYNQ_I2C_INTERRUPT_NACK)
ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
}
@@ -177,6 +181,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev,
uint addr,
u32 status;
u32 i = 0;
u8 *cur_data = data;
+ struct zynq_i2c_registers *zynq_i2c = i2c_select(adap);
/* Check the hardware can handle the requested bytes */
if ((length 0) || (length ZYNQ_I2C_TRANSFERT_SIZE_MAX))
@@ -198,7 +203,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev,
uint addr,
writel(addr (8 * alen), zynq_i2c-data);
/* Wait for the address to be sent */
- if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) {
+ if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) {
/* Release the bus */
clrbits_le32(zynq_i2c-control, ZYNQ_I2C_CONTROL_HOLD);
return -ETIMEDOUT;
@@ -214,7 +219,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev,
uint addr,
/* Wait for data */
do {
- status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP |
+ status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP |
ZYNQ_I2C_INTERRUPT_DATA);
if (!status) {
/* Release the bus */
@@ -243,6 +248,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev,
uint addr,
int alen, u8 *data, int length)
{
u8 *cur_data = data;
+ struct
[U-Boot] T4QDS e6500 core and U-Boot 64-bit
Hi All, The T4240 on the T4QDS board is a PPC e6500 core (64 bit), but it is configured in U-Boot as an e500 core, which is 32 bit. Why is this? Can it be updated to e6500? This leads directly into another question: can U-Boot be compiled and run 64-bit? So far, I have been unable to make it work with a 64-bit compiler. I'm running into these errors: cc1: error: -mcall not supported in this configuration cc1: error: -mrelocatable not supported in this configuration cc1: error: -meabi not supported in this configuration Specifying CFLAGS=-meabi -mrelocatable -mcall-sysv will get through make T4240QDS_config without errors, but the above errors show up when making the following targets: include/autoconf.mk include/autoconf.mk.dep include/spl-autoconf.mk include/tpl-autoconf.mk The build then fails, with a call to cross-gcc which does not include the specified CFLAGS. Is this a bug in the Makefile, that CFLAGS is not being passed to the call to cross-gcc? Thanks, Danny ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] xilinx_spi: Move timeout calculation out of the loop
Timeout calculation should be out of the data loop.
This patch increase spi bandwidth for 30%.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/spi/xilinx_spi.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 5ac0184..56d99d1 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -149,6 +149,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout,
const unsigned char *txp = dout;
unsigned char *rxp = din;
unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
+ unsigned global_timeout;
debug(%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n, __func__,
slave-bus, slave-cs, bitlen, bytes, flags);
@@ -176,11 +177,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *dout,
if (flags SPI_XFER_BEGIN)
spi_cs_activate(slave);
- while (bytes--) {
- unsigned timeout = /* at least 1usec or greater, leftover 1 */
- xilspi-freq XILSPI_MAX_XFER_BITS * 100 ? 2 :
+ /* at least 1usec or greater, leftover 1 */
+ global_timeout = xilspi-freq XILSPI_MAX_XFER_BITS * 100 ? 2 :
(XILSPI_MAX_XFER_BITS * 100 / xilspi-freq) + 1;
+ while (bytes--) {
+ unsigned timeout = global_timeout;
/* get Tx element from data out buffer and count up */
unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
debug(%s: tx:%x , __func__, d);
--
1.8.2.3
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[U-Boot] [PATCH] blackfin: update default config for bf609
From: Sonic Zhang sonic.zh...@analog.com Signed-off-by: Sonic Zhang sonic.zh...@analog.com --- include/configs/bf609-ezkit.h | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 1a43e1b..d97f063 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -39,7 +39,7 @@ #define CONFIG_CCLK_DIV(1) /* SCLK_DIV controls the system clock divider */ /* Values can range from 0-31 (where 0 means 32) */ -#define CONFIG_SCLK_DIV(4) +#define CONFIG_SCLK_DIV(4) /* Values can range from 0-7 (where 0 means 8) */ #define CONFIG_SCLK0_DIV (1) #define CONFIG_SCLK1_DIV (1) @@ -56,7 +56,11 @@ #define CONFIG_MEM_SIZE128 #define CONFIG_SMC_GCTL_VAL0x0010 +#ifdef CONFIG_BFIN_BOARD_VERSION_1_0 #define CONFIG_SMC_B0CTL_VAL 0x01007011 +#else +#define CONFIG_SMC_B0CTL_VAL 0x01005011 +#endif #define CONFIG_SMC_B0TIM_VAL 0x08170977 #define CONFIG_SMC_B0ETIM_VAL 0x00092231 @@ -64,6 +68,7 @@ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) #define CONFIG_HW_WATCHDOG + /* * Network Settings */ @@ -78,6 +83,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII +#define CONFIG_ETHADDR 02:80:ad:20:31:e8 /* i2c Settings */ #define CONFIG_BFIN_TWI_I2C @@ -126,6 +132,10 @@ #define CONFIG_ENV_SIZE 0x8000 #define CONFIG_ENV_SECT_SIZE0x8000 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#define UBOOT_ENV_UPDATE \ +protect off 0xB000 +$(filesize); \ +erase 0xB000 +$(filesize); \ +cp.b $(loadaddr) 0xB000 $(filesize) #endif #define FLASHBOOT_ENV_SETTINGS flashboot=bootm 0xB010\0 @@ -146,11 +156,17 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_SOFTSWITCH -#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4) +#define CONFIG_MISC_INIT_R #define CONFIG_BFIN_SOFT_SWITCH #define CONFIG_ADI_GPIO2 +/* linkport switch, uncomment to enable, conflict with nor flash +#define CONFIG_BFIN_LINKPORT +*/ + +#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4) + #if 0 #define CONFIG_UART_MEM 1024 #undef CONFIG_UART_CONSOLE -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: m53evk: Rename mxc-nand to mxc_nand
On 21/01/2014 22:00, Marek Vasut wrote: The name the Linux kernel expects is 'mxc_nand' , not 'mxc-nand' . This patch renames the driver name. Signed-off-by: Marek Vasut ma...@denx.de Cc: Stefano Babic sba...@denx.de --- include/configs/m53evk.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index d812349..db3697d 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -128,9 +128,9 @@ #define CONFIG_LZO #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT nand0=mxc-nand +#define MTDIDS_DEFAULT nand0=mxc_nand #define MTDPARTS_DEFAULT \ - mtdparts=mxc-nand:\ + mtdparts=mxc_nand:\ 1m(bootloader)ro, \ 512k(environment),\ 512k(redundant-environment), \ Acked-by: Stefano Babic sba...@denx.de Best regards, Stefano Babic -- = DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] T4QDS e6500 core and U-Boot 64-bit
Dear Danny Gale, In message 52df18b3.1080...@coloradoengineeringinc.com you wrote: The T4240 on the T4QDS board is a PPC e6500 core (64 bit), but it is configured in U-Boot as an e500 core, which is 32 bit. Why is this? Becuase it simply works :-) Can it be updated to e6500? Yes - if you add support for 64 bit configurations in general, and for powerpc64 in particular. This leads directly into another question: can U-Boot be compiled and run 64-bit? So far, I have been unable to make it work with a 64-bit compiler. I'm running into these errors: Not out of the box. What is your actual reason for wanting to run a 64 bit boot loader? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de 1st Old Man: Gee, its windy today. 2nd Old Man: No it's not... it's Thursday. 3rd Old Man: Yeh, me too. Let's go for a beer. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net/designware - switch driver to phylib usage
Hi Alexey, I failed to apply your patch on the 2014.01 release head. Regards, Sonic Zhang Applying: net/designware - switch driver to phylib usage /home/sonic/projects/u-boot-blackfin.up/.git/rebase-apply/patch:66: space before tab in indent. u16 val) error: patch failed: drivers/net/designware.c:102 error: drivers/net/designware.c: patch does not apply Patch failed at 0001 net/designware - switch driver to phylib usage When you have resolved this problem run git am --resolved. If you would prefer to skip this patch, instead run git am --skip. To restore the original branch and stop patching run git am --abort. On Mon, Jan 20, 2014 at 5:21 PM, Alexey Brodkin abrod...@synopsys.com wrote: On Mon, 2014-01-13 at 15:11 +0400, Alexey Brodkin wrote: With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing board_phy_config. I'm wondering if any owner of bf609-ezkit or spear board(s) may try this change and provide some feedback? -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7] zynq: Fix incorrect header name
Zynq common configuration is placed in zynq-common.h not zynq_common.h. Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq_zc70x.h | 2 +- include/configs/zynq_zed.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h index 673660e..de0e241 100644 --- a/include/configs/zynq_zc70x.h +++ b/include/configs/zynq_zc70x.h @@ -2,7 +2,7 @@ * (C) Copyright 2013 Xilinx, Inc. * * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards - * See zynq_common.h for Zynq common configs + * See zynq-common.h for Zynq common configs * * SPDX-License-Identifier:GPL-2.0+ */ diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h index 412dede..274140c 100644 --- a/include/configs/zynq_zed.h +++ b/include/configs/zynq_zed.h @@ -2,7 +2,7 @@ * (C) Copyright 2013 Xilinx, Inc. * * Configuration for Zynq Evaluation and Development Board - ZedBoard - * See zynq_common.h for Zynq common configs + * See zynq-common.h for Zynq common configs * * SPDX-License-Identifier:GPL-2.0+ */ -- 1.8.2.3 pgpf5aajnNq25.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] zynq: Enable dcache support
Enable dcache.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/cpu/armv7/zynq/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 9af340e..c771759 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -46,3 +46,11 @@ void reset_cpu(ulong addr)
while (1)
;
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
--
1.8.2.3
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[U-Boot] [PATCH 1/7] zynq: Do not explicitely enable icache
icache is already enabled by default. Signed-off-by: Michal Simek michal.si...@xilinx.com --- board/xilinx/zynq/board.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index a5b9bde..08932a2 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -55,8 +55,6 @@ int board_init(void) } #endif - icache_enable(); - #ifdef CONFIG_FPGA fpga_init(); fpga_add(fpga_xilinx, fpga); -- 1.8.2.3 pgpDcdNQnYtqB.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/7] zynq: Extend kernel image size to 20MB
Extend max kernel image size. Gunzip is checking this value. If kernel is larger, message below is shown. Uncompressing Kernel Image ... Error: inflate() returned -5 GUNZIP: uncompress, out-of-mem or overwrite error - must RESET board to recover Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq-common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e7a8e9f..08b53d0 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -221,6 +221,9 @@ #define CONFIG_FIT_SIGNATURE #define CONFIG_RSA +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024) + /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) # define CONFIG_API -- 1.8.2.3 pgpsWn0v562tf.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/7] zynq: Enable tftp put command
For saving content of memory via tftp to file. Signed-off-by: Michal Simek michal.si...@xilinx.com --- include/configs/zynq-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 08b53d0..6591372 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -237,5 +237,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII +#define CONFIG_CMD_TFTPPUT #endif /* __CONFIG_ZYNQ_COMMON_H */ -- 1.8.2.3 pgpv6B8rO0P8_.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/7] zynq: Move bootmode to headers
These numbers will be reused by SPL.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/include/asm/arch-zynq/hardware.h | 6 ++
board/xilinx/zynq/board.c | 6 --
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index cd69677..1fe0448 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -21,6 +21,12 @@
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK 0xF
+#define ZYNQ_BM_NOR0x2
+#define ZYNQ_BM_SD 0x5
+#define ZYNQ_BM_JTAG 0x0
+
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 27aeaa4..82595fb 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -12,12 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Bootmode setting values */
-#define ZYNQ_BM_MASK 0x0F
-#define ZYNQ_BM_NOR0x02
-#define ZYNQ_BM_SD 0x05
-#define ZYNQ_BM_JTAG 0x0
-
#ifdef CONFIG_FPGA
Xilinx_desc fpga;
--
1.8.2.3
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[U-Boot] [PATCH 6/7] zynq: Use board_eth_init if CMD_NET is not enabled
board_eth_init can be also called in cases where CMD_NET
is not enabled.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
board/xilinx/zynq/board.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 08932a2..27aeaa4 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -83,7 +83,6 @@ int board_late_init(void)
return 0;
}
-#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
@@ -117,7 +116,6 @@ int board_eth_init(bd_t *bis)
#endif
return ret;
}
-#endif
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
--
1.8.2.3
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Re: [U-Boot] [PATCH] net/designware - switch driver to phylib usage
Hi Sonic, On Wed, 2014-01-22 at 17:10 +0800, Sonic Zhang wrote: Hi Alexey, I failed to apply your patch on the 2014.01 release head. Indeed this one requires 2 other patches which didn't made it to mainline yet. Do you mind to try to apply both patches (http://patchwork.ozlabs.org/patch/309762/ and http://patchwork.ozlabs.org/patch/309764/) before this one? Even though I do see now that there're whitespace errors in 2 of 3 patches I'd like to test functionality of the patch on hardware that differs from mine. Your confirmation/update would be very helpful. In the meantime I'll update patches so they don't have whitespace errors any more. Regards, Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] zynq: serial: Simplify serial driver initialization
Define both serial uarts in the driver and return
default uart based on board configuration.
- Move baseaddresses to hardware.h
- Define default baudrate and clock values
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
On the top of zynq series [7/7] I have just sent.
Forget to add it on the top of it.
arch/arm/include/asm/arch-zynq/hardware.h | 2 ++
drivers/serial/serial_zynq.c | 34 ++-
include/configs/zynq-common.h | 19 ++---
3 files changed, 24 insertions(+), 31 deletions(-)
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index 1fe0448..d0fba64 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -7,6 +7,8 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
+#define ZYNQ_SERIAL_BASEADDR0 0xE000
+#define ZYNQ_SERIAL_BASEADDR1 0xE0001000
#define ZYNQ_SYS_CTRL_BASEADDR 0xF800
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F0
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index ff28f3c..9a1ee00 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -10,6 +10,7 @@
#include asm/io.h
#include linux/compiler.h
#include serial.h
+#include asm/arch/hardware.h
#define ZYNQ_UART_SR_TXFULL0x0010 /* TX FIFO full */
#define ZYNQ_UART_SR_RXEMPTY 0x0002 /* RX FIFO empty */
@@ -33,13 +34,23 @@ struct uart_zynq {
};
static struct uart_zynq *uart_zynq_ports[2] = {
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
- [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0,
+ [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
+ [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
+};
+
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
#endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
- [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1,
+#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
+# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
+#endif
+
+#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
+# define CONFIG_ZYNQ_SERIAL_CLOCK0 5000
+#endif
+#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
+# define CONFIG_ZYNQ_SERIAL_CLOCK1 5000
#endif
-};
struct uart_zynq_params {
u32 baudrate;
@@ -47,14 +58,10 @@ struct uart_zynq_params {
};
static struct uart_zynq_params uart_zynq_ports_param[2] = {
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
[0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
[0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
-#endif
-#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
[1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
[1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
-#endif
};
/* Set up the baud rate in gd struct */
@@ -186,20 +193,19 @@ struct serial_device uart_zynq_serial1_device =
__weak struct serial_device *default_serial_console(void)
{
+#if defined(CONFIG_ZYNQ_SERIAL_UART0)
if (uart_zynq_ports[0])
return uart_zynq_serial0_device;
+#endif
+#if defined(CONFIG_ZYNQ_SERIAL_UART1)
if (uart_zynq_ports[1])
return uart_zynq_serial1_device;
-
+#endif
return NULL;
}
void zynq_serial_initalize(void)
{
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
serial_register(uart_zynq_serial0_device);
-#endif
-#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
serial_register(uart_zynq_serial1_device);
-#endif
}
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 6591372..dfa337f 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -35,27 +35,12 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-/* Zynq Serial driver */
-#ifdef CONFIG_ZYNQ_SERIAL_UART0
-# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE000
-# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
-# define CONFIG_ZYNQ_SERIAL_CLOCK0 5000
-#endif
-
-#ifdef CONFIG_ZYNQ_SERIAL_UART1
-# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000
-# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
-# define CONFIG_ZYNQ_SERIAL_CLOCK1 5000
-#endif
-
-#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
-# define CONFIG_ZYNQ_SERIAL
-#endif
-
/* DCC driver */
#if defined(CONFIG_ZYNQ_DCC)
# define CONFIG_ARM_DCC
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
+#else
+# define CONFIG_ZYNQ_SERIAL
#endif
/* Ethernet driver */
--
1.8.2.3
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[U-Boot] [PATCH v6 00/11] Introduce Samsung misc file and LCD menu.
This patch set includes changes required to: - properly use of all gpios - introduce common file for Samsung misc code - keys support (PWR, VOL:UP,DOWN) - console support on LCD - 16bpp logo support - introduce LCD menu on Samsung devices Each version changes are described in each patch commit msg. Przemyslaw Marczak (11): s5p: gpio: change gpio coding method for s5p gpio. trats2: Code cleanup. samsung: common: Add file for common functions, draw_logo() cleanup. common: lcd.c: fix data abort exception when try to access bmp header lib: tizen: change Tizen logo with the new one. video: exynos: fimd: add support for various display color modes samsung: boards: update display configs with 16bpp mode. samsung: misc: Add LCD download menu. trats: add LCD download menu support trats2: add LCD download menu support universal: add LCD download menu support arch/arm/include/asm/arch-exynos/gpio.h | 245 +- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 47 +- board/samsung/common/Makefile|1 + board/samsung/common/misc.c | 387 ++ board/samsung/trats/trats.c | 18 +- board/samsung/trats2/trats2.c| 31 +- board/samsung/universal_c210/universal.c | 18 +- common/lcd.c | 27 +- drivers/gpio/s5p_gpio.c | 15 +- drivers/power/battery/bat_trats2.c |2 +- drivers/video/exynos_fb.c| 28 - drivers/video/exynos_fimd.c | 15 +- include/configs/s5p_goni.h |4 +- include/configs/s5pc210_universal.h | 43 +- include/configs/trats.h | 35 +- include/configs/trats2.h | 32 +- include/lcd.h|2 + include/power/max77686_pmic.h|2 + include/power/pmic.h |1 - include/samsung/misc.h | 25 + lib/tizen/tizen.c| 21 +- lib/tizen/tizen_hd_logo.h| 5057 --- lib/tizen/tizen_hd_logo_data.h | 15 - lib/tizen/tizen_logo_16bpp.h |10025 ++ lib/tizen/tizen_logo_16bpp_gzip.h| 727 +++ 25 files changed, 11470 insertions(+), 5353 deletions(-) create mode 100644 board/samsung/common/misc.c create mode 100644 include/samsung/misc.h delete mode 100644 lib/tizen/tizen_hd_logo.h delete mode 100644 lib/tizen/tizen_hd_logo_data.h create mode 100644 lib/tizen/tizen_logo_16bpp.h create mode 100644 lib/tizen/tizen_logo_16bpp_gzip.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 01/11] s5p: gpio: change gpio coding method for s5p gpio.
Old s5p gpio coding method was not clean and was not working properly for all parts and banks. New method is clean and easy to extend. Gpio coding mask: 0x00ff - pin number 0x0000 - bank offset 0xff00 - part number Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com --- Changes v2: - none Changes v3: - fix merge conflict in arch/arm/include/asm/arch-exynos/gpio.h - add exynos5420 gpio coding - update file: board/samsung/trats2/trats2.c Changes v4: - code cleanup Changes v5: - none Changes v6: - none arch/arm/include/asm/arch-exynos/gpio.h | 245 +- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 47 -- board/samsung/trats2/trats2.c|8 +- drivers/gpio/s5p_gpio.c | 15 +- include/configs/s5p_goni.h |4 +- include/configs/s5pc210_universal.h | 12 +- include/configs/trats.h |4 +- 7 files changed, 132 insertions(+), 203 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 2a19852..d6868fa 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -247,180 +247,81 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* GPIO pins per bank */ #define GPIO_PER_BANK 8 - -#define exynos4_gpio_part1_get_nr(bank, pin) \ - ((unsigned int) (((struct exynos4_gpio_part1 *) \ - EXYNOS4_GPIO_PART1_BASE)-bank)) \ - - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4_gpio_part2_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos4_gpio_part2 *) \ - EXYNOS4_GPIO_PART2_BASE)-bank)) \ - - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) - -#define exynos4x12_gpio_part1_get_nr(bank, pin) \ - ((unsigned int) (((struct exynos4x12_gpio_part1 *) \ - EXYNOS4X12_GPIO_PART1_BASE)-bank)) \ - - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part2_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos4x12_gpio_part2 *) \ - EXYNOS4X12_GPIO_PART2_BASE)-bank)) \ - - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) - -#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part3_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos4x12_gpio_part3 *) \ - EXYNOS4X12_GPIO_PART3_BASE)-bank)) \ - - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) - -#define exynos5_gpio_part1_get_nr(bank, pin) \ - ((unsigned int) (((struct exynos5_gpio_part1 *) \ - EXYNOS5_GPIO_PART1_BASE)-bank)) \ - - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part2_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos5_gpio_part2 *) \ - EXYNOS5_GPIO_PART2_BASE)-bank)) \ - - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX) - -#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part3_get_nr(bank, pin) \ - (((unsigned int) (((struct exynos5_gpio_part3 *) \ - EXYNOS5_GPIO_PART3_BASE)-bank)) \ - - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) - - -/* EXYNOS5420 */ -#define exynos5420_gpio_part1_get_nr(bank, pin) \ - ((unsigned int) (((struct exynos5420_gpio_part1 *)\ - EXYNOS5420_GPIO_PART1_BASE)-bank)) \ - - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \ - / sizeof(struct
[U-Boot] [PATCH v6 06/11] video: exynos: fimd: add support for various display color modes
Now fimd BPP color mode depends on vl_bpp value in struct panel_info.
There is only 16BPP mode check, default mode is 24BPP.
Other fimd modes are usually unneeded and also needs some fimd driver
modifications and tests.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v2:
- check panel_info vl_bpix when setting fimd color mode
- move boards configs update to another commit.
Changes v3:
- none
Changes v4:
- none
Changes v5:
- none
Changes v6:
- none
drivers/video/exynos_fimd.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index f962c4f..cebbba7 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -73,18 +73,19 @@ static void exynos_fimd_set_par(unsigned int win_id)
/* DATAPATH is DMA */
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
- if (pvid-logo_on) /* To get proprietary LOGO */
- cfg |= EXYNOS_WINCON_WSWP_ENABLE;
- else /* To get output console on LCD */
- cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+ cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
/* dma burst is 16 */
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
- if (pvid-logo_on) /* To get proprietary LOGO */
- cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
- else /* To get output console on LCD */
+ switch (pvid-vl_bpix) {
+ case 4:
cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+ break;
+ default:
+ cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+ break;
+ }
writel(cfg, (unsigned int)fimd_ctrl-wincon0 +
EXYNOS_WINCON(win_id));
--
1.7.9.5
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[U-Boot] [PATCH v6 07/11] samsung: boards: update display configs with 16bpp mode.
16 bpp mode is required by LCD console mode.
This change updates exynos board files.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
---
Changes v2:
-- new patch
Changes v3:
- none
Changes v4:
- none
Changes v5:
- none
Changes v6:
- none
board/samsung/trats/trats.c |2 +-
board/samsung/trats2/trats2.c|2 +-
board/samsung/universal_c210/universal.c |2 +-
include/configs/s5pc210_universal.h |2 +-
include/configs/trats.h |2 +-
include/configs/trats2.h |2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index a644b60..32a6cee 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -742,7 +742,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+ .vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 4834f90..b60a2da 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -565,7 +565,7 @@ vidinfo_t panel_info = {
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
- .vl_bpix= 5,/* Bits per pixel, 2^5 = 32 */
+ .vl_bpix= 4,/* Bits per pixel, 2^4 = 16 */
/* s6e8ax0 Panel infomation */
.vl_hspw= 5,
diff --git a/board/samsung/universal_c210/universal.c
b/board/samsung/universal_c210/universal.c
index 1c8b8b8..e300da3 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -446,7 +446,7 @@ vidinfo_t panel_info = {
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
- .vl_bpix= 5,/* Bits per pixel */
+ .vl_bpix= 4,/* Bits per pixel */
/* LD9040 LCD Panel */
.vl_hspw= 2,
diff --git a/include/configs/s5pc210_universal.h
b/include/configs/s5pc210_universal.h
index 67b08fc..93b9dfb 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -280,7 +280,7 @@ int universal_spi_read(void);
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
#define CONFIG_LD9040
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
diff --git a/include/configs/trats.h b/include/configs/trats.h
index b1bdeaa..f5e796a 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -311,7 +311,7 @@
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
#define CONFIG_FB_ADDR 0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 528e9a3..a856b56 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -321,7 +321,7 @@ int get_soft_i2c_sda_pin(void);
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
-#define CONFIG_BMP_32BPP
+#define CONFIG_BMP_16BPP
#define CONFIG_FB_ADDR 0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
--
1.7.9.5
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[U-Boot] [PATCH v6 04/11] common: lcd.c: fix data abort exception when try to access bmp header
Changes:
- le16_to_cpu() to get_unaligned_le16()
- le32_to_cpu() to get_unaligned_le32()
when access fields in struct bmp header.
This changes avoids data abort exception caused by unaligned data access.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Acked-by: Anatolij Gustschin ag...@denx.de
---
Changes v2:
- new patch
Changes v3:
- common/Makefile - remove CFLAG: -mno-unaligned-access
- common/lcd.c - fix data abort exception when access bmp_header
Changes v4:
- add Acked-by
Changes v5:
- none
Changes v6:
- none
common/lcd.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/common/lcd.c b/common/lcd.c
index 56bf067..aa81522 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -26,7 +26,7 @@
#endif
#include lcd.h
#include watchdog.h
-
+#include asm/unaligned.h
#include splash.h
#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
@@ -777,9 +777,9 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp,
ushort *cmap, uchar *fb,
int x, y;
int decode = 1;
- width = le32_to_cpu(bmp-header.width);
- height = le32_to_cpu(bmp-header.height);
- bmap = (uchar *)bmp + le32_to_cpu(bmp-header.data_offset);
+ width = get_unaligned_le32(bmp-header.width);
+ height = get_unaligned_le32(bmp-header.height);
+ bmap = (uchar *)bmp + get_unaligned_le32(bmp-header.data_offset);
x = 0;
y = height - 1;
@@ -900,9 +900,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
return 1;
}
- width = le32_to_cpu(bmp-header.width);
- height = le32_to_cpu(bmp-header.height);
- bmp_bpix = le16_to_cpu(bmp-header.bit_count);
+ width = get_unaligned_le32(bmp-header.width);
+ height = get_unaligned_le32(bmp-header.height);
+ bmp_bpix = get_unaligned_le16(bmp-header.bit_count);
+
colors = 1 bmp_bpix;
bpix = NBITS(panel_info.vl_bpix);
@@ -917,9 +918,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
/* We support displaying 8bpp BMPs on 16bpp LCDs */
if (bpix != bmp_bpix !(bmp_bpix == 8 bpix == 16)) {
printf (Error: %d bit/pixel mode, but BMP has %d bit/pixel\n,
- bpix,
- le16_to_cpu(bmp-header.bit_count));
-
+ bpix, get_unaligned_le16(bmp-header.bit_count));
return 1;
}
@@ -956,7 +955,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
}
}
#endif
-
/*
* BMP format for Monochrome assumes that the state of a
* pixel is described on a per Bit basis, not per Byte.
@@ -987,15 +985,16 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
if ((y + height) panel_info.vl_row)
height = panel_info.vl_row - y;
- bmap = (uchar *) bmp + le32_to_cpu(bmp-header.data_offset);
- fb = (uchar *) (lcd_base +
+ bmap = (uchar *)bmp + get_unaligned_le32(bmp-header.data_offset);
+ fb = (uchar *)(lcd_base +
(y + height - 1) * lcd_line_length + x * bpix / 8);
switch (bmp_bpix) {
case 1: /* pass through */
case 8:
#ifdef CONFIG_LCD_BMP_RLE8
- if (le32_to_cpu(bmp-header.compression) == BMP_BI_RLE8) {
+ u32 compression = get_unaligned_le32(bmp-header.compression);
+ if (compression == BMP_BI_RLE8) {
if (bpix != 16) {
/* TODO implement render code for bpix != 16 */
printf(Error: only support 16 bpix);
--
1.7.9.5
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[U-Boot] [PATCH v6 02/11] trats2: Code cleanup.
Remove wrong and unused env variables
Trats2 is not as GT-I8800.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Acked-by: Jaehoon Chung jh80.ch...@samsung.com
Cc: Piotr Wilczek p.wilc...@samsung.com
---
Changes v2:
- none
Changes v3:
- none
Changes v4:
- add include pmic.h to max77686_pmic.h
Changes v5:
- add acked-by
Changes v6:
- misc_init_r() - leave in trats2.c
board/samsung/trats2/trats2.c | 12 ++--
drivers/power/battery/bat_trats2.c |2 +-
include/power/max77686_pmic.h |2 ++
3 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 1e96fdc..feb6c4c 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -72,15 +72,12 @@ static void check_hw_revision(void)
int checkboard(void)
{
puts(Board:\tTRATS2\n);
+ printf(HW Revision:\t0x%04x\n, board_rev);
+
return 0;
}
#endif
-static void show_hw_revision(void)
-{
- printf(HW Revision:\t0x%04x\n, board_rev);
-}
-
u32 get_board_rev(void)
{
return board_rev;
@@ -618,11 +615,6 @@ void init_panel_info(vidinfo_t *vid)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
- setenv(model, GT-I8800);
- setenv(board, TRATS2);
-
- show_hw_revision();
-
return 0;
}
#endif
diff --git a/drivers/power/battery/bat_trats2.c
b/drivers/power/battery/bat_trats2.c
index f264832..94015aa 100644
--- a/drivers/power/battery/bat_trats2.c
+++ b/drivers/power/battery/bat_trats2.c
@@ -8,7 +8,7 @@
#include common.h
#include power/pmic.h
#include power/battery.h
-#include power/max8997_pmic.h
+#include power/max77693_pmic.h
#include errno.h
static struct battery battery_trats;
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
index 16e9016..c2a772a 100644
--- a/include/power/max77686_pmic.h
+++ b/include/power/max77686_pmic.h
@@ -8,6 +8,8 @@
#ifndef __MAX77686_H_
#define __MAX77686_H_
+#include power/pmic.h
+
enum {
MAX77686_REG_PMIC_ID= 0x0,
MAX77686_REG_PMIC_INTSRC,
--
1.7.9.5
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