Re: [U-Boot] [PATCH v11 6/6] arm: faraday: add virtual machine support

[Wolfgang Denk]

Dear Kuo-Jung Su,

In message <1395813799-3672-7-git-send-email-dant...@gmail.com> you wrote:
> From: Kuo-Jung Su 
> 
> Faraday Virtual Machine (FVM) is a QEMU based emulator
> which is designed for early stage software development
> (i.e., IPL, SPL development).
...
> +ulong clk_get_rate(const char *id)
> +{
> + ulong ret = 0;
> +
> + if (!strcmp(id, "AHB"))
> + ret = clk_get_rate_ahb();
> + else if (!strcmp(id, "APB"))
> + ret = clk_get_rate_apb();
> + else if (!strcmp(id, "CPU"))
> + ret = clk_get_rate_cpu();
> + else if (!strcmp(id, "I2C"))
> + ret = clk_get_rate_apb();
> + else if (!strcmp(id, "SSP"))
> + ret = clk_get_rate_apb();
> + else if (!strcmp(id, "SPI"))
> + ret = clk_get_rate_ahb();
> + else if (!strcmp(id, "MMC") || !strcmp(id, "SDC"))
> + ret = clk_get_rate_ahb();
> +
> + return ret;
> +}

I have seen basically identical code in  [PATCH v11 4/6] arm: faraday:
add A369 evaluation board; please move this (and other common code)
into a common location so we have only one implementation of common
code.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
You don't stop doing things because you get old.  You get old because
you stop doing things.- Rosamunde Pilcher
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Re: [U-Boot] [PATCH v11 1/6] arm: add Faraday ARMv5TE cores support

[Wolfgang Denk]

Dear Kuo-Jung Su,

In message <1395813799-3672-2-git-send-email-dant...@gmail.com> you wrote:
> From: Kuo-Jung Su 
> 
> Here is the list of verified cores:
> 
> 1. FA606TE (ARMv5TE, no mmu)
> 2. FA626TE (ARMv5TE)
...
> diff --git a/include/configs/faraday-common.h 
> b/include/configs/faraday-common.h
> new file mode 100644
> index 000..546c0a9
> --- /dev/null
> +++ b/include/configs/faraday-common.h
...
> +#ifndef CONFIG_ETHADDR
> +#define CONFIG_ETHADDR  00:41:71:00:00:50
> +#endif
> +
> +#ifndef CONFIG_IPADDR
> +#define CONFIG_IPADDR   10.0.0.192
> +#endif
> +
> +#ifndef CONFIG_NETMASK
> +#define CONFIG_NETMASK  255.255.255.0
> +#endif
> +
> +#ifndef CONFIG_SERVERIP
> +#define CONFIG_SERVERIP 10.0.0.128
> +#endif

We do not allow such static network configuration.  Especially
assigning the same MAC address to all devices is deadly.  Also,
the address is not an officially assigned nor a local one.
Please remove all this code.

> +# endif
> +# ifndef CONFIG_G_DNL_VENDOR_NUM
> +# define CONFIG_G_DNL_VENDOR_NUM0x1d50  /* OpenMoko */
> +# endif

This looks wrong to me?

> +# ifndef CONFIG_G_DNL_PRODUCT_NUM
> +# define CONFIG_G_DNL_PRODUCT_NUM   0x5119
> +# endif

Is this a valid ID?

> +/* Console I/O Buffer Size */
> +#define CONFIG_SYS_CBSIZE   256
> +
> +/* Max number of command args */
> +#define CONFIG_SYS_MAXARGS  32

You use a large number of args with a tiny console buffer?  This looks
suspicious.  Please check.

> +#define CONFIG_CMD_AUTOSCRIPT   /* support autoscript */

This has been removed years ago.  Please use CONFIG_CMD_SOURCE
instead.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
To program is to be.
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Re: [U-Boot] [PATCH v10 0/6] arm: add Faraday SoC platform support

[Kuo-Jung Su]

2014-03-25 20:41 GMT+08:00 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Thu, 20 Feb 2014 11:40:32 +0800, Kuo-Jung Su 
> wrote:
>
>> From: Kuo-Jung Su 
>>
>> These patches introduce Faraday A369 & Virtual SoC platform support.
>
> Except for patches 4/6 and 6/6 in which boards.cfg needed manual
> fixing (due to commit 3fa67050), the series applies to current
> u-boot-arm/master, but building fails for both a369evb and fvm with
> multiple instances of this error:
>
> include/asm/arch/hardware.h:14:23: fatal error: asm/sizes.h: No such
> file or directory
>

It's because that the 'asm/sizes.h' has been moved to 'linux/sizes.h'
by commit 1ace4022394.

> Can you please rebase (for boards.cfg) and diagnose?
>

Sure, the updated patches are on the way.

-- 
Best wishes,
Kuo-Jung Su
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[U-Boot] [PATCH v11 5/6] arm: faraday: add missing header file for FTSDC021

[Kuo-Jung Su]

From: Kuo-Jung Su 

For the Faraday FTSDC021 (SDHCI) controller driver source is
sent out before the patches for Faraday Virtual Machine (FVM)
which actually uses this chip.

The header file (ftsdc021.h) has been accidentally removed
by commit: 3b98b57fa - include: delete unused header files

This patch simply rollback this removal.

Signed-off-by: Kuo-Jung Su 
CC: Albert Aribaud 
---
Changes for v11:
- Nothing updates

Changes for v10:
- Initial commit

 include/faraday/ftsdc021.h |   13 +
 1 file changed, 13 insertions(+)
 create mode 100644 include/faraday/ftsdc021.h

diff --git a/include/faraday/ftsdc021.h b/include/faraday/ftsdc021.h
new file mode 100644
index 000..de8e250
--- /dev/null
+++ b/include/faraday/ftsdc021.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FTSDC021_H
+#define __FTSDC021_H
+
+int ftsdc021_sdhci_init(u32 regbase);
+
+#endif /* __FTSDC021_H */
--
1.7.9.5

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[U-Boot] [PATCH v11 3/6] arm: faraday: add FTPWMTMR010 timer support

[Kuo-Jung Su]

From: Kuo-Jung Su 

Faraday FTPWMTMR010 is a simple APB device which supports
both timer and pwm functions.

Signed-off-by: Kuo-Jung Su 
CC: Albert Aribaud 
---
Changes for v11:
- Directly specify the timer object in 
'arch/arm/cpu/faraday//Makefile'
  instead of using CONFIG_FTPWMTMR010 in 'arch/arm/cpu/faraday/Makefile'

Changes for v8, v9, v10:
- Nothing updates

Changes for v7:
- Update license to use SPDX identifiers.

Changes for v6:
- Nothing updates

Changes for v5:
- Drop IRQ dependant implementation
- Use gd->arch.timer_rate_hz for timer clock source
- Use gd->arch.tbl for timestamp

Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]

Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Add '__iomem' to all the declaration of HW register pointers.

Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().

 arch/arm/cpu/faraday/ftpwmtmr010.c |  112 
 include/faraday/ftpwmtmr010.h  |   41 +
 2 files changed, 153 insertions(+)
 create mode 100644 arch/arm/cpu/faraday/ftpwmtmr010.c
 create mode 100644 include/faraday/ftpwmtmr010.h

diff --git a/arch/arm/cpu/faraday/ftpwmtmr010.c 
b/arch/arm/cpu/faraday/ftpwmtmr010.c
new file mode 100644
index 000..1032e44
--- /dev/null
+++ b/arch/arm/cpu/faraday/ftpwmtmr010.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. 
+ * Kuo-Jung Su 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_ID0
+
+static struct ftpwmtmr010_regs *regs =
+   (void __iomem *)CONFIG_FTPWMTMR010_BASE;
+
+void udelay_masked(unsigned long usec)
+{
+   int id = TIMER_ID + 1;
+   ulong freq = gd->arch.timer_rate_hz;
+
+   /* timer re-start */
+   writel(0, ®s->t[id].ctrl);
+   writel(BIT_MASK(id), ®s->isr);
+   writel(0, ®s->t[id].cmpb);
+   writel((freq / 100) * usec, ®s->t[id].cntb);
+   writel(CTRL_INTEN | CTRL_START | CTRL_UPDATE, ®s->t[id].ctrl);
+
+   /* wait for timer interrupt */
+   while (!(readl(®s->isr) & BIT_MASK(id)))
+   ;
+
+   /* timer disabled */
+   writel(0, ®s->t[id].ctrl);
+   writel(BIT_MASK(id), ®s->isr);
+}
+
+void reset_timer_masked(void)
+{
+   int id = TIMER_ID;
+   ulong freq = gd->arch.timer_rate_hz;
+
+   writel(0, ®s->t[id].ctrl);
+   writel(BIT_MASK(id), ®s->isr);
+
+   /* setup a longest periodic timer */
+   writel((0x / freq) * freq, ®s->t[id].cntb);
+
+   writel(0, ®s->t[id].cmpb);
+   writel(CTRL_AUTORELOAD | CTRL_INTEN | CTRL_START | CTRL_UPDATE,
+   ®s->t[id].ctrl);
+}
+
+ulong get_timer_masked(void)
+{
+   int id = TIMER_ID;
+   ulong freq = gd->arch.timer_rate_hz;
+   ulong secs = 0x / freq;
+   ulong ms = freq / CONFIG_SYS_HZ;
+
+   if (readl(®s->isr) & BIT_MASK(id)) {
+   writel(BIT_MASK(id), ®s->isr);
+   gd->arch.tbl += secs * CONFIG_SYS_HZ;
+   }
+
+   return gd->arch.tbl
+   + ((secs * freq - readl(®s->t[id].cnto)) / ms);
+}
+
+int timer_init(void)
+{
+   gd->arch.tbl = 0;
+   reset_timer_masked();
+   return 0;
+}
+
+void reset_timer(void)
+{
+   reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+   return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+   udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+   return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+   return CONFIG_SYS_HZ;
+}
diff --git a/include/faraday/ftpwmtmr010.h b/include/faraday/ftpwmtmr010.h
new file mode 100644
index 000..29f4f05
--- /dev/null
+++ b/include/faraday/ftpwmtmr010.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/cpu/faraday/ftpwmtmr010.h
+ *
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. 
+ * Kuo-Jung Su 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_CPU_FARADAY_FTPWMTMR010_H
+#define ARCH_ARM_CPU_FARADAY_FTPWMTMR010_H
+
+struct ftpwmtmr010_timer {
+   uint32_t ctrl;  /* Control */
+#define CTRL_EXTCLK(1 << 0) /* use external clock */
+#define CTRL_START (1 << 1) /* t

[U-Boot] [PATCH v11 0/6] arm: add Faraday SoC platform support

[Kuo-Jung Su]

From: Kuo-Jung Su 

These patches introduce Faraday A369 & Virtual SoC platform support.

Here are some public documents for your reference.

   http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
   http://www.faraday-tech.com/html/documentation/index.html

There is also a QEMU based A369 emulator available at my github:

   https://github.com/dantesu1218/qemu.git

Here is a quick start for QEMU + U-Boot:

1. Download the QEMU source tree

   $ git clone -b qemu-1.5.1 https://github.com/dantesu1218/qemu.git

2. Build & Install the QEMU:

   $ ./configure --target-list=arm-softmmu
   $ make
   $ make install

3. Launch u-boot with QEMU:

   $ qemu-system-arm -M a369 -m 512M -nographic -kernel ~/u-boot-2014.01/u-boot

Changes for v11:
   - Fix boards.cfg (due to commit 3fa67050)
   - Rename  to  (due to commit 1ace4022)
   - Directly specify the timer object in 'arch/arm/cpu/faraday//Makefile'
 instead of using CONFIG_FTTMR010 in 'arch/arm/cpu/faraday/Makefile'
   - Directly specify the timer object in 'arch/arm/cpu/faraday//Makefile'
 instead of using CONFIG_FTPWMTMR010 in 'arch/arm/cpu/faraday/Makefile'

Changes for v10:
   - As per Albert's request, merge patch 1, 2 and patch 5, 6
   - Add missing header file for FTSDC021

Changes for v9:
   - Shrink the patch by dropping MMU/D-cache support, and see if we could get
 this patch accepted ASAP.
   - Replace the out-of-date A360 EVB with Faraday Virtual Machine (FVM).
   - Build 'arch_preboot_os()' only when CONFIG_CMD_BOOTM is defined.
   - Add do_go_exec() to override the default behavior of 'go' command.
   - Make Faraday SoC helper files & ftsmc020 standalone changesets.
   - Coding style cleanup.

Changes for v8:
   - Revise MMU/D-cache support
   - Revise Faraday SoC common configurations.
   - Drop FTINTC020 interrupt controller support.
   - Drop FTLCDC200 LCD controller support.
   - Drop FTNANDC021 NAND flash controller support, it would be latter submitted
 as a standalone patch set.
   - Drop proprietary Faraday SPL support, the u-boot-spl would be adapted 
instead.
 However because it depends on the FTNANDC021 patch set, so it would be 
submitted
 after the FTNANDC021 patch set get committed.

Changes for v7:
   - Update license to use SPDX identifiers.
   - cfi_flash: drop the patch to unmap_physmem(),
 because it's already applied.
   - ftnandc021: put_unaligned() -> memcpy()
   - ftnandc021: update ecc relatived function prototypes to fix
 compile warnnings.

Changes for v6:
   - Drop ethernet driver updates for ftmac110&ftgmac100,
 because they are already commited.
   - arch/arm/cpu/faraday/cpu.c:
 struct ftwdt010_wdt __iomem *regs -> struct ftwdt010_wdt *regs
   - arch/arm/cpu/faraday/cmd_bootfa.c: fix compiler warnning
   - arch/arm/cpu/faraday/cmd_bootfa.c: use shorter paragraph
 in commit message, and move the original statement into the
 top of source file.
   - ftnandc021: update README for CONFIG_SYS_FTNANDC021_TIMING
   - ftnandc021: remove illegal type-punning

Changes for v5:
   - Coding Style cleanup:
 1. struct chip_regs __iomem *regs -> struct chip_regs *regs
 2. Move Faraday specific APIs into asm/arch-faraday/*.h
   - Fix Copyright notices (dates) throughout the patch
   - Make 'arm: dma_alloc_coherent: malloc() -> memalign()' as a separate patch
   - Make 'cfi_flash: use buffer length in unmap_physmem()' as a separate patch
   - Define Faraday machine type in board's config header file
   - Add the rationale to the command 'bootfa'
   - Add myself as the maintainer for Faraday A360/A369 in MAINTAINERS.
   - Chain the video:FTLCDC200 back to this patch series.
   - Chain the nand:FTNANDC021 back to this patch series.
   - Chain the net:FTGMAC100 & FTMAC110 back to this patch series.
   - Update Faraday Firmware Image Format:
 1. Drop u-boot image support to simplify the design.
Since it's not possible for the hard-wired ROM code of A360/A369
to support U-boot images. And the real bootloader for A360/A369
is actually Faraday bootcode2, rather than U-Boot.
 2. Add image creation timestamp
   - Update 'arch/arm/cpu/faraday/start.S' with the new design, which move
 relocation into 'arch/arm/lib/relocate.S'
   - Drop i2c:FTI2C010 & spi:FTSSP010_SPI support. The corresponding patch
 would restart after this patch series have been accepted.
   - Revise IRQ & MMU design: Now the exception table would be mapped to
 0x as a small page(4KB), rather than runtime adjust after
 relocation finished.
   - Revise irq:FTINTC020 design, now the irq is always enabled inside
 irq_install_handler().
   - Revise clock management system
   - Revise FTPWMTMR010 & FTTMR010 timer design:
 1. Drop IRQ dependant implementation
 2. Use gd->arch.timer_rate_hz for timer clock source
 3. Use gd->arch.tbl for timestamp

Changes for v4:
   - Coding Style cleanup.
   - Break down the patch series:
   - Patches w

[U-Boot] [PATCH v11 6/6] arm: faraday: add virtual machine support

[Kuo-Jung Su]

From: Kuo-Jung Su 

Faraday Virtual Machine (FVM) is a QEMU based emulator
which is designed for early stage software development
(i.e., IPL, SPL development).

Please check the link bellow for details:
https://github.com/dantesu1218/qemu/blob/qemu-1.5.1/hw/arm/faraday_fvm.c

Signed-off-by: Kuo-Jung Su 
CC: Albert Aribaud 
---
Changes for v11:
- Fix boards.cfg (due to commit 3fa67050)
- Rename  to  (due to commit 1ace4022)
- Directly specify the timer object in 
'arch/arm/cpu/faraday/fvm/Makefile'
  instead of using CONFIG_FTTMR010 in 'arch/arm/cpu/faraday/Makefile'

Changes for v10:
- Nothing updates

Changes for v9:
- Initial commit

 arch/arm/cpu/faraday/fvm/Makefile|8 
 arch/arm/include/asm/arch-fvm/hardware.h |   76 ++
 board/faraday/fvm/Makefile   |9 
 board/faraday/fvm/board.c|   60 +++
 board/faraday/fvm/clock.c|   49 +++
 board/faraday/fvm/lowlevel_init.S|   15 ++
 boards.cfg   |1 +
 include/configs/fvm.h|   58 +++
 8 files changed, 276 insertions(+)
 create mode 100644 arch/arm/cpu/faraday/fvm/Makefile
 create mode 100644 arch/arm/include/asm/arch-fvm/hardware.h
 create mode 100644 board/faraday/fvm/Makefile
 create mode 100644 board/faraday/fvm/board.c
 create mode 100644 board/faraday/fvm/clock.c
 create mode 100644 board/faraday/fvm/lowlevel_init.S
 create mode 100644 include/configs/fvm.h

diff --git a/arch/arm/cpu/faraday/fvm/Makefile 
b/arch/arm/cpu/faraday/fvm/Makefile
new file mode 100644
index 000..9c1eaa8
--- /dev/null
+++ b/arch/arm/cpu/faraday/fvm/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../fttmr010.o
diff --git a/arch/arm/include/asm/arch-fvm/hardware.h 
b/arch/arm/include/asm/arch-fvm/hardware.h
new file mode 100644
index 000..dd04ced
--- /dev/null
+++ b/arch/arm/include/asm/arch-fvm/hardware.h
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/include/asm/arch-fvm/hardware.h
+ *
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. 
+ * Kuo-Jung Su 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include 
+
+#define CONFIG_DRAM_BASE0x1000
+
+#define CONFIG_SRAM_BASE0xA000
+#define CONFIG_SRAM_SIZE0x0002
+
+#define CONFIG_SYSC_BASE0x90f0
+#define CONFIG_SYSC_IRQ 15
+
+#define CONFIG_FTINTC030_BASE   0x9100
+
+#define CONFIG_FTTMR010_BASE0x9020
+#define CONFIG_FTTMR010_IRQ 1
+
+#define CONFIG_FTUART010_BASE0  0x9000
+#define CONFIG_FTUART010_IRQ0   2
+#define CONFIG_FTUART010_BASE1  0x9010
+#define CONFIG_FTUART010_IRQ1   3
+#define CONFIG_FTUART010_BASE   CONFIG_FTUART010_BASE0
+
+#define CONFIG_DDRC_BASE0x9030
+
+#define CONFIG_FTI2C010_BASE0x9040
+#define CONFIG_FTI2C010_IRQ 4
+
+#define CONFIG_FTSSP010_BASE0x9050
+#define CONFIG_FTSSP010_IRQ 5
+
+#define CONFIG_FTWDT010_BASE0x9060
+#define CONFIG_FTWDT010_IRQ 6
+
+#define CONFIG_FTRTC011_BASE0x9070
+#define CONFIG_FTRTC011_IRQ 7
+
+#define CONFIG_FTTSC010_BASE0x9080
+#define CONFIG_FTTSC010_IRQ 8
+
+#define CONFIG_FTAPBBRG020_BASE 0x9110
+#define CONFIG_FTAPBBRG020_IRQ  16
+
+#define CONFIG_FTDMAC020_BASE   0x9120
+#define CONFIG_FTDMAC020_IRQ17
+
+#define CONFIG_FTMAC110_BASE0x9130
+#define CONFIG_FTMAC110_IRQ 18
+
+#define CONFIG_FTSPI020_BASE0x9140
+#define CONFIG_FTSPI020_IRQ 19
+
+#define CONFIG_FTNANDC021_BASE  0x9150
+#define CONFIG_FTNANDC021_IRQ   20
+
+#define CONFIG_FTSDC021_BASE0x9160
+#define CONFIG_FTSDC021_IRQ 21
+
+#define CONFIG_FOTG210_BASE 0x9170
+#define CONFIG_FOTG210_IRQ  22
+
+#define CONFIG_FTLCDC200_BASE   0x9180
+#define CONFIG_FTLCDC200_IRQ23
+
+#endif /* EOF */
diff --git a/board/faraday/fvm/Makefile b/board/faraday/fvm/Makefile
new file mode 100644
index 000..42fef70
--- /dev/null
+++ b/board/faraday/fvm/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  := board.o clock.o
+obj-y  += lowlevel_init.o
diff --git a/board/faraday/fvm/board.c b/board/faraday/fvm/board.c
new file mode 100644
index 000..6c2b03a
--- /dev/null
+++ b/board/faraday/fvm/board.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. 
+ * Kuo-Jung Su 
+ *
+ * SPDX-License-Identifier: GPL-

[U-Boot] [PATCH v11 4/6] arm: faraday: add A369 evaluation board support

[Kuo-Jung Su]

From: Kuo-Jung Su 

The A369 is an ARM CPU-based SoC with rich SoC features and
convenient FPGA link for building fast system prototyping
and mass production.

More information about this hardware can be found at:
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm

Signed-off-by: Kuo-Jung Su 
CC: Albert Aribaud 
---
Changes for v11:
- Fix boards.cfg (due to commit 3fa67050)
- Rename  to  (due to commit 1ace4022)
- Directly specify the timer object in 
'arch/arm/cpu/faraday/a369/Makefile'
  instead of using CONFIG_FTPWMTMR010 in 'arch/arm/cpu/faraday/Makefile'

Changes for v10:
- Merge [arm: faraday: ftsmc020: add a fail-safe macro constant]

Changes for v9:
- Revise the commit message.

Changes for v8:
- Make A369 a standalong changeset.

Changes for v7:
- Update license to use SPDX identifiers.

Changes for v6:
- arch/arm/cpu/faraday/cpu.c:
  struct ftwdt010_wdt __iomem *regs -> struct ftwdt010_wdt *regs

Changes for v5:
- Coding Style cleanup:
  1. struct chip_regs __iomem *regs -> struct chip_regs *regs
  2. Move Faraday specific APIs into asm/arch-faraday/*.h
- Fix Copyright notices (dates) throughout the patch
- Define Faraday machine type in board's config header file
- Add myself as the maintainer for Faraday A360/A369 in MAINTAINERS.
- Drop i2c:FTI2C010 & spi:FTSSP010_SPI support. The corresponding patch
  would restart after this patch series have been accepted.
- Revise clock management system

Changes for v4:
- Coding Style cleanup.
- Break-down the interrupt, timers and common utilties.

Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Add '__iomem' to all the declaration of HW register pointers.
- a36x_config: No more static global network configurations.
- a36x_config: Add a common file for the redundant configurations.

Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().

 arch/arm/cpu/faraday/a369/Makefile|8 ++
 arch/arm/include/asm/arch-a369/hardware.h |   88 
 arch/arm/include/asm/arch-a369/sysc.h |  211 +
 board/faraday/a369evb/Makefile|9 ++
 board/faraday/a369evb/board.c |  122 +
 board/faraday/a369evb/clock.c |   68 ++
 board/faraday/a369evb/lowlevel_init.S |   15 ++
 boards.cfg|1 +
 include/configs/a369.h|  108 +++
 include/faraday/ftsmc020.h|1 +
 10 files changed, 631 insertions(+)
 create mode 100644 arch/arm/cpu/faraday/a369/Makefile
 create mode 100644 arch/arm/include/asm/arch-a369/hardware.h
 create mode 100644 arch/arm/include/asm/arch-a369/sysc.h
 create mode 100644 board/faraday/a369evb/Makefile
 create mode 100644 board/faraday/a369evb/board.c
 create mode 100644 board/faraday/a369evb/clock.c
 create mode 100644 board/faraday/a369evb/lowlevel_init.S
 create mode 100644 include/configs/a369.h

diff --git a/arch/arm/cpu/faraday/a369/Makefile 
b/arch/arm/cpu/faraday/a369/Makefile
new file mode 100644
index 000..8a7c979
--- /dev/null
+++ b/arch/arm/cpu/faraday/a369/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../ftpwmtmr010.o
diff --git a/arch/arm/include/asm/arch-a369/hardware.h 
b/arch/arm/include/asm/arch-a369/hardware.h
new file mode 100644
index 000..9c824ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-a369/hardware.h
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/include/asm/arch-a369/hardware.h
+ *
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. 
+ * Kuo-Jung Su 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include 
+
+#define CONFIG_DRAM_BASE0x1000
+
+#define CONFIG_SRAM_BASE0xA000
+#define CONFIG_SRAM_SIZE0x8000
+
+#define CONFIG_SYSC_BASE0x9200
+#define CONFIG_DDRC_BASE0x9310
+#define CONFIG_AHBC_BASE0x9400
+#define CONFIG_SMC_BASE 0x9480
+#define CONFIG_AHBC2_BASE   0x9420
+
+/*
+ * Timer
+ */
+#define CONFIG_FTPWMTMR010_BASE 0x9230
+#define CONFIG_FTPWMTMR010_IRQ  8
+
+/*
+ * UART
+ */
+#define CONFIG_FTUART010_BASE   0x92B0
+
+/*
+ * Interrupt
+ */
+#define CONFIG_FTINTC020_BASE0  0x9010
+#define CONFIG_FTINTC020_BASE1  0x9600
+#define CO

[U-Boot] [PATCH v11 2/6] arm: faraday: add FTTMR010 timer support

[Kuo-Jung Su]

From: Kuo-Jung Su 

Faraday FTTMR010 is a simple APB device which supports
generic timer functions.

Signed-off-by: Kuo-Jung Su 
CC: Albert Aribaud 
---
Changes for v11:
- Directly specify the timer object in 
'arch/arm/cpu/faraday//Makefile'
  instead of using CONFIG_FTTMR010 in 'arch/arm/cpu/faraday/Makefile'

Changes for v8, v9, v10:
- Nothing updates

Changes for v7:
- Update license to use SPDX identifiers.

Changes for v6:
- Nothing updates

Changes for v5:
- Drop IRQ dependant implementation
- Use gd->arch.timer_rate_hz for timer clock source
- Use gd->arch.tbl for timestamp

Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]

Changes for v3:
- Coding Style cleanup.
- Drop macros for wirtel()/readl(), call them directly.
- Always insert a blank line between declarations and code.
- Add '__iomem' to all the declaration of HW register pointers.

Changes for v2:
- Coding Style cleanup.
- Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
- Use structure based hardware registers to replace the macro constants.
- Replace BIT() with BIT_MASK().

 arch/arm/cpu/faraday/fttmr010.c |  123 +++
 include/faraday/fttmr010.h  |   17 ++
 2 files changed, 140 insertions(+)
 create mode 100644 arch/arm/cpu/faraday/fttmr010.c

diff --git a/arch/arm/cpu/faraday/fttmr010.c b/arch/arm/cpu/faraday/fttmr010.c
new file mode 100644
index 000..28b0086
--- /dev/null
+++ b/arch/arm/cpu/faraday/fttmr010.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. 
+ * Kuo-Jung Su 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fttmr010 *regs = (void __iomem *)CONFIG_FTTMR010_BASE;
+
+void udelay_masked(unsigned long usec)
+{
+   ulong freq = gd->arch.timer_rate_hz;
+
+   /* Disable Timer2 */
+   clrbits_le32(®s->cr, FTTMR010_TM2_CRMASK);
+   /* Disable Timer2 interrupts */
+   writel(FTTMR010_TM2_ISRMASK, ®s->interrupt_mask);
+   /* Clear Timer2 interrupts */
+   writel(FTTMR010_TM2_ISRMASK, ®s->interrupt_state);
+
+   /* Configure Timer2 */
+   writel((freq / 100) * usec, ®s->timer2_counter);
+   writel(0, ®s->timer2_load);
+   writel(0, ®s->timer2_match1);
+   writel(0, ®s->timer2_match2);
+
+   /* Enable Timer2 */
+   setbits_le32(®s->cr,
+   FTTMR010_TM2_OFENABLE | FTTMR010_TM2_ENABLE);
+
+   /* Wait until timeout */
+   while (!(readl(®s->interrupt_state) & FTTMR010_TM2_ISRMASK))
+   ;
+}
+
+void reset_timer_masked(void)
+{
+   ulong freq = gd->arch.timer_rate_hz;
+
+   /* Disable Timer1 */
+   clrbits_le32(®s->cr, FTTMR010_TM1_CRMASK);
+
+   /* Disable & Clear Timer1 interrupts */
+   writel(FTTMR010_TM1_ISRMASK, ®s->interrupt_mask);
+   writel(FTTMR010_TM1_ISRMASK, ®s->interrupt_state);
+
+   /* Setup a longest periodic timer */
+   writel((0x / freq) * freq, ®s->timer1_counter);
+   writel((0x / freq) * freq, ®s->timer1_load);
+
+   writel(0, ®s->timer1_match1);
+   writel(0, ®s->timer1_match2);
+
+   /* Disable match interrupts */
+   writel(FTTMR010_TM1_MATCH1 | FTTMR010_TM1_MATCH2,
+   ®s->interrupt_mask);
+
+   /* Enable Timer1 with overflow interrupt */
+   setbits_le32(®s->cr,
+   FTTMR010_TM1_OFENABLE | FTTMR010_TM1_ENABLE);
+}
+
+ulong get_timer_masked(void)
+{
+   ulong freq = gd->arch.timer_rate_hz;
+   ulong secs = 0x / freq;
+   ulong ms = freq / CONFIG_SYS_HZ;
+
+   if (readl(®s->interrupt_state) & FTTMR010_TM1_ISRMASK) {
+   writel(FTTMR010_TM1_ISRMASK, ®s->interrupt_state);
+   gd->arch.tbl += secs * CONFIG_SYS_HZ;
+   }
+
+   return gd->arch.tbl
+   + ((secs * freq) - readl(®s->timer1_counter)) / ms;
+}
+
+int timer_init(void)
+{
+   gd->arch.tbl = 0;
+   reset_timer_masked();
+   return 0;
+}
+
+void reset_timer(void)
+{
+   reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+   return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+   udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+   return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+   return CONFIG_SYS_HZ;
+}
diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h
index 2ab68d1..21ab113 100644
--- a/include/faraday/fttmr010.h
+++ b/include/fara

[U-Boot] [PATCH v11 1/6] arm: add Faraday ARMv5TE cores support

[Kuo-Jung Su]

From: Kuo-Jung Su 

Here is the list of verified cores:

1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)

Signed-off-by: Kuo-Jung Su 
CC: Albert Aribaud 
---
Changes for v11:
- Nothing updates

Changes for v10:
- Merge [arm: add Faraday SoC helper files]

Changes for v9:
- Build 'arch_preboot_os()' only when CONFIG_CMD_BOOTM is defined.
- Add do_go_exec() to override the default behavior of 'go' command.

Changes for v8:
- add arm_init_before_mmu() & mmu_page_table_flush()

Changes for v7:
- Update license to use SPDX identifiers.

Changes for v6:
- Nothing updates

Changes for v5:
- Initial commit

 arch/arm/cpu/faraday/Makefile|   10 +
 arch/arm/cpu/faraday/cache.c |  164 +++
 arch/arm/cpu/faraday/config.mk   |   15 ++
 arch/arm/cpu/faraday/cpu.c   |  115 +++
 arch/arm/cpu/faraday/start.S |  407 ++
 arch/arm/include/asm/faraday.h   |   13 ++
 include/common.h |3 +
 include/configs/faraday-common.h |  314 +
 8 files changed, 1041 insertions(+)
 create mode 100644 arch/arm/cpu/faraday/Makefile
 create mode 100644 arch/arm/cpu/faraday/cache.c
 create mode 100644 arch/arm/cpu/faraday/config.mk
 create mode 100644 arch/arm/cpu/faraday/cpu.c
 create mode 100644 arch/arm/cpu/faraday/start.S
 create mode 100644 arch/arm/include/asm/faraday.h
 create mode 100644 include/configs/faraday-common.h

diff --git a/arch/arm/cpu/faraday/Makefile b/arch/arm/cpu/faraday/Makefile
new file mode 100644
index 000..c859238
--- /dev/null
+++ b/arch/arm/cpu/faraday/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+extra-y := start.o
+
+obj-y   += cpu.o cache.o
diff --git a/arch/arm/cpu/faraday/cache.c b/arch/arm/cpu/faraday/cache.c
new file mode 100644
index 000..2acb954
--- /dev/null
+++ b/arch/arm/cpu/faraday/cache.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2013
+ * Faraday Technology Corporation. 
+ * Kuo-Jung Su 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * I-Cache
+ */
+
+void invalidate_icache_all(void)
+{
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+   asm volatile (
+   "mov r0, #0\n"
+   "mcr p15, 0, r0, c7, c5, 0\n"
+   : /* output */
+   : /* input */
+   : "r0"
+   );
+#endif /* !CONFIG_SYS_ICACHE_OFF */
+}
+
+/*
+ * D-Cache
+ */
+
+void flush_dcache_all(void)
+{
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+   asm volatile (
+   "mov r0, #0\n"
+   "mcr p15, 0, r0, c7, c14, 0\n" /* clean & invalidate */
+   "mcr p15, 0, r0, c7, c10, 4\n" /* drain write buffer */
+   : /* output */
+   : /* input */
+   : "r0"
+   );
+#endif /* !CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+   unsigned long line = CONFIG_SYS_CACHELINE_SIZE;
+   unsigned long mask = ~(line - 1);
+
+   /* aligned to cache line */
+   stop = (line - 1 + stop) & mask;
+   start = start & mask;
+
+   asm volatile (
+   "1:\n"
+   "mcr p15, 0, %0, c7, c14, 1\n" /* clean & invalidate */
+   "add %0, %0, %2\n"
+   "cmp %0, %1\n"
+   "blo 1b\n"
+   "mov r0, #0\n"
+   "mcr p15, 0, r0, c7, c10, 4\n" /* drain write buffer */
+   : "+r"(start)
+   : "r"(stop), "r"(line)
+   : "r0"
+   );
+#endif /* !CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+   unsigned long line = CONFIG_SYS_CACHELINE_SIZE;
+   unsigned long mask = ~(line - 1);
+
+   /* aligned to cache line */
+   stop = (line - 1 + stop) & mask;
+   start = start & mask;
+
+   asm volatile (
+   "1:\n"
+   "mcr p15, 0, %0, c7, c6, 1\n"
+   "add %0, %0, %2\n"
+   "cmp %0, %1\n"
+   "blo 1b\n"
+   : "+r"(start)
+   : "r"(stop), "r"(line)
+   );
+#endif /* !CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_all(void)
+{
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+   asm volatile (
+   "mov r0, #0\n"
+   "mcr p15, 0, r0, c7, c6, 0\n"
+   : /* output */
+   : /* input */
+   : "r0"
+   );
+#endif /* !CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+   flush_dcache_range(start, start + size);
+}
+
+/*
+ * MMU
+ */
+
+static void invalidate_utlb_all(void)
+{
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+   asm volatile (
+   "mov r0, #0

Re: [U-Boot] [PATCH 2/2] T1040QDS: Add support of 2 stage SPI bootloader

[Priyanka Jain]

Hello Rommel,

This patch is abandoned. We are working on new set of patches.
We will send them upstream and in FSL SDK once ready.

Regards
Priyanka


> -Original Message-
> From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
> On Behalf Of Rommel G Custodio
> Sent: Wednesday, March 26, 2014 4:19 AM
> To: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH 2/2] T1040QDS: Add support of 2 stage SPI
> bootloader
> 
> Dear Priyanka Jain,
> 
> Priyanka Jain  freescale.com> writes:
> 
> >
> > Add support of 2-stage T1040QDS SPI bootloader using SPL framework.
> > In this, PBL (hardware) initializes SRAM (256K) and copy SPL
> > (192K) from SPI flash to SRAM and transfer control to SPL.
> > This SPL bootloader furthur initializes DDR using SPD and environment
> > and copy final u-boot image (512K) from SPI flash to DDR and transfer
> > control to final u-boot.
> 
> Is this code already in mainline? Or in the FSL SDK (which version)?
> 
> I'm locally testing out these series of patches on the QDS and it doesn't
> want to boot. The DIP switches are set to serial NOR Flash, which
> contains RCW + PBI + SPL + main u-boot.
> 
> ><8 snip 8><
> 
> All the best,
> Rommel
> 
> 
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
> 

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Re: [U-Boot] [PATCH 2/2] T1040QDS: Add support of 2 stage SPI bootloader

[Rommel G Custodio]

Dear Priyanka Jain,

Priyanka Jain  freescale.com> writes:

> 
> Add support of 2-stage T1040QDS SPI bootloader using SPL framework.
> In this, PBL (hardware) initializes SRAM (256K) and copy SPL
> (192K) from SPI flash to SRAM and transfer control to SPL.
> This SPL bootloader furthur initializes DDR using SPD and
> environment and copy final u-boot image (512K) from SPI flash
> to DDR and transfer control to final u-boot.

Is this code already in mainline? Or in the FSL SDK (which version)?

I'm locally testing out these series of patches on the QDS and it doesn't want 
to boot. The DIP switches are set to serial NOR Flash, which contains RCW + 
PBI + SPL + main u-boot.

><8 snip 8><

All the best,
Rommel


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Re: [U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

Dear Tom,

In message <20140325200435.GV16360@bill-the-cat> you wrote:
> 
> But as Wolfgang's v4 shows, it's also not hard to just call
> clrsetbits_le32 directly.  Arguably the cases where mask==1 we should
> just call setbits_le32 but that's not a big deal.

We would have to call setbits_le32() or clrbits_le32() depending on
the arguments...

I was already about to rewrite the code more in the style previously
used, i. e. turn for example

134 clrsetbits_le32(reg, 1 << TRI_SHIFT(pin),
135 (tri == PMUX_TRI_TRISTATE) << TRI_SHIFT(pin));

back into

if (tri == PMUX_TRI_TRISTATE)
setbits_le32(reg, 1 << TRI_SHIFT(pin));
else
clrbits_le32(reg, 1 << TRI_SHIFT(pin));

but then I decided to keep the changes copmpared to the
update_reg_mask_shift_val() version minimal.

If the if/then version should be preferred, I can easily redo that
patch.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
No, I'm not going to explain it. If you  can't  figure  it  out,  you
didn't want to know anyway... :-)
   - Larry Wall in <1991aug7.180856.2...@netlabs.com>
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Re: [U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

Dear Tom,

In message <20140325200420.GU16360@bill-the-cat> you wrote:
> 
> With respect to danger / readability, no, either way is just as
> dangerous (or not dangerous) and it's still fairly dense code either
> way and fixing a problem with an incorrect shift value is the same
> effort.

The key problem which I detected with sr32() was that it was in
several places called with a width of 32 - which looked perfectly fine
when the intention was to clear / set the whole 32 bit variable.  This
went unnoticed becuase it was just a normally looking argument.  If
the shift operation that resulted from that had been visible, the
problem would have been much easier to detect.  Seeing an expression
"value << 32" on u32 data types rings some alarms.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
If I had to live my life again,  I'd  make  the  same  mistakes, only
sooner.  -- Tallulah Bankhead
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[U-Boot] [PATCH V2] 4xx: add support for new PMC440 revision with cleanup

[Matthias Fuchs]

This patch adds support for the new PMC440 hardware revision 1.4.
The board now uses Micrel KSZ9031 phys.

Add missing i2c initialization before reading bootstrap eeprom.

Fix a couple of coding style issues.

Make local functions static.

Signed-off-by: Matthias Fuchs 
---
 board/esd/pmc440/pmc440.c |  165 +++--
 1 file changed, 101 insertions(+), 64 deletions(-)

V2: 
 - combine two previous patches into a single one
 - put vsc8601 setup into a separate function
 - general cleanup
  - make local functions static
  - fix a couple of coding style issues

diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index e86996c..062ae67 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -12,7 +12,6 @@
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -34,14 +33,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH 
chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 extern void __ft_board_setup(void *blob, bd_t *bd);
 
 ulong flash_get_size(ulong base, int banknum);
-int pci_is_66mhz(void);
+static int pci_is_66mhz(void);
 int is_monarch(void);
-int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
+static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+uchar *buffer, unsigned cnt);
 
 struct serial_device *default_serial_console(void)
 {
@@ -58,23 +57,24 @@ struct serial_device *default_serial_console(void)
if (((val & 0xf000) >> 29) != 7)
return &eserial2_device;
 
-   ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
+   ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
if (!(scratchreg & 0x80)) {
/* mark scratchreg valid */
scratchreg = (scratchreg & 0xff00) | 0x80;
 
+   i2c_init_all();
+
i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
  0x10, buf, 4);
if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
scratchreg |= buf[2];
 
/* bringup delay for console */
-   for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
+   for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
udelay(1000);
-   }
} else
scratchreg |= 0x01;
-   out_be32((void*)GPIO0_ISR3L, scratchreg);
+   out_be32((void *)GPIO0_ISR3L, scratchreg);
}
 
if (scratchreg & 0x01)
@@ -93,10 +93,7 @@ int board_early_init_f(void)
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, 0xf840);
 
-   /*
-* Setup the GPIO pins
-* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config 
file
-*/
+   /* Setup the GPIO pins */
out_be32((void *)GPIO0_OR,0x4102);
out_be32((void *)GPIO0_TCR,   0x4c90011f);
out_be32((void *)GPIO0_OSRL,  0x28051400);
@@ -259,7 +256,7 @@ int misc_init_r(void)
 * USB suff...
 */
if ((act == NULL || strcmp(act, "host") == 0) &&
-   !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
+   !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
@@ -326,16 +323,16 @@ int misc_init_r(void)
mtsdr(SDR0_SRST1, 0x);
mtsdr(SDR0_SRST0, 0x);
 
-   if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+   if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
/* enable power on USB socket */
-   out_be32((void*)GPIO1_OR,
-in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+   out_be32((void *)GPIO1_OR,
+in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
}
 
printf("USB:   Host\n");
 
} else if ((strcmp(act, "dev") == 0) ||
-  (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+  (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
@@ -414,30 +411,31 @@ int misc_init_r(void)
 #endif
 
/* turn off POST LED */
-   out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
+   out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
/* turn on RUN LED */
-   out_be32((void*)GPIO0_OR,  in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
+   out_be32((void *)GPIO0_OR,
+in_be32((void 

Re: [U-Boot] [PATCH 6/6] pxe: additionaly check for fdt_file env variable

[Stephen Warren]

On 03/20/2014 04:13 PM, Dennis Gilmore wrote:
> some boards have used fdt_file while others have used fdtfile to
> define the name of the fdt file. If we do notget a fdtfile environment
> variable, additionally check for fdt_file.

Is this variable typically set by the user or by the default
environment? If the default environment, perhaps the variable name could
simply be changed?

Still, this change is fine by me,
Acked-by: Stephen Warren  diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c
> + if (!f1) {
> + f1 = getenv("fdt_file");
> + }

Doesn't checkpatch say to remove the {} there?
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Re: [U-Boot] [PATCH 1/6] add README.distro file

[Stephen Warren]

On 03/21/2014 12:48 PM, Tom Rini wrote:
> On Thu, Mar 20, 2014 at 05:12:56PM -0500, Dennis Gilmore wrote:
> 
>> Add documentation on how to setup a system to use the generic distro
>> configs and boot commands. This spells out what is needed to make a
>> system conformant, but does not limit the board to only the defaults.
>>
>> Signed-off-by: Dennis Gilmore 
> 
> [snip]
>> +suggested mapping:
>> +For suggestions on memory locations for arm systems  you must follow the
>> +guidelines specified in Documentation/arm/Booting in the Linux kernel tree.
>> +For other architectures you must follow the guidelines for the architecture.
> 
> Can you add something about what this means?  ie below base+128MB for
> kernel, because of this if possible base+128MB for fdt, fdt+512KB for
> ramdisk. And mention bootm_size to limit the relocation pool as well.  

I'm biased, but I like the explanations in
include/configs/tegraNN-common.h:-)
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Re: [U-Boot] [PATCH 2/6] add header with a generic set of boot commands defined.

[Stephen Warren]

On 03/21/2014 12:48 PM, Tom Rini wrote:
> On Thu, Mar 20, 2014 at 05:12:57PM -0500, Dennis Gilmore wrote:
> 
>> As the next step in a generic config we are introducing a set of generic boot
>> paramaters. Depending on the hardwares configuration, booting from supported
>> hardware will be enabled, mmc, usb, sata, scsi, ide, pxe and dhcp.
>>
>> There is nothing to stop this being extended to support nand and any other
>> type of storage that comes along. An ideal future enhancement will be to
>> allow the user to dynamically reorder the boot devices, and allow one off
>> boots. for example simply be able to pxe boot to reinstall
> [snip]
>> +"bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" \
>> +"bootcmd_mmc1=setenv devnum 1; run mmc_boot;\0"
>> +#define BOOT_TARGETS_MMC "mmc1 mmc0"
> 
> This is because we want to prefer eMMC to SD card?  Or is mmc1=SD,
> mmc0=eMMC on Tegra?  That's opposite of TI parts so we might need to
> #ifndef/define/endif that combo at least.

On most (all?) Tegra devices, mmc1 is SD and mmc0 is eMMC. We prefer to
try to boot from SD first so that the user can just plug in an SD card
to boot from it if they want, but otherwise boot from eMMC (just like
floppy vs HDD on a PC) without having to muck with boot order manually.

Well, that and I almost exclusively boot from SD, so it's marginally
faster and less noisy:-)
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Re: [U-Boot] [PATCH 2/6] add header with a generic set of boot commands defined.

[Stephen Warren]

On 03/20/2014 04:12 PM, Dennis Gilmore wrote:
> As the next step in a generic config we are introducing a set of generic boot
> paramaters. Depending on the hardwares configuration, booting from supported
> hardware will be enabled, mmc, usb, sata, scsi, ide, pxe and dhcp.
> 
> There is nothing to stop this being extended to support nand and any other
> type of storage that comes along. An ideal future enhancement will be to
> allow the user to dynamically reorder the boot devices, and allow one off
> boots. for example simply be able to pxe boot to reinstall

One-off boots can already be performed: "run bootcmd_mmc1" or "run
bootcmd_dhcp" work for me.

> diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h

> +#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H
> +#define _CONFIG_CMD_DISTRO_BOOTCMD_H
> +
> +

Nit: double blank line there.

> +#ifdef CONFIG_CMD_MMC
> +#define BOOTCMDS_MMC \
> + "mmc_boot=" \
> + "setenv devtype mmc; " \
> + "if mmc dev ${devnum}; then " \
> + "run scan_boot; " \
> + "fi\0" \
> + "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" \
> + "bootcmd_mmc1=setenv devnum 1; run mmc_boot;\0"
> +#define BOOT_TARGETS_MMC "mmc1 mmc0"

It would be nice if this required the file that includes this file to
define how many MMC devices there are (some only have 1...) and the best
default boot order.

Still, that's probably challenging using the C pre-processor. Perhaps a
Python script to auto-generate these command could be more flexible.
Probably a job for a follow-on patch though.

> +#define BOOTCMDS_COMMON \
> + "rootpart=1\0" \
> + \
> + "do_envimport="   \
> + "load ${devtype} ${devnum}:${rootpart} ${loadaddr} "  \
> + "${environment}\0"\
> + "env import -t ${loadaddr} $filesize\0"   \

I think that should be:

if load ; then
env import ...;
fi

So the script doesn't accidentally import something stale at $loadaddr
that wasn't actually loaded.

> + \
> + "envimport="  \
> + "for environment in ${boot_envs}; do "\
> + "if test -e ${devtype} ${devnum}:${rootpart} "\
> + "${prefix}${environment}; then "  \
> + "echo Found U-Boot environment "  \
> + "${prefix}${environment}; "   \
> + "run do_envimport;"   \
> + "echo Import FAILED; continuing...; " \
> + "fi; "\
> + "done\0"  \
> + \

envimport doesn't actually seem to be used anywhere at least in this
patch. Is it really needed? It shouldn't be needed for generic distro
support, but more for boards without any non-filesystem-based
environment storage, and in those cases, shouldn't they use
CONFIG_PREBOOT like rpi_b.h does, so it's well-defined where the
environment comes from, before ${boot_targets} is evaluated?

> + "do_script_boot=" \
> + "load ${devtype} ${devnum}:${rootpart} "  \
> + "${scriptaddr} ${prefix}${script}; "  \
> + "source ${scriptaddr}\0"  \

That should be "if load ; ...; fi" too. Sorry, the Tegra/RPI scripts
give bad examples for this.
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Re: [U-Boot] [PATCH 1/6] add README.distro file

[Stephen Warren]

On 03/20/2014 04:12 PM, Dennis Gilmore wrote:
> Add documentation on how to setup a system to use the generic distro
> configs and boot commands. This spells out what is needed to make a
> system conformant, but does not limit the board to only the defaults.

> diff --git a/doc/README.distro b/doc/README.distro

> +There is some memory addresses you will need to define in
> +CONFIG_EXTRA_ENV_SETTINGS
> +fdt_addr:
> +Optional, If specified a dtb to boot the system must be available at the 
> given
> +address.

Perhaps add "when the kernel is booted"? To avoid someone putting it
somewhere that will get over-written between when U-Boot starts and the
kernel is booted.

> +fdt_addr_r:
> +Mandatory, This is the location where the sysboot/pxeboot with load the dtb 
> to,

s/with/will/ Both here and other place(s).

> +using the fdtdir/devicetreedir or fdt/devicetree options in the pxe/extlinux
> +config file. The location can be anywhere in ram it just needs to not overlap
> +with anything, allowing 1 megabyte seems to be a safe option.

Related to Tom's comments, I think saying that the location doesn't
matter isn't quite true. For example, an ARM zImage assumes it's located
with the first 128M of RAM, and will decompress the image to the start
of RAM. If the DTB was located in the decompression target region, it
would at least need to be moved by the decompressor (wasted effort) or
perhaps just get blindly over-written (boot fails).

> +ramdisk_addr_r:
> +Mandatory, This is the location where the sysboot/pxeboot with load the
> +initramfs to, using the initrd option in the pxe/extlinux config file, the
> +location of the initramfs does not matter, there needs to be enough room to 
> be
> +able to store any image. Making the image the last item stored should allow 
> for
> +any initramfs to fit and not overwrite anything else.

"last item" could refer to time not space. Perhaps s/Making the image
the last item stored/Placing the image higher in RAM than any other image/

> +kernel_addr_r:
> +Mandatory, This is the location where the sysboot/pxeboot with load the 
> kernel
> +to,using the kernel option in the pxe/extlinux config file, the location of 
> the
> +kernel needs to 

That sentence isn't complete.

> +You should not set initrd_high and fdt_high to 0x as the user should
> +not need to edit the memory locations having the initramfs and dtb being
> +relocatable is best to ensure the system will boot in all situations. 

Perhaps CONFIG_SYS_BOOTMAPSZ is worth a mention too. The commit
description for 7f1b767aea94 "ARM: tegra: define CONFIG_SYS_BOOTMAPSZ"
might be useful when writing this part of the document.

> +booting your system
> +---
> +in the most simplest form CONFIG_BOOTCOMMAND just needs one line
> +
> +"for target in ${boot_targets}; do run bootcmd_${target}; done "
> +
> +you can run any setup before going through the targets for example run a
> +command to set "fdtfile" variable for the dtb for your board.

Isn't this automatic based on using config_distro_defaults.h? It seems
like it should be, and it is were, you wouldn't need this section of
this document at all; it's happen automatically.
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Re: [U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Tom Rini]

On Tue, Mar 25, 2014 at 05:54:10PM +0100, Wolfgang Denk wrote:
> Dear Stephen Warren,
> 
> In message <1395764855-23377-1-git-send-email-swar...@wwwdotorg.org> you 
> wrote:
> > 
> > +static inline void update_reg_mask_shift_val(u32 *reg, u32 mask, u32 shift,
> > +u32 val)
> > +{
> > +   clrsetbits_le32(reg, mask << shift, val << shift);
> > +}
> 
> No, please do not do that.  Please use plain clrsetbits_le32() as is.
> All these hidden shifts are (a) mostly unreadable and (b) sometimes
> dangerous.

No, this is why the lack of comments hurts things.  This isn't sr32 from
OMAP-land (which was on my todo list somewhere, thanks).  sr32 was an
incorrect generic function.  This is a specific-use function that should
say something like:
/*
 * Set the correct pinmux value for a given part.  We need to clear out
 * M bits worth of the field and then set possibly less than M bits
 * worth of value.
 */

With respect to danger / readability, no, either way is just as
dangerous (or not dangerous) and it's still fairly dense code either
way and fixing a problem with an incorrect shift value is the same
effort.

-- 
Tom


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Re: [U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Tom Rini]

On Tue, Mar 25, 2014 at 10:27:35AM -0600, Stephen Warren wrote:

> From: Stephen Warren 
> 
> This removes a bunch of open-coded register IO, masking, and shifting.
> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
> except that keeping it a separate commit allows easier bisection of any
> issues that are introduced by this patch. I also wrote this patch on top
> of the series, and pushing it any lower in the series results in some
> conflicts I didn't feel like fixing.

Since things got a bit heated here while I was reading some other
stuff...

[snip]

> +static inline void update_reg_mask_shift_val(u32 *reg, u32 mask, u32 shift,
> +  u32 val)
> +{
> + clrsetbits_le32(reg, mask << shift, val << shift);
> +}

So, lack of comments bad.  Intention, good.  We have a bitfield of size
M (that's all cleared in the mask) and value that may be less than M
bits wide.  The name is a mouthful (but I see where Simon was coming
from, had I caught in time I might have suggested a comment instead.

But as Wolfgang's v4 shows, it's also not hard to just call
clrsetbits_le32 directly.  Arguably the cases where mask==1 we should
just call setbits_le32 but that's not a big deal.

-- 
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Re: [U-Boot] [PATCH V4 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Stephen Warren]

On 03/25/2014 01:09 PM, Wolfgang Denk wrote:
> From: Stephen Warren 
> 
> This removes a bunch of open-coded register IO, masking, and shifting.
> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
> except that keeping it a separate commit allows easier bisection of any
> issues that are introduced by this patch. I also wrote this patch on top
> of the series, and pushing it any lower in the series results in some
> conflicts I didn't feel like fixing.
> 
> Signed-off-by: Stephen Warren 
> Signed-off-by: Wolfgang Denk 
> ---
> V4: [wd] Drop update_reg_mask_shift_val() and use clrsetbits_le32()
> directly.

I believe your own argument compels you to NAK this patch yourself.

In both V3 and V4:

1) Some very simple and obviously understandable open-coded bit
manipulation is replaced with a function call which hides the details of
the bit manipulation.

2) In both cases, the order of parameters to the function does actually
appear to be obvious from the function name: clrsetbits_le32(clr, set),
update_reg_mask_shift_val(reg, mask, shift, val)

3) I've seen plenty of examples where the function name doesn't
correctly describe what the function does, or the parameter order
doesn't match what would appear to be logical. Hence, in neither case is
point (2) relevant; one must /always/ check or remember the prototype of
a function in order to validate that the parameters at a call-site are
correct. Not checking means making an assumption, and assumptions can be
incorrect.

Now, I believe you argued that it was unsafe to hide the details of the
bit manipulation behind a function precisely because it was then harder
to see what the code was doing, and easier to pass the wrong values to
the function parameters, and this wouldn't be obvious at the call site.

I believe the /exact/ same argument applies no matter whether the
function is clrsetbits_le32() or update_reg_mask_shift_val().

Hence, if V3 which used update_reg_mask_shift_val() was unacceptable,
then so is this.

So NAK.
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Re: [U-Boot] [PATCH v4 6/6] trats/trats2: enable CONFIG_RANDOM_UUID

[Stephen Warren]

On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
> Signed-off-by: Przemyslaw Marczak 

Patch description? Why are these function useful on these platforms?

For completeness (I have no real ack power of Samsung platforms),
Acked-by: Stephen Warren 
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Re: [U-Boot] [PATCH v4 5/6] cmd:gpt: randomly generate each partition uuid if undefined

[Stephen Warren]

On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
> Changes:
> - randomly generate partition uuid if any is undefined and CONFIG_RAND_UUID
>   is defined
> - print debug info about set/unset/generated uuid
> - update doc/README.gpt
> 
> Update existing code to the new library functions.

The changelog should be below the --- line, and a patch description
should exist.

Assuming the comments below are fixed,
Acked-by: Stephen Warren 

> diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c

> -static char extract_env(const char *str, char **env)
> +static int extract_env(const char *str, char **env)
>  {
> + int ret = -1;
>   char *e, *s;
> -
> +#ifdef CONFIG_RANDOM_UUID
> + char uuid_str[UUID_STR_LEN + 1];
> +#endif
>   if (!str || strlen(str) < 4)

The blank line needs to be after the #endif not before the #ifdef, so
the variable declarations are separate from the code.

>   return -1;
>  
> - if ((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')) {
> - s = strdup(str);
> - if (s == NULL)
> - return -1;
> - memset(s + strlen(s) - 1, '\0', 1);
> - memmove(s, s + 2, strlen(s) - 1);
> + if (!((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')))
> + return -1;

Since you're inverting that test, you need to change && to || too.

> diff --git a/doc/README.gpt b/doc/README.gpt
> index 5c133f3..51515c8 100644
> --- a/doc/README.gpt
> +++ b/doc/README.gpt
> @@ -101,7 +101,7 @@ Offset  SizeDescription
>  40  8 B First usable LBA for partitions (primary partition table last
>   LBA + 1)
>  48  8 B Last usable LBA (secondary partition table first LBA - 1)
> -56  16 BDisk GUID (also referred as UUID on UNIXes)
> +56  16 BDisk GUID (also referred as UUID on UNIXes) in big endian

According to your earlier comment, GUIDs have a mix of LE and BE fields,
so I would simply drop this change and the similar change below. Let
wikipedia or the comment you added near to top of lib/uuid.c specify the
details.

> @@ -160,6 +160,9 @@ To restore GUID partition table one needs to:
> Fields 'name', 'size' and 'uuid' are mandatory for every partition.
> The field 'start' is optional.
>  
> +   option: CONFIG_RANDOM_UUID
> +   If any partition "uuid" no exists then it is randomly generated.

s/"uuid"/UUID/
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Re: [U-Boot] [PATCH v4 4/6] new commands: uuid and guid - generate random unique identifier

[Stephen Warren]

On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
> Those commands basis on implementation of random UUID generator version 4
> which is described in RFC4122. The same algorithm is used for generation
> both ids but string representation is different as below.
> 
> char:  0914   19   24 36
>----
> UUID: be be   be   be   be
> GUID: le le   le   be   be
> 
> Commands usage:
> - uuid 
> - guid 

Square brackets are usually used to indicate optional parameters:

- uuid []
- guid []

> diff --git a/include/common.h b/include/common.h

>  #if defined(CONFIG_RANDOM_MACADDR) || \
>   defined(CONFIG_BOOTP_RANDOM_DELAY) || \
>   defined(CONFIG_CMD_LINK_LOCAL) || \
> - defined(CONFIG_RANDOM_UUID)
> + defined(CONFIG_RANDOM_UUID) || \
> + defined(CONFIG_CMD_UUID)

Why not require that if you want to use CONFIG_CMD_UUID, you must define
CONFIG_RANDOM_UUID too? You can even make that automatic in
include/config_fallbacks.h which already does similar things:

#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT)
#define CONFIG_FS_FAT
#endif

That way, you won't need to touch lib/Makefile in this patch either, or
modify the ifdef that wraps gen_rand_uuid().

> diff --git a/lib/uuid.c b/lib/uuid.c


> +#ifdef CONFIG_CMD_UUID
> +int do_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> + char uuid[UUID_STR_LEN + 1];
> + uuid_str_t str_format;
> +
> + if (!strcmp(argv[0], "uuid"))
> + str_format = UUID_STR_FORMAT_STD;
> + else
> + str_format = UUID_STR_FORMAT_GUID;
> +
> + if (argc == 1) {
> + gen_rand_uuid_str(uuid, str_format);
> + printf("%s\n", uuid);
> + } else if (argc == 2) {
> + gen_rand_uuid_str(uuid, str_format);
> + setenv(argv[1], uuid);
> + } else {
> + return CMD_RET_USAGE;
> + }

This duplicates some code; the call to gen_rand_uuid(). I think it would
be better as:

if (argc < 2)
return CMD_RET_USAGE;
gen_rand_uuid_str(uuid, str_format);
if (argc == 1)
printf("%s\n", uuid);
else
setenv(argv[1], uuid);

> +U_BOOT_CMD(uuid, CONFIG_SYS_MAXARGS, 1, do_uuid,
> + "UUID - generate Universally Unique Identifier version 4",

Would it be batter to say "a random ..." rather than "... version 4"?
I'm not sure if the details of the version matter so long as its a valid
UUID, and certainly the fact the generated UUID is random is likely more
interesting.

> + "\n"

"[]\n"

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Re: [U-Boot] [PATCH v4 3/6] lib: uuid: add functions to generate UUID version 4

[Stephen Warren]

On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
> This patch adds support to generate UUID (Universally Unique Identifier)
> in version 4 based on RFC4122, which is randomly.
> 
> Source: https://www.ietf.org/rfc/rfc4122.txt

Some nits in the comments below, but otherwise:
Acked-by: Stephen Warren 

> diff --git a/include/uuid.h b/include/uuid.h

> +/* This is structure is in big-endian */
> +struct uuid {

Not any more; with the introduction of enum uuid_str_t, some of the
fields could be either LE or BE. I would say "See the comment near the
top of lib/uuid.c for details of the endianness of fields in this struct".

> diff --git a/lib/uuid.c b/lib/uuid.c

>  /*
>   * UUID - Universally Unique IDentifier - 128 bits unique number.
>   *There are 5 versions and one variant of UUID defined by RFC4122
> - *specification. Depends on version uuid number base on a time,
> - *host name, MAC address or random data.
> + *specification. Depends on version uuid number base on:

I still have no idea what "Depends on version uuid number base on" means.

> + *- time, MAC address(v1),
> + *- user ID(v2),
> + *- MD5 of name or URL(v3),
> + *- random data(v4),
> + *- SHA-1 of name or URL(v5),
> + *
> + * This library implements UUID v4.

I think that should say "gen_rand_uuid()" not "This library", since the
source of the data in the UUID fields only matters when creating the
UUID, not when performing str<->bin conversion.

> + *
> + * Layout of UUID Version 4:
> + * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
> + * version   - 4 bit (bit 4 through 7 of the time_hi_and_version)
> + * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
> + * variant:  - bit 6 and 7 of clock_seq_hi_and_reserved
> + * node  - 48 bit
> + * In this version all fields beside 4 bit version are randomly generated.
> + * source: https://www.ietf.org/rfc/rfc4122.txt

gen_rand_uuid() doesn't actually honor that format; it creates pure
random data rather than filling in any timestamps, clock sequence data, etc.
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Re: [U-Boot] [PATCH] ARM: tegra: add Jetson TK1 board

[Stephen Warren]

On 03/25/2014 01:13 PM, Wolfgang Denk wrote:
> Dear Stephen,
> 
> In message <1395769173-8143-1-git-send-email-swar...@wwwdotorg.org> you wrote:
>>
>> Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of
>> its design with Venice2.
> ...
>> +++ b/include/configs/jetson-tk1.h
>> @@ -0,0 +1,79 @@
>> +/*
>> + * (C) Copyright 2013-2014
>> + * NVIDIA Corporation 
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
> 
> Is there any specific reason this is not GPL-2.0+ ?

Oops. I evidently cut/paste from the wrong place. Please consider that
to say GPL-2.0+. Tom, can you fix this while applying, or do you want a
repost (I'd probably hold off on a repost until after 2014.04 is out in
case there are any other comments).
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Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

Dear Tom,

In message <5331bc48.7020...@wwwdotorg.org> Stephen Warren wrote:
> On 03/21/2014 12:28 PM, Stephen Warren wrote:
> > From: Stephen Warren 
> > 
> > This removes a bunch of open-coded register IO, masking, and shifting.
> > I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
> > except that keeping it a separate commit allows easier bisection of any
> > issues that are introduced by this patch. I also wrote this patch on top
> > of the series, and pushing it any lower in the series results in some
> > conflicts I didn't feel like fixing.
> 
> Tom, when applying this series, please just drop this patch. Also,
> ignore V3 of this patch. Thanks.

Alternatively, please consider patch V4 which I just posted.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH] ARM: tegra: add Jetson TK1 board

[Wolfgang Denk]

Dear Stephen,

In message <1395769173-8143-1-git-send-email-swar...@wwwdotorg.org> you wrote:
> 
> Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of
> its design with Venice2.
...
> +++ b/include/configs/jetson-tk1.h
> @@ -0,0 +1,79 @@
> +/*
> + * (C) Copyright 2013-2014
> + * NVIDIA Corporation 
> + *
> + * SPDX-License-Identifier: GPL-2.0

Is there any specific reason this is not GPL-2.0+ ?


Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH v4 2/6] lib: uuid: code refactor for proper maintain between uuid bin and string

[Stephen Warren]

On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
> Changes in lib/uuid.c to:
> - uuid_str_to_bin()
> - uuid_bin_to_str()
> 
> New parameter is added to specify input/output string format in listed 
> functions
> This change allows easy recognize which UUID type is or should be stored in 
> given
> string array. Binary data of UUID and GUID is always stored in big endian, 
> only
> string representations are different as follows.
> 
> String byte: 0  36
> String char: ----
> string UUID:be be   be   be   be
> string GUID:le le   le   be   be
> 
> This patch also updates functions calls and declarations in a whole code.

Ah, this patch pretty much solves all the comments I had on patch 1/6,
so feel free to ignore those.

Just a couple minor points below, but otherwise, patches 1 and 2,
Acked-by: Stephen Warren 

> diff --git a/include/uuid.h b/include/uuid.h

> +typedef enum {
> + UUID_STR_FORMAT_STD,
> + UUID_STR_FORMAT_GUID
> +} uuid_str_t;

I would rename "STD" to "UUID"; after all, someone wanting to use GUIDs
might think /that/ is the standard format:-)

But this is a bit bike-sheddy/nit-picky, so if you don't want to I won't
object.

> diff --git a/lib/uuid.c b/lib/uuid.c


> +void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str,
> +  uuid_str_t str_format)
>  {
> - static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
> -   12, 13, 14, 15};
> + const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8,
> +   9, 10, 11, 12, 13, 14, 15};
> + const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
> +   9, 10, 11, 12, 13, 14, 15};

These are really more binary data order than char order, since each one
of the bytes pointed at by entries in these arrays ends up being 2
characters. s/char/bin/ in the variable names perhaps?

> + const u8 *char_order;
>   int i;
>  
> + /*
> +  * UUID and GUID bin data - always in big endian:
> +  * 4B-2B-2B-2B-6B
> +  * be be be be be

Strings don't really have an endianness, since they're already byte
data. Rather than endianness, you really mean "normal numerical digit
ordering". This comment also applies to the description of UUID string
formats in patch 1/6.
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[U-Boot] [PATCH V4 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

From: Stephen Warren 

This removes a bunch of open-coded register IO, masking, and shifting.
I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
except that keeping it a separate commit allows easier bisection of any
issues that are introduced by this patch. I also wrote this patch on top
of the series, and pushing it any lower in the series results in some
conflicts I didn't feel like fixing.

Signed-off-by: Stephen Warren 
Signed-off-by: Wolfgang Denk 
---
V4: [wd] Drop update_reg_mask_shift_val() and use clrsetbits_le32()
directly.
V3: Rename update_field() to update_reg_mask_shift_val() to make the
parameter order more obvious.
V2: New patch.

 arch/arm/cpu/tegra-common/pinmux-common.c | 137 ++
 1 file changed, 25 insertions(+), 112 deletions(-)

diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c 
b/arch/arm/cpu/tegra-common/pinmux-common.c
index 32a46d5..fec5e37 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -91,7 +91,6 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func 
func)
 {
u32 *reg = MUX_REG(pin);
int i, mux = -1;
-   u32 val;
 
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
@@ -110,42 +109,30 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func 
func)
}
assert(mux != -1);
 
-   val = readl(reg);
-   val &= ~(3 << MUX_SHIFT(pin));
-   val |= (mux << MUX_SHIFT(pin));
-   writel(val, reg);
+   clrsetbits_le32(reg, 3 << MUX_SHIFT(pin), mux << MUX_SHIFT(pin));
 }
 
 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
 {
u32 *reg = PULL_REG(pin);
-   u32 val;
 
/* Error check on pin and pupd */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_pupd_isvalid(pupd));
 
-   val = readl(reg);
-   val &= ~(3 << PULL_SHIFT(pin));
-   val |= (pupd << PULL_SHIFT(pin));
-   writel(val, reg);
+   clrsetbits_le32(reg, 3 << PULL_SHIFT(pin), pupd << PULL_SHIFT(pin));
 }
 
 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
 {
u32 *reg = TRI_REG(pin);
-   u32 val;
 
/* Error check on pin */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_tristate_isvalid(tri));
 
-   val = readl(reg);
-   if (tri == PMUX_TRI_TRISTATE)
-   val |= (1 << TRI_SHIFT(pin));
-   else
-   val &= ~(1 << TRI_SHIFT(pin));
-   writel(val, reg);
+   clrsetbits_le32(reg, 1 << TRI_SHIFT(pin),
+   (tri == PMUX_TRI_TRISTATE) << TRI_SHIFT(pin));
 }
 
 void pinmux_tristate_enable(enum pmux_pingrp pin)
@@ -162,7 +149,6 @@ void pinmux_tristate_disable(enum pmux_pingrp pin)
 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
 {
u32 *reg = REG(pin);
-   u32 val;
 
if (io == PMUX_PIN_NONE)
return;
@@ -171,18 +157,13 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io 
io)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_io_isvalid(io));
 
-   val = readl(reg);
-   if (io == PMUX_PIN_INPUT)
-   val |= (io & 1) << IO_SHIFT;
-   else
-   val &= ~(1 << IO_SHIFT);
-   writel(val, reg);
+   clrsetbits_le32(reg, 1 << IO_SHIFT,
+   (io == PMUX_PIN_INPUT) << IO_SHIFT);
 }
 
 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 {
u32 *reg = REG(pin);
-   u32 val;
 
if (lock == PMUX_PIN_LOCK_DEFAULT)
return;
@@ -191,23 +172,19 @@ static void pinmux_set_lock(enum pmux_pingrp pin, enum 
pmux_pin_lock lock)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_lock_isvalid(lock));
 
-   val = readl(reg);
-   if (lock == PMUX_PIN_LOCK_ENABLE) {
-   val |= (1 << LOCK_SHIFT);
-   } else {
+   if (lock == PMUX_PIN_LOCK_DISABLE) {
+   u32 val = readl(reg);
if (val & (1 << LOCK_SHIFT))
printf("%s: Cannot clear LOCK bit!\n", __func__);
-   val &= ~(1 << LOCK_SHIFT);
}
-   writel(val, reg);
 
-   return;
+   clrsetbits_le32(reg, 1 << LOCK_SHIFT,
+   (lock == PMUX_PIN_LOCK_ENABLE) << LOCK_SHIFT);
 }
 
 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 {
u32 *reg = REG(pin);
-   u32 val;
 
if (od == PMUX_PIN_OD_DEFAULT)
return;
@@ -216,21 +193,14 @@ static void pinmux_set_od(enum pmux_pingrp pin, enum 
pmux_pin_od od)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_od_isvalid(od));
 
-   val = readl(reg);
-   if (od == PMUX_PIN_OD_ENABLE)
-   val |= (1 << OD_SHIFT);
-   else
-   val &= ~(1 << OD_SHIFT);
-   writel(val, reg);
-
-   return;
+   clrsetbits_le32(reg, 1 << OD_SHIFT,
+   (od == PMU

Re: [U-Boot] [PATCH v4 1/6] part_efi: move uuid<->string conversion functions into lib/uuid.c

[Stephen Warren]

On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
> Changes:
> - move uuid<->string conversion functions into lib/uuid.c so they can be
>   used by code outside part_efi.c.
> - rename uuid_string() to uuid_bin_to_str() for consistency with existing
>   uuid_str_to_bin()
> - add an error return code to uuid_str_to_bin()
> 
> Update existing code to the new library functions.

> diff --git a/lib/uuid.c b/lib/uuid.c

> + * UUID string is 36 length of characters (36 bytes):
> + *
> + * 0914   19   24
> + * ----
> + *be be   be   be   be
...
> + * GUID:
>   * 0914   19   24
>   * ----
>   *le le   le   be   be
> + *
> + * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique 
> numbers.

Given that ...

> +void uuid_bin_to_str(unsigned char *uuid, char *str)
> +{
> + static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
> +   12, 13, 14, 15};

Should this actually be named uuid_bin_to_guid_str or guid_bin_to_str?

And "le" doesn't seem like the correct variable name, since it's
actually a mix of 3 LE and 2 BE conversions, isn't it?
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[U-Boot] [PATCH] ARM: tegra: add Jetson TK1 board

[Stephen Warren]

From: Stephen Warren 

Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of
its design with Venice2.

Signed-off-by: Stephen Warren 
---
This patch depends on my recent pinmux cleanup series.

 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/tegra124-jetson-tk1.dts   |  84 
 board/nvidia/jetson-tk1/Makefile   |   9 +
 board/nvidia/jetson-tk1/jetson-tk1.c   |  23 +++
 board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 227 +
 board/nvidia/venice2/as3722_init.h |   4 +
 boards.cfg |   1 +
 include/configs/jetson-tk1.h   |  79 +++
 8 files changed, 428 insertions(+)
 create mode 100644 arch/arm/dts/tegra124-jetson-tk1.dts
 create mode 100644 board/nvidia/jetson-tk1/Makefile
 create mode 100644 board/nvidia/jetson-tk1/jetson-tk1.c
 create mode 100644 board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
 create mode 100644 include/configs/jetson-tk1.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e2fcca567012..674b4f6ed727 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra30-cardhu.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
+   tegra124-jetson-tk1.dtb \
tegra124-venice2.dtb
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts 
b/arch/arm/dts/tegra124-jetson-tk1.dts
new file mode 100644
index ..52e8c0e59c6b
--- /dev/null
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+   model = "NVIDIA Jetson TK1";
+   compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
+
+   aliases {
+   i2c0 = "/i2c@7000d000";
+   i2c1 = "/i2c@7000c000";
+   i2c2 = "/i2c@7000c400";
+   i2c3 = "/i2c@7000c500";
+   i2c4 = "/i2c@7000c700";
+   i2c5 = "/i2c@7000d100";
+   sdhci0 = "/sdhci@700b0600";
+   sdhci1 = "/sdhci@700b0400";
+   spi0 = "/spi@7000d400";
+   spi1 = "/spi@7000da00";
+   usb0 = "/usb@7d008000";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x8000>;
+   };
+
+   i2c@7000c000 {
+   status = "okay";
+   clock-frequency = <10>;
+   };
+
+   i2c@7000c400 {
+   status = "okay";
+   clock-frequency = <10>;
+   };
+
+   i2c@7000c500 {
+   status = "okay";
+   clock-frequency = <10>;
+   };
+
+   i2c@7000c700 {
+   status = "okay";
+   clock-frequency = <10>;
+   };
+
+   i2c@7000d000 {
+   status = "okay";
+   clock-frequency = <40>;
+   };
+
+   i2c@7000d100 {
+   status = "okay";
+   clock-frequency = <40>;
+   };
+
+   spi@7000d400 {
+   status = "okay";
+   spi-max-frequency = <2500>;
+   };
+
+   spi@7000da00 {
+   status = "okay";
+   spi-max-frequency = <2500>;
+   };
+
+   sdhci@700b0400 {
+   status = "okay";
+   cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+   power-gpios = <&gpio 136 0>; /* gpio PR0 */
+   bus-width = <4>;
+   };
+
+   sdhci@700b0600 {
+   status = "okay";
+   bus-width = <8>;
+   };
+
+   usb@7d008000 {
+   status = "okay";
+   nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+   };
+};
diff --git a/board/nvidia/jetson-tk1/Makefile b/board/nvidia/jetson-tk1/Makefile
new file mode 100644
index ..0f054117c418
--- /dev/null
+++ b/board/nvidia/jetson-tk1/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y  += ../venice2/as3722_init.o
+obj-y  += jetson-tk1.o
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c 
b/board/nvidia/jetson-tk1/jetson-tk1.c
new file mode 100644
index ..f97aafad422b
--- /dev/null
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include "pinmux-config-jetson-tk1.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+   pinmux_config_pingrp_table(jetson_tk1_pingrps,
+  ARRAY_SIZE(jetson_tk1_pingrps));
+
+   pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
+  ARRAY_SIZE(jetson_tk1_drvgrps));
+}
diff --git a/board/nvidia/jetson-tk1/pinmux-config-j

Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Stephen Warren]

On 03/21/2014 12:28 PM, Stephen Warren wrote:
> From: Stephen Warren 
> 
> This removes a bunch of open-coded register IO, masking, and shifting.
> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
> except that keeping it a separate commit allows easier bisection of any
> issues that are introduced by this patch. I also wrote this patch on top
> of the series, and pushing it any lower in the series results in some
> conflicts I didn't feel like fixing.

Tom, when applying this series, please just drop this patch. Also,
ignore V3 of this patch. Thanks.
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Re: [U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

Dear Stephen Warren,

In message <5331b55b.7080...@wwwdotorg.org> you wrote:
>
> > No, please do not do that.  Please use plain clrsetbits_le32() as is.
> > All these hidden shifts are (a) mostly unreadable and (b) sometimes
> > dangerous.
> 
> Seriously, are you joking now?

No, I am not.

> If I was to write out the clrsetbits_le32() at each call site, I'd be
> writing out this supposedly dangerous shift N times instead of once. If

N = 2, to be precise.  And you have to type it only once, but to
maintain that code for a long, long time.

> the shift is somehow dangerous (BTW, it isn't!) then surely isolating it
> in one place, so that mistakes aren't made when writing the duplicate
> copies, is the right thing to do.

Well, I've just fixed a number of places were such code _was_
dangerous, but well hidden under a nice wrapper function like yours.

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

Dear Stephen Warren,

In message <5331b4e4.5090...@wwwdotorg.org> you wrote:
>
> > Please do not invent new bit manipulation functions.  Just use the
> > standard I/O accessors.  And whenever possible, please remove pre-
> > existing functions.
> > 
> > I've just recently sent patches to get rid of such "inventions" that
> > resulted in undefined code.
> 
> That's not what this code is doing. The existing IO accessors are used;
> it's just removing duplication from the parameters passed to the
> existing functions (the shift needs to be written out twice).

Yes, I've seen that.  You can save a little typ[ing this way.  But you
have to type it only once, and then maintain it forever.  And the
helper function obscures what is happening, which is bad.  It makes
the code more difficult to read and understand and maintain,
especially when the shift count is not easily recognizable - at least I
cannot really read what PULL_SHIFT(pin) decodes to.

Please make the code simple to read, use existing standard functions.



Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Stephen Warren]

On 03/25/2014 10:54 AM, Wolfgang Denk wrote:
> Dear Stephen Warren,
> 
> In message <1395764855-23377-1-git-send-email-swar...@wwwdotorg.org> you 
> wrote:
>>
>> +static inline void update_reg_mask_shift_val(u32 *reg, u32 mask, u32 shift,
>> + u32 val)
>> +{
>> +clrsetbits_le32(reg, mask << shift, val << shift);
>> +}
> 
> No, please do not do that.  Please use plain clrsetbits_le32() as is.
> All these hidden shifts are (a) mostly unreadable and (b) sometimes
> dangerous.

Seriously, are you joking now?

If I was to write out the clrsetbits_le32() at each call site, I'd be
writing out this supposedly dangerous shift N times instead of once. If
the shift is somehow dangerous (BTW, it isn't!) then surely isolating it
in one place, so that mistakes aren't made when writing the duplicate
copies, is the right thing to do.
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Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Stephen Warren]

On 03/25/2014 10:51 AM, Wolfgang Denk wrote:
> Dear Stephen Warren,
> 
> In message <5331a6b6.8090...@wwwdotorg.org> you wrote:
>>
>>> Or perhaps update_reg_mask_shift_val()?
>>
>> Still, I can rename the function if you want; it certainly does make it
>> obvious. It's rather a long name though, but I guess wrapping the
>> parameters isn't too bad.
> 
> Please do not invent new bit manipulation functions.  Just use the
> standard I/O accessors.  And whenever possible, please remove pre-
> existing functions.
> 
> I've just recently sent patches to get rid of such "inventions" that
> resulted in undefined code.

That's not what this code is doing. The existing IO accessors are used;
it's just removing duplication from the parameters passed to the
existing functions (the shift needs to be written out twice).

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Re: [U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

Dear Stephen Warren,

In message <1395764855-23377-1-git-send-email-swar...@wwwdotorg.org> you wrote:
> 
> +static inline void update_reg_mask_shift_val(u32 *reg, u32 mask, u32 shift,
> +  u32 val)
> +{
> + clrsetbits_le32(reg, mask << shift, val << shift);
> +}

No, please do not do that.  Please use plain clrsetbits_le32() as is.
All these hidden shifts are (a) mostly unreadable and (b) sometimes
dangerous.

Thanks.

Wolfgang Denk

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Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Wolfgang Denk]

Dear Stephen Warren,

In message <5331a6b6.8090...@wwwdotorg.org> you wrote:
>
> > Or perhaps update_reg_mask_shift_val()?
> 
> Still, I can rename the function if you want; it certainly does make it
> obvious. It's rather a long name though, but I guess wrapping the
> parameters isn't too bad.

Please do not invent new bit manipulation functions.  Just use the
standard I/O accessors.  And whenever possible, please remove pre-
existing functions.

I've just recently sent patches to get rid of such "inventions" that
resulted in undefined code.

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Stephen Warren]

On 03/25/2014 10:04 AM, Simon Glass wrote:
> On 25 March 2014 08:54, Stephen Warren  wrote:
>> On 03/24/2014 08:27 PM, Simon Glass wrote:
>>> On 21 March 2014 11:28, Stephen Warren  wrote:
 This removes a bunch of open-coded register IO, masking, and shifting.
 I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
 except that keeping it a separate commit allows easier bisection of any
 issues that are introduced by this patch. I also wrote this patch on top
 of the series, and pushing it any lower in the series results in some
 conflicts I didn't feel like fixing.

 Signed-off-by: Stephen Warren 
>>>
>>> Acked-by: Simon Glass 
>>>
>>> But see comment below.
>>
 diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c 
 b/arch/arm/cpu/tegra-common/pinmux-common.c
>>
 +static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
 +{
 +   clrsetbits_le32(reg, mask << shift, val << shift);
>>>
>>> I wonder if it would be better to write this out explicitly in each site.
...
 +   update_field(reg, 3, MUX_SHIFT(pin), mux);
>>>
>>> Because here you are obscuring the shift - the parameter order is by
>>> no means obvious.
>>
>> Well, for pretty much no function is it obvious from the function name
>> what the parameter order is; it's just one of those things you memorize
>> or look up. The exact same issue exists for clrsetbits_le32() itself IMHO.
> 
> Well that at least indicates that the clr mask comes before set.
> 
>>
>>> Or perhaps update_reg_mask_shift_val()?
>>
>> Still, I can rename the function if you want; it certainly does make it
>> obvious. It's rather a long name though, but I guess wrapping the
>> parameters isn't too bad.
> 
> I'll leave it to you, it's just a thought.

Well, the wrapping didn't work out to badly, so I posted V3 including
this rename.
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[U-Boot] [PATCH V3 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Stephen Warren]

From: Stephen Warren 

This removes a bunch of open-coded register IO, masking, and shifting.
I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
except that keeping it a separate commit allows easier bisection of any
issues that are introduced by this patch. I also wrote this patch on top
of the series, and pushing it any lower in the series results in some
conflicts I didn't feel like fixing.

Signed-off-by: Stephen Warren 
Acked-by: Simon Glass 
---
V3: Rename update_field() to update_reg_mask_shift_val() to make the
parameter order more obvious.
V2: New patch.

(I'm only reposting V3 of this one patch in order to avoid spamming the
list with the other huge table replacements in the series. Hopefully this
isn't too painful when applying them).
---
 arch/arm/cpu/tegra-common/pinmux-common.c | 140 ++
 1 file changed, 28 insertions(+), 112 deletions(-)

diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c 
b/arch/arm/cpu/tegra-common/pinmux-common.c
index 32a46d53f068..7d5c74055644 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -87,11 +87,16 @@
 #define IO_RESET_SHIFT 8
 #define RCV_SEL_SHIFT  9
 
+static inline void update_reg_mask_shift_val(u32 *reg, u32 mask, u32 shift,
+u32 val)
+{
+   clrsetbits_le32(reg, mask << shift, val << shift);
+}
+
 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
 {
u32 *reg = MUX_REG(pin);
int i, mux = -1;
-   u32 val;
 
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
@@ -110,42 +115,30 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func 
func)
}
assert(mux != -1);
 
-   val = readl(reg);
-   val &= ~(3 << MUX_SHIFT(pin));
-   val |= (mux << MUX_SHIFT(pin));
-   writel(val, reg);
+   update_reg_mask_shift_val(reg, 3, MUX_SHIFT(pin), mux);
 }
 
 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
 {
u32 *reg = PULL_REG(pin);
-   u32 val;
 
/* Error check on pin and pupd */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_pupd_isvalid(pupd));
 
-   val = readl(reg);
-   val &= ~(3 << PULL_SHIFT(pin));
-   val |= (pupd << PULL_SHIFT(pin));
-   writel(val, reg);
+   update_reg_mask_shift_val(reg, 3, PULL_SHIFT(pin), pupd);
 }
 
 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
 {
u32 *reg = TRI_REG(pin);
-   u32 val;
 
/* Error check on pin */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_tristate_isvalid(tri));
 
-   val = readl(reg);
-   if (tri == PMUX_TRI_TRISTATE)
-   val |= (1 << TRI_SHIFT(pin));
-   else
-   val &= ~(1 << TRI_SHIFT(pin));
-   writel(val, reg);
+   update_reg_mask_shift_val(reg, 1, TRI_SHIFT(pin),
+ tri == PMUX_TRI_TRISTATE);
 }
 
 void pinmux_tristate_enable(enum pmux_pingrp pin)
@@ -162,7 +155,6 @@ void pinmux_tristate_disable(enum pmux_pingrp pin)
 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
 {
u32 *reg = REG(pin);
-   u32 val;
 
if (io == PMUX_PIN_NONE)
return;
@@ -171,18 +163,12 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io 
io)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_io_isvalid(io));
 
-   val = readl(reg);
-   if (io == PMUX_PIN_INPUT)
-   val |= (io & 1) << IO_SHIFT;
-   else
-   val &= ~(1 << IO_SHIFT);
-   writel(val, reg);
+   update_reg_mask_shift_val(reg, 1, IO_SHIFT, io == PMUX_PIN_INPUT);
 }
 
 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
 {
u32 *reg = REG(pin);
-   u32 val;
 
if (lock == PMUX_PIN_LOCK_DEFAULT)
return;
@@ -191,23 +177,19 @@ static void pinmux_set_lock(enum pmux_pingrp pin, enum 
pmux_pin_lock lock)
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_lock_isvalid(lock));
 
-   val = readl(reg);
-   if (lock == PMUX_PIN_LOCK_ENABLE) {
-   val |= (1 << LOCK_SHIFT);
-   } else {
+   if (lock == PMUX_PIN_LOCK_DISABLE) {
+   u32 val = readl(reg);
if (val & (1 << LOCK_SHIFT))
printf("%s: Cannot clear LOCK bit!\n", __func__);
-   val &= ~(1 << LOCK_SHIFT);
}
-   writel(val, reg);
 
-   return;
+   update_reg_mask_shift_val(reg, 1, LOCK_SHIFT,
+ lock == PMUX_PIN_LOCK_ENABLE);
 }
 
 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
 {
u32 *reg = REG(pin);
-   u32 val;
 
if (od == PMUX_PIN_OD_DEFAULT)
return;
@@ -216,21 +198,13 @@ static void pinmux_set_od(enum pmux_pingrp pin, enum 
pmux_pin_od od)
assert(pmux_pingrp_isvalid(pin));
as

Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Simon Glass]

Hi Stephen,

On 25 March 2014 08:54, Stephen Warren  wrote:
> On 03/24/2014 08:27 PM, Simon Glass wrote:
>> Hi Stephen,
>>
>> On 21 March 2014 11:28, Stephen Warren  wrote:
>>> From: Stephen Warren 
>>>
>>> This removes a bunch of open-coded register IO, masking, and shifting.
>>> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
>>> except that keeping it a separate commit allows easier bisection of any
>>> issues that are introduced by this patch. I also wrote this patch on top
>>> of the series, and pushing it any lower in the series results in some
>>> conflicts I didn't feel like fixing.
>>>
>>> Signed-off-by: Stephen Warren 
>>
>> Acked-by: Simon Glass 
>>
>> But see comment below.
>
>>> diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c 
>>> b/arch/arm/cpu/tegra-common/pinmux-common.c
>
>>> +static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
>>> +{
>>> +   clrsetbits_le32(reg, mask << shift, val << shift);
>>
>> I wonder if it would be better to write this out explicitly in each site.
>>
>>> +}
>>> +
>>>  void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
>>>  {
>>> u32 *reg = MUX_REG(pin);
>>> int i, mux = -1;
>>> -   u32 val;
>>>
>>> /* Error check on pin and func */
>>> assert(pmux_pingrp_isvalid(pin));
>>> @@ -110,42 +114,29 @@ void pinmux_set_func(enum pmux_pingrp pin, enum 
>>> pmux_func func)
>>> }
>>> assert(mux != -1);
>>>
>>> -   val = readl(reg);
>>> -   val &= ~(3 << MUX_SHIFT(pin));
>>> -   val |= (mux << MUX_SHIFT(pin));
>>> -   writel(val, reg);
>>> +   update_field(reg, 3, MUX_SHIFT(pin), mux);
>>
>> Because here you are obscuring the shift - the parameter order is by
>> no means obvious.
>
> Well, for pretty much no function is it obvious from the function name
> what the parameter order is; it's just one of those things you memorize
> or look up. The exact same issue exists for clrsetbits_le32() itself IMHO.

Well that at least indicates that the clr mask comes before set.

>
>> Or perhaps update_reg_mask_shift_val()?
>
> Still, I can rename the function if you want; it certainly does make it
> obvious. It's rather a long name though, but I guess wrapping the
> parameters isn't too bad.

I'll leave it to you, it's just a thought.

Regards,
Simon
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Re: [U-Boot] [PATCH V2 09/13] ARM: tegra: use clrsetbits_le32 in pinmux driver

[Stephen Warren]

On 03/24/2014 08:27 PM, Simon Glass wrote:
> Hi Stephen,
> 
> On 21 March 2014 11:28, Stephen Warren  wrote:
>> From: Stephen Warren 
>>
>> This removes a bunch of open-coded register IO, masking, and shifting.
>> I would have squashed this into "ARM: tegra: pinctrl: remove duplication"
>> except that keeping it a separate commit allows easier bisection of any
>> issues that are introduced by this patch. I also wrote this patch on top
>> of the series, and pushing it any lower in the series results in some
>> conflicts I didn't feel like fixing.
>>
>> Signed-off-by: Stephen Warren 
> 
> Acked-by: Simon Glass 
> 
> But see comment below.

>> diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c 
>> b/arch/arm/cpu/tegra-common/pinmux-common.c

>> +static inline void update_field(u32 *reg, u32 mask, u32 shift, u32 val)
>> +{
>> +   clrsetbits_le32(reg, mask << shift, val << shift);
> 
> I wonder if it would be better to write this out explicitly in each site.
> 
>> +}
>> +
>>  void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
>>  {
>> u32 *reg = MUX_REG(pin);
>> int i, mux = -1;
>> -   u32 val;
>>
>> /* Error check on pin and func */
>> assert(pmux_pingrp_isvalid(pin));
>> @@ -110,42 +114,29 @@ void pinmux_set_func(enum pmux_pingrp pin, enum 
>> pmux_func func)
>> }
>> assert(mux != -1);
>>
>> -   val = readl(reg);
>> -   val &= ~(3 << MUX_SHIFT(pin));
>> -   val |= (mux << MUX_SHIFT(pin));
>> -   writel(val, reg);
>> +   update_field(reg, 3, MUX_SHIFT(pin), mux);
> 
> Because here you are obscuring the shift - the parameter order is by
> no means obvious.

Well, for pretty much no function is it obvious from the function name
what the parameter order is; it's just one of those things you memorize
or look up. The exact same issue exists for clrsetbits_le32() itself IMHO.

> Or perhaps update_reg_mask_shift_val()?

Still, I can rename the function if you want; it certainly does make it
obvious. It's rather a long name though, but I guess wrapping the
parameters isn't too bad.
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[U-Boot] [PATCH 2/3 v2] ARM: OMAP: hide custom bit manipulation function sr32()

[Wolfgang Denk]

The only remaining user of the custom bit manipulation function sr32()
is arch/arm/cpu/armv7/omap3/clock.c, so  make it a static function in
that file to prepare complete removal.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 
---
V2: fix checkpatch issues

 arch/arm/cpu/armv7/omap3/clock.c| 13 +
 arch/arm/cpu/armv7/syslib.c | 13 -
 arch/arm/include/asm/arch-omap3/sys_proto.h |  1 -
 arch/arm/include/asm/arch-omap4/sys_proto.h |  1 -
 arch/arm/include/asm/arch-omap5/sys_proto.h |  1 -
 5 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 1bc27bd..16e6c5f 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -21,6 +21,19 @@
 #include 
 #include 
 
+/*
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ */
+static inline void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
+{
+   u32 tmp, msk = 0;
+   msk = 1 << num_bits;
+   --msk;
+   tmp = readl((u32)addr) & ~(msk << start_bit);
+   tmp |= value << start_bit;
+   writel(tmp, (u32)addr);
+}
+
 /**
  * get_sys_clk_speed() - determine reference oscillator speed
  *   based on known 32kHz clock and gptimer.
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c
index caf9fbc..4ae2596 100644
--- a/arch/arm/cpu/armv7/syslib.c
+++ b/arch/arm/cpu/armv7/syslib.c
@@ -24,19 +24,6 @@ void sdelay(unsigned long loops)
  "bne 1b":"=r" (loops):"0"(loops));
 }
 
-/*
- * sr32 - clear & set a value in a bit range for a 32 bit address
- */
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
-   u32 tmp, msk = 0;
-   msk = 1 << num_bits;
-   --msk;
-   tmp = readl((u32)addr) & ~(msk << start_bit);
-   tmp |= value << start_bit;
-   writel(tmp, (u32)addr);
-}
-
 /*
  * wait_on_value() - common routine to allow waiting for changes in
  *   volatile regs.
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h 
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 44fa66f..10300f4 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -62,7 +62,6 @@ void secureworld_exit(void);
 void try_unlock_memory(void);
 u32 get_boot_type(void);
 void invalidate_dcache(u32);
-void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void make_cs1_contiguous(void);
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index b338a15..80172f3 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -31,7 +31,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 9e007c8..bf12c73 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -32,7 +32,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void setup_clocks_for_console(void);
-- 
1.8.5.3

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[U-Boot] [PATCH 3/3 v2] ARM: OMAP: replace custom sr32() by standard I/O accessors

[Wolfgang Denk]

Replace the custom bit manipulation function sr32() by standard I/O
accessors.  A major motivation for this cleanup was the fact, that a
number of calls of that function resulted in 32 bit wide shift
operations on u32 data, which according to the C-ISO/IEC-9899-Standard
provokes undefined behaviour:

6.5.7 Bitwise shift operators
...
If the value of the right operand is negative or is greater
than or equal to the width of the promoted left operand, the
behavior is undefined.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 
---
V2: fix checkpatch issues

 arch/arm/cpu/armv7/omap3/clock.c | 368 ++-
 1 file changed, 205 insertions(+), 163 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 16e6c5f..529ad9a 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -21,19 +21,6 @@
 #include 
 #include 
 
-/*
- * sr32 - clear & set a value in a bit range for a 32 bit address
- */
-static inline void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
-   u32 tmp, msk = 0;
-   msk = 1 << num_bits;
-   --msk;
-   tmp = readl((u32)addr) & ~(msk << start_bit);
-   tmp |= value << start_bit;
-   writel(tmp, (u32)addr);
-}
-
 /**
  * get_sys_clk_speed() - determine reference oscillator speed
  *   based on known 32kHz clock and gptimer.
@@ -145,9 +132,9 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
if (xip_safe) {
/*
 * CORE DPLL
-* sr32(CM_CLKSEL2_EMU) set override to work when asleep
 */
-   sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+   clrsetbits_le32(&prcm_base->clken_pll,
+   0x0007, PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
 
@@ -157,37 +144,50 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
 */
 
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
-   sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
-   sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+   clrsetbits_le32(&prcm_base->clksel1_emu,
+   0x001F, (CORE_M3X2 + 1) << 16) ;
+   clrsetbits_le32(&prcm_base->clksel1_emu,
+   0x001F, CORE_M3X2 << 16);
 
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
-   sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+   clrsetbits_le32(&prcm_base->clksel1_pll,
+   0xF800, ptr->m2 << 27);
 
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
-   sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+   clrsetbits_le32(&prcm_base->clksel1_pll,
+   0x07FF, ptr->m << 16);
 
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
-   sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+   clrsetbits_le32(&prcm_base->clksel1_pll,
+   0x7F00, ptr->n << 8);
 
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
-   sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+   clrbits_le32(&prcm_base->clksel1_pll, 0x0040);
 
/* SSI */
-   sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x0F00, CORE_SSI_DIV << 8);
/* FSUSB */
-   sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x0030, CORE_FUSB_DIV << 4);
/* L4 */
-   sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x000C, CORE_L4_DIV << 2);
/* L3 */
-   sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x0003, CORE_L3_DIV);
/* GFX */
-   sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
+   clrsetbits_le32(&prcm_base->clksel_gfx,
+   0x0007, GFX_DIV);
/* RESET MGR */
-   sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+   clrsetbits_le32(&prcm_base->clksel_wkup,
+   0x0006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
-   sr32(&prcm_base->clken_pll,   4, 4, ptr->fsel);
+   clrsetbits_le32(&prcm_base

[U-Boot] [PATCH 1/3 v2] ARM: OMAP: remove sr32() from OMAP board code

[Wolfgang Denk]

Replace the custom sr32() bit manipulation function in
arch/arm/cpu/armv7/omap3/board.c and board/ti/panda/panda.c
by standard I/O accessors.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 
---
V2: fix checkpatch issues

 arch/arm/cpu/armv7/omap3/board.c | 4 ++--
 board/ti/panda/panda.c   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 2922816..9bb1a1c 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -290,8 +290,8 @@ void watchdog_init(void)
 * should not be running and does not generate a PRCM reset.
 */
 
-   sr32(&prcm_base->fclken_wkup, 5, 1, 1);
-   sr32(&prcm_base->iclken_wkup, 5, 1, 1);
+   setbits_le32(&prcm_base->fclken_wkup, 0x20);
+   setbits_le32(&prcm_base->iclken_wkup, 0x20);
wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
 
writel(WD_UNLOCK1, &wd2_base->wspr);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 5ab6db9..0dfb4ad 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -308,7 +308,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
/* Now we can enable our port clocks */
utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
-   sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
+   setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
 
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
-- 
1.8.5.3

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[U-Boot] [PATCH 0/3 v2] ARM: OMAP: replace custom sr32() by standard I/O accessors

[Wolfgang Denk]

This patch series replaces the custom bit manipulation function sr32()
by standard I/O accessors.  A major motivation for this cleanup was
the fact that a number of calls of that function resulted in 32 bit
wide shift operations on u32 data, which according to the C-ISO
IEC-9899-Standard provokes undefined behaviour:

6.5.7 Bitwise shift operators
...
If the value of the right operand is negative or is
greater than or equal to the width of the promoted left
operand, the behavior is undefined.

The code was built-tested for all TI boards (using "./MAKEALL -v ti")
without errors or warnings.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 

Wolfgang Denk (3):
  ARM: OMAP: remove sr32() from OMAP board code
  ARM: OMAP: hide custom bit manipulation function sr32()
  ARM: OMAP: replace custom sr32() by standard I/O accessors

 arch/arm/cpu/armv7/omap3/board.c|   4 +-
 arch/arm/cpu/armv7/omap3/clock.c| 355 
 arch/arm/cpu/armv7/syslib.c |  13 -
 arch/arm/include/asm/arch-omap3/sys_proto.h |   1 -
 arch/arm/include/asm/arch-omap4/sys_proto.h |   1 -
 arch/arm/include/asm/arch-omap5/sys_proto.h |   1 -
 board/ti/panda/panda.c  |   2 +-
 7 files changed, 208 insertions(+), 169 deletions(-)

-- 
V2: fix checkpatch issues

1.8.5.3

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[U-Boot] [PATCH 2/3] ARM: OMAP: hide custom bit manipulation function sr32()

[Wolfgang Denk]

The only remaining user of the custom bit manipulation function sr32()
is arch/arm/cpu/armv7/omap3/clock.c, so  make it a static function in
that file to prepare complete removal.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 
---
 arch/arm/cpu/armv7/omap3/clock.c| 13 +
 arch/arm/cpu/armv7/syslib.c | 13 -
 arch/arm/include/asm/arch-omap3/sys_proto.h |  1 -
 arch/arm/include/asm/arch-omap4/sys_proto.h |  1 -
 arch/arm/include/asm/arch-omap5/sys_proto.h |  1 -
 5 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 1bc27bd..16e6c5f 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -21,6 +21,19 @@
 #include 
 #include 
 
+/*
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ */
+static inline void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
+{
+   u32 tmp, msk = 0;
+   msk = 1 << num_bits;
+   --msk;
+   tmp = readl((u32)addr) & ~(msk << start_bit);
+   tmp |= value << start_bit;
+   writel(tmp, (u32)addr);
+}
+
 /**
  * get_sys_clk_speed() - determine reference oscillator speed
  *   based on known 32kHz clock and gptimer.
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c
index caf9fbc..4ae2596 100644
--- a/arch/arm/cpu/armv7/syslib.c
+++ b/arch/arm/cpu/armv7/syslib.c
@@ -24,19 +24,6 @@ void sdelay(unsigned long loops)
  "bne 1b":"=r" (loops):"0"(loops));
 }
 
-/*
- * sr32 - clear & set a value in a bit range for a 32 bit address
- */
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
-   u32 tmp, msk = 0;
-   msk = 1 << num_bits;
-   --msk;
-   tmp = readl((u32)addr) & ~(msk << start_bit);
-   tmp |= value << start_bit;
-   writel(tmp, (u32)addr);
-}
-
 /*
  * wait_on_value() - common routine to allow waiting for changes in
  *   volatile regs.
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h 
b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 44fa66f..10300f4 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -62,7 +62,6 @@ void secureworld_exit(void);
 void try_unlock_memory(void);
 u32 get_boot_type(void);
 void invalidate_dcache(u32);
-void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void make_cs1_contiguous(void);
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index b338a15..80172f3 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -31,7 +31,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void set_pl310_ctrl_reg(u32 val);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 9e007c8..bf12c73 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -32,7 +32,6 @@ void watchdog_init(void);
 u32 get_device_type(void);
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void setup_clocks_for_console(void);
-- 
1.8.5.3

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[U-Boot] [PATCH 0/3] ARM: OMAP: replace custom sr32() by standard I/O accessors

[Wolfgang Denk]

This patch series replaces the custom bit manipulation function sr32()
by standard I/O accessors.  A major motivation for this cleanup was
the fact that a number of calls of that function resulted in 32 bit
wide shift operations on u32 data, which according to the C-ISO
IEC-9899-Standard provokes undefined behaviour:

6.5.7 Bitwise shift operators
...
If the value of the right operand is negative or is
greater than or equal to the width of the promoted left
operand, the behavior is undefined.

The code was built-tested for all TI boards (using "./MAKEALL -v ti")
without errors or warnings.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 

Wolfgang Denk (3):
  ARM: OMAP: remove sr32() from OMAP board code
  ARM: OMAP: hide custom bit manipulation function sr32()
  ARM: OMAP: replace custom sr32() by standard I/O accessors

 arch/arm/cpu/armv7/omap3/board.c|   4 +-
 arch/arm/cpu/armv7/omap3/clock.c| 354 
 arch/arm/cpu/armv7/syslib.c |  13 -
 arch/arm/include/asm/arch-omap3/sys_proto.h |   1 -
 arch/arm/include/asm/arch-omap4/sys_proto.h |   1 -
 arch/arm/include/asm/arch-omap5/sys_proto.h |   1 -
 board/ti/panda/panda.c  |   2 +-
 7 files changed, 207 insertions(+), 169 deletions(-)

-- 
1.8.5.3

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[U-Boot] [PATCH 3/3] ARM: OMAP: replace custom sr32() by standard I/O accessors

[Wolfgang Denk]

Replace the custom bit manipulation function sr32() by standard I/O
accessors.  A major motivation for this cleanup was the fact, that a
number of calls of that function resulted in 32 bit wide shift
operations on u32 data, which according to the C-ISO/IEC-9899-Standard
provokes undefined behaviour:

6.5.7 Bitwise shift operators
...
If the value of the right operand is negative or is greater
than or equal to the width of the promoted left operand, the
behavior is undefined.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 
---
 arch/arm/cpu/armv7/omap3/clock.c | 367 ++-
 1 file changed, 204 insertions(+), 163 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 16e6c5f..226f846 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -21,19 +21,6 @@
 #include 
 #include 
 
-/*
- * sr32 - clear & set a value in a bit range for a 32 bit address
- */
-static inline void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
-   u32 tmp, msk = 0;
-   msk = 1 << num_bits;
-   --msk;
-   tmp = readl((u32)addr) & ~(msk << start_bit);
-   tmp |= value << start_bit;
-   writel(tmp, (u32)addr);
-}
-
 /**
  * get_sys_clk_speed() - determine reference oscillator speed
  *   based on known 32kHz clock and gptimer.
@@ -145,9 +132,8 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
if (xip_safe) {
/*
 * CORE DPLL
-* sr32(CM_CLKSEL2_EMU) set override to work when asleep
 */
-   sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
+   clrsetbits_le32(&prcm_base->clken_pll, 0x7, 
PLL_FAST_RELOCK_BYPASS);
wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
LDELAY);
 
@@ -157,37 +143,50 @@ static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
 */
 
/* CM_CLKSEL1_EMU[DIV_DPLL3] */
-   sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
-   sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
+   clrsetbits_le32(&prcm_base->clksel1_emu,
+   0x001F, (CORE_M3X2 + 1) << 16) ;
+   clrsetbits_le32(&prcm_base->clksel1_emu,
+   0x001F, CORE_M3X2 << 16);
 
/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
-   sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
+   clrsetbits_le32(&prcm_base->clksel1_pll,
+   0xF800, ptr->m2 << 27);
 
/* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
-   sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
+   clrsetbits_le32(&prcm_base->clksel1_pll,
+   0x07FF, ptr->m << 16);
 
/* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
-   sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
+   clrsetbits_le32(&prcm_base->clksel1_pll,
+   0x7F00, ptr->n << 8);
 
/* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
-   sr32(&prcm_base->clksel1_pll, 6, 1, 0);
+   clrbits_le32(&prcm_base->clksel1_pll, 0x0040);
 
/* SSI */
-   sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x0F00, CORE_SSI_DIV << 8);
/* FSUSB */
-   sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x0030, CORE_FUSB_DIV << 4);
/* L4 */
-   sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x000C, CORE_L4_DIV << 2);
/* L3 */
-   sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
+   clrsetbits_le32(&prcm_base->clksel_core,
+   0x0003, CORE_L3_DIV);
/* GFX */
-   sr32(&prcm_base->clksel_gfx,  0, 3, GFX_DIV);
+   clrsetbits_le32(&prcm_base->clksel_gfx,
+   0x0007, GFX_DIV);
/* RESET MGR */
-   sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
+   clrsetbits_le32(&prcm_base->clksel_wkup,
+   0x0006, WKUP_RSM << 1);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
-   sr32(&prcm_base->clken_pll,   4, 4, ptr->fsel);
+   clrsetbits_le32(&prcm_base->clken_pll,
+   0x00F0, ptr->fse

[U-Boot] [PATCH 1/3] ARM: OMAP: remove sr32() from OMAP board code

[Wolfgang Denk]

Replace the custom sr32() bit manipulation function in
arch/arm/cpu/armv7/omap3/board.c and board/ti/panda/panda.c
by standard I/O accessors.

Signed-off-by: Wolfgang Denk 
Cc: Tom Rini 
Cc: Albert ARIBAUD 
---
 arch/arm/cpu/armv7/omap3/board.c | 4 ++--
 board/ti/panda/panda.c   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 2922816..9bb1a1c 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -290,8 +290,8 @@ void watchdog_init(void)
 * should not be running and does not generate a PRCM reset.
 */
 
-   sr32(&prcm_base->fclken_wkup, 5, 1, 1);
-   sr32(&prcm_base->iclken_wkup, 5, 1, 1);
+   setbits_le32(&prcm_base->fclken_wkup, 0x20);
+   setbits_le32(&prcm_base->iclken_wkup, 0x20);
wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
 
writel(WD_UNLOCK1, &wd2_base->wspr);
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 5ab6db9..ec42faf 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -308,7 +308,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
/* Now we can enable our port clocks */
utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
-   sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
+   setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL,utmi_clk);
 
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
-- 
1.8.5.3

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Re: [U-Boot] [PATCH v10 0/6] arm: add Faraday SoC platform support

[Albert ARIBAUD]

Hi Kuo-Jung,

On Thu, 20 Feb 2014 11:40:32 +0800, Kuo-Jung Su 
wrote:

> From: Kuo-Jung Su 
> 
> These patches introduce Faraday A369 & Virtual SoC platform support.

Except for patches 4/6 and 6/6 in which boards.cfg needed manual
fixing (due to commit 3fa67050), the series applies to current
u-boot-arm/master, but building fails for both a369evb and fvm with
multiple instances of this error:

include/asm/arch/hardware.h:14:23: fatal error: asm/sizes.h: No such
file or directory

Can you please rebase (for boards.cfg) and diagnose?

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH] build:arm: Remove setting of CROSS_COMPILE environment variable

[Lukasz Majewski]

Hi Albert,

> Hi Lukasz,
> 
> On Tue, 25 Mar 2014 09:55:45 +0100, Lukasz Majewski
>  wrote:
> 
> > Hi Albert,
> > 
> > > Hi Lukasz, Tom,
> > > 
> > > 
> > > > Hi Tom,
> > > > 
> > > > > On Tue, Mar 18, 2014 at 04:46:48PM +0100, Lukasz Majewski
> > > > > wrote:
> > > > > 
> > > > > > After Kbuild introduction, the CROSS_COMPILE environment
> > > > > > variable has been set to some default value (prefix
> > > > > > arm-linux-).
> > > > > 
> > > > > Note that this is quite a long-standing thing.  Perhaps we're
> > > > > now not detecting a native build when we used to?
> > > > 
> > > > My point is that we are relying on assigning default prefix
> > > > (i.e. arm-linux-)
> > > > 
> > > > For example OSELAS toolchains can have an arbitrary prefix
> > > > (e.g. arm-linux-gnueabi-).
> > > > 
> > > > When I cross compile I set explicitly "CROSS_COMPILE=
> > > > make" and it works as it should (with or without this patch).
> > > > Such approach seems natural for me.
> > > >
> > > > However, I don't know what is the exact rationale for seting
> > > > this arm-linux- prefix to CROSS_COMPILE.
> > > > I can only guess, that it is connected with situation when one
> > > > just type "make" on x86_64 host and expect u-boot to be
> > > > CROSS_COMPILE'd out of the box.
> > > 
> > > Agree.
> > > It is useful only for people using "arm-linux-gcc" on x86 host.
> > > I usually use "arm-linux-gnueabi-gcc". Someone else may be using
> > > other prefixes.
> > > 
> > > I think there is no rationale more sophisticated than that it
> > > just has been there since long time before.
> > > 
> > > So, I agree with this patch except a little misleading
> > > commit description I commented below.
> > > 
> > > Acked-by: Masahiro Yamada 
> > > 
> > 
> > Albert, could you take this patch for your arm repository?
> 
> I can. How would you like me to rephrase the commit message?

Maybe something like this:

-- 8< --
For building u-boot on ARM the CROSS_COMPILE environment variable, when
not defined, was set to default value (prefix arm-linux-).

Since not all cross compilers have the arm-linux- prefix and this
setting prevents from building u-boot on natively arm powered devices it
would be best to remove it.

As a side note:
The most universal way to cross compile u-boot is to
specify the CROSS_COMPILE environment variable explicitly - e.g.:
CROSS_COMPILE=/  /arm-v7a-linux-gnueabi- make

-- >8 --

And also please add the Acked-by from Masahiro.

> 
> Amicalement,

Thanks a lot for your support.

-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH v5 1/4] lib: rand: introduce new configs: CONFIG_LIB_RAND and CONFIG_LIB_HW_RAND

[Przemyslaw Marczak]

Hello Tom,

On 03/25/2014 10:58 AM, Przemyslaw Marczak wrote:

New configs:
- CONFIG_LIB_RAND- to enable implementation of rand library in lib/rand.c
- CONFIG_LIB_HW_RAND - to enable hardware based implementations of lib rand

Other changes:
- add CONFIG_LIB_RAND to boards configs which needs rand()
- put only one rand.o dependency in lib/Makefile

CONFIG_LIB_HW_RAND should be defined for drivers which implements rand library
(declared in include/common.h):
- void srand(unsigned int seed)
- unsigned int rand(void)
- unsigned int rand_r(unsigned int *seedp)

Signed-off-by: Przemyslaw Marczak 
Cc: Michael Walle 
Cc: Tom Rini 
Cc: Masahiro Yamada 

---
Changes v3:
- new commit

Changes v4:
- cosmetic change in commit subject

Changes v5:
- none


This patch set is rebased onto u-boot master. Could you apply this in 
the next few days? Then I will rebase and send again patch set for UUID 
generation feature starting from this patch: 
http://patchwork.ozlabs.org/patch/331816/


Thanks
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH] build:arm: Remove setting of CROSS_COMPILE environment variable

[Albert ARIBAUD]

Hi Lukasz,

On Tue, 25 Mar 2014 09:55:45 +0100, Lukasz Majewski
 wrote:

> Hi Albert,
> 
> > Hi Lukasz, Tom,
> > 
> > 
> > > Hi Tom,
> > > 
> > > > On Tue, Mar 18, 2014 at 04:46:48PM +0100, Lukasz Majewski wrote:
> > > > 
> > > > > After Kbuild introduction, the CROSS_COMPILE environment
> > > > > variable has been set to some default value (prefix arm-linux-).
> > > > 
> > > > Note that this is quite a long-standing thing.  Perhaps we're now
> > > > not detecting a native build when we used to?
> > > 
> > > My point is that we are relying on assigning default prefix (i.e.
> > > arm-linux-)
> > > 
> > > For example OSELAS toolchains can have an arbitrary prefix
> > > (e.g. arm-linux-gnueabi-).
> > > 
> > > When I cross compile I set explicitly "CROSS_COMPILE=
> > > make" and it works as it should (with or without this patch). Such
> > > approach seems natural for me.
> > >
> > > However, I don't know what is the exact rationale for seting this
> > > arm-linux- prefix to CROSS_COMPILE.
> > > I can only guess, that it is connected with situation when one just
> > > type "make" on x86_64 host and expect u-boot to be CROSS_COMPILE'd
> > > out of the box.
> > 
> > Agree.
> > It is useful only for people using "arm-linux-gcc" on x86 host.
> > I usually use "arm-linux-gnueabi-gcc". Someone else may be using other
> > prefixes.
> > 
> > I think there is no rationale more sophisticated than that it just has
> > been there since long time before.
> > 
> > So, I agree with this patch except a little misleading
> > commit description I commented below.
> > 
> > Acked-by: Masahiro Yamada 
> > 
> 
> Albert, could you take this patch for your arm repository?

I can. How would you like me to rephrase the commit message?

Amicalement,
-- 
Albert.
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[U-Boot] [PATCH v5 3/4] drivers: crypto: ace_sha: add implementation of hardware based lib rand

[Przemyslaw Marczak]

This patch adds implementation of rand library based on hardware random
number generator of security subsystem in Exynos SOC.

This library includes:
- srand()  - used for seed hardware block
- rand()   - returns random number
- rand_r() - the same as above with given seed

which depends on CONFIG_EXYNOS_ACE_SHA and CONFIG_LIB_HW_RAND.

Signed-off-by: Przemyslaw Marczak 
cc: Akshay Saraswat 
cc: ARUN MANKUZHI 
cc: Minkyu Kang 
Cc: Michael Walle 
Cc: Tom Rini 
Cc: Masahiro Yamada 

---
Changes v2:
- none

Changes v3:
- add implementation of rand library to ace_sha
- add proper ifdef for ace_sha SHA functions
- move cpu refer change to new commit

Changes v4:
- remove unused variables

Changes v5:
- none
---
 drivers/crypto/ace_sha.c | 73 +++-
 drivers/crypto/ace_sha.h |  8 --
 2 files changed, 77 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c
index acbafde..ed4f541 100644
--- a/drivers/crypto/ace_sha.c
+++ b/drivers/crypto/ace_sha.c
@@ -5,10 +5,12 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 #include 
+#include "ace_sha.h"
+
+#ifdef CONFIG_SHA_HW_ACCEL
 #include 
 #include 
 #include 
-#include "ace_sha.h"
 
 /* SHA1 value for the message of zero length */
 static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
@@ -111,3 +113,72 @@ void hw_sha1(const unsigned char *pbuf, unsigned int 
buf_len,
if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
debug("ACE was not setup properly or it is faulty\n");
 }
+#endif /* CONFIG_SHA_HW_ACCEL */
+
+#ifdef CONFIG_LIB_HW_RAND
+static unsigned int seed_done;
+
+void srand(unsigned int seed)
+{
+   struct exynos_ace_sfr *reg =
+   (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
+   int i, status;
+
+   /* Seed data */
+   for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
+   writel(seed << i, ®->hash_seed[i]);
+
+   /* Wait for seed setup done */
+   while (1) {
+   status = readl(®->hash_status);
+   if ((status & ACE_HASH_SEEDSETTING_MASK) ||
+   (status & ACE_HASH_PRNGERROR_MASK))
+   break;
+   }
+
+   seed_done = 1;
+}
+
+unsigned int rand(void)
+{
+   struct exynos_ace_sfr *reg =
+   (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
+   int i, status;
+   unsigned int seed = (unsigned int)&status;
+   unsigned int ret = 0;
+
+   if (!seed_done)
+   srand(seed);
+
+   /* Start PRNG */
+   writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, ®->hash_control);
+
+   /* Wait for PRNG done */
+   while (1) {
+   status = readl(®->hash_status);
+   if (status & ACE_HASH_PRNGDONE_MASK)
+   break;
+   if (status & ACE_HASH_PRNGERROR_MASK) {
+   seed_done = 0;
+   return 0;
+   }
+   }
+
+   /* Clear Done IRQ */
+   writel(ACE_HASH_PRNGDONE_MASK, ®->hash_status);
+
+   /* Read a PRNG result */
+   for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
+   ret += readl(®->hash_prng[i]);
+
+   seed_done = 0;
+   return ret;
+}
+
+unsigned int rand_r(unsigned int *seedp)
+{
+   srand(*seedp);
+
+   return rand();
+}
+#endif /* CONFIG_LIB_HW_RAND */
diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h
index a426d52..f1097f7 100644
--- a/drivers/crypto/ace_sha.h
+++ b/drivers/crypto/ace_sha.h
@@ -72,9 +72,10 @@ struct exynos_ace_sfr {
unsigned char   res12[0x30];
unsigned inthash_result[8];
unsigned char   res13[0x20];
-   unsigned inthash_seed[8];
-   unsigned inthash_prng[8];
-   unsigned char   res14[0x180];
+   unsigned inthash_seed[5];
+   unsigned char   res14[12];
+   unsigned inthash_prng[5];
+   unsigned char   res15[0x18c];
 
unsigned intpka_sfr[5]; /* base + 0x700 */
 };
@@ -291,6 +292,7 @@ struct exynos_ace_sfr {
 #define ACE_HASH_PRNGERROR_MASK(1 << 7)
 #define ACE_HASH_PRNGERROR_OFF (0 << 7)
 #define ACE_HASH_PRNGERROR_ON  (1 << 7)
+#define ACE_HASH_PRNG_REG_NUM  5
 
 #define ACE_SHA_TYPE_SHA1  1
 #define ACE_SHA_TYPE_SHA2562
-- 
1.9.0

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[U-Boot] [PATCH v5 4/4] trats/trats2: enable exynos ace sha subsystem and hardware based lib rand

[Przemyslaw Marczak]

This allows to use exynos random number generator by enabling configs:
- CONFIG_EXYNOS_ACE_SHA
- CONFIG_LIB_HW_RAND

Signed-off-by: Przemyslaw Marczak 
Acked-by: Lukasz Majewski 
cc: Piotr Wilczek 
cc: Minkyu Kang 

---
Changes v2:
- none

Changes v3:
- change config name CONFIG_RAND_HW_ACCEL to CONFIG_LIB_HW_RAND

Changes v4:
- correct config name to CONFIG_LIB_HW_RAND after mistake
- add more info to commit message

Changes v5:
- none
---
 include/configs/trats.h  | 4 
 include/configs/trats2.h | 4 
 2 files changed, 8 insertions(+)

diff --git a/include/configs/trats.h b/include/configs/trats.h
index 7cea259..c00d60a 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -313,6 +313,10 @@
 #define CONFIG_USB_GADGET_VBUS_DRAW2
 #define CONFIG_USB_CABLE_CHECK
 
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_LIB_HW_RAND
+
 /* Common misc for Samsung */
 #define CONFIG_MISC_COMMON
 
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 6d389df..59896b1 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -324,6 +324,10 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_USB_GADGET_VBUS_DRAW2
 #define CONFIG_USB_CABLE_CHECK
 
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_LIB_HW_RAND
+
 /* Common misc for Samsung */
 #define CONFIG_MISC_COMMON
 
-- 
1.9.0

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[U-Boot] [PATCH v5 2/4] cpu: exynos4: add ace sha base address

[Przemyslaw Marczak]

Signed-off-by: Przemyslaw Marczak 
Cc: Minkyu Kang 

---
Changes v3:
- new commit - after separate changes from next commit

Changes v4:
- none

Changes v5:
- put base addresses in growing order
---
 arch/arm/include/asm/arch-exynos/cpu.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h 
b/arch/arm/include/asm/arch-exynos/cpu.h
index bccce63..fdf73b5 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -25,8 +25,9 @@
 #define EXYNOS4_SYSTIMER_BASE  0x1005
 #define EXYNOS4_WATCHDOG_BASE  0x1006
 #define EXYNOS4_TZPC_BASE  0x1011
-#define EXYNOS4_MIU_BASE   0x1060
 #define EXYNOS4_DMC_CTRL_BASE  0x1040
+#define EXYNOS4_MIU_BASE   0x1060
+#define EXYNOS4_ACE_SFR_BASE   0x1083
 #define EXYNOS4_GPIO_PART2_BASE0x1100
 #define EXYNOS4_GPIO_PART1_BASE0x1140
 #define EXYNOS4_FIMD_BASE  0x11C0
@@ -48,7 +49,6 @@
 #define EXYNOS4_GPIO_PART4_BASEDEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASEDEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE   DEVICE_NOT_AVAILABLE
-#define EXYNOS4_ACE_SFR_BASE   DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DMC_PHY_BASE   DEVICE_NOT_AVAILABLE
 #define EXYNOS4_AUDIOSS_BASE   DEVICE_NOT_AVAILABLE
 #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
@@ -68,6 +68,7 @@
 #define EXYNOS4X12_TZPC_BASE   0x1011
 #define EXYNOS4X12_DMC_CTRL_BASE   0x1060
 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E
+#define EXYNOS4X12_ACE_SFR_BASE0x1083
 #define EXYNOS4X12_GPIO_PART2_BASE 0x1100
 #define EXYNOS4X12_GPIO_PART1_BASE 0x1140
 #define EXYNOS4X12_FIMD_BASE   0x11C0
@@ -87,7 +88,6 @@
 #define EXYNOS4X12_I2S_BASEDEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_BASEDEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASEDEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_ACE_SFR_BASEDEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_DMC_PHY_BASEDEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_AUDIOSS_BASEDEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
@@ -106,7 +106,7 @@
 #define EXYNOS5_SYSREG_BASE0x1005
 #define EXYNOS5_TZPC_BASE  0x1010
 #define EXYNOS5_WATCHDOG_BASE  0x101D
-#define EXYNOS5_ACE_SFR_BASE0x1083
+#define EXYNOS5_ACE_SFR_BASE   0x1083
 #define EXYNOS5_DMC_PHY_BASE   0x10C0
 #define EXYNOS5_GPIO_PART3_BASE0x10D1
 #define EXYNOS5_DMC_CTRL_BASE  0x10DD
-- 
1.9.0

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[U-Boot] [PATCH v5 1/4] lib: rand: introduce new configs: CONFIG_LIB_RAND and CONFIG_LIB_HW_RAND

[Przemyslaw Marczak]

New configs:
- CONFIG_LIB_RAND- to enable implementation of rand library in lib/rand.c
- CONFIG_LIB_HW_RAND - to enable hardware based implementations of lib rand

Other changes:
- add CONFIG_LIB_RAND to boards configs which needs rand()
- put only one rand.o dependency in lib/Makefile

CONFIG_LIB_HW_RAND should be defined for drivers which implements rand library
(declared in include/common.h):
- void srand(unsigned int seed)
- unsigned int rand(void)
- unsigned int rand_r(unsigned int *seedp)

Signed-off-by: Przemyslaw Marczak 
Cc: Michael Walle 
Cc: Tom Rini 
Cc: Masahiro Yamada 

---
Changes v3:
- new commit

Changes v4:
- cosmetic change in commit subject

Changes v5:
- none
---
 include/common.h  | 4 +---
 include/configs/MERGERBOX.h   | 1 +
 include/configs/MVBC_P.h  | 1 +
 include/configs/MVBLM7.h  | 1 +
 include/configs/MVSMR.h   | 1 +
 include/configs/a3m071.h  | 1 +
 include/configs/bfin_adi_common.h | 1 +
 include/configs/lsxl.h| 1 +
 include/configs/sacsng.h  | 1 +
 lib/Makefile  | 4 +---
 10 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/include/common.h b/include/common.h
index 090fcde..fcf4318 100644
--- a/include/common.h
+++ b/include/common.h
@@ -829,9 +829,7 @@ char *  strmhz(char *buf, unsigned long hz);
 #include 
 
 /* lib/rand.c */
-#if defined(CONFIG_RANDOM_MACADDR) || \
-   defined(CONFIG_BOOTP_RANDOM_DELAY) || \
-   defined(CONFIG_CMD_LINK_LOCAL)
+#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND)
 #define RAND_MAX -1U
 void srand(unsigned int seed);
 unsigned int rand(void);
diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index 930699b..19ea316 100644
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -312,6 +312,7 @@
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_RANDOM_DELAY
 #define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
 
 /*
  * Command line configuration.
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
index 99e4e90..036396c 100644
--- a/include/configs/MVBC_P.h
+++ b/include/configs/MVBC_P.h
@@ -104,6 +104,7 @@
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_RANDOM_DELAY
 #define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
 
 /*
  * Autoboot
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 30af691..27c2fa0 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -227,6 +227,7 @@
 #define CONFIG_BOOTP_NTPSERVER
 #define CONFIG_BOOTP_RANDOM_DELAY
 #define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
 
 /* USB */
 #define CONFIG_SYS_USB_HOST
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
index bb565b6..ad15506 100644
--- a/include/configs/MVSMR.h
+++ b/include/configs/MVSMR.h
@@ -92,6 +92,7 @@
 #define CONFIG_BOOTP_SEND_HOSTNAME
 #define CONFIG_BOOTP_SUBNETMASK
 #define CONFIG_BOOTP_VENDOREX
+#define CONFIG_LIB_RAND
 
 /*
  * Autoboot
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index 1e65cd1..205adfd 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -58,6 +58,7 @@
 #define CONFIG_BOOTP_SERVERIP
 #define CONFIG_NET_RETRY_COUNT 3
 #define CONFIG_CMD_LINK_LOCAL
+#define CONFIG_LIB_RAND
 #define CONFIG_NETCONSOLE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_CMD_PING
diff --git a/include/configs/bfin_adi_common.h 
b/include/configs/bfin_adi_common.h
index 08ccce0..ea9acf6 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -17,6 +17,7 @@
 #  define CONFIG_BOOTP_DNS
 #  define CONFIG_BOOTP_NTPSERVER
 #  define CONFIG_BOOTP_RANDOM_DELAY
+#  define CONFIG_LIB_RAND
 #  define CONFIG_KEEP_SERVERADDR
 #  define CONFIG_CMD_DNS
 #  define CONFIG_CMD_PING
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 2ae8a27..96a889f 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -37,6 +37,7 @@
 #define CONFIG_SHOW_BOOT_PROGRESS
 
 #define CONFIG_RANDOM_MACADDR
+#define CONFIG_LIB_RAND
 #define CONFIG_KIRKWOOD_GPIO
 #define CONFIG_OF_LIBFDT
 
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 0a694fb..b5064ab 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -457,6 +457,7 @@
 #endif /* CONFIG_BOOT_ROOT_NFS */
 
 #define CONFIG_BOOTP_RANDOM_DELAY   /* Randomize the BOOTP retry delay */
+#define CONFIG_LIB_RAND
 
 /*
  * BOOTP options
diff --git a/lib/Makefile b/lib/Makefile
index 8814ff9..ae80865 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -62,8 +62,6 @@ obj-y += time.o
 obj-$(CONFIG_TRACE) += trace.o
 obj-$(CONFIG_BOOTP_PXE) += uuid.o
 obj-y += vsprintf.o
-obj-$(CONFIG_RANDOM_MACADDR) += rand.o
-obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o
-obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o
+obj-$(CONFIG_LIB_RAND) += rand.o
 
 subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
-- 
1.9.0

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Re: [U-Boot] [PATCH] build:arm: Remove setting of CROSS_COMPILE environment variable

[Lukasz Majewski]

Hi Albert,

> Hi Lukasz, Tom,
> 
> 
> > Hi Tom,
> > 
> > > On Tue, Mar 18, 2014 at 04:46:48PM +0100, Lukasz Majewski wrote:
> > > 
> > > > After Kbuild introduction, the CROSS_COMPILE environment
> > > > variable has been set to some default value (prefix arm-linux-).
> > > 
> > > Note that this is quite a long-standing thing.  Perhaps we're now
> > > not detecting a native build when we used to?
> > 
> > My point is that we are relying on assigning default prefix (i.e.
> > arm-linux-)
> > 
> > For example OSELAS toolchains can have an arbitrary prefix
> > (e.g. arm-linux-gnueabi-).
> > 
> > When I cross compile I set explicitly "CROSS_COMPILE=
> > make" and it works as it should (with or without this patch). Such
> > approach seems natural for me.
> >
> > However, I don't know what is the exact rationale for seting this
> > arm-linux- prefix to CROSS_COMPILE.
> > I can only guess, that it is connected with situation when one just
> > type "make" on x86_64 host and expect u-boot to be CROSS_COMPILE'd
> > out of the box.
> 
> Agree.
> It is useful only for people using "arm-linux-gcc" on x86 host.
> I usually use "arm-linux-gnueabi-gcc". Someone else may be using other
> prefixes.
> 
> I think there is no rationale more sophisticated than that it just has
> been there since long time before.
> 
> So, I agree with this patch except a little misleading
> commit description I commented below.
> 
> Acked-by: Masahiro Yamada 
> 

Albert, could you take this patch for your arm repository?

> 
> 
> > Unfortunately this doesn't work with ARM host emulated with qemu
> > (like OBS). Here when I type "make" I expect that "native" gcc for
> > arm will run without even touching CROSS_COMPILE environment
> > variable.
> 
> I believe it is the same as prior to Kbuild.
> 
> So, I am not convined with this part of your commit description:
> > After Kbuild introduction, the CROSS_COMPILE environment variable
> > has been set to some default value (prefix arm-linux-).
> 
> 
> > Any idea how to fix this is more than welcome.
> 
> If you are searching some other choices,
> 
> 
> [1]
> ifneq ("$(origin CROSS_COMPILE)", "command line")
> ifeq ($(CROSS_COMPILE),)
> CROSS_COMPILE := arm-linux-
> endif
> endif
> 
> For native build on ARM, you can explicitely set CROSS_COMPILE as
> empty:"make CROSS_COMPILE="
> In this case, CROSS_COMPILE will not be overwritten in
> arch/arm/config.mk.
> 
> 
> [2]
> ifneq ($(HOSTARCH),$(ARCH))
> ifeq ($(CROSS_COMPILE),)
> CROSS_COMPILE := arm-linux-
> endif
> endif
> 
> For native build on ARM, both $(HOSTARCH) and $(ARCH)
> are "arm", so CROSS_COMPILE will not be set.
> 
> 
> 
> But, I think deleting CROSS_COMPILE setting is the simplest and the
> best.
> 
> 
> Best Regards
> Masahiro Yamada
> 



-- 
Best regards,

Lukasz Majewski

Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH v4 2/4] cpu: exynos4: add ace sha base address

[Przemyslaw Marczak]

Hello Minkyu,

On 03/25/2014 02:26 AM, Minkyu Kang wrote:

On 24/03/14 16:44, Przemyslaw Marczak wrote:

Hello Minkyu,

On 03/22/2014 04:18 PM, Minkyu Kang wrote:

Dear Przemyslaw Marczak,


On 21 March 2014 17:56, Przemyslaw Marczak  wrote:


Signed-off-by: Przemyslaw Marczak 
Cc: Minkyu Kang 

---
Changes v3:
- new commit - after separate changes from next commit

Changes v4:
- none
---
   arch/arm/include/asm/arch-exynos/cpu.h | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index bccce63..bd3300a 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -44,11 +44,11 @@
   #define EXYNOS4_MODEM_BASE 0x13A0
   #define EXYNOS4_USBPHY_CONTROL 0x10020704
   #define EXYNOS4_I2S_BASE   0xE210
+#define EXYNOS4_ACE_SFR_BASE   0x1083



Could you please align this list?




I am not sure why this is not aligned in patch - it was generated by "git format patch". 
The source was aligned and after apply this patch by "git am" the code is also aligned.


hm, sorry to misunderstanding.
It means the ordering.
I want to keep ordering of this list by base address. (although it looks 
already broken)

  #define EXYNOS4_DMC_CTRL_BASE 0x1040
+#define EXYNOS4_ACE_SFR_BASE   0x1083
  #define EXYNOS4_GPIO_PART2_BASE   0x1100

Thanks,
Minkyu Kang.



ok, I will move those lines for proper address order.

Thanks
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marc...@samsung.com
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