Re: [U-Boot] [PATCH v1 2/7] board/ti/am335x: add support for beaglebone NAND cape
From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Rini, Tom On Sat, Jul 05, 2014 at 12:35:12AM +0530, Pekon Gupta wrote: Beaglebone Board can be connected to expansion boards to add devices to them. These expansion boards are called 'capes'. This patch adds support for following versions of Beaglebone(AM335x) NAND capes (a) NAND Device with bus-width=16, block-size=128k, page-size=2k, oob-size=64 (b) NAND Device with bus-width=16, block-size=256k, page-size=4k, oob-size=224 Further information and datasheets can be found at [1] and [2] [snip] @@ -377,7 +391,11 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); +#if defined(CONFIG_NAND) +configure_module_pin_mux(nand_pin_mux); +#else configure_module_pin_mux(mmc1_pin_mux); +#endif The above is the case for Beaglebone Black. Did you test the capes there as well? AFAIK the eMMC makes it a bit more tricky (or impossible?) to use some of the memory capes. Yes, slightly tricky, but not impossible :-) On Beaglebone all storage devices (NAND, NOR and eMMC) share GPMC pins. So this patch gives priority based on configs enabled in board-profile: #ifdef CONFIG_NAND /* define NAND pin-mux */ #elseif CONFIG_NOR /* configure NOR pin-mux */ #else /* config eMMC pin-mux (default, if no NAND | NOR cape is present) */ #endif Please refer to following log from beaglebone Black booting from NAND. U-boot was flashed on NAND using following commands: /* Flash MLO to NAND */ fatload mmc 0 0x8200 mlo nand write 0x8200 0x0 0x2 /* Flash u-boot.img to NAND */ fatload mmc 0 0x8200 u-boot.img nand write 0x8200 0xc 0x8 - U-Boot 2014.07-00013-g838a657-dirty (Jul 21 2014 - 10:27:34) I2C: ready DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 *** Warning - bad CRC, using default environment Net: ethaddr not set. Validating first E-fuse MAC cpsw, usb_ether Hit any key to stop autoboot: 1 0 U-Boot# -- *IMPORTANT NOTE* As Beaglebone board shares the same config as AM335x EVM, so following changes are required in addition to this patch for Beaglebone NAND cape. Therefore above image has a 'dirty commit'. (1) Enable NAND in am335x_beaglebone board profile (2) Add CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config because: - AM335x EVM has NAND device with datawidth=8, whereas - Beaglebone NAND cape has NAND device with data-width=16 diff --git a/boards.cfg b/boards.cfg -Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL +Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT with regards, pekon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Bug u-boot-tools: /usr/include/image.h gets included instead of WC/include/image.h
Hi list,
the package lensfun (http://lensfun.sourceforge.net/) ships an image.h which
gets installed in /usr/include/image.h.
When I build u-boot from the latest commit 524123a, it bails out with the
following error:
git clone git://git.denx.de/u-boot.git
cd u-boot
make coreboot-x86_config
make
1 CHK include/config/uboot.release
2 CHK include/generated/version_autogenerated.h
3 CHK include/generated/timestamp_autogenerated.h
4 UPD include/generated/timestamp_autogenerated.h
5 HOSTCC tools/aisimage.o
6 In file included from /usr/include/image.h:22:0,
7 from tools/aisimage.c:10:
8 /usr/include/rgbpixel.h:61:3: error: expected specifier-qualifier-list before
'RGBpixel'
9 In file included from tools/aisimage.c:10:0:
10 /usr/include/image.h:40:1: error: unknown type name 'class'
11 /usr/include/image.h:41:1: error: expected '=', ',', ';', 'asm' or
'__attribute__' before '{' token
12 tools/aisimage.c:22:1: error: unknown type name 'table_entry_t'
13 tools/aisimage.c:23:2: warning: braces around scalar initializer [enabled by
default]
14 tools/aisimage.c:23:2: warning: (near initialization for 'aisimage_cmds[0]')
[enabled by default]
[snip]
As far as I understand the messages, it erroneously tries to include
/usr/include/image.h instead of wc/include/image.h
Can you confirm this error?
Best
Chris
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Re: [U-Boot] [PATCH] cmd_nand/cmd_ubi/cmd_nboot: Set environment variable 'filesize'
Dear Mr. Denk;
On St, 2014-07-16 at 14:45 +0200, Wolfgang Denk wrote:
I'm not happy with that. I think this is actually dangerous.
First, you mix two different concepts here. As the name FILEsize
suggests, it is related to the size of a data object file. This
comes as natural name when loading data from a TFTP server or when
reading a *file* from some file system. Extending this to mean any
amount of data looks inconsistent and even broken to me.
Second, there might be scripts out there which get broken by your
modification. For example, when I download a file over TFTP to RAM, I
expect that filesize holds the exact amount of bytes of this file.
When I now use nand write ... +${filesize}, the write size would be
rounded up to the next full erase block size of the NAND. Any later
reference to filesize will now see a different (larger) value than
expected.
Thank you for the review. I see your point.
One possible solution would be to add new environment variable called
datasize, but then there is the question if this variable should be
updated any time the filesize is updated (+ in a few situations where
the filesize will stay unchanged -- i.e. what adds this patch).
Best regards;
Rostislav Lisovy
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Re: [U-Boot] [PATCH] cmd_nand/cmd_ubi/cmd_nboot: Set environment variable 'filesize'
Dear Lisovy, In message 1405930094.30277.1.ca...@lp-lvrv.comap.cz you wrote: One possible solution would be to add new environment variable called datasize, but then there is the question if this variable should be updated any time the filesize is updated (+ in a few situations where the filesize will stay unchanged -- i.e. what adds this patch). I have to admit that I don't even see the use case where such a new variable would be helpful. Your patch was adding this to commands like nand read etc. All these commands require you to pass the size to be read as argument, so you already have the size information present. Why would you want to store it in another variable? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de I really hate this damned machine It never does quite what I want I wish that they would sell it. But only what I tell it. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] RTC: add support for DS1339 (using DS1307 driver)
From: Markus Niebel markus.nie...@tq-group.com Signed-off-by: Markus Niebel markus.nie...@tq-group.com --- README |1 + drivers/rtc/Makefile |1 + drivers/rtc/ds1307.c |2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/README b/README index 4ac7399..e6d953e 100644 --- a/README +++ b/README @@ -1152,6 +1152,7 @@ The following options need to be configured: CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC + CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 003d322..43f8546 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_RTC_DS1302) += ds1302.o obj-$(CONFIG_RTC_DS1306) += ds1306.o obj-$(CONFIG_RTC_DS1307) += ds1307.o obj-$(CONFIG_RTC_DS1338) += ds1307.o +obj-$(CONFIG_RTC_DS1339) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o obj-$(CONFIG_RTC_DS1388) += ds1337.o diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 1a2bad3..03ab1a8 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -9,7 +9,7 @@ /* * Date Time support (no alarms) for Dallas Semiconductor (now Maxim) - * DS1307 and DS1338 Real Time Clock (RTC). + * DS1307 and DS1338/9 Real Time Clock (RTC). * * based on ds1337.c */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cmd_nand/cmd_ubi/cmd_nboot: Set environment variable 'filesize'
On Po, 2014-07-21 at 10:29 +0200, Wolfgang Denk wrote: I have to admit that I don't even see the use case where such a new variable would be helpful. Your patch was adding this to commands like nand read etc. All these commands require you to pass the size to be read as argument, so you already have the size information present. Why would you want to store it in another variable? The motivation for the nand read is that when the whole NAND flash partition is read (without passing the size as an argument) it may happen that the bad blocks are skipped thus amount of data read is not the same as the partition size. When we want to nand write the data to another partition, it would be nice to know the exact size. For the nboot case we use it to speed up copying of the kernel from the image-for-upgrade partition to the production-kernel partition. This helps us to avoid unnecessary copying of the whole partition (and saves some time). Best regards; Rostislav Lisovy ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] socfpga: initialize MMC
Hi!
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -14,5 +14,8 @@
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_SDMMC_ADDRESS 0xff704000
Please keep list sorted.
It was sorted by address before, so I'll keep it like that.
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
obj-$(CONFIG_DWMMC) += dw_mmc.o
obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+obj-$(CONFIG_ALTERA_DWMMC) += altera_dw_mmc.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
Ditto. This should be a sorted list.
This was not sorted and I will not need to modify it in next patch
version, so I'll leave this unfixed.
+static char *ALTERA_NAME = ALTERA DWMMC;
Please use lower case variable names only.
Actually, it turns out we don't need the variable :-).
+int altera_dwmmc_init(u32 regbase, int bus_width, int index)
+{
+ struct dwmci_host *host = NULL;
+ host = malloc(sizeof(struct dwmci_host));
Please separate declartions and code by a blank line.
Ok.
Hm, which sense does it make to initialize host as NULL, just to assign
a different value in the next step?
Please fix.
Fixed.
+ host-name = ALTERA_NAME;
+ host-ioaddr = (void *)regbase;
+ host-buswidth = bus_width;
+ host-clksel = altera_dwmci_clksel;
+ host-dev_index = index;
+ host-bus_hz = 40;
+ host-fifoth_val = MSIZE(0x2) |
+ RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) |
+ TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2);
+
+ add_dwmci(host, host-bus_hz, host-bus_hz);
Is there a free(host) anywhere?
Dynamic allocation does not make much sense here, agreed. But as it is
existing code, and there are bigger issues around, I'd prefer to leave
it to someone else to clean it up...
Thanks,
Pavel
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Re: [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape
From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Rini, Tom
On Sat, Jul 05, 2014 at 12:35:14AM +0530, Pekon Gupta wrote:
This patch updates pin-mux for beaglebone NOR cape [1]
This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device.
On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes,
so only one of them can be enabled at a time from board profile configs.
[1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module
[snip]
@@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
{-1},
};
-#endif
-#if defined(CONFIG_NOR) !defined(CONFIG_NOR_BOOT)
+#elif defined(CONFIG_NOR)
static struct module_pin_mux bone_norcape_pin_mux[] = {
-{OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
It _looks_ like this is jsut whitespace only. Since that doesn't match
the rest of the file, please don't do that.
Will be fixed in next version of this patch.
[snip]
#endif
#if defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux norboot_pin_mux[] = {
-{OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
-{OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
-{-1},
-};
-
void enable_norboot_pin_mux(void)
{
-configure_module_pin_mux(norboot_pin_mux);
+configure_module_pin_mux(bone_norcape_pin_mux);
Did you boot test this? The system requirements here are a bit strict
and I don't know if we can just do what you're doing here...
Yes, this one is also tested on Beaglebone-Black with following change in
boards.cfg to enable NOR on Beaglebone-Black
diff --git a/boards.cfg b/boards.cfg
-Active arm armv7 am33xx ti am335x
am335x_boneblack am335x_evm:SERIAL1,CO
+Active arm armv7 am33xx ti am335x
am335x_boneblack am335x_evm:SERIAL1,CO
-
U-Boot SPL 2014.07-00012-g0e5512a-dirty (Jul 21 2014 - 15:38:26)
reading u-boot.img
reading u-boot.img
U-Boot 2014.07-00012-g0e5512a-dirty (Jul 21 2014 - 15:38:26)
I2C: ready
DRAM: 512 MiB
Flash: 16 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
Net: ethaddr not set. Validating first E-fuse MAC
cpsw, usb_ether
Hit any key to stop autoboot: 1 0
U-Boot#
U-Boot# flinfo
Bank # 1: CFI conformant flash (16 x 16) Size: 16 MB in 128 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x227E2100
Advanced Sector Protection (PPB) enabled
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 1 ms, buffer size: 64 bytes
Sector Start Addresses:
0800 RO 0802 RO 0804 RO 0806 RO 0808 RO
080A RO 080C RO 080E RO 0810 RO 0812 RO
...
08E6 RO 08E8 RO 08EA RO 08EC RO 08EE RO
08F0 RO 08F2 RO 08F4 RO 08F6 RO 08F8 RO
08FA RO 08FC RO 08FE RO
U-Boot#
-
with regards, pekon
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[U-Boot] [PATCH] socfpga: cleanup socfpga_dw_mmc
Cleanups as suggested by wd on mailing list, plus I replaced
calloc(...,1) with malloc().
Signed-off-by: Pavel Machek pa...@denx.de
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -16,8 +16,6 @@ static const struct socfpga_clock_manager *clock_manager_base
=
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static char *SOCFPGA_NAME = SOCFPGA DWMMC;
-
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK (1 8)
static void socfpga_dwmci_clksel(struct dwmci_host *host)
@@ -47,14 +45,15 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
- struct dwmci_host *host = NULL;
- host = calloc(sizeof(struct dwmci_host), 1);
+ struct dwmci_host *host;
+
+ host = malloc(sizeof(struct dwmci_host));
if (!host) {
printf(dwmci_host calloc fail!\n);
return -1;
}
- host-name = SOCFPGA_NAME;
+ host-name = SOCFPGA DWMMC;
host-ioaddr = (void *)regbase;
host-buswidth = bus_width;
host-clksel = socfpga_dwmci_clksel;
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Re: [U-Boot] [PATCH] socfpga: cleanup socfpga_dw_mmc
Hi Pavel,
On Mon, 2014-07-21 at 12:30 +0200, ZY - pavel wrote:
Cleanups as suggested by wd on mailing list, plus I replaced
calloc(...,1) with malloc().
Signed-off-by: Pavel Machek pa...@denx.de
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -16,8 +16,6 @@ static const struct socfpga_clock_manager
*clock_manager_base =
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static char *SOCFPGA_NAME = SOCFPGA DWMMC;
-
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK (1 8)
static void socfpga_dwmci_clksel(struct dwmci_host *host)
@@ -47,14 +45,15 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
- struct dwmci_host *host = NULL;
- host = calloc(sizeof(struct dwmci_host), 1);
+ struct dwmci_host *host;
+
+ host = malloc(sizeof(struct dwmci_host));
We need calloc as it will initialize the allocated region. It will
prevent errors due to NULL comparison against uninitialized structure
member.
Thanks
Chin Liang
if (!host) {
printf(dwmci_host calloc fail!\n);
return -1;
}
- host-name = SOCFPGA_NAME;
+ host-name = SOCFPGA DWMMC;
host-ioaddr = (void *)regbase;
host-buswidth = bus_width;
host-clksel = socfpga_dwmci_clksel;
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Re: [U-Boot] socfpga: initialize MMC
Dear Pavel, In message 20140721102004.ga12...@amd.pavel.ucw.cz you wrote: #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 Please keep list sorted. It was sorted by address before, so I'll keep it like that. Yes, it was sorted by address, and 0xff704000 goes _before_ 0xffd08000, not after. --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_ALTERA_DWMMC) += altera_dw_mmc.o obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o Ditto. This should be a sorted list. This was not sorted and I will not need to modify it in next patch version, so I'll leave this unfixed. No, please clean up and fix it. Is there a free(host) anywhere? Dynamic allocation does not make much sense here, agreed. But as it is existing code, and there are bigger issues around, I'd prefer to leave it to someone else to clean it up... I tend to disagree. If we do not fix the problems as we see them, and when we are working on the code anyway, they will never get fixed. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de When the bosses talk about improving productivity, they are never talking about themselves. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv2] socfpga: cleanup socfpga_dw_mmc
Cleanups as suggested by wd on mailing list.
Signed-off-by: Pavel Machek pa...@denx.de
---
v2: calloc is actually needed, document it.
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -16,8 +16,6 @@ static const struct socfpga_clock_manager *clock_manager_base
=
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static char *SOCFPGA_NAME = SOCFPGA DWMMC;
-
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK (1 8)
static void socfpga_dwmci_clksel(struct dwmci_host *host)
@@ -47,14 +45,16 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
- struct dwmci_host *host = NULL;
+ struct dwmci_host *host;
+
+ /* calloc for zero init */
host = calloc(sizeof(struct dwmci_host), 1);
if (!host) {
printf(dwmci_host calloc fail!\n);
return -1;
}
- host-name = SOCFPGA_NAME;
+ host-name = SOCFPGA DWMMC;
host-ioaddr = (void *)regbase;
host-buswidth = bus_width;
host-clksel = socfpga_dwmci_clksel;
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Re: [U-Boot] socfpga: initialize MMC
Hi! #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 Please keep list sorted. It was sorted by address before, so I'll keep it like that. Yes, it was sorted by address, and 0xff704000 goes _before_ 0xffd08000, not after. Sorry, I meant will fix it so that it is sorted after my patches. Is there a free(host) anywhere? Dynamic allocation does not make much sense here, agreed. But as it is existing code, and there are bigger issues around, I'd prefer to leave it to someone else to clean it up... I tend to disagree. If we do not fix the problems as we see them, and when we are working on the code anyway, they will never get fixed. I'm working on the code, anyway, yes. Currently, u-boot is completely unusable on socfpga. I'd rather fix big problems first, so that code could be actually tested, and does not bitrot further as happened in clock and time areas. There are just too many small problems around. Could we talk on jabber or phone? Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] WIP for SPI
And I think I am saying that we already *have* it generalized for the GPIOs but only if we remove that renumbering function! Consider again that the U_CLASS lookup of a GPIO simply matches versus the range in each uclass data (gpio base and count). That search doesn't care about their order within the UCLASS_GPIO list. (Never mind that the renumbering breaks the association of the device base register and pin ranges as set up by the bind/probe code!) I wonder if we could do something similar then, where there is a default numbering if none is provided, but the GPIO devices are able to 'request' particular number ranges? I think we are talking past each other now. Isn't that already in place? One can already register a device with a range in the UCLASS so that the lookup happens and matches to a particular device instance. (But only assuming they are NOT renumbered.) What am I missing here? Thanks, jdl ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] How to find latest stable uboot version currently.
Is it Apr,2014 Thanks , Rohit ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] net/phy: Add support for CS4315/CS4340 PHY
Hi Shengzhou Liu, On Fri, Jul 18, 2014 at 4:33 PM, York Sun york...@freescale.com wrote: On 05/19/2014 01:29 AM, Shengzhou Liu wrote: Add support for Cortina CS4315/CS4340 10G PHY. - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device to initialize Cortina PHY. - Cortina PHY has non-standard offset of PHY ID registers, thus we define own get_phy_id() to override default get_phy_id(). - To define macro CONFIG_PHY_CORTINA will enable this driver. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- v5: fix unclaimed variable in case of nand boot. v4: add support for loading cortina phy ucode from NAND/SPI/SD v3: move devad as '0' in cortina.c instead of in phy.c v2: no change. Joe, Would you take this patch, or ack it so I can take it in? http://patchwork.ozlabs.org/patch/350162/ NAK Please add your new phy to phy.c and phy.h in alphabetical order like the rest of them. Thanks, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] i2c: tegra: use repeated start for reads
On 07/02/2014 10:34 PM, Heiko Schocher wrote: Hello Stephen, Am 02.07.2014 20:37, schrieb Stephen Warren: On 06/25/2014 10:57 AM, Stephen Warren wrote: From: Stephen Warrenswar...@nvidia.com I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Heiko, do these patches look good? Yes, they look good to me... Hmm.. as you ask, I think you want to have them in v2014.07 ? As it is a bugfix it should go into it, but as it also changes the behaviour of the driver, I am unsure if it can go in so close before the new release ... some Tested-by would be nice ... Sorry for the slow response; I was on vacation. I see the patches made it into the release, which should be fine. The I2C functionality is likely used very little, so even if there were problems with the patch, the fallout from it would be minimal. I applied them to the u-boot-i2c.git tree, and if nobody objects against them, I send tomorrow a pull request to Tom. Thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] esd:cmd_loadpci.c: Switch from do_source to source
Rather than calling do_source directly (which is not officially exported from cmd_source.c) call 'source' which is exported and requires a little less code to do so as well. Signed-off-by: Tom Rini tr...@ti.com --- board/esd/common/cmd_loadpci.c |8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index 803179a..95d1891 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -12,9 +12,6 @@ #endif #if defined(CONFIG_CMD_BSP) - -extern int do_source (cmd_tbl_t *, int, int, char *[]); - #define ADDRMASK 0xf000 /* @@ -27,7 +24,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int count2 = 0; char addr[16]; char str[] = \\|/-; - char *local_args[2]; u32 la, ptm1la; #if defined(CONFIG_440) @@ -84,9 +80,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Boot image via source command */ printf(executing script at addr 0x%s ...\n, addr); - local_args[0] = addr; - local_args[1] = NULL; - do_source(cmdtp, 0, 1, local_args); + source(la, NULL); break; case 2: -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] dfu: fix: Add the absolute path to the file name for ext4 write operation
On 07/16/2014 03:38 AM, Lukasz Majewski wrote: Commit 1151b7ac10b81ecbb has cleaned up read and write operations. Unfortunately, for correct operation the write for ext4 fs requires absolute patch. This patch fixes this case. Shouldn't the user simply supply the absolute patch name as the entity name? That's what I've been doing. This way, it makes files in sub-directories look more natural; you'd pass in e.g. /boot/zImage rather than boot/zImage, which looks like a relative path. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Bug u-boot-tools: /usr/include/image.h gets included instead of WC/include/image.h
Hello Chris,
On 20-07-14 12:30, disposa...@gmx.net wrote:
Hi list,
the package lensfun (http://lensfun.sourceforge.net/) ships an image.h which
gets installed in /usr/include/image.h.
When I build u-boot from the latest commit 524123a, it bails out with the
following error:
git clone git://git.denx.de/u-boot.git
cd u-boot
make coreboot-x86_config
make
1 CHK include/config/uboot.release
2 CHK include/generated/version_autogenerated.h
3 CHK include/generated/timestamp_autogenerated.h
4 UPD include/generated/timestamp_autogenerated.h
5 HOSTCC tools/aisimage.o
6 In file included from /usr/include/image.h:22:0,
7 from tools/aisimage.c:10:
8 /usr/include/rgbpixel.h:61:3: error: expected specifier-qualifier-list before
'RGBpixel'
9 In file included from tools/aisimage.c:10:0:
10 /usr/include/image.h:40:1: error: unknown type name 'class'
11 /usr/include/image.h:41:1: error: expected '=', ',', ';', 'asm' or
'__attribute__' before '{' token
12 tools/aisimage.c:22:1: error: unknown type name 'table_entry_t'
13 tools/aisimage.c:23:2: warning: braces around scalar initializer [enabled by
default]
14 tools/aisimage.c:23:2: warning: (near initialization for 'aisimage_cmds[0]')
[enabled by default]
[snip]
As far as I understand the messages, it erroneously tries to include
/usr/include/image.h instead of wc/include/image.h
Can you confirm this error?
yes this is an issue with u-boot tools.
see tools/Makefile
HOST_EXTRACFLAGS += -include $(srctree)/include/libfdt_env.h \
$(patsubst -I%,-idirafter%, $(UBOOTINCLUDE)) \
if you are lucky you can get away with adding image.h as a -include
like above. And yes this needs a decent solution one day.
Regards,
Jeroen
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[U-Boot] [PATCH] board_r: Add missing return to initr_doc
I happened to spot this while working in the area.
Signed-off-by: Ian Campbell i...@hellion.org.uk
Cc: Simon Glass s...@chromium.org
---
common/board_r.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/board_r.c b/common/board_r.c
index 4479acb..427ee67 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -600,6 +600,7 @@ static int initr_doc(void)
{
puts(DOC: );
doc_init();
+ return 0
}
#endif
--
2.0.1
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Re: [U-Boot] [PATCH 2/3] board_r: run scsi init() on ARM too
On Fri, 2014-07-18 at 21:12 -0600, Simon Glass wrote:
Hi Ian,
On 18 July 2014 13:38, Ian Campbell i...@hellion.org.uk wrote:
This has been disabled for ARM in initr_scsi since that function was
introduced. However it works fine for me on Cubieboard and Cubietruck (with
the
upcoming AHCI glue patch).
I also tested on two random ARM platforms which seem to define
CONFIG_CMD_SCSI:
- highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were as
expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the
comment
seems to be the prevailing style in this file) and add a missing return to
initr_doc which I happened to spot while editing.
That's great, but I think the latter should be a separate patch.
I've just sent that out. So here is v3 of this patch. I noticed that you
acked v1 and I failed to pick that up so I've taken the liberty of
adding it here after removing the initr_doc change -- I hope that was
OK.
8-
From dfbcd187178e3b15504657ebdb434ead4d417f2e Mon Sep 17 00:00:00 2001
From: Ian Campbell i...@hellion.org.uk
Date: Wed, 7 May 2014 19:54:05 +0100
Subject: [PATCH v3] board_r: run scsi init() on ARM too
This has been disabled for ARM in initr_scsi since that function was
introduced. However it works fine for me on Cubieboard and Cubietruck (with the
upcoming AHCI glue patch).
I also tested on two random ARM platforms which seem to define CONFIG_CMD_SCSI:
- highbank worked fine (on midway hardware)
- omap5_uevm built OK and I confirmed using objdump that things were as
expected (i.e. the default weak scsi_init nop was used).
While there remove the mismatched comment from the #endif (omitting the comment
seems to be the prevailing style in this file).
Signed-off-by: Ian Campbell i...@hellion.org.uk
Acked-by: Simon Glass s...@chromium.org
---
common/board_r.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/common/board_r.c b/common/board_r.c
index 602a239..4479acb 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -588,15 +588,12 @@ static int initr_status_led(void)
#if defined(CONFIG_CMD_SCSI)
static int initr_scsi(void)
{
- /* Not supported properly on ARM yet */
-#ifndef CONFIG_ARM
puts(SCSI: );
scsi_init();
-#endif
return 0;
}
-#endif /* CONFIG_CMD_NET */
+#endif
#if defined(CONFIG_CMD_DOC)
static int initr_doc(void)
--
2.0.1
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Re: [U-Boot] [PATCH 1/2] sunxi: Use Thumb2 and move stack to gain more SRAM space in FEL mode
On Fri, 2014-07-18 at 20:09 +0300, Siarhei Siamashka wrote: http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html I think a better reference is https://github.com/hno/Allwinner-Info/blob/master/FEL-usb/USB-protocol.txt +.syntax unified +.text +.arm +.arch armv7a +.p2align 2 + +.globl _start_fel Is there any reason not to use ENTRY() for this? +.globl s_init +.globl __bss_start +.globl __bss_end I don't think you need .globl to access external symbols, all .globl does is control the visibility of things defined in this file. IOW you can drop all 3 of these AFAICT. [...] + /* Pass control to the 's_init()' function */ + b s_init Since this code is in arm mode and s_init will, I think, be in Thumb mode after this patch shouldn't this be a bx? Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
On Sat, 2014-07-19 at 13:20 +0200, Hans de Goede wrote: Hi, On 07/18/2014 07:09 PM, Siarhei Siamashka wrote: This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start. If this is not done, the Linux system ends up booted with the L2 cache disabled. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com --- arch/arm/cpu/armv7/sunxi/board.c | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c9448..86cf4c9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -69,6 +69,18 @@ void s_init(void) mcr p15, 0, r0, c1, c0, 1\n); #endif +#if defined(CONFIG_SPL_FEL) (defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)) + /* For ARM Cortex-A8 based hardware (sun4i and sun5i), the L2EN bit is +* set by the BROM code in the normal mode, but not in the FEL mode. +* Here we fix this inconsistency in the Auxiliary Ctl reg by also +* setting the missing L2EN bit. +*/ + asm volatile( + mrc p15, 0, r0, c1, c0, 1\n + orr r0, r0, #2\n + mcr p15, 0, r0, c1, c0, 1\n : : : r0); +#endif + Wouldn't it be better to do this in the start_fel.S file you've introduced in the first patch of this series ? That wouldn't remove the need for the ifdef if that's what you are thinking since it still needs to be sun4i/sun5i specific. I think doing it here is in keeping with setting ACTLR.SMP on the sun6i/sun7i platforms which is just above the context here. Acked-by: Ian Campbell i...@hellion.org.uk Although I also wouldn't object to doing it in in start_fel.S if that is preferred. I expect this needs to be done on secondary processors. Need to keep that in mind if/when someone works on PSCI for sun[45]i. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/14] sunxi: dram: Remove useless 'dramc_scan_dll_para()' function
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()' function by trying different DLL adjustments and using the hardware DQS gate training result as a feedback is a great source of inspiration, but it just can't work properly the way it is implemented now. The fatal problem of this implementation is that the DQS gating window can be successfully found for almost every DLL delay adjustment setup that gets tried. Thus making it unable to see any real difference between 'good' and 'bad' settings. Also this code was supposed to be only activated by setting the highest bit in the 'dram_tpr3' variable of the 'dram_para' struct (per-board dram configuration). But none of the linux-sunxi devices has ever used it for real. Basically, this code is just a dead weight. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/14] sunxi: dram: Remove broken super-standby remnants
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: If the dram-ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this means that DRAM is currently in self-refresh mode and retaining the old data. Since we have no idea what to do in this situation yet, just set this register to 0 and initialize DRAM in the same way as on any normal reboot (discarding whatever was stored there). This part of code was apparently used by the Allwinner boot0 bootloader to handle resume from the so-called super-standby mode. But this particular code got somehow mangled on the way from the boot0 bootloader to the u-boot-sunxi bootloader and has no chance of doing anything even remotely sane. For example: 1. in the original boot0 code we had mctl_write_w(SDR_DPCR, 0x1651) (write to the register) and in the u-boot it now looks like setbits_le32(dram-ppwrsctl, 0x1651) (set bits in the register) 2. in the original boot0 code it was issuing three commands 0x12, 0x17, 0x13 (Self-Refresh entry, Self-Refresh exit, Refresh), but in the u-boot they have become 0x12, 0x12, 0x13 (Self-Refresh entry, Self-Refresh entry, Refresh) Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 03/14] sunxi: dram: Respect the DDR3 reset timing requirements
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: The RESET pin needs to be kept low for at least 200 us according to the DDR3 spec. So just do it the right way. This issue did not cause any visible major problems earlier, because the DRAM RESET pin is usually already low after the board reset. And the time gap before reaching the sunxi u-boot DRAM initialization code appeared to be sufficient. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/14] sunxi: dram: Code cleanup and comments for the CKE delay handling
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires to wait for additional 500 us after the RESET pin is de-asserted. The DRAM controller takes care of this delay by itself, using a configurable counter in the SDR_IDCR register. This works in the same way on sun4i/sun5i/sun7i hardware (even the default register value 0x00c80064 is identical). Except that the counter is ticking a bit slower on sun7i (3 DRAM clock cycles instead of 2), resulting in longer actual delays for the same settings. This patch keeps the old code and only removes the CONFIG_SUN7I ifdef. But maybe we should drop all of this and just add 'udelay(500)' after the DDR3 reset without bothering to play with these undocumented registers. I'm happy to go with whichever you think is better. Another interesting observation is that the u-boot-sunxi code (derived from the Allwinner boot0) did not configure the SDR_IDCR register for sun4i/sun5i, but performed the DDR3 reset very early. Possibly resulting in a sufficient time gap between the DDR3 reset and the DDR3 initialization steps. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/14] sunxi: dram: Code cleanup for the impedance calibration
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: Moved the impedance setup code part into a separate function. Added explicit wait for ZQ calibration completion before proceeding to the next initialization steps. Removed the CONFIG_SUN7I ifdef guard around the code, which has identical behaviour on sun4i/sun5i/sun7i. And if 'odt_en' is set in the 'dram_para' struct, then ODT now actually gets enabled in the DRAM_IOCR register (which the older code failed to do and was always running without ODT no matter the settings). There's a few aspects of this code which don't seem to be explained here. Firstly if odt_en is not enabled we now skip setting the impedance. Which seems logical but should me mentioned. It's also worth noting that none of the platforms in u-boot-sunxi.git#master set odt_en Secondly the weird sun7i magic has changed from - setbits_le32(dram-zqcr1, (0x1 24) | (0x1 1)); - if (para-tpr4 0x2) - clrsetbits_le32(dram-zqcr1, (0x1 24), (0x1 1)); into just a write of the raw value. This should be mentioned. Also this now occurs after the call to dramc_clock_output_en(). Thirdly why do we not wait for ZQ calibration on sun7i? Lastly it now seems to support calibration using an external resistor. And neither half of that new if (zdata) seems to correspond to the old code. I think part of the problem here is that this patch is trying to do too much in one go. If separating things out isn't possible (e.g. because these changes are all interdependent) then it is important that the commit message describes them. I'd also steer clear of describing this as a code cleanup when it also has functional changes. + * Wait up to 1s for mask to be set in given reg. + */ +static void await_bits_set(u32 *reg, u32 mask) This could be combined with the existing await_completion into a function which takes a mask and a val. Perhaps with convenience wrappers for the two cases. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/14] sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote:
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock speed.
Allwinner A13 uses only 16-bit data bus width to connect the external DRAM,
which is halved compared to the 32-bit data bus of sun4i (Allwinner A10), so
it does not make much sense to clock a wider internal bus at a very high
speed.
The Allwinner A13 manual specifies 300 MHz MBUS clock speed limit and 533 MHz
DRAM clock speed limit. Newer sun7i hardware (Allwinner A20) has a full width
32-bit external memory interface again, but still keeps the MBUS clock speed
configurable. Clocking MBUS too low inhibits memory performance and one has
to find the optimal MBUS/DRAM clock speed ratio, which may depend on many
factors.
This patch introduces a new 'mbus_clock' parameter for the 'dram_para' struct
and uses it as a desired MBUS clock speed target. If 'mbus_clock' is not set,
300 MHz is used by default to match the older hardcoded settings.
Nothing in this series seems to set it for any board -- is that
expected?
+ if (pll6x_div = 16 pll6x_clk / pll6x_div pll5p_clk / pll5p_div) {
Some brackets or perhaps some temporaries ({pll5p,pll6x}_rate ?) might
help clarity/readability here.
When pll6 is viable you prefer the faster clock, even if it might happen
to be further from the requested clock, is that right? Or does all the
arithmetic end up with that never being the case?
Ian.
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Re: [U-Boot] [PATCH 07/14] sunxi: dram: Use divisor P=1 for PLL5
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: This configures the PLL5P clock frequency to something in the ballpark of 1GHz and allows more choices for MBUS and G2D clock frequency selection (using their own divisors). In particular, it enables the use of 2/3 clock speed ratio between MBUS and DRAM. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 08/14] sunxi: dram: Improve DQS gate data training error handling
On Fri, 2014-07-18 at 19:22 +0300, Siarhei Siamashka wrote: The stale error status should be cleared for all sun4i/sun5i/sun7i hardware and not just for sun7i. Also there are two types of DQS gate training errors (found no result and found more than one possible result). Both are handled now. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/14] sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote:
It is going to be useful in more than one place.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
arch/arm/cpu/armv7/sunxi/dram.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
index 18a5c3b..49d1770 100644
--- a/arch/arm/cpu/armv7/sunxi/dram.c
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -115,23 +115,31 @@ static void mctl_enable_dll0(u32 phase)
udelay(22);
}
+/* Get the number of DDR byte lanes */
+static u32 mctl_get_number_of_lanes(void)
+{
+ struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+ switch (readl(dram-dcr) DRAM_DCR_BUS_WIDTH_MASK) {
+ case DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT):
+ return 4;
+ case DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_16BIT):
+ return 2;
+ default:
+ return 1;
+ }
+}
+
/*
* Note: This differs from pm/standby in that it checks the bus width
*/
static void mctl_enable_dllx(u32 phase)
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
- u32 i, n, bus_width;
-
- bus_width = readl(dram-dcr);
+ u32 i, number_of_lanes;
- if ((bus_width DRAM_DCR_BUS_WIDTH_MASK) ==
- DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
- n = DRAM_DCR_NR_DLLCR_32BIT;
- else
- n = DRAM_DCR_NR_DLLCR_16BIT;
Either DRAM_DCR_NR_DLLCR_??BIT are obsolete now and should be removed or
they should be be adjusted and used in the new function.
ISTM they don't add much so removing would be fine by me.
+ number_of_lanes = mctl_get_number_of_lanes();
There is a subtle functional change here since number_of_lanes can be 1
whereas n could never have been 2. Is that intended/ok? Please mention
in the commit message.
Ian.
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Re: [U-Boot] [PATCH 11/14] sunxi: dram: Support sun4i (Allwinner A10) and sun5i (Allwinner A13)
On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote: Add the necessary missing bits from the legacy u-boot-sunxi for the Allwinner A10 and A13 support (originally authored by Henrik Nordstrom, Stefan Roese, Oliver Schinagl and Hans de Goede). Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com This is already in u-boot-sunxi.git#master. Please rebase. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/14] sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote: All the known Allwinner A10/A13/A20 devices are using just single rank DDR3 memory. So don't pretend that we support DDR2 or more than one rank, because nobody could ever test these configurations for real and they are likely broken. Support for these features can be added back in the case if such hardware actually exists. + if (para-type != DRAM_MEMORY_TYPE_DDR3 || para-rank_num != 1) + return 0; Can we not go further and remove these fields from the para struct too? Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/14] sunxi: dram: Derive write recovery delay from DRAM clock speed
On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote: The write recovery time is 15ns for all JEDEC DDR3 speed bins. And instead of hardcoding it to 10 cycles, it is possible to set tighter timings based on accurate calculations. For example, DRAM clock frequencies up to 533MHz need only 8 cycles for write recovery. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 14/14] sunxi: dram: Autodetect DDR3 bus width and density
On Fri, 2014-07-18 at 19:23 +0300, Siarhei Siamashka wrote: In the case if the 'dram_para' struct does not specify the exact bus width or chip density, just use a trial and error method to find a usable configuration. Because all the major bugs in the DRAM initialization sequence are now hopefully fixed, it should be safe to re-initialize the DRAM controller multiple times until we get it configured right. The original Allwinner's boot0 bootloader also used a similar autodetection trick. The DDR3 spec contains the package pinout and addressing table for different possible chip densities. It appears to be impossible to distinguish between a single chip with 16 I/O data lines and a pair of chips with 8 I/O data lines in the case if they provide the same storage capacity. Because a single 16-bit chip has a higher density than a pair of equivalent 8-bit chips, it has stricter refresh timings. So in the case of doubt, we assume that 16-bit chips are used. Additionally, only Allwinner A20 has all A0-A15 address lines and can support densities up to 8192. The older Allwinner A10 and Allwinner A13 can only support densities up to 4096. We deliberately leave out DDR2, dual-rank configurations and the special case of a 8-bit chip with density 8192. None of these configurations seem to have been ever used in real devices. And no new devices are likely to use these exotic configurations (because only up to 2GB of RAM can be populated in any case). This DRAM autodetection feature potentially allows to have a single low performance fail-safe DDR3 initialiazation for a universal single bootloader binary, which can be compatible with all Allwinner A10/A13/A20 based devices (if the ifdefs are replaced with a runtime SoC type detection). Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com Acked-by: Ian Campbell i...@hellion.org.uk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/14] sunxi: Allwinner A10/A13/A20 DRAM controller fixes
On Sat, 2014-07-19 at 12:59 +0200, Hans de Goede wrote: can you please rebase your set on top of this tree? Yes, please. I understand this may be non trivial and thus may require some extra work from you side, and I'm sorry about that. Me too. Having been through the series though I don't think there is much other than the rebase (and review comments) to address which is massively more complex on top of the current custodian master, but maybe I'm being overly optimistic. Once you've posted a new rebased version I or Ian will review it and get it into the above tree for merging upstream. I actually went through it as it stands already and I've acked various bits which seemed like they just need the obvious rebasing onto u-boot-sunxi#master. Siarhei, if the rebase turns out to be non-trivial/obvious then please drop the ack. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote: Hello Siarhei, On 18-07-14 19:09, Siarhei Siamashka wrote: This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start. If this is not done, the Linux system ends up booted with the L2 cache disabled. I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue. The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode. In any case I think these sorts of low level platform specific details are the sort of thing which the bootloader probably ought to be setting up. Ian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
On Mon, 2014-07-21 at 19:39 +0100, Ian Campbell wrote: I expect this needs to be done on secondary processors. Need to keep that in mind if/when someone works on PSCI for sun[45]i. Except as Tom points out on IRC, sun[45]i are both single core... Oops! Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
Hello Ian, On 21-07-14 22:07, Ian Campbell wrote: On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote: Hello Siarhei, On 18-07-14 19:09, Siarhei Siamashka wrote: This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start. If this is not done, the Linux system ends up booted with the L2 cache disabled. I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue. The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode. mmm, I guess there is something wrong with the boot sequence if the kernel itself can't access raw hw. In any case I think these sorts of low level platform specific details are the sort of thing which the bootloader probably ought to be setting up. No, u-boot tries not to touch anything it doesn't use and, if anything disables it after use. Hence, this seems like a kernel bug and nothing to do with u-boot. They should be independent, iow a kernel should not rely on u-boot setting thing up, that is a bug. Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mtd: cfi_flash: fix clang warning
On Tue, Jun 17, 2014 at 10:47:31PM +0200, Jeroen Hofstee wrote:
clang warns this check is silly; it is since s is
a local variable.
u-boot/drivers/mtd/cfi_flash.c:2363:13: warning: comparison of
array 's' not equal to a null pointer is always true
else if ((s != NULL) (strcmp(s, yes) == 0)) {
cc: Stefan Roese s...@denx.de
Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl
Applied to u-boot/master, thanks!
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Re: [U-Boot] lib: div64: add missing include
On Sun, Jun 22, 2014 at 11:24:04PM +0200, Jeroen Hofstee wrote: Include the function its prototype to prevent the warning that it has no prototype. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common: commands: make commands static
On Mon, Jun 23, 2014 at 12:22:08AM +0200, Jeroen Hofstee wrote: Since most commands are not public, make them static. This prevents warnings that no common prototype is available. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common: board_f: cosmetic use __weak for leds
On Mon, Jun 23, 2014 at 11:20:19PM +0200, Jeroen Hofstee wrote: First of all this looks a lot better, but it also prevents a gcc warning (W=1), that the weak function has no previous prototype. cc: Simon Glass s...@chromium.org Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Acked-by: Simon Glass s...@chromium.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] env_callback.h: spl: mark callback as maybe_unused
On Thu, Jul 10, 2014 at 08:38:35PM +0200, Jeroen Hofstee wrote: When static inline is used in a header file the function should preferably be inlined and if not possible made a static function. When declared inside a c file there is a static function, which might be inlined. Since SPL uses a define to declare the static inline it becomes part of the c file although it is declared in a header and clang will warn that you have introduced unused static functions. Add maybe_unused to prevent such warnings. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common:splash: use __weak
On Thu, Jun 26, 2014 at 07:53:16PM +0200, Jeroen Hofstee wrote: This not only looks a bit better it also prevents a warning with W=1 (no previous prototype). cc: ag...@denx.de Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] lib:lmb: use __weak
On Thu, Jun 26, 2014 at 08:04:37PM +0200, Jeroen Hofstee wrote: This not only looks a bit better it also prevents a warning with W=1 (no previous prototype). Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common: main.c: make show_boot_progress __weak
On Thu, Jun 26, 2014 at 08:18:31PM +0200, Jeroen Hofstee wrote: This not only looks a bit better it also prevents a warning with W=1 (no previous prototype). Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Acked-by: Simon Glass s...@chromium.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] dm: add missing includes
On Wed, Jun 25, 2014 at 09:57:45PM +0200, Jeroen Hofstee wrote: lists.c / root.c do not include their own header and they could potentially implement a different function. Therefore actually include the headers. cc: s...@chromium.org Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Acked-by: Simon Glass s...@chromium.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] lib:sha1: remove unused constant
On Thu, Jul 10, 2014 at 08:12:45PM +0200, Jeroen Hofstee wrote: This prevents a clang warning. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] dirvers: mmc: use __weak
On Thu, Jul 10, 2014 at 10:46:28PM +0200, Jeroen Hofstee wrote: use weak instead of alias to prevent some clang warnings. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 1/2] yaffs2: cosmetic: remove self assignments
On Sat, Jul 12, 2014 at 03:16:51PM +0200, Jeroen Hofstee wrote: Remove self assignments which is just dead code to prevent compiler warnings about non used arguments. For u-boot this does not prevent any warning though, on the contrary it actual introduces warnings when compiling with clang. Remove them. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] lib:vsprintf: reduce scope of pack_hex_byte
On Thu, Jul 10, 2014 at 10:33:00PM +0200, Jeroen Hofstee wrote: pack_hex_byte is only used when CONFIG_CMD_NET is defined so limit it to that scope. This prevents a clang warning. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] common: env_common: make env_get_char_spec __weak
On Sat, Jul 12, 2014 at 03:22:13PM +0200, Jeroen Hofstee wrote: Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2,2/2] yaffs2: preprocessor cleanup
On Sat, Jul 12, 2014 at 03:16:52PM +0200, Jeroen Hofstee wrote: Current code uses the preprocessor to change an else case to a statement without any if condition at all. Although this works, change the optional code to return early, so all optional code is contained within a single #ifdef. Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common: bootm_os: make arch_preboot_os __weak
On Thu, Jul 10, 2014 at 11:06:25PM +0200, Jeroen Hofstee wrote: Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] board: rpi_b: include mmc header and fix prototype
On Sun, Jul 13, 2014 at 10:01:51PM +0200, Jeroen Hofstee wrote: While at it add fdt_support.h as well. cc: Stephen Warren swar...@wwwdotorg.org Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] mmc: prevent some warnings with make W=1
On Sat, Jul 12, 2014 at 09:24:08PM +0200, Jeroen Hofstee wrote: Add missing prototypes for global functions and make local functions static. cc: pa...@antoniou-consulting.com Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] autoboot: add its own header
On Sun, Jul 13, 2014 at 10:57:58PM +0200, Jeroen Hofstee wrote: Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] common: cmd_mii: fix printf format warning
On Sun, Jul 13, 2014 at 11:44:21PM +0200, Jeroen Hofstee wrote: The and operator implicitly upcasts the value to int, hence the format should expect an int type as well. (and make checkpatch happy) Signed-off-by: Jeroen Hofstee jer...@myspectrum.nl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [i2c] Pull request
On Wed, Jul 16, 2014 at 07:16:50AM +0200, Heiko Schocher wrote: Hello Tom, please pull from u-boot-i2c.git The following changes since commit 524123a70761110c5cf3ccc5f52f6d4da071b959: Prepare v2014.07 (2014-07-14 13:16:45 -0400) are available in the git repository at: git://git.denx.de/u-boot-i2c.git master for you to fetch changes up to a17fd10fb516df3a0b00fcceb8678de2689951fc: fsl_i2c: add support for 3rd and 4th I2C (2014-07-16 05:19:15 +0200) Heiko Schocher (1): i2c, omap24xx: add i2c deblock sequenz Shengzhou Liu (1): fsl_i2c: add support for 3rd and 4th I2C drivers/i2c/fsl_i2c.c | 22 -- drivers/i2c/omap24xx_i2c.c | 57 + 2 files changed, 77 insertions(+), 2 deletions(-) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
On Mon, 2014-07-21 at 22:39 +0200, Jeroen Hofstee wrote: Hello Ian, On 21-07-14 22:07, Ian Campbell wrote: On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote: Hello Siarhei, On 18-07-14 19:09, Siarhei Siamashka wrote: This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start. If this is not done, the Linux system ends up booted with the L2 cache disabled. I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue. The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode. mmm, I guess there is something wrong with the boot sequence if the kernel itself can't access raw hw. Do you know what ARM Secure and Non-Secure worlds are? The kernel expects to be launched in NS mode and simply cannot access this register. This is a feature not a bug. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/10] arm: ls102xa: Add Freescale LS102xA SoC support
On 07/03/2014 12:24 AM, Alison Wang wrote: The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang alison.w...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: Jingchang Lu jingchang...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Change log: v2: Add serdes support. Update DDR frequency and data rate information. Fix overflow condition error for the timer. Albert, As you can see, Freescale starts to make ARM core SoCs on QorIQ product line. As previously discussed, I will maintain fsl-qoriq repository to host these patches. Beside ARMv8, I am new to ARM cores. To start, I would like to solicit your comments/ack for this series. It will be helpful if you can share how ARM maintainers do the daily jobs like sending notice, pull requests, etc. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] esd:cmd_loadpci.c: Switch from do_source to source
On Mon, Jul 21, 2014 at 11:19:03AM -0400, Tom Rini wrote: Rather than calling do_source directly (which is not officially exported from cmd_source.c) call 'source' which is exported and requires a little less code to do so as well. Signed-off-by: Tom Rini tr...@ti.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] driver/mtd: Use generic timer API for FSL IFC, eLBC
On Tue, 2014-07-15 at 14:09 +0530, Prabhakar Kushwaha wrote: diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 8b453cb..6c158f5 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -26,8 +26,6 @@ #define MAX_BANKSCONFIG_SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ -#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC - NAND Machine */ struct fsl_ifc_ctrl; @@ -292,7 +290,8 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) struct fsl_ifc_mtd *priv = chip-priv; struct fsl_ifc_ctrl *ctrl = priv-ctrl; struct fsl_ifc *ifc = ctrl-regs; - long long end_tick; + u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; + u32 time_start; u32 eccstat[4]; int i; Why are you changing the timeout from 10ms to 20ms? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Am 2014-05-14 23:29, schrieb Anthony Felice: Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice tony.fel...@timesys.com --- arch/arm/include/asm/arch-vf610/imx-regs.h| 50 +++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- arch/arm/include/asm/imx-common/iomux-v3.h| 2 + board/freescale/vf610twr/vf610twr.c | 93 +-- 4 files changed, 128 insertions(+), 61 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index c2f9761..a11b419 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -100,9 +100,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING 0x2613 #define DDRMC_PHY_DQS_TIMING 0x2615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x0021 #define DDRMC_PHY_MASTER_CTRL0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x2000 +#define DDRMC_PHY_OFF0x +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE(1 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 8) @@ -135,7 +137,7 @@ #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) 0x3f) 16) #define DDRMC_CR23_BSTLEN(v) (((v) 0x7) 24) -#define DDRMC_CR23_TDLL(v) ((v) 0xff) +#define DDRMC_CR23_TDLL(v) ((v) 0x) #define DDRMC_CR24_TRP_AB(v) ((v) 0x1f) #define DDRMC_CR25_TREF_EN (1 16) #define DDRMC_CR26_TREF(v) (((v) 0x) 16) @@ -148,7 +150,7 @@ #define DDRMC_CR33_EN_QK_SREF(1 16) #define DDRMC_CR34_CKSRX(v) (((v) 0xf) 16) #define DDRMC_CR34_CKSRE(v) (((v) 0xf) 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 8) +#define DDRMC_CR38_FREQ_CHG_EN(v)(((v) 0x1) 8) #define DDRMC_CR39_PHY_INI_COM(v)(((v) 0x) 16) #define DDRMC_CR39_PHY_INI_STA(v)(((v) 0xff) 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) 0x3) @@ -160,7 +162,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) 0xf) 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 24) +#define DDRMC_CR72_ZQCS_ROTATE(v)(((v) 0x1) 24) #define DDRMC_CR73_APREBIT(v)(((v) 0xf) 24) #define DDRMC_CR73_COL_DIFF(v) (((v) 0x7) 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) 0x3) 8) @@ -179,9 +181,10 @@ #define DDRMC_CR77_CS_MAP(1 24) #define DDRMC_CR77_DI_RD_INTLEAVE(1 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) 0x7) 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 24) -#define DDRMC_CR82_INT_MASK 0x1fff +#define DDRMC_CR79_CTLUPD_AREF(v)(((v) 0x1) 24) +#define DDRMC_CR82_INT_MASK 0x1000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) 0x1f) 16) @@ -189,9 +192,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) 0x7) 16) #define DDRMC_CR96_WLMRD(v) (((v) 0x3f) 8) #define DDRMC_CR96_WLDQSEN(v)((v) 0x3f) +#define DDRMC_CR97_WRLVL_EN (1 24) +#define DDRMC_CR98_WRLVL_DL_0(0) +#define DDRMC_CR99_WRLVL_DL_1(0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 8) #define DDRMC_CR105_RDLVL_DL_0(v)(((v) 0xff)
Re: [U-Boot] [PATCH 4/4] arm: add Cygnus and NSP boards
On 14-07-20 12:54 AM, Wolfgang Denk wrote:
Dear Steve Rae,
In message 1405733854-20194-5-git-send-email-s...@broadcom.com you wrote:
The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.
...
+/* uArchitecture specifics */
...
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM30x18023000
Is the console inex really architecture specific and identical for all
boards based on this? I would expect to find this in the board config
header.
Yes -- the bootrom code always uses 3 for this architecture
+/* uArchitecture specifics */
...
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM10x18000300
Ditto here.
Ditto -- the bootrom code always uses 1 for this architecture
...
+ /* Address of boot parameters passed to kernel
+* Use default offset 0x100
+*/
Incorrect multiline comment style. Please check (and fix, if needed)
globally.
will fix in [v2]
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+ return 0;
+}
It makes no sense to add an empty function here. Just do not define
CONFIG_MISC_INIT_R
will fix in [v2]
+#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */
+#define CONFIG_STACKSIZE SZ_256K
Please do not use the SZ_ defines. They are deprecated.
will fix in [v2]
+/* Init functions */
+#define CONFIG_MISC_INIT_R /* board's misc_init_r function */
Unused, so remove.
will fix in [v2]
+#define CONFIG_ENV_SIZE0x1
Do you really, really need 64 kB of environmnt? I doubt that.
will fix in [v2]
Best regards,
Wolfgang Denk
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Re: [U-Boot] [PATCH 1/4] arm: iproc: Initial commit of iproc architecture code
On 14-07-20 12:46 AM, Wolfgang Denk wrote: Dear Steve Rae, In message 1405733854-20194-2-git-send-email-s...@broadcom.com you wrote: From: Scott Branden sbran...@broadcom.com The iproc architecture code is present in several Broadcom chip architectures, including Cygnus and NSP. ... + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE0_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_CORE1_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_SWITCH_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_ARM_PERIPH_CLKGATE); + writel(IPROC_CLKCT_HDELAY_SW_EN, IHOST_PROC_CLK_APB0_CLKGATE); Instead of using #defines for IHOST_PROC_CLK_CORE0_CLKGATE etc. it would be better to use a C struct to describe the register map. In our situation, the register map is an automatically generated list of #defines (which actually comes directly from another department within the company)... It might be better to use a C struct, but to be able to use this generated file is more accurate. + count_h = readl(IPROC_PERIPH_GLB_TIM_REG_BASE + + TIMER_GLB_HI_OFFSET); + count_l = readl(IPROC_PERIPH_GLB_TIM_REG_BASE + + TIMER_GLB_LOW_OFFSET); + cur_tick = readl(IPROC_PERIPH_GLB_TIM_REG_BASE + +TIMER_GLB_HI_OFFSET); NAK. We do not support accessing device registers through a base address + offset notation. Please use a C struct instead. Please clarify -- does the readl() (and writel()) have issues with this base + offset notation? We have used this extensively (in the non-upstreamed code), and we would like to upstream this. ( ...looking at the existing U-Boot code, this notation is used elsewhere... ) Please fix globally. ... +#define IHOST_PROC_CLK_WR_ACCESS 0X1900 +#define IHOST_PROC_CLK_POLICY_FREQ 0X1908 ... +#define IHOST_PROC_CLK_POLICY_CTL 0X190C ... Make C struct? (automatically generated code) +/* ARM A9 Private Timer */ +#define TIMER_PVT_LOAD_OFFSET 0x +#define TIMER_PVT_COUNTER_OFFSET 0x0004 +#define TIMER_PVT_CTRL_OFFSET 0x0008 +#define TIMER_PVT_STATUS_OFFSET0x000C ... +#define TIMER_GLB_LOW_OFFSET 0x +#define TIMER_GLB_HI_OFFSET0x0004 +#define TIMER_GLB_CTRL_OFFSET 0x0008 Please make C struct !!! (automatically generated code) Best regards, Wolfgang Denk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/12] video: Add S3C24xx framebuffer support
Add basic framebuffer driver for the S3C24xx family of CPUs.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Anatolij Gustschin ag...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
drivers/video/Makefile | 1 +
drivers/video/cfb_console.c | 2 +-
drivers/video/s3c-fb.c | 172
3 files changed, 174 insertions(+), 1 deletion(-)
create mode 100644 drivers/video/s3c-fb.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 945f35d..7441783 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
+obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index b52e9ed..4a56da8 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -135,7 +135,7 @@
#endif
#endif
-#ifdef CONFIG_VIDEO_MXS
+#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C)
#define VIDEO_FB_16BPP_WORD_SWAP
#endif
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
new file mode 100644
index 000..521eb75
--- /dev/null
+++ b/drivers/video/s3c-fb.c
@@ -0,0 +1,172 @@
+/*
+ * S3C24x0 LCD driver
+ *
+ * NOTE: Only 16/24 bpp operation with TFT LCD is supported.
+ *
+ * Copyright (C) 2014 Marek Vasut ma...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include malloc.h
+#include video_fb.h
+
+#include asm/errno.h
+#include asm/io.h
+#include asm/arch/s3c24x0_cpu.h
+
+#include videomodes.h
+
+static GraphicDevice panel;
+
+/* S3C requires the FB to be 4MiB aligned. */
+#define S3CFB_ALIGN(4 20)
+
+#define S3CFB_LCDCON1_CLKVAL(x)((x) 8)
+#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 5)
+#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP(0xc 1)
+#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP(0xd 1)
+
+#define S3CFB_LCDCON2_VBPD(x) ((x) 24)
+#define S3CFB_LCDCON2_LINEVAL(x) ((x) 14)
+#define S3CFB_LCDCON2_VFPD(x) ((x) 6)
+#define S3CFB_LCDCON2_VSPW(x) ((x) 0)
+
+#define S3CFB_LCDCON3_HBPD(x) ((x) 19)
+#define S3CFB_LCDCON3_HOZVAL(x)((x) 8)
+#define S3CFB_LCDCON3_HFPD(x) ((x) 0)
+
+#define S3CFB_LCDCON4_HSPW(x) ((x) 0)
+
+#define S3CFB_LCDCON5_BPP24BL (1 12)
+#define S3CFB_LCDCON5_FRM565 (1 11)
+#define S3CFB_LCDCON5_HWSWP(1 0)
+
+#definePS2KHZ(ps) (10UL / (ps))
+
+/*
+ * Example:
+ * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\
+ *pclk:30066,le:41,ri:89,up:45,lo:12,\
+ *hs:1,vs:1,sync:100663296,vmode:0
+ */
+static void s3c_lcd_init(GraphicDevice *panel,
+ struct ctfb_res_modes *mode, int bpp)
+{
+ uint32_t clk_divider;
+ struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd();
+
+ /* Stop the controller. */
+ clrbits_le32(regs-lcdcon1, 1);
+
+ /* Calculate clock divider. */
+ clk_divider = (get_HCLK() / PS2KHZ(mode-pixclock)) / 1000;
+ clk_divider = DIV_ROUND_UP(clk_divider, 2);
+ if (clk_divider)
+ clk_divider -= 1;
+
+ /* Program LCD configuration. */
+ switch (bpp) {
+ case 16:
+ writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP |
+ S3CFB_LCDCON1_PNRMODE_TFT |
+ S3CFB_LCDCON1_CLKVAL(clk_divider),
+ regs-lcdcon1);
+ writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565,
+ regs-lcdcon5);
+ break;
+ case 24:
+ writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP |
+ S3CFB_LCDCON1_PNRMODE_TFT |
+ S3CFB_LCDCON1_CLKVAL(clk_divider),
+ regs-lcdcon1);
+ writel(S3CFB_LCDCON5_BPP24BL, regs-lcdcon5);
+ break;
+ }
+
+ writel(S3CFB_LCDCON2_LINEVAL(mode-yres - 1) |
+ S3CFB_LCDCON2_VBPD(mode-upper_margin - 1) |
+ S3CFB_LCDCON2_VFPD(mode-lower_margin - 1) |
+ S3CFB_LCDCON2_VSPW(mode-vsync_len - 1),
+ regs-lcdcon2);
+
+ writel(S3CFB_LCDCON3_HBPD(mode-right_margin - 1) |
+ S3CFB_LCDCON3_HFPD(mode-left_margin - 1) |
+ S3CFB_LCDCON3_HOZVAL(mode-xres - 1),
+ regs-lcdcon3);
+
+ writel(S3CFB_LCDCON4_HSPW(mode-hsync_len - 1),
+ regs-lcdcon4);
+
+ /* Write FB address. */
+ writel(panel-frameAdrs 1,
[U-Boot] [PATCH 08/12] i2c: s3c: Implant support for S3C2440
This is a matter of simple additional ifdefery to cater
for the different register layout of the S3C2440 chip.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Heiko Schocher h...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
drivers/i2c/s3c24x0_i2c.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index fd328f0..927cf61 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -153,7 +153,7 @@ static int GetI2CSDA(void)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
return (readl(gpio-gpedat) 0x8000) 15;
#endif
#ifdef CONFIG_S3C2400
@@ -165,7 +165,7 @@ static void SetI2CSCL(int x)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
writel((readl(gpio-gpedat) ~0x4000) |
(x 1) 14, gpio-gpedat);
#endif
@@ -427,7 +427,7 @@ static void s3c24x0_i2c_init(struct i2c_adapter *adap, int
speed, int slaveadd)
int i;
if ((readl(i2c-iicstat) I2CSTAT_BSY) || GetI2CSDA() == 0) {
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
ulong old_gpecon = readl(gpio-gpecon);
#endif
#ifdef CONFIG_S3C2400
@@ -436,7 +436,7 @@ static void s3c24x0_i2c_init(struct i2c_adapter *adap, int
speed, int slaveadd)
/* bus still busy probably by (most) previously interrupted
transfer */
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
writel((readl(gpio-gpecon) ~0xF000) | 0x1000,
gpio-gpecon);
@@ -462,7 +462,7 @@ static void s3c24x0_i2c_init(struct i2c_adapter *adap, int
speed, int slaveadd)
udelay(1000);
/* restore pin functions */
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
writel(old_gpecon, gpio-gpecon);
#endif
#ifdef CONFIG_S3C2400
--
2.0.0.rc2
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[U-Boot] [PATCH 12/12] net: smc911x: Keep MAC programmed
Make sure to keep the MAC address programmed in the SMC911x ADDRH
and ADDRL registers. Linux can read those registers to determine
the MAC address on EEPROM-less configurations.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Joe Hershberger joe.hershber...@ni.com
Cc: Tom Rini tr...@ti.com
---
drivers/net/smc911x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index b097c1a..5959672 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -187,6 +187,7 @@ static int smc911x_send(struct eth_device *dev, void
*packet, int length)
static void smc911x_halt(struct eth_device *dev)
{
smc911x_reset(dev);
+ smc911x_handle_mac_address(dev);
}
static int smc911x_rx(struct eth_device *dev)
--
2.0.0.rc2
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[U-Boot] [PATCH 02/12] arm: s3c24xx: Fix incorrect CONFIG_SYS_S3C2410_NAND_HWECC name
The correct name of this symbol is CONFIG_S3C2410_NAND_HWECC , the _SYS is redundant. Signed-off-by: Marek Vasut ma...@denx.de Cc: Kyungmin Park kyungmin.p...@samsung.com Cc: Lukasz Majewski l.majew...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com Cc: Scott Wood scottw...@freescale.com Cc: Vladimir Zapolskiy v...@mleia.com --- include/configs/VCMA9.h| 2 +- include/configs/smdk2410.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index d40185e..a2ce7c5 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -201,7 +201,7 @@ /* NAND configuration */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_S3C2410 -#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_S3C2410_NAND_HWECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x4E00 #define CONFIG_S3C24XX_CUSTOM_NAND_TIMING diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index d4ae19f..0d0da28 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -172,7 +172,7 @@ */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_S3C2410 -#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_S3C2410_NAND_HWECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x4E00 #endif -- 2.0.0.rc2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/12] mmc: s3c: Add SD driver
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Pantelis Antoniou pa...@antoniou-consulting.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 6 +
drivers/mmc/Makefile| 1 +
drivers/mmc/s3c_sdi.c | 321
3 files changed, 328 insertions(+)
create mode 100644 drivers/mmc/s3c_sdi.c
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index b9f752d..2dae9fc 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -699,4 +699,10 @@ struct s3c24x0_sdi {
#endif
};
+#ifdef CONFIG_CMD_MMC
+#include mmc.h
+int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *),
+ int (*getwp)(struct mmc *));
+#endif
+
#endif /*__S3C24X0_H__*/
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 34febf5..a3d033b 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
diff --git a/drivers/mmc/s3c_sdi.c b/drivers/mmc/s3c_sdi.c
new file mode 100644
index 000..1b5b705
--- /dev/null
+++ b/drivers/mmc/s3c_sdi.c
@@ -0,0 +1,321 @@
+/*
+ * S3C24xx SD/MMC driver
+ *
+ * Based on OpenMoko S3C24xx driver by Harald Welte lafo...@openmoko.org
+ *
+ * Copyright (C) 2014 Marek Vasut ma...@denx.de
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include malloc.h
+#include mmc.h
+#include errno.h
+#include asm/arch/s3c24x0_cpu.h
+#include asm/io.h
+#include asm/unaligned.h
+
+#define S3C2440_SDICON_SDRESET (1 8)
+#define S3C2410_SDICON_FIFORESET (1 1)
+#define S3C2410_SDICON_CLOCKTYPE (1 0)
+
+#define S3C2410_SDICMDCON_LONGRSP (1 10)
+#define S3C2410_SDICMDCON_WAITRSP (1 9)
+#define S3C2410_SDICMDCON_CMDSTART (1 8)
+#define S3C2410_SDICMDCON_SENDERHOST (1 6)
+#define S3C2410_SDICMDCON_INDEX0x3f
+
+#define S3C2410_SDICMDSTAT_CRCFAIL (1 12)
+#define S3C2410_SDICMDSTAT_CMDSENT (1 11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 10)
+#define S3C2410_SDICMDSTAT_RSPFIN (1 9)
+
+#define S3C2440_SDIDCON_DS_WORD(2 22)
+#define S3C2410_SDIDCON_TXAFTERRESP(1 20)
+#define S3C2410_SDIDCON_RXAFTERCMD (1 19)
+#define S3C2410_SDIDCON_BLOCKMODE (1 17)
+#define S3C2410_SDIDCON_WIDEBUS(1 16)
+#define S3C2440_SDIDCON_DATSTART (1 14)
+#define S3C2410_SDIDCON_XFER_RXSTART (2 12)
+#define S3C2410_SDIDCON_XFER_TXSTART (3 12)
+#define S3C2410_SDIDCON_BLKNUM 0x7ff
+
+#define S3C2410_SDIDSTA_FIFOFAIL (1 8)
+#define S3C2410_SDIDSTA_CRCFAIL(1 7)
+#define S3C2410_SDIDSTA_RXCRCFAIL (1 6)
+#define S3C2410_SDIDSTA_DATATIMEOUT(1 5)
+#define S3C2410_SDIDSTA_XFERFINISH (1 4)
+
+#define S3C2410_SDIFSTA_TFHALF (1 11)
+#define S3C2410_SDIFSTA_COUNTMASK 0x7f
+
+/*
+ * WARNING: We only support one SD IP block.
+ * NOTE: It's not likely there will ever exist an S3C24xx with two,
+ * at least not in this universe all right.
+ */
+static int wide_bus;
+
+static int
+s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+ struct s3c24x0_sdi *sdi_regs = s3c24x0_get_base_sdi();
+ uint32_t sdiccon, sdicsta, sdidcon, sdidsta, sdidat, sdifsta;
+ uint32_t sdicsta_wait_bit = S3C2410_SDICMDSTAT_CMDSENT;
+ unsigned int timeout = 10;
+ int ret = 0, xfer_len, data_offset = 0;
+ const uint32_t sdidsta_err_mask = S3C2410_SDIDSTA_FIFOFAIL |
+ S3C2410_SDIDSTA_CRCFAIL | S3C2410_SDIDSTA_RXCRCFAIL |
+ S3C2410_SDIDSTA_DATATIMEOUT;
+
+
+ writel(0x, sdi_regs-sdicsta);
+ writel(0x, sdi_regs-sdidsta);
+ writel(0x, sdi_regs-sdifsta);
+
+ /* Set up data transfer (if applicable). */
+ if (data) {
+ writel(data-blocksize, sdi_regs-sdibsize);
+
+ sdidcon = data-blocks S3C2410_SDIDCON_BLKNUM;
+ sdidcon |= S3C2410_SDIDCON_BLOCKMODE;
+#if defined(CONFIG_S3C2440)
+ sdidcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
+#endif
+ if (wide_bus)
+ sdidcon |= S3C2410_SDIDCON_WIDEBUS;
+
+ if (data-flags MMC_DATA_READ) {
+ sdidcon |= S3C2410_SDIDCON_RXAFTERCMD;
[U-Boot] [PATCH 10/12] arm: s3c: Unify the S3C24xx SDI structure
Unify the register structure so they can be easily used across all
of S3C24xx lineup.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Pantelis Antoniou pa...@antoniou-consulting.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
arch/arm/include/asm/arch-s3c24x0/s3c2410.h | 4 ++--
arch/arm/include/asm/arch-s3c24x0/s3c2440.h | 4 ++--
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 13 ++---
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
index 1a925fb..8773ce3 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
@@ -139,9 +139,9 @@ static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
-static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
+static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void)
{
- return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
+ return (struct s3c24x0_sdi *)S3C2410_SDI_BASE;
}
#endif /*__S3C2410_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
index bf21bb9..7a525f2 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -137,9 +137,9 @@ static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
-static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
+static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void)
{
- return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
+ return (struct s3c24x0_sdi *)S3C2440_SDI_BASE;
}
#endif /*__S3C2440_H__*/
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index 0621e16..b9f752d 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -674,7 +674,7 @@ struct s3c2400_mmc {
/* SD INTERFACE (see S3C2410 manual chapter 19) */
-struct s3c2410_sdi {
+struct s3c24x0_sdi {
u32 sdicon;
u32 sdipre;
u32 sdicarg;
@@ -690,14 +690,13 @@ struct s3c2410_sdi {
u32 sdidcnt;
u32 sdidsta;
u32 sdifsta;
-#ifdef __BIG_ENDIAN
- u8 res[3];
- u8 sdidat;
+#ifdef CONFIG_S3C2410
+ u32 sdidat;
+ u32 sdiimsk;
#else
- u8 sdidat;
- u8 res[3];
-#endif
u32 sdiimsk;
+ u32 sdidat;
+#endif
};
#endif /*__S3C24X0_H__*/
--
2.0.0.rc2
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/12] mtd: nand: s3c: Fix data type width in debug()
Printing u32 with %02x is just a bad idea, fix it.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Scott Wood scottw...@freescale.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
drivers/mtd/nand/s3c2410_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index db87d07..b607cc5 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -43,7 +43,7 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
struct nand_chip *chip = mtd-priv;
struct s3c2410_nand *nand = s3c2410_get_base_nand();
- debug(hwcontrol(): 0x%02x 0x%02x\n, cmd, ctrl);
+ debug(hwcontrol(): 0x%08x 0x%08x\n, cmd, ctrl);
if (ctrl NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong)nand;
--
2.0.0.rc2
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/12] mtd: nand: s3c: Unify the register definition and naming
Merge struct s3c2410_nand and struct s3c2440_nand into one unified
struct s3c24x0_nand. While at it, fix up and rename the functions
to retrieve the NAND base address and fix up the s3c NAND driver to
reflect this change.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Scott Wood scottw...@freescale.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
arch/arm/include/asm/arch-s3c24x0/s3c2410.h | 4 +--
arch/arm/include/asm/arch-s3c24x0/s3c2440.h | 4 +--
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 31 ---
drivers/mtd/nand/s3c2410_nand.c | 38 ++---
4 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
index 01fe0f2..1a925fb 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h
@@ -83,9 +83,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
-static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
+static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void)
{
- return (struct s3c2410_nand *)S3C2410_NAND_BASE;
+ return (struct s3c24x0_nand *)S3C2410_NAND_BASE;
}
static inline struct s3c24x0_uart
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
index 15a7cb4..bf21bb9 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h
@@ -81,9 +81,9 @@ static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
-static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
+static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void)
{
- return (struct s3c2440_nand *)S3C2440_NAND_BASE;
+ return (struct s3c24x0_nand *)S3C2440_NAND_BASE;
}
static inline struct s3c24x0_uart
diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index 86d720c..0621e16 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -135,34 +135,33 @@ struct s3c24x0_lcd {
};
-#ifdef CONFIG_S3C2410
-/* NAND FLASH (see S3C2410 manual chapter 6) */
-struct s3c2410_nand {
- u32 nfconf;
- u32 nfcmd;
- u32 nfaddr;
- u32 nfdata;
- u32 nfstat;
- u32 nfecc;
-};
-#endif
-#ifdef CONFIG_S3C2440
-/* NAND FLASH (see S3C2440 manual chapter 6) */
-struct s3c2440_nand {
+/* NAND FLASH (see manual chapter 6) */
+struct s3c24x0_nand {
u32 nfconf;
+#ifndef CONFIG_S3C2410
u32 nfcont;
+#endif
u32 nfcmd;
u32 nfaddr;
u32 nfdata;
+#ifndef CONFIG_S3C2410
u32 nfeccd0;
u32 nfeccd1;
u32 nfeccd;
+#endif
u32 nfstat;
+#ifdef CONFIG_S3C2410
+ u32 nfecc;
+#else
u32 nfstat0;
u32 nfstat1;
-};
+ u32 nfmecc0;
+ u32 nfmecc1;
+ u32 nfsecc;
+ u32 nfsblk;
+ u32 nfeblk;
#endif
-
+};
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index b607cc5..f638801 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -38,10 +38,10 @@ static void nand_read_buf(struct mtd_info *mtd, u_char
*buf, int len)
}
#endif
-static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd-priv;
- struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
debug(hwcontrol(): 0x%08x 0x%08x\n, cmd, ctrl);
@@ -67,35 +67,35 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int
cmd, unsigned int ctrl)
writeb(cmd, chip-IO_ADDR_W);
}
-static int s3c2410_dev_ready(struct mtd_info *mtd)
+static int s3c24x0_dev_ready(struct mtd_info *mtd)
{
- struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
debug(dev_ready\n);
return readl(nand-nfstat) 0x01;
}
#ifdef CONFIG_S3C2410_NAND_HWECC
-void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
- struct s3c2410_nand *nand = s3c2410_get_base_nand();
- debug(s3c2410_nand_enable_hwecc(%p, %d)\n, mtd, mode);
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+ debug(s3c24x0_nand_enable_hwecc(%p, %d)\n, mtd, mode);
writel(readl(nand-nfconf) | S3C2410_NFCONF_INITECC, nand-nfconf);
[U-Boot] [PATCH 05/12] mtd: nand: s3c: Add S3C2440 specifics
Add support for S3C2440 into the NAND driver by filling in the
S3C2440 bits and differences.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Scott Wood scottw...@freescale.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
drivers/mtd/nand/s3c2410_nand.c | 55 -
1 file changed, 43 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index f638801..a358be4 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -12,13 +12,22 @@
#include asm/io.h
#define S3C2410_NFCONF_EN (115)
+#define S3C2440_NFCONT_EN (10)
#define S3C2410_NFCONF_512BYTE (114)
#define S3C2410_NFCONF_4STEP (113)
#define S3C2410_NFCONF_INITECC (112)
+#define S3C2440_NFCONT_INITECC (14)
#define S3C2410_NFCONF_nFCE(111)
+#define S3C2440_NFCONT_nFCE(11)
+#ifdef CONFIG_S3C2410
#define S3C2410_NFCONF_TACLS(x)((x)8)
#define S3C2410_NFCONF_TWRPH0(x) ((x)4)
#define S3C2410_NFCONF_TWRPH1(x) ((x)0)
+#else /* S3C2412, S3C2440 */
+#define S3C2410_NFCONF_TACLS(x)((x)12)
+#define S3C2410_NFCONF_TWRPH0(x) ((x)8)
+#define S3C2410_NFCONF_TWRPH1(x) ((x)4)
+#endif
#define S3C2410_ADDR_NALE 4
#define S3C2410_ADDR_NCLE 8
@@ -42,25 +51,30 @@ static void s3c24x0_hwcontrol(struct mtd_info *mtd, int
cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd-priv;
struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+ uint32_t sel_reg, sel_bit;
debug(hwcontrol(): 0x%08x 0x%08x\n, cmd, ctrl);
if (ctrl NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong)nand;
+ chip-IO_ADDR_W = nand-nfconf;
if (!(ctrl NAND_CLE))
- IO_ADDR_W |= S3C2410_ADDR_NCLE;
+ chip-IO_ADDR_W = nand-nfaddr;
if (!(ctrl NAND_ALE))
- IO_ADDR_W |= S3C2410_ADDR_NALE;
+ chip-IO_ADDR_W = nand-nfcmd;
- chip-IO_ADDR_W = (void *)IO_ADDR_W;
+#ifdef CONFIG_S3C2410
+ sel_reg = (uint32_t)nand-nfconf;
+ sel_bit = S3C2410_NFCONF_nFCE;
+#else
+ sel_reg = (uint32_t)nand-nfcont;
+ sel_bit = S3C2440_NFCONT_nFCE;
+#endif
if (ctrl NAND_NCE)
- writel(readl(nand-nfconf) ~S3C2410_NFCONF_nFCE,
- nand-nfconf);
+ clrbits_le32(sel_reg, sel_bit);
else
- writel(readl(nand-nfconf) | S3C2410_NFCONF_nFCE,
- nand-nfconf);
+ setbits_le32(sel_reg, sel_bit);
}
if (cmd != NAND_CMD_NONE)
@@ -79,16 +93,27 @@ void s3c24x0_nand_enable_hwecc(struct mtd_info *mtd, int
mode)
{
struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
debug(s3c24x0_nand_enable_hwecc(%p, %d)\n, mtd, mode);
- writel(readl(nand-nfconf) | S3C2410_NFCONF_INITECC, nand-nfconf);
+#ifdef CONFIG_S3C2410
+ setbits_le32(nand-nfconf, S3C2410_NFCONF_INITECC);
+#else
+ setbits_le32(nand-nfcont, S3C2440_NFCONT_INITECC);
+#endif
}
static int s3c24x0_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+#ifdef CONFIG_S3C2410
ecc_code[0] = readb(nand-nfecc);
ecc_code[1] = readb(nand-nfecc + 1);
ecc_code[2] = readb(nand-nfecc + 2);
+#else
+ uint32_t ecc = readl(nand-nfmecc0);
+ ecc_code[0] = ecc;
+ ecc_code[1] = ecc 8;
+ ecc_code[2] = ecc 16;
+#endif
debug(s3c24x0_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n,
mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
@@ -110,14 +135,14 @@ static int s3c24x0_nand_correct_data(struct mtd_info
*mtd, u_char *dat,
int board_nand_init(struct nand_chip *nand)
{
- u_int32_t cfg;
+ uint32_t cfg = 0;
u_int8_t tacls, twrph0, twrph1;
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_nand *nand_reg = s3c24x0_get_base_nand();
debug(board_nand_init()\n);
- writel(readl(clk_power-clkcon) | (1 4), clk_power-clkcon);
+ setbits_le32(clk_power-clkcon, 1 4);
/* initialize hardware */
#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
@@ -130,12 +155,18 @@ int board_nand_init(struct nand_chip *nand)
twrph1 = 8;
#endif
- cfg = S3C2410_NFCONF_EN;
+#ifdef CONFIG_S3C2410
+ cfg |= S3C2410_NFCONF_EN;
+#endif
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
writel(cfg, nand_reg-nfconf);
+#ifndef CONFIG_S3C2410
+
[U-Boot] [PATCH 07/12] mtd: nand: s3c: Add missing correction and select_chip functions
Implant a missing ECC correction implementation and select_chip
implementation from Linux.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Scott Wood scottw...@freescale.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
drivers/mtd/nand/s3c2410_nand.c | 89 ++---
1 file changed, 84 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index c71f874..511e85b 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -157,16 +157,93 @@ static int s3c24x0_nand_calculate_ecc(struct mtd_info
*mtd, const u_char *dat,
static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
- if (read_ecc[0] == calc_ecc[0]
- read_ecc[1] == calc_ecc[1]
- read_ecc[2] == calc_ecc[2])
+ unsigned int diff0, diff1, diff2;
+ unsigned int bit, byte;
+
+ debug(%s(%p,%p,%p,%p)\n, __func__, mtd, dat, read_ecc, calc_ecc);
+
+ diff0 = read_ecc[0] ^ calc_ecc[0];
+ diff1 = read_ecc[1] ^ calc_ecc[1];
+ diff2 = read_ecc[2] ^ calc_ecc[2];
+
+ debug(%s: rd %*phN calc %*phN diff %02x%02x%02x\n,
+ __func__, 3, read_ecc, 3, calc_ecc,
+ diff0, diff1, diff2);
+
+ if (diff0 == 0 diff1 == 0 diff2 == 0)
+ return 0; /* ECC is ok */
+
+ /* sometimes people do not think about using the ECC, so check
+* to see if we have an 0xff,0xff,0xff read ECC and then ignore
+* the error, on the assumption that this is an un-eccd page.
+*/
+ if (read_ecc[0] == 0xff read_ecc[1] == 0xff read_ecc[2] == 0xff
+ /* info-platform-ignore_unset_ecc*/)
return 0;
- printf(s3c24x0_nand_correct_data: not implemented\n);
+ /* Can we correct this ECC (ie, one row and column change).
+* Note, this is similar to the 256 error code on smartmedia */
+
+ if (((diff0 ^ (diff0 1)) 0x55) == 0x55
+ ((diff1 ^ (diff1 1)) 0x55) == 0x55
+ ((diff2 ^ (diff2 1)) 0x55) == 0x55) {
+ /* calculate the bit position of the error */
+
+ bit = ((diff2 3) 1) |
+ ((diff2 4) 2) |
+ ((diff2 5) 4);
+
+ /* calculate the byte position of the error */
+
+ byte = ((diff2 7) 0x100) |
+ ((diff1 0) 0x80) |
+ ((diff1 1) 0x40) |
+ ((diff1 2) 0x20) |
+ ((diff1 3) 0x10) |
+ ((diff0 4) 0x08) |
+ ((diff0 3) 0x04) |
+ ((diff0 2) 0x02) |
+ ((diff0 1) 0x01);
+
+ debug(correcting error bit %d, byte %d\n, bit, byte);
+
+ dat[byte] ^= (1 bit);
+ return 1;
+ }
+
+ /* if there is only one bit difference in the ECC, then
+* one of only a row or column parity has changed, which
+* means the error is most probably in the ECC itself */
+
+ diff0 |= (diff1 8);
+ diff0 |= (diff2 16);
+
+ if ((diff0 ~(1fls(diff0))) == 0)
+ return 1;
+
return -1;
}
#endif
+static void s3c24x0_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+ uint32_t sel_reg, sel_bit;
+
+#ifdef CONFIG_S3C2410
+ sel_reg = (uint32_t)nand-nfconf;
+ sel_bit = S3C2410_NFCONF_nFCE;
+#else
+ sel_reg = (uint32_t)nand-nfcont;
+ sel_bit = S3C2440_NFCONT_nFCE;
+#endif
+
+ if (chip == -1)
+ setbits_le32(sel_reg, sel_bit);
+ else
+ clrbits_le32(sel_reg, sel_bit);
+}
+
int board_nand_init(struct nand_chip *nand)
{
uint32_t cfg = 0;
@@ -205,7 +282,7 @@ int board_nand_init(struct nand_chip *nand)
nand-IO_ADDR_R = (void *)nand_reg-nfdata;
nand-IO_ADDR_W = (void *)nand_reg-nfdata;
- nand-select_chip = NULL;
+ nand-select_chip = s3c24x0_nand_select_chip;
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
@@ -221,6 +298,8 @@ int board_nand_init(struct nand_chip *nand)
nand-dev_ready = s3c24x0_dev_ready;
+ nand-chip_delay = 50;
+
#ifdef CONFIG_S3C2410_NAND_HWECC
nand-ecc.hwctl = s3c24x0_nand_enable_hwecc;
nand-ecc.calculate = s3c24x0_nand_calculate_ecc;
--
2.0.0.rc2
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[U-Boot] [PATCH 09/12] gpio: s3c: Fix the GPIO driver
The GPIO driver didn't correctly compute the bank offset
from the GPIO number and caused random writes into the
GPIO block address space. Fix the driver so it actually
does the writes correctly. While at it, make use of the
clrsetbits_le32() mechanisms.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
drivers/gpio/s3c2440_gpio.c | 75 +
1 file changed, 42 insertions(+), 33 deletions(-)
diff --git a/drivers/gpio/s3c2440_gpio.c b/drivers/gpio/s3c2440_gpio.c
index e1e2d3f..d6c7eeb 100644
--- a/drivers/gpio/s3c2440_gpio.c
+++ b/drivers/gpio/s3c2440_gpio.c
@@ -8,53 +8,50 @@
#include asm/arch/s3c2440.h
#include asm/gpio.h
#include asm/io.h
+#include errno.h
#define GPIO_INPUT 0x0
#define GPIO_OUTPUT 0x1
-/* 0x4 means that we want DAT and not CON register */
-#define GPIO_PORT(x) x) 5) 0x3) + 0x4)
-#define GPIO_BIT(x)((x) 0x3f)
+#define S3C_GPIO_CON 0x0
+#define S3C_GPIO_DAT 0x4
-/*
- * It's how we calculate the full port address
- * We have to get the number of the port + 1 (Port A is at 0x5601 ...)
- * We move it at the second digit, and finally we add 0x4 because we want
- * to modify GPIO DAT and not CON
- */
-#define GPIO_FULLPORT(x) (S3C24X0_GPIO_BASE | ((GPIO_PORT(gpio) + 1) 1))
+static uint32_t s3c_gpio_get_bank_addr(unsigned gpio)
+{
+ /* There is up to 16 pins per bank, one bank is 0x10 big. */
+ uint32_t addr = gpio ~0xf;
+
+ if (addr = 0x80 addr != 0xd0) { /* Wrong GPIO bank. */
+ printf(Invalid GPIO bank (bank %02x)\n, addr);
+ return 0x;
+ }
+
+ return addr | S3C24X0_GPIO_BASE;
+}
int gpio_set_value(unsigned gpio, int value)
{
- unsigned l = readl(GPIO_FULLPORT(gpio));
- unsigned bit;
- unsigned port = GPIO_FULLPORT(gpio);
-
- /*
-* All GPIO Port have a configuration on
-* 2 bits excepted the first GPIO (A) which
-* have only 1 bit of configuration.
-*/
- if (!GPIO_PORT(gpio))
- bit = (0x1 GPIO_BIT(gpio));
- else
- bit = (0x3 GPIO_BIT(gpio));
+ uint32_t addr = s3c_gpio_get_bank_addr(gpio);
+
+ if (addr == 0x)
+ return -EINVAL;
if (value)
- l |= bit;
+ setbits_le32(addr | S3C_GPIO_DAT, 1 (gpio 0xf));
else
- l = ~bit;
+ clrbits_le32(addr | S3C_GPIO_DAT, 1 (gpio 0xf));
- return writel(l, port);
+ return 0;
}
int gpio_get_value(unsigned gpio)
{
- unsigned l = readl(GPIO_FULLPORT(gpio));
+ uint32_t addr = s3c_gpio_get_bank_addr(gpio);
+
+ if (addr == 0x)
+ return -EINVAL;
- if (GPIO_PORT(gpio) == 0) /* PORT A */
- return (l GPIO_BIT(gpio)) 0x1;
- return (l GPIO_BIT(gpio)) 0x3;
+ return !!(readl(addr | S3C_GPIO_DAT) (1 (gpio 0xf)));
}
int gpio_request(unsigned gpio, const char *label)
@@ -67,13 +64,25 @@ int gpio_free(unsigned gpio)
return 0;
}
+static int s3c_gpio_direction(unsigned gpio, uint8_t dir)
+{
+ uint32_t addr = s3c_gpio_get_bank_addr(gpio);
+ const uint32_t mask = 0x3 ((gpio 0xf) 1);
+ const uint32_t dirm = dir ((gpio 0xf) 1);
+
+ if (addr == 0x)
+ return -EINVAL;
+
+ clrsetbits_le32(addr | S3C_GPIO_CON, mask, dirm);
+ return 0;
+}
+
int gpio_direction_input(unsigned gpio)
{
- return writel(GPIO_INPUT GPIO_BIT(gpio), GPIO_FULLPORT(gpio));
+ return s3c_gpio_direction(gpio, GPIO_INPUT);
}
int gpio_direction_output(unsigned gpio, int value)
{
- writel(GPIO_OUTPUT GPIO_BIT(gpio), GPIO_FULLPORT(gpio));
- return gpio_set_value(gpio, value);
+ return s3c_gpio_direction(gpio, GPIO_OUTPUT);
}
--
2.0.0.rc2
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[U-Boot] [PATCH 06/12] mtd: nand: s3c: Add S3C2440 buffer reading
Add buffer reading code, should make the IO a little faster.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Scott Wood scottw...@freescale.com
Cc: Vladimir Zapolskiy v...@mleia.com
---
drivers/mtd/nand/s3c2410_nand.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index a358be4..c71f874 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -10,6 +10,7 @@
#include nand.h
#include asm/arch/s3c24x0_cpu.h
#include asm/io.h
+#include asm/unaligned.h
#define S3C2410_NFCONF_EN (115)
#define S3C2440_NFCONT_EN (10)
@@ -45,6 +46,39 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf,
int len)
for (i = 0; i len; i++)
buf[i] = readb(this-IO_ADDR_R);
}
+#elif !defined(CONFIG_S3C2410)
+static void s3c2440_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+ uint32_t data;
+
+ while (len = 4) {
+ data = readl(nand-nfdata);
+ put_unaligned_le32(data, buf);
+ buf += 4;
+ len -= 4;
+ }
+
+ for (; len 3; len--)
+ *buf++ = readb(nand-nfdata);
+}
+
+static void s3c2440_write_buf(struct mtd_info *mtd, const u_char *buf,
+ int len)
+{
+ struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
+ uint32_t data;
+
+ while (len = 4) {
+ data = get_unaligned_le32(buf);
+ writel(data, nand-nfdata);
+ buf += 4;
+ len -= 4;
+ }
+
+ for (; len 3; len--, buf++)
+ writeb(*buf, nand-nfdata);
+}
#endif
static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -177,6 +211,9 @@ int board_nand_init(struct nand_chip *nand)
/* read_byte and write_byte are default */
#ifdef CONFIG_NAND_SPL
nand-read_buf = nand_read_buf;
+#elif !defined(CONFIG_S3C2410)
+ nand-read_buf = s3c2440_read_buf;
+ nand-write_buf = s3c2440_write_buf;
#endif
/* hwcontrol always must be implemented */
--
2.0.0.rc2
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[U-Boot] [PATCH 2/2] m68k: define __kernel_size_t as unsinged int again
Commit ddc94378d changed the definition of __kernel_size_t from unsigned int to unsigned long. It is true that it fixed warnings on some crosstools but it increased warnings on the others. The problem is that we cannot see consistency in terms of the typedef of __kernel_size_t on M68K architecture. However, I'd like to suggest to have __kernel_size_t to be unsigned int again. Rationale: [1] Linux Kernel defines __kernel_size_t on M68K as unsigned int. Let's stick to the Linux's way. [2] We want to build boards with popular pre-built toolchains, not the one locally-built by indivisuals. I think m68-linux-gcc which can be downloaded from www.kernel.org is the candidate for our _recommended_ toolchains. With this patch, all the m68k boards can be built without any warnings. Give it a try with the following crosstools: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ x86_64-gcc-4.6.3-nolibc_m68k-linux.tar.xz or https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ x86_64-gcc-4.9.0-nolibc_m68k-linux.tar.xz (The latter is newer.) Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Simon Glass s...@chromium.org Cc: Jason Jin jason@freescale.com --- arch/m68k/include/asm/posix_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h index b97d267..4fbc040 100644 --- a/arch/m68k/include/asm/posix_types.h +++ b/arch/m68k/include/asm/posix_types.h @@ -15,7 +15,7 @@ typedef long __kernel_off_t; typedef int__kernel_pid_t; typedef unsigned int __kernel_uid_t; typedef unsigned int __kernel_gid_t; -typedef unsigned long __kernel_size_t; +typedef unsigned int __kernel_size_t; typedef int__kernel_ssize_t; typedef long __kernel_ptrdiff_t; typedef long __kernel_time_t; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] m68k: fix an undefined behavior warning of M5253DEMO board
The latest GCC is so clever that it reports more warnings
than old ones did:
--8--
board/freescale/m5253demo/flash.c: In function 'flash_get_offsets':
board/freescale/m5253demo/flash.c:65:23: warning: iteration 2047u
invokes undefined behavior [-Waggressive-loop-optimizations]
info-start[k + 1] = info-start[k] + CONFIG_SYS_SST_SECTSZ;
^
board/freescale/m5253demo/flash.c:64:3: note: containing loop
for (k = 0, j = 0; j CONFIG_SYS_SST_SECT; j++, k++) {
^
--8--
The cause of the warning is like this:
The for statement iterates 2048 times in flash_get_offsets() func.
(Notice CONFIG_SYS_SST_SECT is defined as 2048)
The last iteration does
info-start[2048] = info-start[2047] + CONFIG_SYS_SST_SECTSZ;
causing an undefined behavior.
(Please note the array size of info-start is 2048.
CONFIG_SYS_MAX_FLASH_SECT is defined as 2048 for this board.)
This commit fixes that so as not to overrun the info-start array.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Cc: Jason Jin jason@freescale.com
---
board/freescale/m5253demo/flash.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/board/freescale/m5253demo/flash.c
b/board/freescale/m5253demo/flash.c
index 16bba59..071701d 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -56,14 +56,16 @@ ulong flash_init(void)
int flash_get_offsets(ulong base, flash_info_t * info)
{
- int j, k;
+ int i;
if ((info-flash_id FLASH_VENDMASK) == FLASH_MAN_SST) {
info-start[0] = base;
- for (k = 0, j = 0; j CONFIG_SYS_SST_SECT; j++, k++) {
- info-start[k + 1] = info-start[k] +
CONFIG_SYS_SST_SECTSZ;
- info-protect[k] = 0;
+ info-protect[0] = 0;
+ for (i = 1; i CONFIG_SYS_SST_SECT; i++) {
+ info-start[i] = info-start[i - 1]
+ + CONFIG_SYS_SST_SECTSZ;
+ info-protect[i] = 0;
}
}
--
1.9.1
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[U-Boot] [PATCH 0/2] Now all the M68K boards can be cleanly built
This series consists of two fixes. With this series and the crosstools distributed on www.kernel.org, M68K boards can be built without any warnings. You can download it from: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ x86_64-gcc-4.9.0-nolibc_m68k-linux.tar.xz My build log is as follows: $ m68k-linux-gcc --version m68k-linux-gcc (GCC) 4.9.0 Copyright (C) 2014 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ CROSS_COMPILE=m68k-linux- ./MAKEALL -a m68k Configuring for M52277EVB - Board: M52277EVB, Options: SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x textdata bss dec hex filename 115847 115424096 131485 2019d ./u-boot Configuring for M52277EVB_stmicro - Board: M52277EVB, Options: CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E0 textdata bss dec hex filename 115474 115424100 131116 2002c ./u-boot Configuring for M5235EVB - Board: M5235EVB, Options: SYS_TEXT_BASE=0xFFE0 textdata bss dec hex filename 132258 12240 21132 165630 286fe ./u-boot Configuring for M5235EVB_Flash32 - Board: M5235EVB, Options: NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC0 textdata bss dec hex filename 132258 12240 21132 165630 286fe ./u-boot Configuring for cobra5272 board... textdata bss dec hex filename 1121669360 19880 141406 2285e ./u-boot Configuring for eb_cpu5282 - Board: eb_cpu5282, Options: SYS_TEXT_BASE=0xFF00,SYS_MONITOR_BASE=0xFF000400 textdata bss dec hex filename 117802 12608 59632 190042 2e65a ./u-boot Configuring for eb_cpu5282_internal - Board: eb_cpu5282, Options: SYS_TEXT_BASE=0xF000,SYS_MONITOR_BASE=0xF418 textdata bss dec hex filename 117871 12612 59632 190115 2e6a3 ./u-boot Configuring for TASREG board... textdata bss dec hex filename 173998 102904784 189072 2e290 ./u-boot Configuring for M5208EVBE board... textdata bss dec hex filename 125563 11252 22852 159667 26fb3 ./u-boot Configuring for M5249EVB board... textdata bss dec hex filename 10790586544224 120783 1d7cf ./u-boot Configuring for M5253DEMO board... textdata bss dec hex filename 153476 11348 222476 387300 5e8e4 ./u-boot Configuring for M5272C3 board... textdata bss dec hex filename 126385 10676 20588 157649 267d1 ./u-boot Configuring for M5275EVB board... textdata bss dec hex filename 134047 12284 21016 167347 28db3 ./u-boot Configuring for M5282EVB board... textdata bss dec hex filename 124852 10544 21100 156496 26350 ./u-boot Configuring for astro_mcf5373l board... textdata bss dec hex filename 130047 12516 10304 152867 25523 ./u-boot Configuring for M53017EVB board... textdata bss dec hex filename 151345 11564 22268 185177 2d359 ./u-boot Configuring for M5329AFEE - Board: M5329EVB, Options: NANDFLASH_SIZE=0 textdata bss dec hex filename 176789 28016 22896 227701 37975 ./u-boot Configuring for M5329BFEE - Board: M5329EVB, Options: NANDFLASH_SIZE=16 textdata bss dec hex filename 176793 28016 22896 227705 37979 ./u-boot Configuring for M5373EVB - Board: M5373EVB, Options: NANDFLASH_SIZE=16 textdata bss dec hex filename 176811 28016 22896 227723 3798b ./u-boot Configuring for M54418TWR - Board: M54418TWR, Options: CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E0,SYS_INPUT_CLKSRC=5000 textdata bss dec hex filename 110939 10362 11620 132921 20739 ./u-boot Configuring for M54418TWR_nand_mii - Board: M54418TWR, Options: SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E0,SYS_INPUT_CLKSRC=2500 textdata bss dec hex filename 109786 10226 11620 131632 20230 ./u-boot Configuring for M54418TWR_nand_rmii - Board: M54418TWR, Options: SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E0,SYS_INPUT_CLKSRC=5000 textdata bss dec hex filename 109786 10226 11620 131632 20230 ./u-boot Configuring for M54418TWR_nand_rmii_lowfreq - Board: M54418TWR, Options: SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E0,SYS_INPUT_CLKSRC=5000 textdata bss dec hex filename 109830 10226 11620 131676 2025c ./u-boot Configuring for M54418TWR_serial_mii - Board: M54418TWR, Options: CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E0,SYS_INPUT_CLKSRC=2500 textdata bss dec hex filename 110939 10362 11620 132921 20739 ./u-boot Configuring for M54418TWR_serial_rmii - Board: M54418TWR, Options: CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E0,SYS_INPUT_CLKSRC=5000 textdata
[U-Boot] [PATCH v2 2/3] MAKEALL: make sure to invoke GNU Make
Since the command name 'make' may not be GNU Make on some platforms
such as FreeBSD, MAKEALL should call scripts/show-gnu-make to get
the command name for GNU MAKE (and error out if it is not found).
The GNU Make should be searched after parsing options because we want
to allow MAKEALL -h even if GNU Make is missing on the system.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v2:
- Check GNU Make only once at startup.
It seems more reasonable because MAKEALL generally invokes
make over and over again.
MAKEALL | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 37ef71e..9510982 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -162,6 +162,12 @@ while true ; do
echo Internal error! 2 ; exit 1 ;;
esac
done
+
+GNU_MAKE=$(scripts/show-gnu-make) || {
+ echo GNU Make not found 2
+ exit 1
+}
+
# echo Remaining arguments:
# for arg do echo '-- '\`$arg' ; done
@@ -633,11 +639,11 @@ build_target() {
target_arch=$(get_target_arch ${target})
eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr
'[:lower:]' '[:upper:]'`
if [ ${cross_toolchain} ] ; then
- MAKE=make CROSS_COMPILE=${cross_toolchain}
+ MAKE=$GNU_MAKE CROSS_COMPILE=${cross_toolchain}
elif [ ${CROSS_COMPILE} ] ; then
- MAKE=make CROSS_COMPILE=${CROSS_COMPILE}
+ MAKE=$GNU_MAKE CROSS_COMPILE=${CROSS_COMPILE}
else
- MAKE=make
+ MAKE=$GNU_MAKE
fi
if [ ${output_dir} != . ] ; then
--
1.9.1
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[U-Boot] [PATCH v2 3/3] buildman: make sure to invoke GNU Make
Since the command name 'make' may not be GNU Make on some platforms such as FreeBSD, buildman should call scripts/show-gnu-make to get the command name for GNU MAKE (and error out if it is not found). Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Acked-by: Simon Glass s...@chromium.org Tested-by: Jeroen Hofstee jer...@myspectrum.nl --- Changes in v2: - Check GNU Make only once at startup. It seems more reasonable because buildman generally invokes make over and over again. tools/buildman/builder.py | 6 -- tools/buildman/control.py | 9 - 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 4a2d753..4987fc9 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -546,7 +546,7 @@ class Builder: self.func_sizes = func_sizes def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs, - checkout=True, show_unknown=True, step=1): + gnu_make='make', checkout=True, show_unknown=True, step=1): Create a new Builder object Args: @@ -555,6 +555,7 @@ class Builder: git_dir: Git directory containing source repository num_threads: Number of builder threads to run num_jobs: Number of jobs to run at once (passed to make as -j) +gnu_make: the command name of GNU Make. checkout: True to check out source, False to skip that step. This is used for testing. show_unknown: Show unknown boards (those not built) in summary @@ -566,6 +567,7 @@ class Builder: self.threads = [] self.active = True self.do_make = self.Make +self.gnu_make = gnu_make self.checkout = checkout self.num_threads = num_threads self.num_jobs = num_jobs @@ -667,7 +669,7 @@ class Builder: args: Arguments to pass to make kwargs: Arguments to pass to command.RunPipe() -cmd = ['make'] + list(args) +cmd = [self.gnu_make] + list(args) result = command.RunPipe([cmd], capture=True, capture_stderr=True, cwd=cwd, raise_on_error=False, **kwargs) return result diff --git a/tools/buildman/control.py b/tools/buildman/control.py index d2f4102..fd6f197 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -14,6 +14,7 @@ import gitutil import patchstream import terminal import toolchain +import command def GetPlural(count): Returns a plural 's' if count is not 1 @@ -144,10 +145,16 @@ def DoBuildman(options, args): if not options.step: options.step = len(series.commits) - 1 +gnu_make = command.Output(os.path.join(options.git, + 'scripts/show-gnu-make')).rstrip() +if not gnu_make: +print sys.stderr, 'GNU Make not found' +sys.exit(1) + # Create a new builder with the selected options output_dir = os.path.join(options.output_dir, options.branch) builder = Builder(toolchains, output_dir, options.git_dir, -options.threads, options.jobs, checkout=True, +options.threads, options.jobs, gnu_make=gnu_make, checkout=True, show_unknown=options.show_unknown, step=options.step) builder.force_config_on_failure = not options.quick -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] scripts: add scripts/show-gnu-make to get GNU Make command name
U-Boot is expected to be built on various platforms. We should keep in mind that the command 'make' is not always GNU Make, while all the makefiles are written for GNU Make. For example, on Linux, people generally do: make board_config; make But FreeBSD folks do gmake board_config; gmake (The command 'make' on FreeBSD is BSD Make, not GNU Make) It is not a good idea to hard-code the command name 'make' in MAKEALL or buildman. They should call this helper script and get the command name for GNU Make. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Changes in v2: - Use dashes for filename - Show the command name instead of invoking make. It allows us to check the command name once at startup (and error out if no GNU Make is found.) scripts/show-gnu-make | 25 + 1 file changed, 25 insertions(+) create mode 100755 scripts/show-gnu-make diff --git a/scripts/show-gnu-make b/scripts/show-gnu-make new file mode 100755 index 000..26271b5 --- /dev/null +++ b/scripts/show-gnu-make @@ -0,0 +1,25 @@ +#!/bin/sh +# +# Show the command name for GNU Make +# +# U-Boot is supposed to be built on various platforms. +# One problem is that the command 'make' is not always GNU Make. +# (For ex. the command name for GNU Make on FreeBSD is usually 'gmake'.) +# It is not a good idea to hard-code the command name in scripts +# where where GNU Make is expected. +# Call this helper script to get the command name for GNU Make. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +gnu_make= + +for m in make gmake +do + if $m --version 2/dev/null | grep -q GNU; then + echo $m + exit 0 + fi +done + +exit 1 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/3] Do not hard-code the command name 'make' in higher-level tools
Masahiro Yamada (3): scripts: add scripts/show-gnu-make to get GNU Make command name MAKEALL: make sure to invoke GNU Make buildman: make sure to invoke GNU Make MAKEALL | 12 +--- scripts/show-gnu-make | 25 + tools/buildman/builder.py | 6 -- tools/buildman/control.py | 9 - 4 files changed, 46 insertions(+), 6 deletions(-) create mode 100755 scripts/show-gnu-make -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] A way to change the status of the whole series on Patchwork ?
Hi Brian, (Sorry for my late reply.) On Wed, 16 Jul 2014 19:49:09 -0700 Brian Norris computersforpe...@gmail.com wrote: On Thu, Jul 17, 2014 at 11:19:42AM +0900, Masahiro Yamada wrote: When I change the status of patches, I always do it one by one. But it is painful if the series consists of a bunch of patches. Does Patchwork have any good way to change the status of the whole series? You can use pwclient via scripts. (I wrote my own hooks for mutt so I can do quicker management straight from my mailbox.) From the web interface, you can also select multiple patch checkboxes, then use the Change state drop down at the bottom of the page. Thanks for your advice. I am trying the web interface and I see multiple checkboxes at the left-hand side of the page. But I don't see any Change state drop down at the bottom. (Instead, I see Bundling stuff such as Create bundle and Add to bundle boxes at the bottom of the page.) What is missing from my operation? Thanks Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] A way to change the status of the whole series on Patchwork ?
On Tue, Jul 22, 2014 at 11:37:26AM +0900, Masahiro Yamada wrote: On Wed, 16 Jul 2014 19:49:09 -0700 Brian Norris computersforpe...@gmail.com wrote: On Thu, Jul 17, 2014 at 11:19:42AM +0900, Masahiro Yamada wrote: Does Patchwork have any good way to change the status of the whole series? You can use pwclient via scripts. (I wrote my own hooks for mutt so I can do quicker management straight from my mailbox.) From the web interface, you can also select multiple patch checkboxes, then use the Change state drop down at the bottom of the page. Thanks for your advice. I am trying the web interface and I see multiple checkboxes at the left-hand side of the page. But I don't see any Change state drop down at the bottom. (Instead, I see Bundling stuff such as Create bundle and Add to bundle boxes at the bottom of the page.) I see Bundling too, but I also have a similar box labeled Properties on my view. Notably, I only see the Properties (with Change State, Delegate to and Archive drop-downs) on linux-mtd [1] for which I'm a maintainer. But I don't see it on uboot [2], for which I'm not a maintainer. My best guess is that some functions are reserved for project maintainers, and the web interface only gives access to maintainers (I believe non-maintainers are typically given permission to change the status of their own patches, but this portion of the UI may have been overlooked). Maybe Jeremy knows better. Regards, Brian [1] http://patchwork.ozlabs.org/project/linux-mtd/list/ [2] http://patchwork.ozlabs.org/project/uboot/list/ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] socfpga: initialize MMC
Hi,
I don't know what differ with socfpga_dw_mmc.c.
I think you can use it.
Best Regards,
Jaehoon Chung
On 07/16/2014 09:34 PM, Pavel Machek wrote:
Hi!
Once ethernet changes I merged, I can rediff mmc changes for
application. It will look something like this:
Albert, can you apply the ethernet patch? I'd like to continue on top
of it...
Pavel
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c
b/arch/arm/cpu/armv7/socfpga/misc.c
index 2f1c716..7af384e 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -14,3 +16,27 @@ int dram_init(void)
+
+#ifdef CONFIG_DWMMC
+/*
+ * Initializes MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+ return altera_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 4, 0);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f564046..9b488d9 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -14,5 +14,8 @@
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_SDMMC_ADDRESS 0xff704000
#endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 34febf5..5902105 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
obj-$(CONFIG_DWMMC) += dw_mmc.o
obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+obj-$(CONFIG_ALTERA_DWMMC) += altera_dw_mmc.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
diff --git a/drivers/mmc/altera_dw_mmc.c b/drivers/mmc/altera_dw_mmc.c
new file mode 100644
index 000..b22dc45
--- /dev/null
+++ b/drivers/mmc/altera_dw_mmc.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Altera Corporation www.altera.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include malloc.h
+#include dwmmc.h
+#include asm/arch/dwmmc.h
+#include errno.h
+
+#define CLKMGR_PERPLLGRP_EN_REG (SOCFPGA_CLKMGR_ADDRESS + 0xA0)
+#define CLKMGR_SDMMC_CLK_ENABLE (1 8)
+#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108)
+
+static char *ALTERA_NAME = ALTERA DWMMC;
+
+static void altera_dwmci_clksel(struct dwmci_host *host)
+{
+ unsigned int drvsel;
+ unsigned int smplsel;
+
+ /* Disable SDMMC clock. */
+ clrbits_le32(CLKMGR_PERPLLGRP_EN_REG, CLKMGR_SDMMC_CLK_ENABLE);
+
+ /* Configures drv_sel and smpl_sel */
+ drvsel = 3;
+ smplsel = 0;
+
+ debug(%s: drvsel %d smplsel %d\n, __FUNCTION__, drvsel, smplsel);
+ writel((smplsel 3) | drvsel, SYSMGR_SDMMCGRP_CTRL_REG);
+
+ /* Enable SDMMC clock */
+ setbits_le32(CLKMGR_PERPLLGRP_EN_REG, CLKMGR_SDMMC_CLK_ENABLE);
+}
+
+int altera_dwmmc_init(u32 regbase, int bus_width, int index)
+{
+ struct dwmci_host *host = NULL;
+ host = malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ printf(dwmci_host malloc failed!\n);
+ return -ENOMEM;
+ }
+
+ host-name = ALTERA_NAME;
+ host-ioaddr = (void *)regbase;
+ host-buswidth = bus_width;
+ host-clksel = altera_dwmci_clksel;
+ host-dev_index = index;
+ host-bus_hz = 40;
+ host-fifoth_val = MSIZE(0x2) |
+ RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) |
+ TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2);
+
+ add_dwmci(host, host-bus_hz, host-bus_hz);
+
+ return 0;
+}
+
diff --git a/include/configs/socfpga_cyclone5.h
b/include/configs/socfpga_cyclone5.h
index 0254249..189dcde 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -180,13 +183,30 @@
/*
* FLASH
*/
#define CONFIG_SYS_NO_FLASH
+
+/*
+ * MMC support
+ */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_BOUNCE_BUFFER
+#define
Re: [U-Boot] m68k: Build problems on some boards
Tom, Vasili On Mon, 23 Jun 2014 09:10:01 -0400 Tom Rini tr...@ti.com wrote: On Sun, Jun 22, 2014 at 12:19:21PM +0300, Vasili Galka wrote: I'll really appreciate any help on this. On Sun, Jun 15, 2014 at 3:57 PM, Vasili Galka vvv...@gmail.com wrote: Hi, I've installed a m68k-elf toolchain (based on gcc 4.8.1) and tried building all m68k boards on latest u-boot/master (MAKEALL -a m68k). While the build succeeds for most of the boards, the following four fail with similar errors: TASREG M5249EVB M5253DEMO M5253EVBE m68k-elf-ld.bfd: m68k:isa-a:mac architecture of input file `/usr/m68k-elf/lib/gcc/m68k-elf/4.8.1/m5206e/libgcc.a(_float.o)' is incompatible with m68k:isa-a:emac output m68k-elf-ld.bfd: m68k:isa-a:mac architecture of input file `/usr/m68k-elf/lib/gcc/m68k-elf/4.8.1/m5206e/libgcc.a(_floatex.o)' is incompatible with m68k:isa-a:emac output m68k-elf-ld.bfd: m68k:isa-a:mac architecture of input file `/usr/m68k-elf/lib/gcc/m68k-elf/4.8.1/m5206e/libgcc.a(_muldi3.o)' is incompatible with m68k:isa-a:emac output ... AFAIU, the architecture of chosen libgcc differs from the architecture of generated object files (one has mac while the other emac). I'm not really familiar with m68k arch... What is wrong here and how should be fixed? Best regards, Vasili Jason, is there a toolchain that can work for all m68k boards? Should we start removing some boards perhaps? I think all m68k boards can build file with my series. http://lists.denx.de/pipermail/u-boot/2014-July/184135.html http://patchwork.ozlabs.org/patch/372320/ http://patchwork.ozlabs.org/patch/372321/ Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] scripts: add scripts/gnu_make to not hard-code make command
Hi Jeroen, On Fri, 18 Jul 2014 20:19:52 +0200 Jeroen Hofstee jer...@myspectrum.nl wrote: Instead, they should call the make command via this helper script to make sure it is GNU Make. yup, or the name of the executable could be displayed, so it only needs to be checked once at startup (and error out if no GNU make is found at all). Good idea! MAKEALL and buildman generally invoke make for a lot of boards. Searching it once at startup seems better. +++ b/scripts/gnu_make nitpicking, most script use a dash instead of an underscore. Renamed in v2. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] cosmetic: boards.cfg: fix some maintainers fields
Add a whitespace between the name and the email address. When switching to Kconfig, the first version of MAINTAINERS files will be generated based on the boards.cfg file. So, the maintainers field should be corrected even if it is a really minor fix. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- boards.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards.cfg b/boards.cfg index 3be1e0d..1808131 100644 --- a/boards.cfg +++ b/boards.cfg @@ -106,8 +106,8 @@ Active arm arm926ejs at91atmel at91sam9263ek Active arm arm926ejs at91atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop stel...@popies.net Active arm arm926ejs at91atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop stel...@popies.net Active arm arm926ejs at91atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop stel...@popies.net -Active arm arm926ejs at91atmel at91sam9m10g45ekat91sam9m10g45ek_mmc at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_MMC Bo Shenvoice.s...@atmel.com -Active arm arm926ejs at91atmel at91sam9m10g45ekat91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shenvoice.s...@atmel.com +Active arm arm926ejs at91atmel at91sam9m10g45ekat91sam9m10g45ek_mmc at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_MMC Bo Shen voice.s...@atmel.com +Active arm arm926ejs at91atmel at91sam9m10g45ekat91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen voice.s...@atmel.com Active arm arm926ejs at91atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu josh...@atmel.com Active arm arm926ejs at91atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu josh...@atmel.com Active arm arm926ejs at91atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu josh...@atmel.com -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] About verify uboot
Hi
I try to make use of uboot's secure verify feature, but failed. My procedure is
below:
1) Enable control device tree
Ø Add CONFIG_OF_CONTROL / CONFIG_OF_SEPARATE to file vexpress_aemv8a.h
2) Enable FIT and verify boot
Ø Add CONFIG_FIT/CONFIG_RSA/CONFIG_FIT_SIGNATURE to file vexpress_aemv8a.h
3) Create RSA key pair use openssl named dev
4) Create uboot.dts file as bellow
/dts-v1/;
/ {
model = Keys;
compatible = denx, arm64 ;
signature {
key-dev {
required = conf;
algo = sha1,rsa2048;
key-name-hint = dev;
};
};
};
5) Compile uboot.dtb file
dtc -p 0x1000 .uboot.dts -O dtb -o work/uboot.dtb
6) Create kernel.its file as bellow
/dts-v1/;
/ {
description = Simple image with single Linux kernel and FDT blob;
#address-cells = 1;
images {
kernel@1 {
description = Linux kernel;
data = /incbin/(./arch/arm/boot/zImage);
type = kernel;
arch = arm;
os = linux;
compression = none;
load = 0x40008000;
entry = 0x40008000;
hash@1 {
algo = sha1;
};
};
fdt@1 {
description = Flattened Device Tree blob;
data = /incbin/(./arch/arm/boot/arm64.dtb);
type = flat_dt;
arch = arm;
compression = none;
hash@1 {
algo = sha1;
};
};
};
configurations {
default = conf@1;
conf@1 {
description = Boot Linux kernel with FDT blob;
kernel = kernel@1;
fdt = fdt@1;
signature@1 {
algo = sha1,rsa2048;
key-name-hint = dev ;
};
};
};
};
7) Sign the image
Mkimage -D -I dts -O dtb -p 2000 -f kernel.its - K uboot.dtb -k keys -r
rsa.img
8) Make uboot FDT
Make vexpress_aem64a_config
Make DEV_TREE_BIN = work/uboot.dtb
And the Error is happened when build uboot FDT, error information is
Please define CONFIG_DEFAULT_DEVICE_TREE or build with DEVICE_TREE= argument.
My question is :
Should I need to specify uboot.dts file when building FDT uboot
Best regards
Jason.
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[U-Boot] Silly question regarding mx28_adjust_mac and MAC OUIs?
Hi all, Apoligies if this has been asked before. I'm very new to U-Boot, and did look around but found nothing on the topic. I've been doing some porting of U-Boot to a board based around a Freescale i.MX286 CPU. So far thing are working, but I was wondering how one specifies the MAC OUI? As I understand it on this platform, the hardware fuses only store the lower 32-bits of the MAC, with the upper 16-bits intended to be hardcoded into device firmware. Looking through U-Boot, I see this is done in mx28_adjust_mac (arch/arm/cpu/arm926ejs/mxs/mxs.c +237). If I wanted to set a different OUI, is there a way to specify an alternate one without patching mx28_adjust_mac directly? Regards, -- Stuart Longland Systems Engineer _ ___ \ /|_) | T: +61 7 3535 9619 \/ | \ | 38b Douglas StreetF: +61 7 3535 9699 SYSTEMSMilton QLD 4064 http://www.vrt.com.au ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2] socfpga: cleanup socfpga_dw_mmc
On Mon, 2014-07-21 at 13:30 +0200, ZY - pavel wrote:
Cleanups as suggested by wd on mailing list.
Signed-off-by: Pavel Machek pa...@denx.de
---
v2: calloc is actually needed, document it.
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -16,8 +16,6 @@ static const struct socfpga_clock_manager
*clock_manager_base =
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static char *SOCFPGA_NAME = SOCFPGA DWMMC;
-
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK (1 8)
static void socfpga_dwmci_clksel(struct dwmci_host *host)
@@ -47,14 +45,16 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
- struct dwmci_host *host = NULL;
+ struct dwmci_host *host;
+
+ /* calloc for zero init */
host = calloc(sizeof(struct dwmci_host), 1);
if (!host) {
printf(dwmci_host calloc fail!\n);
return -1;
}
- host-name = SOCFPGA_NAME;
+ host-name = SOCFPGA DWMMC;
host-ioaddr = (void *)regbase;
host-buswidth = bus_width;
host-clksel = socfpga_dwmci_clksel;
Acked-by: Chin Liang See cl...@altera.com
Thanks
Chin Liang
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