Re: [U-Boot] [PATCH 10/10] RFC: Test code for glacier PCI video support
Hi Bin, On 8 January 2015 at 18:34, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Thu, Jan 8, 2015 at 11:06 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 7 January 2015 at 23:18, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Dec 30, 2014 at 10:32 AM, Simon Glass s...@chromium.org wrote: NOT TO APPLY This shows how to enable video for the glacier board, as an example of the emulator working on a VESA-compliant graphics card. Signed-off-by: Simon Glass s...@chromium.org --- include/configs/canyonlands.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 7a1499d..c55e076 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -133,6 +133,9 @@ #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + /*--- * FLASH related *--*/ @@ -359,6 +362,15 @@ ramdisk_addr=fc20\0 \ pciconfighost=1\0 \ pcie_mode=RP:RP\0 \ + eth1addr=00:01:ec:00:f4:9d\0 \ + eth2addr=00:01:ec:00:f4:9e\0 \ + eth3addr=00:01:ec:00:f4:9f\0 \ + ethact=ppc_4xx_eth0\0 \ + ethaddr=00:01:ec:00:f4:9c\0 \ + stderr=serial\0 \ + stdin=serial\0 \ + stdout=serial,vga\0 \ + autoload=n\0 \ #else /* defined(CONFIG_ARCHES) */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -675,4 +687,23 @@ } #endif +#define CONFIG_VIDEO + +#ifdef CONFIG_VIDEO +#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ +#define CONFIG_VIDEO_VESA +#define VIDEO_IO_OFFSET0xd800 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO +#define CONFIG_CFB_CONSOLE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CMD_BMP +#endif + +#define CONFIG_FRAMEBUFFER_SET_VESA_MODE +#define CONFIG_FRAMEBUFFER_VESA_MODE 0x114 +#define CONFIG_CMD_TFTPPUT + #endif /* __CONFIG_H */ -- Could you also post the codes that actually run the vga bios on ppc target? I may find another non-x86 board to test. It is all there - I am using the existing support. If you see pci_run_vga_bios() it calls biosemu_run() in the emulation case. Sorry I mean the complete canyonlands codes which calls pci_run_vga_bios(). I see currently pci_run_vga_bios() is only called by chromebook_link. And do you think the int15_handler() required by the biosemu needs to be common? This series is at u-boot-x86/vesa. You can see the call from the vesa video driver, vesa_fb.c. Re int15_handler(), yes I think it should be, but so far I haven't needed it. I think the ROM access code can be made more common, but I left that task for now. Re your other question I was looking for the VGA enable bit, as I remembered it from years ago. It doesn't seem to be needed for that platforms I have tested. But if it is generally needed we should add it. Which platform do you use? I doubt the VGA enable bit only affects x86 as it opens the A and I/O address decoding which is only applicable on x86. I'm only using glacier and link so far. I suspect there might be something wrong as only one of my video cards works fully on glacier - another once gives a snowy picture. For the ROM, pci_rom_load() works for me, after pciauto_setup_rom() is called. I wonder if you haven't enabled the ROM BAR? I initially got the same result as you. Yes, I called pciauto_setup_rom() in my codes. I also verified the expansion ROM address register has bit0 set to 1 which means enabled. And you still can't see the ROM? Does the BAR give the correct ROM size? Do you enable memory access in the command register? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] samsung: board: support eMMC reset using DT
On Thu, 2015-01-08 at 14:44 +0900, Joonyoung Shim wrote:
Some exynos boards require special handling of SD4_nRESET_OUT line for
eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards.
This will support eMMC reset using DT from reset_misc of samsung common
board file and each board files can support eMMC reset on non DT case.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
diff --git a/doc/device-tree-bindings/exynos/emmc-reset.txt
b/doc/device-tree-bindings/exynos/emmc-reset.txt
new file mode 100644
index 000..e48e508
--- /dev/null
+++ b/doc/device-tree-bindings/exynos/emmc-reset.txt
@@ -0,0 +1,15 @@
+* Samsung eMMC reset
+
+Some exynos boards require special handling of SD4_nRESET_OUT line for eMMC
+memory to perform complete reboot.
Nitpick, on XU3 the line you apparently need to twiddle is
SD0_nRESET_OUT.
Is this type of usage of this pin specific to the Odroid Exynos boards
or potentially on more boards? (Sorry for the simple questions, but my
exynos documentation just says the line exists not what its intended
usage is).
Fwiw, I did a quick check in the linux code and it doesn't seem to be
using those pins for currently for any boards. However my X2 does
successfully reset/reboot in u-boot and linux, so it seems optional
there. The XU3 does fail to reset itself, so it seems required for that
board.
+Required properties:
+- compatible: should be samsung,emmc-reset
+- reset-gpio: gpio chip for eMMC reset.
+
+Example:
+
+emmc-reset {
+compatible = samsung,emmc-reset;
+reset-gpio = gpk1 2 0;
+};
--
Sjoerd Simons sjoerd.sim...@collabora.co.uk
Collabora Ltd.
smime.p7s
Description: S/MIME cryptographic signature
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[U-Boot] [PATCH v2 09/11] x86: config: Enable hook for saving MRC configuration
Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: None include/configs/chromebook_link.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 7e6d239..6e8b9ef 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -20,6 +20,7 @@ #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R #define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_X86_MRC_ADDR0xfffa -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 01/11] x86: dts: Add compatible string for Intel ICH9 SPI controller
Add this to the enum so that we can use the various fdtdec functions. A
later commit will move this driver to driver model.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Use intel,ich-spi as the compatible string
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4901c0d..de46562 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -172,6 +172,7 @@ enum fdt_compat_id {
COMPAT_INTEL_MODEL_206AX, /* Intel Model 206AX CPU */
COMPAT_INTEL_GMA, /* Intel Graphics Media Accelerator */
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
+ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 487122e..e989241 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -83,6 +83,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_MODEL_206AX, intel,model-206ax),
COMPAT(INTEL_GMA, intel,gma),
COMPAT(AMS_AS3722, ams,as3722),
+ COMPAT(INTEL_ICH_SPI, intel,ich-spi),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 08/11] x86: Implement a cache for Memory Reference Code parameters
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.
Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update for the new CMOS RAM access functions in the RTC
- Add a comment about why both CMOS RAM and SPI flash are used for the cache
arch/x86/cpu/ivybridge/Makefile| 1 +
arch/x86/cpu/ivybridge/mrccache.c | 156 +++
arch/x86/cpu/ivybridge/sdram.c | 253 +
arch/x86/include/asm/arch-ivybridge/mrccache.h | 51 +
arch/x86/include/asm/global_data.h | 3 +
5 files changed, 464 insertions(+)
create mode 100644 arch/x86/cpu/ivybridge/mrccache.c
create mode 100644 arch/x86/include/asm/arch-ivybridge/mrccache.h
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 0c7efae..3576b83 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -14,6 +14,7 @@ obj-y += lpc.o
obj-y += me_status.o
obj-y += model_206ax.o
obj-y += microcode_intel.o
+obj-y += mrccache.o
obj-y += northbridge.o
obj-y += pch.o
obj-y += pci.o
diff --git a/arch/x86/cpu/ivybridge/mrccache.c
b/arch/x86/cpu/ivybridge/mrccache.c
new file mode 100644
index 000..182c995
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/mrccache.c
@@ -0,0 +1,156 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/mrccache.c
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include common.h
+#include errno.h
+#include fdtdec.h
+#include spi.h
+#include spi_flash.h
+#include asm/ip_checksum.h
+#include asm/arch/mrccache.h
+#include asm/arch/sandybridge.h
+
+static struct mrc_data_container *next_mrc_block(
+ struct mrc_data_container *mrc_cache)
+{
+ /* MRC data blocks are aligned within the region */
+ u32 mrc_size = sizeof(*mrc_cache) + mrc_cache-data_size;
+ if (mrc_size (MRC_DATA_ALIGN - 1UL)) {
+ mrc_size = ~(MRC_DATA_ALIGN - 1UL);
+ mrc_size += MRC_DATA_ALIGN;
+ }
+
+ u8 *region_ptr = (u8 *)mrc_cache;
+ region_ptr += mrc_size;
+ return (struct mrc_data_container *)region_ptr;
+}
+
+static int is_mrc_cache(struct mrc_data_container *cache)
+{
+ return cache (cache-signature == MRC_DATA_SIGNATURE);
+}
+
+/*
+ * Find the largest index block in the MRC cache. Return NULL if none is
+ * found.
+ */
+struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry)
+{
+ struct mrc_data_container *cache, *next;
+ ulong base_addr, end_addr;
+ uint id;
+
+ base_addr = (1ULL 32) - CONFIG_ROM_SIZE + entry-offset;
+ end_addr = base_addr + entry-length;
+ cache = NULL;
+
+ /* Search for the last filled entry in the region */
+ for (id = 0, next = (struct mrc_data_container *)base_addr;
+is_mrc_cache(next);
+id++) {
+ cache = next;
+ next = next_mrc_block(next);
+ if ((ulong)next = end_addr)
+ break;
+ }
+
+ if (id-- == 0) {
+ debug(%s: No valid MRC cache found.\n, __func__);
+ return NULL;
+ }
+
+ /* Verify checksum */
+ if (cache-checksum != compute_ip_checksum(cache-data,
+ cache-data_size)) {
+ printf(%s: MRC cache checksum mismatch\n, __func__);
+ return NULL;
+ }
+
+ debug(%s: picked entry %u from cache block\n, __func__, id);
+
+ return cache;
+}
+
+/**
+ * find_next_mrc_cache() - get next cache entry
+ *
+ * @entry: MRC cache flash area
+ * @cache: Entry to start from
+ *
+ * @return next cache entry if found, NULL if we got to the end
+ */
+static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry,
+ struct mrc_data_container *cache)
+{
+ ulong base_addr, end_addr;
+
+ base_addr = (1ULL 32) - CONFIG_ROM_SIZE + entry-offset;
+ end_addr = base_addr + entry-length;
+
+ cache = next_mrc_block(cache);
+ if ((ulong)cache = end_addr) {
+ /* Crossed the boundary */
+ cache = NULL;
+ debug(%s: no available entries found\n, __func__);
+ } else {
+ debug(%s: picked next entry from cache block at %p\n,
+ __func__, cache);
+ }
+
+ return cache;
+}
+
+int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry,
+ struct mrc_data_container *cur)
+{
+ struct mrc_data_container *cache;
+ ulong offset;
+ ulong base_addr;
+ int ret;
+
+ /* Find the last used block */
+ base_addr = (1ULL 32) - CONFIG_ROM_SIZE +
[U-Boot] [PATCH v2 05/11] x86: spi: Add device tree support
As a temporary measure before the ICH driver moves over to driver model,
add device tree support to the driver.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/spi/ich.c| 7 +++
include/configs/x86-common.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 0379444..fdff158 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -153,6 +153,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
return ich-slave;
}
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+ int spi_node)
+{
+ /* We only support a single SPI at present */
+ return spi_setup_slave(0, 0, 2000, 0);
+}
+
void spi_free_slave(struct spi_slave *slave)
{
struct ich_spi_slave *ich = to_ich_spi(slave);
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 4f0a3c5..ecedfc3 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -211,6 +211,7 @@
#define CONFIG_CMD_SF_TEST
#define CONFIG_CMD_SPI
#define CONFIG_SPI
+#define CONFIG_OF_SPI_FLASH
/*---
* Environment configuration
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 06/11] Allow architecture-specific memory reservation
All memory to be reserved for use after relocation by adding a new call
to perform this reservation.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/board_f.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 3a4b32c..215108b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -807,6 +807,12 @@ static int initf_dm(void)
return 0;
}
+/* Architecture-specific memory reservation */
+__weak int reserve_arch(void)
+{
+ return 0;
+}
+
static init_fnc_t init_sequence_f[] = {
#ifdef CONFIG_SANDBOX
setup_ram_buf,
@@ -970,6 +976,7 @@ static init_fnc_t init_sequence_f[] = {
setup_machine,
reserve_global_data,
reserve_fdt,
+ reserve_arch,
reserve_stacks,
setup_dram_config,
show_dram_config,
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 07/11] x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Make changes to chromebook_link.dts since link.dts is gone
- Use intel,ich-spi as the compatible string
arch/x86/dts/chromebook_link.dts | 15 ++-
arch/x86/dts/link.dts| 229 +++
2 files changed, 243 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/dts/link.dts
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 9490b16..45ada61 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -7,6 +7,10 @@
model = Google Link;
compatible = google,link, intel,celeron-ivybridge;
+ aliases {
+ spi0 = /spi;
+ };
+
config {
silent_console = 0;
};
@@ -150,11 +154,20 @@
spi {
#address-cells = 1;
#size-cells = 0;
- compatible = intel,ich9;
+ compatible = intel,ich-spi;
spi-flash@0 {
+ #size-cells = 1;
+ #address-cells = 1;
reg = 0;
compatible = winbond,w25q64, spi-flash;
memory-map = 0xff80 0x0080;
+ rw-mrc-cache {
+ label = rw-mrc-cache;
+ /* Alignment: 4k (for updating) */
+ reg = 0x003e 0x0001;
+ type = wiped;
+ wipe-value = [ff];
+ };
};
};
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
new file mode 100644
index 000..52d8b60
--- /dev/null
+++ b/arch/x86/dts/link.dts
@@ -0,0 +1,229 @@
+/dts-v1/;
+
+/include/ skeleton.dtsi
+/include/ serial.dtsi
+
+/ {
+ model = Google Link;
+ compatible = google,link, intel,celeron-ivybridge;
+
+ aliases {
+ spi0 = /spi;
+ };
+
+ config {
+ silent_console = 0;
+ };
+
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x10;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x30 0x10;
+ bank-name = B;
+ };
+
+ gpioc {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x40 0x10;
+ bank-name = C;
+ };
+
+ chosen {
+ stdout-path = /serial;
+ };
+
+ spd {
+ compatible = memory-spd;
+ #address-cells = 1;
+ #size-cells = 0;
+ elpida_4Gb_1600_x16 {
+ reg = 0;
+ data = [92 10 0b 03 04 19 02 02
+ 03 52 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 81
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 42 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 02 fe 00
+ 11 52 00 00 00 07 7f 37
+ 45 42 4a 32 30 55 47 36
+ 45 42 55 30 2d 47 4e 2d
+ 46 20 30 20 02 fe 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00];
+ };
+ samsung_4Gb_1600_1.35v_x16 {
+ reg = 1;
+ data = [92 11 0b 03 04 19 02 02
+
[U-Boot] [PATCH v2 10/11] x86: ivybridge: Drop the Kconfig MRC cache information
This is now stored in the device tree. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: None arch/x86/cpu/ivybridge/Kconfig | 28 1 file changed, 28 deletions(-) diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index afca957..e4595be 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -26,20 +26,6 @@ config CACHE_MRC_SIZE_KB int default 256 -config MRC_CACHE_BASE - hex - default 0xff80 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x1ec000 - -config MRC_CACHE_SIZE - hex - depends on !CHROMEOS - default 0x1 - config DCACHE_RAM_BASE hex default 0xff7f @@ -64,20 +50,6 @@ config CACHE_MRC_SIZE_KB int default 512 -config MRC_CACHE_BASE - hex - default 0xff80 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x37 - -config MRC_CACHE_SIZE - hex - depends on !CHROMEOS - default 0x1 - config DCACHE_RAM_BASE hex default 0xff7e -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 04/11] x86: rtc: mc146818: Add helpers to read/write CMOS RAM
On x86 we use CMOS RAM to read and write some settings. Add basic support
for this, including access to registers 128-255.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Adjust the mc146818 driver instead of adding a new cmos.h header
drivers/rtc/mc146818.c | 53 +-
include/rtc.h | 32 ++
2 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 39e6041..b506b16 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -27,9 +27,6 @@
/* Set this to 1 to clear the CMOS RAM */
#define CLEAR_CMOS 0
-static uchar rtc_read (uchar reg);
-static void rtc_write (uchar reg, uchar val);
-
#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70
#define RTC_SECONDS0x00
#define RTC_SECONDS_ALARM 0x01
@@ -133,32 +130,60 @@ void rtc_reset (void)
/* - */
-#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
/*
* use direct memory access
*/
-static uchar rtc_read (uchar reg)
+int rtc_read(int reg)
{
+#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
return in8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg);
+#else
+ int ofs = 0;
+
+ if (reg = 128) {
+ ofs = 2;
+ reg -= 128;
+ }
+ out8(RTC_PORT_MC146818 + ofs, reg);
+
+ return in8(RTC_PORT_MC146818 + ofs + 1);
+#endif
}
-static void rtc_write (uchar reg, uchar val)
+void rtc_write(int reg, uchar val)
{
+#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
out8(CONFIG_SYS_RTC_REG_BASE_ADDR + reg, val);
-}
#else
-static uchar rtc_read (uchar reg)
+ int ofs = 0;
+
+ if (reg = 128) {
+ ofs = 2;
+ reg -= 128;
+ }
+ out8(RTC_PORT_MC146818 + ofs, reg);
+ out8(RTC_PORT_MC146818 + ofs + 1, val);
+#endif
+}
+
+u32 rtc_read32(int reg)
{
- out8(RTC_PORT_MC146818,reg);
- return in8(RTC_PORT_MC146818 + 1);
+ u32 value = 0;
+ int i;
+
+ for (i = 0; i sizeof(value); i++)
+ value |= rtc_read(reg + i) (i 3);
+
+ return value;
}
-static void rtc_write (uchar reg, uchar val)
+void rtc_write32(int reg, u32 value)
{
- out8(RTC_PORT_MC146818,reg);
- out8(RTC_PORT_MC146818+1, val);
+ int i;
+
+ for (i = 0; i sizeof(value); i++)
+ rtc_write(reg + i, (value (i 3)) 0xff);
}
-#endif
void rtc_init(void)
{
diff --git a/include/rtc.h b/include/rtc.h
index d11aa8b..b6df1f4 100644
--- a/include/rtc.h
+++ b/include/rtc.h
@@ -51,6 +51,38 @@ unsigned long mktime (unsigned int, unsigned int, unsigned
int,
unsigned int, unsigned int, unsigned int);
/**
+ * rtc_read() - Read an 8-bit register
+ *
+ * @reg: Register to read
+ * @return value read
+ */
+int rtc_read(int reg);
+
+/**
+ * rtc_write() - Write an 8-bit register
+ *
+ * @reg: Register to write
+ * @value: Value to write
+ */
+void rtc_write(int reg, uchar val);
+
+/**
+ * rtc_read32() - Read a 32-bit value from the RTC
+ *
+ * @reg: Offset to start reading from
+ * @return value read
+ */
+u32 rtc_read32(int reg);
+
+/**
+ * rtc_write32() - Write a 32-bit value to the RTC
+ *
+ * @reg: Register to start writing to
+ * @value: Value to write
+ */
+void rtc_write32(int reg, u32 value);
+
+/**
* rtc_init() - Set up the real time clock ready for use
*/
void rtc_init(void);
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 02/11] x86: Move ipchecksum into common area and rename it
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Move it into the common area and rename it slightly to remove the
abbreviations.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Refactor IP checksum patches
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/coreboot/Makefile | 1 -
arch/x86/cpu/coreboot/ipchecksum.c | 55 -
arch/x86/cpu/coreboot/tables.c | 8 ++--
arch/x86/cpu/ip_checksum.c | 34 +++
arch/x86/include/asm/arch-coreboot/ipchecksum.h | 37 -
arch/x86/include/asm/ip_checksum.h | 16 +++
7 files changed, 55 insertions(+), 97 deletions(-)
delete mode 100644 arch/x86/cpu/coreboot/ipchecksum.c
create mode 100644 arch/x86/cpu/ip_checksum.c
delete mode 100644 arch/x86/include/asm/arch-coreboot/ipchecksum.h
create mode 100644 arch/x86/include/asm/ip_checksum.h
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 62e43c0..eee2289 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_COREBOOT) += coreboot/
obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
+obj-y += ip_checksum.o
obj-y += lapic.o
obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 35e6cdd..b6e870a 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -16,7 +16,6 @@
obj-y += car.o
obj-y += coreboot.o
obj-y += tables.o
-obj-y += ipchecksum.o
obj-y += sdram.o
obj-y += timestamp.o
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/x86/cpu/coreboot/ipchecksum.c
b/arch/x86/cpu/coreboot/ipchecksum.c
deleted file mode 100644
index 3340872..000
--- a/arch/x86/cpu/coreboot/ipchecksum.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the libpayload project.
- *
- * It has originally been taken from the FreeBSD project.
- *
- * Copyright (c) 2001 Charles Mott c...@linktel.net
- * Copyright (c) 2008 coresystems GmbH
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *notice, this list of conditions and the following disclaimer in the
- *documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include linux/types.h
-#include linux/compiler.h
-#include asm/arch/ipchecksum.h
-
-unsigned short ipchksum(const void *vptr, unsigned long nbytes)
-{
- int sum, oddbyte;
- const unsigned short *ptr = vptr;
-
- sum = 0;
- while (nbytes 1) {
- sum += *ptr++;
- nbytes -= 2;
- }
- if (nbytes == 1) {
- oddbyte = 0;
- ((u8 *)oddbyte)[0] = *(u8 *) ptr;
- ((u8 *)oddbyte)[1] = 0;
- sum += oddbyte;
- }
- sum = (sum 16) + (sum 0x);
- sum += (sum 16);
- return ~sum;
-}
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
index 92b7528..662af95 100644
--- a/arch/x86/cpu/coreboot/tables.c
+++ b/arch/x86/cpu/coreboot/tables.c
@@ -8,7 +8,7 @@
*/
#include common.h
-#include asm/arch/ipchecksum.h
+#include asm/ip_checksum.h
#include asm/arch/sysinfo.h
#include asm/arch/tables.h
@@ -131,11 +131,11 @@ static int cb_parse_header(void *addr, int len, struct
sysinfo_t *info)
return 0;
/* Make sure the checksums match. */
- if (ipchksum((u16 *) header, sizeof(*header)) != 0)
+ if (compute_ip_checksum((u16 *)header, sizeof(*header)) != 0)
return -1;
- if (ipchksum((u16 *) (ptr + sizeof(*header)),
-header-table_bytes) != header-table_checksum)
+ if (compute_ip_checksum((u16 *)(ptr +
[U-Boot] [PATCH v2 03/11] x86: Allow adding of IP checksums
Add a function to add IP checksums.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Refactor IP checksum patches
arch/x86/cpu/ip_checksum.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/x86/cpu/ip_checksum.c b/arch/x86/cpu/ip_checksum.c
index 1b529da..ddfc0d7 100644
--- a/arch/x86/cpu/ip_checksum.c
+++ b/arch/x86/cpu/ip_checksum.c
@@ -32,3 +32,24 @@ unsigned short compute_ip_checksum(const void *vptr,
unsigned long nbytes)
sum += (sum 16);
return ~sum;
}
+
+unsigned long add_ip_checksums(unsigned long offset, unsigned long sum,
+ unsigned long new)
+{
+ unsigned long checksum;
+
+ sum = ~sum 0x;
+ new = ~new 0x;
+ if (offset 1) {
+ /*
+* byte-swap the sum if it came from an odd offset; since the
+* computation is endian independant this works.
+*/
+ new = ((new 8) 0xff) | ((new 8) 0xff00);
+ }
+ checksum = sum + new;
+ if (checksum 0x)
+ checksum -= 0x;
+
+ return (~checksum) 0x;
+}
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 11/11] x86: config: chromebook_link: Enable environment
Enable an environment area. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: None include/configs/chromebook_link.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 6e8b9ef..7b460e8 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -64,6 +64,13 @@ #define CONFIG_CMD_CROS_EC #define CONFIG_ARCH_EARLY_INIT_R +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x003f8000 + #define CONFIG_STD_DEVICES_SETTINGS stdin=usbkbd,vga,serial\0 \ stdout=vga,serial\0 \ stderr=vga,serial\0 -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/11] Add support for caching Memory Reference Code data
Since the memory reference code is so slow on x86, add a feature to bypass this, storing the previous parameters in SPI flash. This saves around 500ms on each boot. Also enable a SPI flash environment. Changes in v2: - Use intel,ich-spi as the compatible string - Refactor IP checksum patches - Refactor IP checksum patches - Adjust the mc146818 driver instead of adding a new cmos.h header - Make changes to chromebook_link.dts since link.dts is gone - Use intel,ich-spi as the compatible string - Update for the new CMOS RAM access functions in the RTC - Add a comment about why both CMOS RAM and SPI flash are used for the cache Simon Glass (11): x86: dts: Add compatible string for Intel ICH9 SPI controller x86: Move ipchecksum into common area and rename it x86: Allow adding of IP checksums x86: rtc: mc146818: Add helpers to read/write CMOS RAM x86: spi: Add device tree support Allow architecture-specific memory reservation x86: dts: Add SPI flash MRC details for chromebook_link x86: Implement a cache for Memory Reference Code parameters x86: config: Enable hook for saving MRC configuration x86: ivybridge: Drop the Kconfig MRC cache information x86: config: chromebook_link: Enable environment arch/x86/cpu/Makefile | 1 + arch/x86/cpu/coreboot/Makefile | 1 - arch/x86/cpu/coreboot/ipchecksum.c | 55 -- arch/x86/cpu/coreboot/tables.c | 8 +- arch/x86/cpu/ip_checksum.c | 55 ++ arch/x86/cpu/ivybridge/Kconfig | 28 --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/mrccache.c | 156 +++ arch/x86/cpu/ivybridge/sdram.c | 253 arch/x86/dts/chromebook_link.dts| 15 +- arch/x86/dts/link.dts | 229 + arch/x86/include/asm/arch-coreboot/ipchecksum.h | 37 arch/x86/include/asm/arch-ivybridge/mrccache.h | 51 + arch/x86/include/asm/global_data.h | 3 + arch/x86/include/asm/ip_checksum.h | 16 ++ common/board_f.c| 7 + drivers/rtc/mc146818.c | 53 +++-- drivers/spi/ich.c | 7 + include/configs/chromebook_link.h | 8 + include/configs/x86-common.h| 1 + include/fdtdec.h| 1 + include/rtc.h | 32 +++ lib/fdtdec.c| 1 + 23 files changed, 879 insertions(+), 140 deletions(-) delete mode 100644 arch/x86/cpu/coreboot/ipchecksum.c create mode 100644 arch/x86/cpu/ip_checksum.c create mode 100644 arch/x86/cpu/ivybridge/mrccache.c create mode 100644 arch/x86/dts/link.dts delete mode 100644 arch/x86/include/asm/arch-coreboot/ipchecksum.h create mode 100644 arch/x86/include/asm/arch-ivybridge/mrccache.h create mode 100644 arch/x86/include/asm/ip_checksum.h -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/10] RFC: Test code for glacier PCI video support
Hi Simon, On Thu, Jan 8, 2015 at 11:06 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 7 January 2015 at 23:18, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Dec 30, 2014 at 10:32 AM, Simon Glass s...@chromium.org wrote: NOT TO APPLY This shows how to enable video for the glacier board, as an example of the emulator working on a VESA-compliant graphics card. Signed-off-by: Simon Glass s...@chromium.org --- include/configs/canyonlands.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 7a1499d..c55e076 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -133,6 +133,9 @@ #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + /*--- * FLASH related *--*/ @@ -359,6 +362,15 @@ ramdisk_addr=fc20\0 \ pciconfighost=1\0 \ pcie_mode=RP:RP\0 \ + eth1addr=00:01:ec:00:f4:9d\0 \ + eth2addr=00:01:ec:00:f4:9e\0 \ + eth3addr=00:01:ec:00:f4:9f\0 \ + ethact=ppc_4xx_eth0\0 \ + ethaddr=00:01:ec:00:f4:9c\0 \ + stderr=serial\0 \ + stdin=serial\0 \ + stdout=serial,vga\0 \ + autoload=n\0 \ #else /* defined(CONFIG_ARCHES) */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -675,4 +687,23 @@ } #endif +#define CONFIG_VIDEO + +#ifdef CONFIG_VIDEO +#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ +#define CONFIG_VIDEO_VESA +#define VIDEO_IO_OFFSET0xd800 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO +#define CONFIG_CFB_CONSOLE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CMD_BMP +#endif + +#define CONFIG_FRAMEBUFFER_SET_VESA_MODE +#define CONFIG_FRAMEBUFFER_VESA_MODE 0x114 +#define CONFIG_CMD_TFTPPUT + #endif /* __CONFIG_H */ -- Could you also post the codes that actually run the vga bios on ppc target? I may find another non-x86 board to test. It is all there - I am using the existing support. If you see pci_run_vga_bios() it calls biosemu_run() in the emulation case. Sorry I mean the complete canyonlands codes which calls pci_run_vga_bios(). I see currently pci_run_vga_bios() is only called by chromebook_link. And do you think the int15_handler() required by the biosemu needs to be common? Re your other question I was looking for the VGA enable bit, as I remembered it from years ago. It doesn't seem to be needed for that platforms I have tested. But if it is generally needed we should add it. Which platform do you use? I doubt the VGA enable bit only affects x86 as it opens the A and I/O address decoding which is only applicable on x86. For the ROM, pci_rom_load() works for me, after pciauto_setup_rom() is called. I wonder if you haven't enabled the ROM BAR? I initially got the same result as you. Yes, I called pciauto_setup_rom() in my codes. I also verified the expansion ROM address register has bit0 set to 1 which means enabled. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: ls1021x: Add support for initializing CAAM's stream id
There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 37 ++
.../include/asm/arch-ls102xa/ls102xa_stream_id.h | 57 ++
board/freescale/common/ls102xa_stream_id.c | 15 ++
board/freescale/ls1021aqds/ls1021aqds.c| 21
board/freescale/ls1021atwr/ls1021atwr.c| 21
6 files changed, 152 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index 5e934da..f200bc8 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -36,6 +36,7 @@
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x0070
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x0760
#define CONFIG_SYS_TSEC1_OFFSET0x01d1
#define CONFIG_SYS_TSEC2_OFFSET0x01d5
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 697d4ca..a73ef2e 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -37,6 +37,43 @@
#define DCFG_DCSR_PORCR1 0
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error Do not define CONFIG_SYS_CCSRBAR_PHYS directly.
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOWCONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) 32 |
\
+CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index abd70fc..fa571b3 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -7,11 +7,68 @@
#ifndef __FSL_LS102XA_STREAM_ID_H_
#define __FSL_LS102XA_STREAM_ID_H_
+#include fsl_sec.h
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+ { .compat = name, \
+ .id = { idA }, .num_ids = 1, \
+ .reg_offset = off + CONFIG_SYS_IMMR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+ { .compat = name, \
+ .id = { idA, idB }, .num_ids = 2, \
+ .reg_offset = off + CONFIG_SYS_IMMR, \
+ .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+ }
+
+/*
+ * handle both old and new versioned SEC properties:
+ * fsl,secX.Y became fsl,sec-vX.Y during development
+ */
+#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
+ SET_LIODN_ENTRY_2(fsl,sec4.0-job-ring, liodnA, liodnB, \
+ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+ SET_LIODN_ENTRY_2(fsl,sec-v4.0-job-ring, liodnA, liodnB,\
+ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+
+/* This is a bit evil since we treat rtic param as both a string hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+ SET_LIODN_ENTRY_1(fsl,sec4.0-rtic-memory, \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ SET_LIODN_ENTRY_1(fsl,sec-v4.0-rtic-memory, \
+ liodnA, \
+ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+ CONFIG_SYS_FSL_SEC_OFFSET, \
+ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 *
Re: [U-Boot] [PATCH 1/3] samsung: board: support eMMC reset using DT
On Fri, 2015-01-09 at 16:42 +0900, Joonyoung Shim wrote: Hi, On 01/09/2015 01:21 PM, Jaehoon Chung wrote: On 01/09/2015 08:23 AM, Sjoerd Simons wrote: On Thu, 2015-01-08 at 14:44 +0900, Joonyoung Shim wrote: Some exynos boards require special handling of SD4_nRESET_OUT line for eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards. This will support eMMC reset using DT from reset_misc of samsung common board file and each board files can support eMMC reset on non DT case. Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com diff --git a/doc/device-tree-bindings/exynos/emmc-reset.txt b/doc/device-tree-bindings/exynos/emmc-reset.txt new file mode 100644 index 000..e48e508 --- /dev/null +++ b/doc/device-tree-bindings/exynos/emmc-reset.txt @@ -0,0 +1,15 @@ +* Samsung eMMC reset + +Some exynos boards require special handling of SD4_nRESET_OUT line for eMMC +memory to perform complete reboot. Nitpick, on XU3 the line you apparently need to twiddle is SD0_nRESET_OUT. Then, i think it's better to omit SD4_. Is this type of usage of this pin specific to the Odroid Exynos boards or potentially on more boards? (Sorry for the simple questions, but my exynos documentation just says the line exists not what its intended usage is). In case of Exynos4, eMMC can be used with sdhci controller or dw-mmc controller. So Pin name should be used to SD0 or SD4. But Exynos5 is only supported the dw-mmc controller. (So eMMC is used pin-name as SD0.) I can find only SD_4_nRESET_OUT from exynos4412 user manual and only SD_0__nRESET_OUT from exynos5422 user manual. Best Regards, Jaehoon Chung Fwiw, I did a quick check in the linux code and it doesn't seem to be using those pins for currently for any boards. However my X2 does successfully reset/reboot in u-boot and linux, so it seems optional there. The XU3 does fail to reset itself, so it seems required for that board. I checked upstream u-boot and hardkernel u-boot and i found codes to reset eMMC using gpio. upstream u-boot: reset_misc() of board/samsung/odroid/odroid.c hardkernel u-boot: reset_cpu() of arch/arm/cpu/armv7/exynos/reset.c Yeah u-boot does it, but linux upstream kernel does not. Hence wondering about the requirements. -- Sjoerd Simons sjoerd.sim...@collabora.co.uk Collabora Ltd. smime.p7s Description: S/MIME cryptographic signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] NAND bug fixes for v2015.01
Hi Scott, U-Boot v2015.01 will be released in a few days. (scheduled on January 12) I know you are busy, but can you please check NAND fixes? [1] http://patchwork.ozlabs.org/patch/421803/ [2] http://patchwork.ozlabs.org/patch/424123/ [3] http://patchwork.ozlabs.org/patch/424122/ Especially, [1] and [2] are apparent regressions. I believe they should be fixed by the release. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/10] RFC: Test code for glacier PCI video support
Hi Simon, On Fri, Jan 9, 2015 at 11:35 AM, Simon Glass s...@chromium.org wrote: Hi Bin, On 8 January 2015 at 18:34, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Thu, Jan 8, 2015 at 11:06 PM, Simon Glass s...@chromium.org wrote: Hi Bin, On 7 January 2015 at 23:18, Bin Meng bmeng...@gmail.com wrote: Hi Simon, On Tue, Dec 30, 2014 at 10:32 AM, Simon Glass s...@chromium.org wrote: NOT TO APPLY This shows how to enable video for the glacier board, as an example of the emulator working on a VESA-compliant graphics card. Signed-off-by: Simon Glass s...@chromium.org --- include/configs/canyonlands.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 7a1499d..c55e076 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -133,6 +133,9 @@ #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + /*--- * FLASH related *--*/ @@ -359,6 +362,15 @@ ramdisk_addr=fc20\0 \ pciconfighost=1\0 \ pcie_mode=RP:RP\0 \ + eth1addr=00:01:ec:00:f4:9d\0 \ + eth2addr=00:01:ec:00:f4:9e\0 \ + eth3addr=00:01:ec:00:f4:9f\0 \ + ethact=ppc_4xx_eth0\0 \ + ethaddr=00:01:ec:00:f4:9c\0 \ + stderr=serial\0 \ + stdin=serial\0 \ + stdout=serial,vga\0 \ + autoload=n\0 \ #else /* defined(CONFIG_ARCHES) */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -675,4 +687,23 @@ } #endif +#define CONFIG_VIDEO + +#ifdef CONFIG_VIDEO +#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ +#define CONFIG_VIDEO_VESA +#define VIDEO_IO_OFFSET0xd800 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VIDEO_LOGO +#define CONFIG_CFB_CONSOLE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CMD_BMP +#endif + +#define CONFIG_FRAMEBUFFER_SET_VESA_MODE +#define CONFIG_FRAMEBUFFER_VESA_MODE 0x114 +#define CONFIG_CMD_TFTPPUT + #endif /* __CONFIG_H */ -- Could you also post the codes that actually run the vga bios on ppc target? I may find another non-x86 board to test. It is all there - I am using the existing support. If you see pci_run_vga_bios() it calls biosemu_run() in the emulation case. Sorry I mean the complete canyonlands codes which calls pci_run_vga_bios(). I see currently pci_run_vga_bios() is only called by chromebook_link. And do you think the int15_handler() required by the biosemu needs to be common? This series is at u-boot-x86/vesa. You can see the call from the vesa video driver, vesa_fb.c. Ah, I see. I can have a try on a non-x86 board. Re int15_handler(), yes I think it should be, but so far I haven't needed it. So what does int15_hander() normally do? I see the vesa_fb.c provided NULL for int15_handler, but the call in arch/x86/cpu/ivybridge/gma.c does not pass NULL. I think the ROM access code can be made more common, but I left that task for now. Re your other question I was looking for the VGA enable bit, as I remembered it from years ago. It doesn't seem to be needed for that platforms I have tested. But if it is generally needed we should add it. Which platform do you use? I doubt the VGA enable bit only affects x86 as it opens the A and I/O address decoding which is only applicable on x86. I'm only using glacier and link so far. I suspect there might be something wrong as only one of my video cards works fully on glacier - another once gives a snowy picture. So VGA enable bit is unset on Link as well? That's interesting. When you mentioned two cards, did you insert them simultaneously? I believe only one card will work due to only one card will respond VGA cycles. For the ROM, pci_rom_load() works for me, after pciauto_setup_rom() is called. I wonder if you haven't enabled the ROM BAR? I initially got the same result as you. Yes, I called pciauto_setup_rom() in my codes. I also verified the expansion ROM address register has bit0 set to 1 which means enabled. And you still can't see the ROM? Does the BAR give the correct ROM size? Do you enable memory access in the command register? I confirm the BAR gave the correct size and memory access in the command register is turned on (this is by U-Boot's pci enumeration process), but it still cannot. And finally I just figured it out the root
Re: [U-Boot] [PATCH] i2c:mxc fix array size of i2c_data
Hello Peng Fan,
Am 06.01.2015 07:12, schrieb Peng Fan:
We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3,
there are 4 i2c interface, but not 3. So the size of i2c_data array should
be calculated using ARRAY_SIZE(i2c_bases).
To avoid compile error, move i2c_bases before sram_data structure which
contains i2c_data array.
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/i2c/mxc_i2c.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
Acked-by: Heiko Schocher h...@denx.de
@Stefano: Would you pick up this patch, or should I?
bye,
Heiko
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 021b2fe..fc5ee35 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -402,17 +402,6 @@ int bus_i2c_write(void *base, uchar chip, uint addr, int
alen,
return ret;
}
-struct i2c_parms {
- void *base;
- void *idle_bus_data;
- int (*idle_bus_fn)(void *p);
-};
-
-struct sram_data {
- unsigned curr_i2c_bus;
- struct i2c_parms i2c_data[3];
-};
-
static void * const i2c_bases[] = {
#if defined(CONFIG_MX25)
(void *)IMX_I2C_BASE,
@@ -439,6 +428,17 @@ static void * const i2c_bases[] = {
#endif
};
+struct i2c_parms {
+ void *base;
+ void *idle_bus_data;
+ int (*idle_bus_fn)(void *p);
+};
+
+struct sram_data {
+ unsigned curr_i2c_bus;
+ struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)];
+};
+
void *i2c_get_base(struct i2c_adapter *adap)
{
return i2c_bases[adap-hwadapnr];
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH 1/3] samsung: board: support eMMC reset using DT
+Cc Jaehoon,
On 01/09/2015 03:18 AM, Simon Glass wrote:
Hi Joonyoung,
On 7 January 2015 at 22:44, Joonyoung Shim jy0922.s...@samsung.com wrote:
Some exynos boards require special handling of SD4_nRESET_OUT line for
eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards.
This will support eMMC reset using DT from reset_misc of samsung common
board file and each board files can support eMMC reset on non DT case.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
---
board/samsung/common/board.c | 27
++
board/samsung/odroid/odroid.c | 2 +-
doc/device-tree-bindings/exynos/emmc-reset.txt | 15 ++
3 files changed, 43 insertions(+), 1 deletion(-)
create mode 100644 doc/device-tree-bindings/exynos/emmc-reset.txt
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index c04ab3c..3218463 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -40,6 +40,8 @@ __weak int exynos_power_init(void)
return 0;
}
+__weak void exynos_reset_misc(void) {}
+
#if defined CONFIG_EXYNOS_TMU
/* Boot Time Thermal Analysis for SoC temperature threshold breach */
static void boot_temp_check(void)
@@ -400,3 +402,28 @@ int misc_init_r(void)
return 0;
}
#endif
+
+void reset_misc(void)
+{
+#ifdef CONFIG_OF_CONTROL
I think all Samsung boards have this defined, so this #ifdef can be removed.
OK, if it is true, we can remove this and i will not to support non DT case.
+ struct gpio_desc gpio = {};
+ int node;
+
+ node = fdt_node_offset_by_compatible(gd-fdt_blob, 0,
+ samsung,emmc-reset);
+ if (node 0)
+ return;
+
+ gpio_request_by_name_nodev(gd-fdt_blob, node, reset-gpio, 0,
gpio,
+ GPIOD_IS_OUT);
+
+ if (dm_gpio_is_valid(gpio)) {
+ /* Reset eMMC*/
+ dm_gpio_set_value(gpio, 0);
+ mdelay(10);
That's a very long reset! Is that what it needs?
Jaehoon, is there any guide about wait time of reset at eMMC spec?
Thanks.
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Re: [U-Boot] [PATCH 2/3] Odroid: Add eMMC-reset node on DT
+Cc Jaehoon,
On 01/09/2015 03:20 AM, Simon Glass wrote:
Hi,
On 7 January 2015 at 22:44, Joonyoung Shim jy0922.s...@samsung.com wrote:
This needs for special handling of SD4_nRESET_OUT line for eMMC memory
to perform complete reboot on Odroid X2/U3 boards.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
---
arch/arm/dts/exynos4412-odroid.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/exynos4412-odroid.dts
b/arch/arm/dts/exynos4412-odroid.dts
index ecb3e23..519a7dd 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -90,4 +90,9 @@
reg = 0x125B 0x100;
};
};
+
+ emmc-reset {
+ compatible = samsung,emmc-reset;
+ reset-gpio = gpk1 2 0;
+ };
};
Shouldn't this go in the relevant sdhci node instead of its own node?
Jaehoon, is it reasonable?
Thanks.
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Re: [U-Boot] [PATCH 1/3] samsung: board: support eMMC reset using DT
On 01/09/2015 08:23 AM, Sjoerd Simons wrote:
On Thu, 2015-01-08 at 14:44 +0900, Joonyoung Shim wrote:
Some exynos boards require special handling of SD4_nRESET_OUT line for
eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards.
This will support eMMC reset using DT from reset_misc of samsung common
board file and each board files can support eMMC reset on non DT case.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
diff --git a/doc/device-tree-bindings/exynos/emmc-reset.txt
b/doc/device-tree-bindings/exynos/emmc-reset.txt
new file mode 100644
index 000..e48e508
--- /dev/null
+++ b/doc/device-tree-bindings/exynos/emmc-reset.txt
@@ -0,0 +1,15 @@
+* Samsung eMMC reset
+
+Some exynos boards require special handling of SD4_nRESET_OUT line for eMMC
+memory to perform complete reboot.
Nitpick, on XU3 the line you apparently need to twiddle is
SD0_nRESET_OUT.
Is this type of usage of this pin specific to the Odroid Exynos boards
or potentially on more boards? (Sorry for the simple questions, but my
exynos documentation just says the line exists not what its intended
usage is).
In case of Exynos4, eMMC can be used with sdhci controller or dw-mmc controller.
So Pin name should be used to SD0 or SD4.
But Exynos5 is only supported the dw-mmc controller.
(So eMMC is used pin-name as SD0.)
Best Regards,
Jaehoon Chung
Fwiw, I did a quick check in the linux code and it doesn't seem to be
using those pins for currently for any boards. However my X2 does
successfully reset/reboot in u-boot and linux, so it seems optional
there. The XU3 does fail to reset itself, so it seems required for that
board.
+Required properties:
+- compatible: should be samsung,emmc-reset
+- reset-gpio: gpio chip for eMMC reset.
+
+Example:
+
+emmc-reset {
+compatible = samsung,emmc-reset;
+reset-gpio = gpk1 2 0;
+};
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Re: [U-Boot] [PATCH] usb: gadget: pxa25x_udc: fix use-before-initialized bug
On Thursday, January 08, 2015 at 07:19:35 PM, Nable wrote: Hi! You can use [PATCH RESEND], which is probably much clearer in expressing the intent. You might add a short note just before the diffstat saying that you only updated the SoB line and author to match the real deal, but didn't change the patch contents. I've edited my patch and it's still applies on to top HEAD of master branch, so I've sent fixed version to mailing list. Thanks! Thank you for mentioning this idea of commentaries before diffstat output, I've never heard about it. It's mostly useful to save reviewers the time figuring out what changed in the patch and such message never propagates into the applied patch in the tree :) You can read [1] for the finer points of patch submission process, but TL;DR it's pretty much the same as Linux ;-) Sounds like a nice joke! In fact, I'm doing my first steps in open-source software, so sending patches to Linux is something like a far dream. But if I reach that stage someday, then I'll be able to say that it's pretty much the same as for U-Boot. Heh, everyone's been there at some point. Good luck and have fun :) [1] http://www.denx.de/wiki/U-Boot/Patches#General_Patch_Submission_Rules I've studied [1] yesterday, and looked through it again today, so I hope that I'm doing everything in a right way this time. Yeah, no worries. You'll quickly get the hang of it and someone will remind you in case you screw up bigtime anyway ;-) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] samsung: board: support eMMC reset using DT
On 09/01/15 16:31, Joonyoung Shim wrote:
+Cc Jaehoon,
On 01/09/2015 03:18 AM, Simon Glass wrote:
Hi Joonyoung,
On 7 January 2015 at 22:44, Joonyoung Shim jy0922.s...@samsung.com wrote:
Some exynos boards require special handling of SD4_nRESET_OUT line for
eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards.
This will support eMMC reset using DT from reset_misc of samsung common
board file and each board files can support eMMC reset on non DT case.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
---
board/samsung/common/board.c | 27
++
board/samsung/odroid/odroid.c | 2 +-
doc/device-tree-bindings/exynos/emmc-reset.txt | 15 ++
3 files changed, 43 insertions(+), 1 deletion(-)
create mode 100644 doc/device-tree-bindings/exynos/emmc-reset.txt
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index c04ab3c..3218463 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -40,6 +40,8 @@ __weak int exynos_power_init(void)
return 0;
}
+__weak void exynos_reset_misc(void) {}
+
#if defined CONFIG_EXYNOS_TMU
/* Boot Time Thermal Analysis for SoC temperature threshold breach */
static void boot_temp_check(void)
@@ -400,3 +402,28 @@ int misc_init_r(void)
return 0;
}
#endif
+
+void reset_misc(void)
+{
+#ifdef CONFIG_OF_CONTROL
I think all Samsung boards have this defined, so this #ifdef can be removed.
OK, if it is true, we can remove this and i will not to support non DT case.
It's OK.
Thanks,
Minkyu Kang.
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Re: [U-Boot] [PATCH 07/18] dm: i2c: s3c24x0: adjust to dm-i2c api
Hello Przemyslaw Marczak,
just some nitpick ...
Am 08.01.2015 12:33, schrieb Przemyslaw Marczak:
This commit adjusts the s3c24x0 driver to new i2c api
based on driver-model. The driver supports standard
and high-speed i2c as previous.
Tested on Trats2 and Arndale (also with HS).
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Heiko Schocher h...@denx.de
Cc: Minkyu Kang mk7.k...@samsung.com
---
drivers/i2c/s3c24x0_i2c.c | 254 --
1 file changed, 222 insertions(+), 32 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index fd328f0..c21d479 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -9,8 +9,9 @@
* as they seem to have the same I2C controller inside.
* The different address mapping is handled by the s3c24xx.h files below.
*/
-
#include common.h
+#include errno.h
+#include dm.h
#include fdtdec.h
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#include asm/arch/clk.h
@@ -121,13 +122,23 @@
#define CONFIG_MAX_I2C_NUM 1
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* For SPL boot some boards need i2c before SDRAM is initialised so force
* variables to live in SRAM
*/
+#ifdef CONFIG_SYS_I2C
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
__attribute__((section(.data)));
+#endif
+enum exynos_i2c_type {
+ EXYNOS_I2C_STD,
+ EXYNOS_I2C_HS,
+};
+
+#ifdef CONFIG_SYS_I2C
/**
* Get a pointer to the given bus index
*
@@ -147,6 +158,7 @@ static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
debug(Undefined bus: %d\n, bus_idx);
return NULL;
}
+#endif
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
static int GetI2CSDA(void)
@@ -251,6 +263,7 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
writel(readl(i2c-iiccon) ~I2CCON_IRPND, i2c-iiccon);
}
+#ifdef CONFIG_SYS_I2C
static struct s3c24x0_i2c *get_base_i2c(int bus)
{
#ifdef CONFIG_EXYNOS4
@@ -267,6 +280,7 @@ static struct s3c24x0_i2c *get_base_i2c(int bus)
return s3c24x0_get_base_i2c();
#endif
}
+#endif
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
@@ -398,18 +412,20 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus
*i2c_bus)
hsi2c_ch_init(i2c_bus);
}
+#ifdef CONFIG_SYS_I2C
static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int
slaveadd)
{
struct s3c24x0_i2c *i2c;
struct s3c24x0_i2c_bus *bus;
-
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#endif
ulong start_time = get_timer(0);
- /* By default i2c channel 0 is the current bus */
i2c = get_base_i2c(adap-hwadapnr);
+ bus = i2c_bus[adap-hwadapnr];
+ if (!bus)
+ return;
/*
* In case the previous transfer is still going, wait to give it a
@@ -470,12 +486,13 @@ static void s3c24x0_i2c_init(struct i2c_adapter *adap,
int speed, int slaveadd)
#endif
}
#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
+
i2c_ch_init(i2c, speed, slaveadd);
- bus = i2c_bus[adap-hwadapnr];
bus-active = true;
bus-regs = i2c;
}
+#endif /* CONFIG_SYS_I2C */
/*
* Poll the appropriate bit of the fifo status register until the interface is
@@ -545,7 +562,6 @@ static int hsi2c_prepare_transaction(struct exynos5_hsi2c
*i2c,
bool issue_stop)
{
u32 conf;
-
why do you delete this empty line?
conf = len | HSI2C_MASTER_RUN;
if (issue_stop)
@@ -698,14 +714,24 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
return rv;
}
+#ifdef CONFIG_SYS_I2C
static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
+ unsigned int speed)
+#else
+static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
+#endif
{
struct s3c24x0_i2c_bus *i2c_bus;
-
here too ...
+#ifdef CONFIG_SYS_I2C
i2c_bus = get_bus(adap-hwadapnr);
+#else
+ if (!dev)
+ return -ENODEV;
+
+ i2c_bus = dev_get_priv(dev);
+#endif
if (!i2c_bus)
- return -1;
+ return -ENODEV;
i2c_bus-clock_frequency = speed;
@@ -715,23 +741,12 @@ static unsigned int s3c24x0_i2c_set_bus_speed(struct
i2c_adapter *adap,
hsi2c_ch_init(i2c_bus);
} else {
i2c_ch_init(i2c_bus-regs, i2c_bus-clock_frequency,
- CONFIG_SYS_I2C_S3C24X0_SLAVE);
+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
}
return 0;
}
-#ifdef CONFIG_EXYNOS5
-static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- /* This
Re: [U-Boot] [PATCH 08/18] exynos5: config: prepare for dm i2c support
Hello Przemyslaw Marczak, Am 08.01.2015 12:33, schrieb Przemyslaw Marczak: This commit allows for test i2c drivers with new i2c api on Exynos5xxx based boards. The S3C24X0 I2C driver supports driver model I2C api, but i2c peripherials drivers on exynos5 boards doesn't. So this commit allows for test ported driver before switch the Exynos5 boards to DM I2C at all. Hmm... so this is just a patch for test purposes not for mainline? Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/exynos5-common.h | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ad63f3c..b7af8a5 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -54,13 +54,6 @@ #define CONFIG_CMD_DTT #define CONFIG_TMU_CMD_DTT -/* TPM */ -#define CONFIG_TPM -#define CONFIG_CMD_TPM -#define CONFIG_TPM_TIS_I2C -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 - /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 #define CONFIG_SUPPORT_EMMC_BOOT @@ -126,15 +119,29 @@ #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) /* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C +#if 0 /* For test */ +#define CONFIG_DM_I2C +#endif Hmm.. no, please no dead code in mainline ... maybe you enable CONFIG_DM_I2C if CONFIG_DM is set? bye, Heiko #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0_SLAVE0x0 +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C +#define CONFIG_I2C_MULTI_BUS +#endif /* ifndef CONFIG_DM_I2C */ #define CONFIG_I2C_EDID +/* TPM */ +#ifndef CONFIG_DM_I2C +#define CONFIG_TPM +#define CONFIG_CMD_TPM +#define CONFIG_TPM_TIS_I2C +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 +#endif + /* SPI */ #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Nokia RX-51: Do not call secure PPA routine on non secure devices
Hi Pali Rohár, Have you tested this patch on a secure device (as the nokia n900)? Regards, Georges Le 08/01/2015 10:11, Pali Rohár a écrit : Since commit 41623c91b09a0c865fab41acdaff30f060f29ad6 u-boot running in qemu is crashing in function do_omap3_emu_romcode_call(). RX-51 board uses this function for Cortex-A8 errata 430973 workaround (Set IBE bit in ACR) which is needed only on real secure device and not in qemu. This board patch just disable calling secure PPA routine on non secure devices. Qemu implements GP device and with this patch u-boot is working in qemu again. Signed-off-by: Pali Rohár pali.ro...@gmail.com --- board/nokia/rx51/rx51.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index b6b8ad6..08fcaf2 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -422,8 +422,12 @@ int misc_init_r(void) /* * Cortex-A8(r1p0..r1p2) errata 430973 workaround * Set IBE bit in Auxiliary Control Register +* +* Call this routine only on real secure device +* Qemu does not implement secure PPA and crash */ - omap3_update_aux_cr_secure_rx51(1 6, 0); + if (get_device_type() == HS_DEVICE) + omap3_update_aux_cr_secure_rx51(1 6, 0); return 0; } ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 10/11] board/T1040qds: Add VSC9953 support for T1040qds board
On 12/19/2014 09:02 AM, Codrin Ciubotariu wrote: This patch configures and initializes the L2 switch on T1040QDS board. The L2 switch ports must be initialized according to the SerDes protocols. Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com Change-Id: I329f9cc1b1be745da23151e78831d8a3219b7f97 --- board/freescale/t1040qds/eth.c | 93 ++ include/configs/T1040QDS.h | 4 ++ 2 files changed, 97 insertions(+) diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 2f8e753..ba6f518 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -18,6 +18,9 @@ #include fsl_mdio.h #include malloc.h #include asm/fsl_dtsec.h +#ifdef CONFIG_VSC9953 +#include vsc9953.h +#endif Don't put ifdef for header file. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] qspi:fsl implement AHB read
On 8 January 2015 at 15:48, Peng Fan peng@freescale.com wrote:
Hi, Jagan
On 1/8/2015 2:20 PM, Jagan Teki wrote:
On 8 January 2015 at 08:10, Peng Fan peng@freescale.com wrote:
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using
IP register and AHB bus.
The original driver only supports reading data from IP interface. The IC
team suggests to use AHB read which is faster then IP read. Using AHB
read,
we can directly memcpy, a missed access to the buffer will cause the
controller to clear the buffer and use the SEQID stored in bfgencr
register
to initiate a read from flash device.
So for the read connections - controller is connected through IP and
AHB interface
is it? and I'm thinking these two are bus protocols which can use any
peripheral unlike
qspi.
Yeah. fsl qspi controller is connected through IP and AHB interface.
register access through IP interface, Data access can use IP interface or
AHB interface. There is a memory mapped region for AHB data read. If want
to use AHB data read for QSPI, the controller should be configured by IP
interface, and then can use memcpy to read data. This patch adds the
configuration for using QSPI AHB read, this configuration is dedicated for
qspi.
Yes - I understand.
I'm thinking this ahb is a generic but not only specific to qspi the
read of this
interface should be generic somewhere in arch code so-that fsl_qspi will call
those routines on based on the need. - does it make sense?
Since AHB bus is 64 bit width, we can not set MCR register using 32bit.
In
order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit
Little
endian but not 32bit Little endia.
Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to
use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore
it.
Actually if Vybrid is migrated to use AHB read, this option can be
removed and
IP read function can be discared. The reason to introduce this option
is that only i.MX SOC is tested in my side, no Vybrid platform for me.
So, where did you define?
The configuration is defined in board header file in mx6sxsabresd.h, using
#define CONFIG_SYS_FSL_QSPI_AHB.
Yes I saw in 2/2
In spi_setup_slave, the original piece code to set AHB is deleted, since
Vybrid platform does not use this to intiate AHB read. Instead, add
qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/spi/fsl_qspi.c | 137
+
drivers/spi/fsl_qspi.h | 15 ++
2 files changed, 142 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ad4f4ce..5e0b069 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -263,6 +263,110 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lckcr, QSPI_LCKCR_LOCK);
}
+#if defined(CONFIG_SYS_FSL_QSPI_AHB)
+/*
+ * If we have changed the content of the flash by writing or erasing,
+ * we need to invalidate the AHB buffer. If we do not do so, we may read
out
+ * the wrong data. The spec tells us reset the AHB domain and Serial
Flash
+ * domain at the same time.
+ */
+static inline void qspi_ahb_invalid(struct fsl_qspi *q)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q-reg_base;
+ u32 reg;
+
+ reg = qspi_read32(regs-mcr);
+ reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
+ qspi_write32(regs-mcr, reg);
+
+ /*
+* The minimum delay : 1 AHB + 2 SFCK clocks.
+* Delay 1 us is enough.
+*/
+ udelay(1);
+
+ reg = ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
+ qspi_write32(regs-mcr, reg);
+}
+
+/* Read out the data from the AHB buffer. */
+static inline void qspi_ahb_read(struct fsl_qspi *q, u8 *rxbuf, int len)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q-reg_base;
+ u32 mcr_reg;
+
+ mcr_reg = qspi_read32(regs-mcr);
+
+ qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK |
QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+
+ /* Read out the data directly from the AHB buffer. */
+ memcpy(rxbuf, (u8 *)(q-amba_base + q-sf_addr), len);
+
+ qspi_write32(regs-mcr, mcr_reg);
+}
+
+static void qspi_enable_ddr_mode(struct fsl_qspi_regs *regs)
+{
+ u32 reg, reg2;
+
+ reg = qspi_read32(regs-mcr);
+ /* Disable the module */
+ qspi_write32(regs-mcr, reg | QSPI_MCR_MDIS_MASK);
+
+ /* Set the Sampling Register for DDR */
+ reg2 = qspi_read32(regs-smpr);
+ reg2 = ~QSPI_SMPR_DDRSMP_MASK;
+ reg2 |= (2 QSPI_SMPR_DDRSMP_SHIFT);
+ qspi_write32(regs-smpr, reg2);
+
+ /* Enable the module again (enable the DDR too) */
+ reg |= QSPI_MCR_DDR_EN_MASK;
+ /* Enable bit 29 for imx6sx
[U-Boot] [PATCH] gpt: Fix the protective MBR partition size
According to the UEFI Spec (Table 16, section 5.2.3 of the version 2.4 Errata
B), the protective MBR partition record size must be set to the size of the
disk minus one, in LBAs.
However, the current code was setting the size as the total number of LBAs on
the disk, resulting in an off-by-one error.
This confused the AM335x ROM code, and will probably confuse other tools as
well.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
disk/part_efi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 612f0926b62b..5ca17c138e96 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -240,7 +240,7 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc)
p_mbr-signature = MSDOS_MBR_SIGNATURE;
p_mbr-partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT;
p_mbr-partition_record[0].start_sect = 1;
- p_mbr-partition_record[0].nr_sects = (u32) dev_desc-lba;
+ p_mbr-partition_record[0].nr_sects = (u32) dev_desc-lba - 1;
/* Write MBR sector to the MMC device */
if (dev_desc-block_write(dev_desc-dev, 0, 1, p_mbr) != 1) {
--
2.2.1
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Re: [U-Boot] [PATCH 1/2] qspi:fsl implement AHB read
On 1/8/2015 7:21 PM, Jagan Teki wrote:
On 8 January 2015 at 15:48, Peng Fan peng@freescale.com wrote:
Hi, Jagan
On 1/8/2015 2:20 PM, Jagan Teki wrote:
On 8 January 2015 at 08:10, Peng Fan peng@freescale.com wrote:
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using
IP register and AHB bus.
The original driver only supports reading data from IP interface. The IC
team suggests to use AHB read which is faster then IP read. Using AHB
read,
we can directly memcpy, a missed access to the buffer will cause the
controller to clear the buffer and use the SEQID stored in bfgencr
register
to initiate a read from flash device.
So for the read connections - controller is connected through IP and
AHB interface
is it? and I'm thinking these two are bus protocols which can use any
peripheral unlike
qspi.
Yeah. fsl qspi controller is connected through IP and AHB interface.
register access through IP interface, Data access can use IP interface or
AHB interface. There is a memory mapped region for AHB data read. If want
to use AHB data read for QSPI, the controller should be configured by IP
interface, and then can use memcpy to read data. This patch adds the
configuration for using QSPI AHB read, this configuration is dedicated for
qspi.
Yes - I understand.
I'm thinking this ahb is a generic but not only specific to qspi the
read of this
interface should be generic somewhere in arch code so-that fsl_qspi will call
those routines on based on the need. - does it make sense?
The AHB read function is just memcpy. This original code use
qspi_op_read to read data from IP interface. In this patch, if
configured CONFIG_FSL_QSPI_AHB_READ, use qsp_ahb_read. This function is
very simple, as following:
+mcr_reg = qspi_read32(regs-mcr);
+
+qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+
+/* Read out the data directly from the AHB buffer. */
+memcpy(rxbuf, (u8 *)(q-amba_base + q-sf_addr), len);
+
+qspi_write32(regs-mcr, mcr_reg);
It's just a wrapper function to call memcpy and save/restore qspi mcr
register, nothing else. I think it's not needed to wrap memcpy and move
it to arch code, since it is simple and contains qspi register save and
restore.
Since AHB bus is 64 bit width, we can not set MCR register using 32bit.
In
order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit
Little
endian but not 32bit Little endia.
Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to
use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore
it.
Actually if Vybrid is migrated to use AHB read, this option can be
removed and
IP read function can be discared. The reason to introduce this option
is that only i.MX SOC is tested in my side, no Vybrid platform for me.
So, where did you define?
The configuration is defined in board header file in mx6sxsabresd.h, using
#define CONFIG_SYS_FSL_QSPI_AHB.
Yes I saw in 2/2
In spi_setup_slave, the original piece code to set AHB is deleted, since
Vybrid platform does not use this to intiate AHB read. Instead, add
qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/spi/fsl_qspi.c | 137
+
drivers/spi/fsl_qspi.h | 15 ++
2 files changed, 142 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ad4f4ce..5e0b069 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -263,6 +263,110 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lckcr, QSPI_LCKCR_LOCK);
}
+#if defined(CONFIG_SYS_FSL_QSPI_AHB)
+/*
+ * If we have changed the content of the flash by writing or erasing,
+ * we need to invalidate the AHB buffer. If we do not do so, we may read
out
+ * the wrong data. The spec tells us reset the AHB domain and Serial
Flash
+ * domain at the same time.
+ */
+static inline void qspi_ahb_invalid(struct fsl_qspi *q)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q-reg_base;
+ u32 reg;
+
+ reg = qspi_read32(regs-mcr);
+ reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
+ qspi_write32(regs-mcr, reg);
+
+ /*
+* The minimum delay : 1 AHB + 2 SFCK clocks.
+* Delay 1 us is enough.
+*/
+ udelay(1);
+
+ reg = ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
+ qspi_write32(regs-mcr, reg);
+}
+
+/* Read out the data from the AHB buffer. */
+static inline void qspi_ahb_read(struct fsl_qspi *q, u8 *rxbuf, int len)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q-reg_base;
+ u32 mcr_reg;
+
+ mcr_reg = qspi_read32(regs-mcr);
+
+ qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK |
QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+
+ /* Read out the data
[U-Boot] [PATCH 00/18] Exynos: move i2c driver to dm api
This patchset adds support to driver model i2c api for Exynos i2c driver. Few boards are using this driver, but the board peripherals are not ported to the new api yet. So this can't be enabled with the full board functionality. In this case each Exynos5 based boards have fixed config dependencies for testing the dm i2c api with the new i2c driver. This will facilitate the peripheral porting. For test, just enable CONFIG_DM_I2C in exynos5-common.h. The i2c command should work with this as previous. This patchset also provides some changes related to Exynos4 boards. Most Exynos4 boards requires only pmic support, and this will be done with the new pmic framework soon. Przemyslaw Marczak (18): arndale: config: disable max77686 support exynos5250: config: disable max77686 driver smdk5250: config: enable max77686 driver support exynos4: dts: add missing i2c properties arndale: dts: add missing i2c aliases exynos5: pinmux: check flag for i2c config dm: i2c: s3c24x0: adjust to dm-i2c api exynos5: config: prepare for dm i2c support exynos5250: config: temporary disable sound for dm i2c arndale: config: temporary disable pmic for dm i2c exynos5-dt: config: temporary disable pmic for dm i2c snow: config: temporary disable cros ec i2c for dm i2c smdk5250: config: temporary disable pmic for dm i2c smdk5420: board: fix build warning for testing dm i2c peach-pi: config: temporary disable video parade for dm i2c peach-pit: config: temporary disable video parade for dm i2c trats2: board: cleanup power init code trats2: config: disable i2c peripherals if testing dm i2c arch/arm/cpu/armv7/exynos/pinmux.c | 27 ++-- arch/arm/dts/exynos4.dtsi | 24 ++-- arch/arm/dts/exynos5250-arndale.dts | 8 ++ board/samsung/smdk5420/smdk5420.c | 2 +- board/samsung/trats2/trats2.c | 144 +++- drivers/i2c/s3c24x0_i2c.c | 254 +++- include/configs/arndale.h | 5 +- include/configs/exynos5-common.h| 29 ++-- include/configs/exynos5-dt-common.h | 2 + include/configs/exynos5250-common.h | 5 +- include/configs/peach-pi.h | 2 + include/configs/peach-pit.h | 2 + include/configs/smdk5250.h | 4 + include/configs/snow.h | 4 +- include/configs/trats2.h| 17 ++- 15 files changed, 395 insertions(+), 134 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 04/18] exynos4: dts: add missing i2c properties
This patch modify i2c nodes in exynos4.dtsi with:
- adding proper interrupts arrays for each i2c node,
which allows to decode periph id
- add reg address for each i2c node for i2c driver internal use
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
---
arch/arm/dts/exynos4.dtsi | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 77fad48..0e46622 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -51,56 +51,64 @@
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 0 0 0;
+ reg = 0x1386 0x100;
+ interrupts = 0 56 0;
};
i2c@1387 {
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 1 1 0;
+ reg = 0x1387 0x100;
+ interrupts = 1 57 0;
};
i2c@1388 {
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 2 2 0;
+ reg = 0x1388 0x100;
+ interrupts = 2 58 0;
};
i2c@1389 {
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 3 3 0;
+ reg = 0x1389 0x100;
+ interrupts = 3 59 0;
};
i2c@138a {
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 4 4 0;
+ reg = 0x138a 0x100;
+ interrupts = 4 60 0;
};
i2c@138b {
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 5 5 0;
+ reg = 0x138b 0x100;
+ interrupts = 5 61 0;
};
i2c@138c {
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 6 6 0;
+ reg = 0x138c 0x100;
+ interrupts = 6 62 0;
};
i2c@138d {
#address-cells = 1;
#size-cells = 0;
compatible = samsung,s3c2440-i2c;
- interrupts = 7 7 0;
+ reg = 0x138d 0x100;
+ interrupts = 7 63 0;
};
sdhci@1251 {
--
1.9.1
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[U-Boot] [PATCH 02/18] exynos5250: config: disable max77686 driver
This PMIC is not common for all Exynos5250 based boards, so should be romoved from common config. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/exynos5250-common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 6714313..ae0e5ff 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -28,9 +28,6 @@ #define CONFIG_SYS_INIT_SP_ADDRCONFIG_IRAM_STACK -/* PMIC */ -#define CONFIG_POWER_MAX77686 - /* Sound */ #define CONFIG_CMD_SOUND #ifdef CONFIG_CMD_SOUND -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/18] smdk5250: config: enable max77686 driver support
This commit enable support for the above driver, which was disabled in common config. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/smdk5250.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 8395372..3b06d30 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -18,6 +18,8 @@ #include configs/exynos5250-common.h +/* PMIC */ +#define CONFIG_POWER_MAX77686 #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/18] arndale: config: disable max77686 support
There is no MAX77686 pmic on this board, so the driver support should be removed. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/arndale.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index d68993b..3ad4a9b 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -51,8 +51,6 @@ /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77686 - #define CONFIG_PREBOOT -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/18] exynos5-dt: config: temporary disable pmic for dm i2c
Disable pmic if CONFIG_DM_I2C in exynos5-common.h is enabled. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/exynos5-dt-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 9cef0b0..a774a41 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -19,9 +19,11 @@ #include exynos5-common.h /* PMIC */ +#ifndef CONFIG_DM_I2C #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_TPS65090 +#endif /* Enable keyboard */ #define CONFIG_CROS_EC /* CROS_EC protocol */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/18] exynos5: config: prepare for dm i2c support
This commit allows for test i2c drivers with new i2c api on Exynos5xxx based boards. The S3C24X0 I2C driver supports driver model I2C api, but i2c peripherials drivers on exynos5 boards doesn't. So this commit allows for test ported driver before switch the Exynos5 boards to DM I2C at all. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/exynos5-common.h | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ad63f3c..b7af8a5 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -54,13 +54,6 @@ #define CONFIG_CMD_DTT #define CONFIG_TMU_CMD_DTT -/* TPM */ -#define CONFIG_TPM -#define CONFIG_CMD_TPM -#define CONFIG_TPM_TIS_I2C -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 - /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR0x02020030 #define CONFIG_SUPPORT_EMMC_BOOT @@ -126,15 +119,29 @@ #define SPI_FLASH_UBOOT_POS(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) /* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C +#if 0 /* For test */ +#define CONFIG_DM_I2C +#endif #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0_SLAVE0x0 +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C +#define CONFIG_I2C_MULTI_BUS +#endif /* ifndef CONFIG_DM_I2C */ #define CONFIG_I2C_EDID +/* TPM */ +#ifndef CONFIG_DM_I2C +#define CONFIG_TPM +#define CONFIG_CMD_TPM +#define CONFIG_TPM_TIS_I2C +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 +#endif + /* SPI */ #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 15/18] peach-pi: config: temporary disable video parade for dm i2c
Disable video parade driver if CONFIG_DM_I2C in exynos5-common.h is enabled. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/peach-pi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index a1c980d..7515e96 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -32,7 +32,9 @@ #define CONFIG_SYS_PROMPT Peach-Pi # #define CONFIG_IDENT_STRING for Peach-Pi +#ifndef CONFIG_DM_I2C #define CONFIG_VIDEO_PARADE +#endif /* Display */ #define CONFIG_LCD -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/18] arndale: config: temporary disable pmic for dm i2c
This commit disables pmic support for testing dm i2c api on arndale. There is no sense for move the current pmic framework to new i2c api, since the new power framework will be ready soon. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/arndale.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 3ad4a9b..b3d3868 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -49,9 +49,10 @@ #define CONFIG_SYS_INIT_SP_ADDRCONFIG_IRAM_STACK /* PMIC */ +#ifndef CONFIG_DM_I2C #define CONFIG_PMIC #define CONFIG_POWER_I2C - +#endif #define CONFIG_PREBOOT #define CONFIG_S5P_PA_SYSRAM 0x0202 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 05/18] arndale: dts: add missing i2c aliases
Without this alias setting, the seq numbers
of the i2c devices are wrong.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
---
arch/arm/dts/exynos5250-arndale.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/exynos5250-arndale.dts
b/arch/arm/dts/exynos5250-arndale.dts
index 202f2ea..21c0a21 100644
--- a/arch/arm/dts/exynos5250-arndale.dts
+++ b/arch/arm/dts/exynos5250-arndale.dts
@@ -15,6 +15,14 @@
compatible = samsung,arndale, samsung,exynos5250;
aliases {
+ i2c0 = /i2c@12c6;
+ i2c1 = /i2c@12c7;
+ i2c2 = /i2c@12c8;
+ i2c3 = /i2c@12c9;
+ i2c4 = /i2c@12ca;
+ i2c5 = /i2c@12cb;
+ i2c6 = /i2c@12cc;
+ i2c7 = /i2c@12cd;
serial0 = /serial@12C2;
console = /serial@12C2;
};
--
1.9.1
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[U-Boot] [PATCH 16/18] peach-pit: config: temporary disable video parade for dm i2c
Disable video parade driver if CONFIG_DM_I2C in exynos5-common.h is enabled. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/peach-pit.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 6516a72..d0c40d3 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -32,7 +32,9 @@ #define CONFIG_SYS_PROMPT Peach-Pit # #define CONFIG_IDENT_STRING for Peach-Pit +#ifndef CONFIG_DM_I2C #define CONFIG_VIDEO_PARADE +#endif /* Display */ #define CONFIG_LCD -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/18] snow: config: temporary disable cros ec i2c for dm i2c
Disable cros ec i2c driver if CONFIG_DM_I2C in exynos5-common.h is enabled. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/snow.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/snow.h b/include/configs/snow.h index 7eaa586..b42766d 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -19,10 +19,10 @@ #include configs/exynos5250-common.h #include configs/exynos5-dt-common.h - +#ifndef CONFIG_DM_I2C #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C - +#endif #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/18] exynos5: pinmux: check flag for i2c config
Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Akshay Saraswat aksha...@samsung.com
Cc: Minkyu Kang mk7.k...@samsung.com
---
arch/arm/cpu/armv7/exynos/pinmux.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 94d0297..b2c5494 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
static void exynos5_i2c_config(int peripheral, int flags)
{
+ int func01, func23;
+
+/* flags only for High-Speed I2C */
+ if (flags) {
+ func01 = 4;
+ func23 = 4;
+ } else {
+ func01 = 2;
+ func23 = 3;
+ }
+
switch (peripheral) {
case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
--
1.9.1
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[U-Boot] [PATCH 17/18] trats2: board: cleanup power init code
This patch makes cleanup in:
- proper ifdefs to the power related functions
- check for pmic null pointers before use
And is a preparation for enabling dm i2c support.
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Lukasz Majewski l.majew...@samsung.com
Cc: Jaehoon Chung jh80.ch...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
---
board/samsung/trats2/trats2.c | 144 --
1 file changed, 82 insertions(+), 62 deletions(-)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index a737749..caa885d 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -151,8 +151,6 @@ int exynos_early_init_f(void)
return 0;
}
-static int pmic_init_max77686(void);
-
int exynos_init(void)
{
struct exynos4_power *pwr =
@@ -174,6 +172,63 @@ int exynos_init(void)
return 0;
}
+#ifdef CONFIG_POWER
+static int pmic_init_max77686(void)
+{
+ struct pmic *p;
+
+ p = pmic_get(MAX77686_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ /* BUCK/LDO Output Voltage */
+ max77686_set_ldo_voltage(p, 21, 280); /* LDO21 VTF_2.8V */
+ max77686_set_ldo_voltage(p, 23, 330); /* LDO23 TSP_AVDD_3.3V*/
+ max77686_set_ldo_voltage(p, 24, 180); /* LDO24 TSP_VDD_1.8V */
+
+ /* BUCK/LDO Output Mode */
+ max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */
+ max77686_set_buck_mode(p, 2, OPMODE_ON);/* BUCK2 VARM_1.0V_AP */
+ max77686_set_buck_mode(p, 3, OPMODE_ON);/* BUCK3 VINT_1.0V_AP */
+ max77686_set_buck_mode(p, 4, OPMODE_ON);/* BUCK4 VG3D_1.0V_AP */
+ max77686_set_buck_mode(p, 5, OPMODE_ON);/* BUCK5 VMEM_1.2V_AP */
+ max77686_set_buck_mode(p, 6, OPMODE_ON);/* BUCK6 VCC_SUB_1.35V*/
+ max77686_set_buck_mode(p, 7, OPMODE_ON);/* BUCK7 VCC_SUB_2.0V */
+ max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */
+ max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/
+
+ max77686_set_ldo_mode(p, 1, OPMODE_LPM);/* LDO1 VALIVE_1.0V_AP*/
+ max77686_set_ldo_mode(p, 2, OPMODE_STANDBY);/* LDO2 VM1M2_1.2V_AP */
+ max77686_set_ldo_mode(p, 3, OPMODE_LPM);/* LDO3 VCC_1.8V_AP */
+ max77686_set_ldo_mode(p, 4, OPMODE_LPM);/* LDO4 VCC_2.8V_AP */
+ max77686_set_ldo_mode(p, 5, OPMODE_OFF);/* LDO5_VCC_1.8V_IO */
+ max77686_set_ldo_mode(p, 6, OPMODE_STANDBY);/* LDO6 VMPLL_1.0V_AP */
+ max77686_set_ldo_mode(p, 7, OPMODE_STANDBY);/* LDO7 VPLL_1.0V_AP */
+ max77686_set_ldo_mode(p, 8, OPMODE_LPM);/* LDO8 VMIPI_1.0V_AP */
+ max77686_set_ldo_mode(p, 9, OPMODE_OFF);/* CAM_ISP_MIPI_1.2*/
+ max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/
+ max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/
+ max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/
+ max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */
+ max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */
+ max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/
+ max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/
+ max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/
+ max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/
+ max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */
+ max77686_set_ldo_mode(p, 20, OPMODE_ON);/* LDO20 VDDQ_PRE_1.8V*/
+ max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */
+ max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/
+ max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/
+ max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */
+ max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */
+ max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/
+ return 0;
+}
+
int exynos_power_init(void)
{
int chrg;
@@ -239,10 +294,12 @@ int exynos_power_init(void)
return 0;
}
+#endif /* CONFIG_POWER */
#ifdef CONFIG_USB_GADGET
static int s5pc210_phy_control(int on)
{
+#ifdef CONFIG_POWER
int ret = 0;
unsigned int val;
struct pmic *p, *p_pmic, *p_muic;
@@ -299,7 +356,7 @@ static int s5pc210_phy_control(int on)
if (ret)
return -1;
-
+#endif
return 0;
}
@@ -319,97 +376,60 @@ int board_usb_init(int index, enum usb_init_type init)
int g_dnl_board_usb_cable_connected(void)
{
- struct pmic *muic = pmic_get(MAX77693_MUIC);
+#ifdef CONFIG_POWER
+ struct
[U-Boot] [PATCH 18/18] trats2: config: disable i2c peripherals if testing dm i2c
Most i2c peripherals for this board doesn't support new i2c api. So CONFIG_DM_I2C on this board can be enabled for test only. The i2c command works fine with it. This is the first step before adding support to the new power framework soon. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Lukasz Majewski l.majew...@samsung.com Cc: Jaehoon Chung jh80.ch...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/trats2.h | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 42481ab..8b099dd 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -159,15 +159,18 @@ #define CONFIG_RANDOM_UUID /* I2C */ -#include asm/arch/gpio.h - +#if 0 /* For test */ +#define CONFIG_DM_I2C +#endif #define CONFIG_CMD_I2C - -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 10 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C #define CONFIG_MAX_I2C_NUM 8 + #define CONFIG_SYS_I2C_SOFT #define CONFIG_SYS_I2C_SOFT_SPEED 5 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 @@ -177,6 +180,8 @@ #define CONFIG_SOFT_I2C_READ_REPEATED_START #define CONFIG_SYS_I2C_INIT_BOARD +#include asm/arch/gpio.h + #ifndef __ASSEMBLY__ int get_soft_i2c_scl_pin(void); int get_soft_i2c_sda_pin(void); @@ -192,6 +197,7 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_POWER_MUIC_MAX77693 #define CONFIG_POWER_FG_MAX77693 #define CONFIG_POWER_BATTERY_TRATS2 +#endif /* ifndef CONFIG_DM_I2C */ /* Security subsystem - enable hw_rand() */ #define CONFIG_EXYNOS_ACE_SHA @@ -203,11 +209,13 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_MISC_INIT_R /* Download menu - Samsung common */ +#ifndef CONFIG_DM_I2C #define CONFIG_LCD_MENU #define CONFIG_LCD_MENU_BOARD /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ +#include power/pmic.h #include power/max77686_pmic.h #define KEY_PWR_PMIC_NAME MAX77686_PMIC @@ -219,6 +227,7 @@ int get_soft_i2c_sda_pin(void); #define KEY_VOL_UP_GPIOEXYNOS4X12_GPIO_X22 #define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 #endif /* __ASSEMBLY__ */ +#endif /* LCD console */ #define LCD_BPP LCD_COLOR16 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/18] exynos5250: config: temporary disable sound for dm i2c
This commit disables sound support for testing new i2c api for Exynos5250 boards. After move i2c part of sound drivers to the new i2c api, then this ifdef will be removed. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/exynos5250-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index ae0e5ff..a6a766a 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -29,7 +29,9 @@ #define CONFIG_SYS_INIT_SP_ADDRCONFIG_IRAM_STACK /* Sound */ +#ifndef CONFIG_DM_I2C #define CONFIG_CMD_SOUND +#endif #ifdef CONFIG_CMD_SOUND #define CONFIG_SOUND #define CONFIG_I2S_SAMSUNG -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/18] dm: i2c: s3c24x0: adjust to dm-i2c api
This commit adjusts the s3c24x0 driver to new i2c api
based on driver-model. The driver supports standard
and high-speed i2c as previous.
Tested on Trats2 and Arndale (also with HS).
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Heiko Schocher h...@denx.de
Cc: Minkyu Kang mk7.k...@samsung.com
---
drivers/i2c/s3c24x0_i2c.c | 254 --
1 file changed, 222 insertions(+), 32 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index fd328f0..c21d479 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -9,8 +9,9 @@
* as they seem to have the same I2C controller inside.
* The different address mapping is handled by the s3c24xx.h files below.
*/
-
#include common.h
+#include errno.h
+#include dm.h
#include fdtdec.h
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#include asm/arch/clk.h
@@ -121,13 +122,23 @@
#define CONFIG_MAX_I2C_NUM 1
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* For SPL boot some boards need i2c before SDRAM is initialised so force
* variables to live in SRAM
*/
+#ifdef CONFIG_SYS_I2C
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
__attribute__((section(.data)));
+#endif
+enum exynos_i2c_type {
+ EXYNOS_I2C_STD,
+ EXYNOS_I2C_HS,
+};
+
+#ifdef CONFIG_SYS_I2C
/**
* Get a pointer to the given bus index
*
@@ -147,6 +158,7 @@ static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
debug(Undefined bus: %d\n, bus_idx);
return NULL;
}
+#endif
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
static int GetI2CSDA(void)
@@ -251,6 +263,7 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
writel(readl(i2c-iiccon) ~I2CCON_IRPND, i2c-iiccon);
}
+#ifdef CONFIG_SYS_I2C
static struct s3c24x0_i2c *get_base_i2c(int bus)
{
#ifdef CONFIG_EXYNOS4
@@ -267,6 +280,7 @@ static struct s3c24x0_i2c *get_base_i2c(int bus)
return s3c24x0_get_base_i2c();
#endif
}
+#endif
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
@@ -398,18 +412,20 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus
*i2c_bus)
hsi2c_ch_init(i2c_bus);
}
+#ifdef CONFIG_SYS_I2C
static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct s3c24x0_i2c *i2c;
struct s3c24x0_i2c_bus *bus;
-
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#endif
ulong start_time = get_timer(0);
- /* By default i2c channel 0 is the current bus */
i2c = get_base_i2c(adap-hwadapnr);
+ bus = i2c_bus[adap-hwadapnr];
+ if (!bus)
+ return;
/*
* In case the previous transfer is still going, wait to give it a
@@ -470,12 +486,13 @@ static void s3c24x0_i2c_init(struct i2c_adapter *adap,
int speed, int slaveadd)
#endif
}
#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
+
i2c_ch_init(i2c, speed, slaveadd);
- bus = i2c_bus[adap-hwadapnr];
bus-active = true;
bus-regs = i2c;
}
+#endif /* CONFIG_SYS_I2C */
/*
* Poll the appropriate bit of the fifo status register until the interface is
@@ -545,7 +562,6 @@ static int hsi2c_prepare_transaction(struct exynos5_hsi2c
*i2c,
bool issue_stop)
{
u32 conf;
-
conf = len | HSI2C_MASTER_RUN;
if (issue_stop)
@@ -698,14 +714,24 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
return rv;
}
+#ifdef CONFIG_SYS_I2C
static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
+ unsigned int speed)
+#else
+static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
+#endif
{
struct s3c24x0_i2c_bus *i2c_bus;
-
+#ifdef CONFIG_SYS_I2C
i2c_bus = get_bus(adap-hwadapnr);
+#else
+ if (!dev)
+ return -ENODEV;
+
+ i2c_bus = dev_get_priv(dev);
+#endif
if (!i2c_bus)
- return -1;
+ return -ENODEV;
i2c_bus-clock_frequency = speed;
@@ -715,23 +741,12 @@ static unsigned int s3c24x0_i2c_set_bus_speed(struct
i2c_adapter *adap,
hsi2c_ch_init(i2c_bus);
} else {
i2c_ch_init(i2c_bus-regs, i2c_bus-clock_frequency,
- CONFIG_SYS_I2C_S3C24X0_SLAVE);
+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
}
return 0;
}
-#ifdef CONFIG_EXYNOS5
-static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- /* This will override the speed selected in the fdt for that port */
- debug(i2c_init(speed=%u, slaveaddr=0x%x)\n, speed, slaveaddr);
- if (i2c_set_bus_speed(speed))
-
[U-Boot] [PATCH 13/18] smdk5250: config: temporary disable pmic for dm i2c
Disable pmic if CONFIG_DM_I2C in exynos5-common.h is enabled. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/smdk5250.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 3b06d30..f57e94a 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -19,7 +19,9 @@ #include configs/exynos5250-common.h /* PMIC */ +#ifndef CONFIG_DM_I2C #define CONFIG_POWER_MAX77686 +#endif #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 14/18] smdk5420: board: fix build warning for testing dm i2c
If pmic is disabled for testing dm i2c then some unused
variable should be moved around proper ifdef in smdk5420.c
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Cc: Akshay Saraswat aksha...@samsung.com
Cc: Simon Glass s...@chromium.org
Cc: Minkyu Kang mk7.k...@samsung.com
---
board/samsung/smdk5420/smdk5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/samsung/smdk5420/smdk5420.c
b/board/samsung/smdk5420/smdk5420.c
index 1aca9fa..5738fd3 100644
--- a/board/samsung/smdk5420/smdk5420.c
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -44,9 +44,9 @@ static int has_edp_bridge(void)
void exynos_lcd_power_on(void)
{
+#ifdef CONFIG_POWER_TPS65090
int ret;
-#ifdef CONFIG_POWER_TPS65090
ret = tps65090_init();
if (ret 0) {
printf(%s: tps65090_init() failed\n, __func__);
--
1.9.1
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Re: [U-Boot] [PATCH 00/18] Exynos: move i2c driver to dm api
Hello all, On 01/08/2015 12:28 PM, Przemyslaw Marczak wrote: This patchset adds support to driver model i2c api for Exynos i2c driver. Few boards are using this driver, but the board peripherals are not ported to the new api yet. So this can't be enabled with the full board functionality. In this case each Exynos5 based boards have fixed config dependencies Helloafor testing the dm i2c api with the new i2c driver. This will facilitate the peripheral porting. For test, just enable CONFIG_DM_I2C in exynos5-common.h. The i2c command should work with this as previous. This patchset also provides some changes related to Exynos4 boards. Most Exynos4 boards requires only pmic support, and this will be done with the new pmic framework soon. Przemyslaw Marczak (18): arndale: config: disable max77686 support exynos5250: config: disable max77686 driver smdk5250: config: enable max77686 driver support exynos4: dts: add missing i2c properties arndale: dts: add missing i2c aliases exynos5: pinmux: check flag for i2c config dm: i2c: s3c24x0: adjust to dm-i2c api exynos5: config: prepare for dm i2c support exynos5250: config: temporary disable sound for dm i2c arndale: config: temporary disable pmic for dm i2c exynos5-dt: config: temporary disable pmic for dm i2c snow: config: temporary disable cros ec i2c for dm i2c smdk5250: config: temporary disable pmic for dm i2c smdk5420: board: fix build warning for testing dm i2c peach-pi: config: temporary disable video parade for dm i2c peach-pit: config: temporary disable video parade for dm i2c trats2: board: cleanup power init code trats2: config: disable i2c peripherals if testing dm i2c arch/arm/cpu/armv7/exynos/pinmux.c | 27 ++-- arch/arm/dts/exynos4.dtsi | 24 ++-- arch/arm/dts/exynos5250-arndale.dts | 8 ++ board/samsung/smdk5420/smdk5420.c | 2 +- board/samsung/trats2/trats2.c | 144 +++- drivers/i2c/s3c24x0_i2c.c | 254 +++- include/configs/arndale.h | 5 +- include/configs/exynos5-common.h| 29 ++-- include/configs/exynos5-dt-common.h | 2 + include/configs/exynos5250-common.h | 5 +- include/configs/peach-pi.h | 2 + include/configs/peach-pit.h | 2 + include/configs/smdk5250.h | 4 + include/configs/snow.h | 4 +- include/configs/trats2.h| 17 ++- 15 files changed, 395 insertions(+), 134 deletions(-) The related patchset is also available here: https://github.com/bobenstein/u-boot/tree/dm-i2c-exynos Best regards, -- Przemyslaw Marczak Samsung RD Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] watchdog: omap: Add handling for CONFIG_WATCHDOG_TIMEOUT_MSECS
On Thu, Jan 08, 2015 at 11:58:53AM +0100, Marek Belisko wrote: This change add possibility to change watchdog timeout compile time. Previous default value is kept when CONFIG_WATCHDOG_TIMEOUT_MSECS is not defined in config file. Lets do this with a Kconfig option please, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 00/12] cleanup and refactor lcd.c
Gentle ping. On 12/08/2014 05:14 PM, Nikita Kiryanov wrote: This series is a first step towards an end goal of merging all CONFIG_LCD related functionality into CONFIG_VIDEO code. My plan is to start by refactoring lcd.c into something cleaner (less ifdefs) and more modular (split code into multiple files), then possibly refactor CONFIG_VIDEO code if needed, and then finally: move CONFIG_LCD related functionality over to CONFIG_VIDEO code, replacing as much CONFIG_LCD related code with CONFIG_VIDEO related code as possible. This specific step eliminates some unused code and refactors lcd console stuff into its own file. The patches (lcd: rename console_(row|col) to lcd: make lcd_drawchars() independant of lcd_base) are preparatory patches meant to illustrate exactly what changed and where in the transition from lcd.c to lcd_console.c, and are not necesserily code improvements when viewed out of context. Changes in V3: - Function documentation - Cache values of lcd_get(bg|fg)color() instead of calling the functions multiple times. The whole series was rebased over current mainline, and compile tested for arm and powerpc. Cc: Anatolij Gustschin ag...@denx.de Cc: Wolfgang Denk w...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stephen Warren swar...@wwwdotorg.org Entire series: Tested-by: Stephen Warren swar...@wwwdotorg.org Tested-by: Simon Glass s...@chromium.org Nikita Kiryanov (12): lcd: remove CONFIG_SYS_INVERT_COLORS lcd: cleanup lcd_drawchars mpc8xx_lcd: get rid of CONFIG_EDT32F10 lcd: remove LCD_MONOCHROME lcd: rename console_(row|col) lcd: replace CONSOLE_(ROWS|COLS) with variables lcd: expand console api lcd: get rid of COLOR_MASK lcd: introduce getters for bg/fg color lcd: make lcd_drawchars() independant of lcd_base lcd: refactor lcd console stuff into its own file lcd_console: remove unused defines common/Makefile| 2 +- common/lcd.c | 313 + common/lcd_console.c | 211 ++ drivers/video/mpc8xx_lcd.c | 49 +-- drivers/video/pxa_lcd.c| 15 --- include/configs/R360MPI.h | 1 - include/lcd.h | 25 ++-- include/lcd_console.h | 86 + 8 files changed, 347 insertions(+), 355 deletions(-) create mode 100644 common/lcd_console.c create mode 100644 include/lcd_console.h -- Regards, Nikita Kiryanov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] usb: eth: asix88179: add ability to modify MAC address
Here is the promised patch, that enables U-Boot to modify the MAC
address of the AX88179.
Tested on RECS5250 (similar to Arndale5250)
Signed-off-by: Rene Griessl rgrie...@cit-ec.uni-bielefeld.de
---
drivers/usb/eth/asix88179.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c
index b8ca720..b551540 100644
--- a/drivers/usb/eth/asix88179.c
+++ b/drivers/usb/eth/asix88179.c
@@ -271,6 +271,22 @@ static int asix_read_mac(struct eth_device *eth)
return 0;
}
+static int asix_write_mac(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth-priv;
+ int ret;
+ u8 buf[ETH_ALEN];
+
+ memcpy(buf, eth-enetaddr, ETH_ALEN);
+
+ ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
+ETH_ALEN, buf);
+ if (ret 0)
+ debug(Failed to set MAC address: %02x\n, ret);
+
+ return ret;
+}
+
static int asix_basic_reset(struct ueth_data *dev)
{
struct asix_private *dev_priv = (struct asix_private *)dev-dev_priv;
@@ -686,6 +702,7 @@ int ax88179_eth_get_info(struct usb_device *dev, struct
ueth_data *ss,
eth-send = asix_send;
eth-recv = asix_recv;
eth-halt = asix_halt;
+ eth-write_hwaddr = asix_write_mac;
eth-priv = ss;
if (asix_basic_reset(ss))
--
1.9.1
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[U-Boot] [PATCH 3/3] imx:mx6 set normal APS and standby PFM mode
To normal mode, use APS switching mode.
To standy mode, use PFM switching mode.
Signed-off-by: Peng Fan peng@freescale.com
---
board/freescale/mx6qsabreauto/mx6qsabreauto.c | 5 +
board/freescale/mx6sabresd/mx6sabresd.c | 6 +-
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 6 +-
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 59387ff..b29ff2b 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -515,11 +515,16 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
int power_init_board(void)
{
struct pmic *p;
+ unsigned int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret 0)
+ return -EIO;
+
return 0;
}
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 2f7198d..59544d9 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -631,12 +631,16 @@ int board_init(void)
int power_init_board(void)
{
struct pmic *p;
- unsigned int reg;
+ unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret 0)
+ return -EIO;
+
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, reg);
reg = ~LDO_VOL_MASK;
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 5cc58ac..fbf3337 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -199,12 +199,16 @@ static struct i2c_pads_info i2c_pad_info1 = {
int power_init_board(void)
{
struct pmic *p;
- unsigned int reg;
+ unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
+ ret = pfuze_mode_init(p, APS_PFM);
+ if (ret 0)
+ return -EIO;
+
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, reg);
reg = ~LDO_VOL_MASK;
--
1.8.4
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[U-Boot] [PATCH 1/3] pmic:pfuz100 add switch mode and more registers
Add more pfuze register offset.
And switch mode definition.
Signed-off-by: Peng Fan peng@freescale.com
---
include/power/pfuze100_pmic.h | 53 +++
1 file changed, 53 insertions(+)
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index 1118489..7474afb 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -16,14 +16,34 @@ enum {
PFUZE100_SW1ABVOL = 0x20,
PFUZE100_SW1ABSTBY = 0x21,
+ PFUZE100_SW1ABOFF = 0x22,
+ PFUZE100_SW1ABMODE = 0x23,
PUZE_100_SW1ABCONF = 0x24,
PFUZE100_SW1CVOL= 0x2e,
PFUZE100_SW1CSTBY = 0x2f,
+ PFUZE100_SW1COFF= 0x30,
+ PFUZE100_SW1CMODE = 0x31,
PFUZE100_SW1CCONF = 0x32,
PFUZE100_SW2VOL = 0x35,
+ PFUZE100_SW2STBY= 0x36,
+ PFUZE100_SW2OFF = 0x37,
+ PFUZE100_SW2MODE= 0x38,
+ PFUZE100_SW2CONF= 0x39,
PFUZE100_SW3AVOL= 0x3c,
+ PFUZE100_SW3ASTBY = 0x3D,
+ PFUZE100_SW3AOFF= 0x3E,
+ PFUZE100_SW3AMODE = 0x3F,
+ PFUZE100_SW3ACONF = 0x40,
PFUZE100_SW3BVOL= 0x43,
+ PFUZE100_SW3BSTBY = 0x44,
+ PFUZE100_SW3BOFF= 0x45,
+ PFUZE100_SW3BMODE = 0x46,
+ PFUZE100_SW3BCONF = 0x47,
PFUZE100_SW4VOL = 0x4a,
+ PFUZE100_SW4STBY= 0x4b,
+ PFUZE100_SW4OFF = 0x4c,
+ PFUZE100_SW4MODE= 0x4d,
+ PFUZE100_SW4CONF= 0x4e,
PFUZE100_SWBSTCON1 = 0x66,
PFUZE100_VREFDDRCON = 0x6a,
PFUZE100_VSNVSVOL = 0x6b,
@@ -177,5 +197,38 @@ enum {
#define SWBST_MODE_AUTO(2 2)
#define SWBST_MODE_APS (2 3)
+/*
+ * Regulator Mode Control
+ *
+ * OFF: The regulator is switched off and the output voltage is discharged.
+ * PFM: In this mode, the regulator is always in PFM mode, which is useful
+ * at light loads for optimized efficiency.
+ * PWM: In this mode, the regulator is always in PWM mode operation
+ * regardless of load conditions.
+ * APS: In this mode, the regulator moves automatically between pulse
+ * skipping mode and PWM mode depending on load conditions.
+ *
+ * SWxMODE[3:0]
+ * Normal Mode | Standby Mode| value
+ * OFF OFF 0x0
+ * PWM OFF 0x1
+ * PFM OFF 0x3
+ * APS OFF 0x4
+ * PWM PWM 0x5
+ * PWM APS 0x6
+ * APS APS 0x8
+ * APS PFM 0xc
+ * PWM PFM 0xd
+ */
+#define OFF_OFF0x0
+#define PWM_OFF0x1
+#define PFM_OFF0x3
+#define APS_OFF0x4
+#define PWM_PWM0x5
+#define PWM_APS0x6
+#define APS_APS0x8
+#define APS_PFM0xc
+#define PWM_PFM0xd
+
int power_pfuze100_init(unsigned char bus);
#endif
--
1.8.4
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[U-Boot] [PATCH 0/3] pmic:pfuze support buck regulator mode switch
This patch set is to support buck regulator can working in different switching modes. To improve system efficiency the buck regulators can operate in different switching modes. patch 1/3 is to add related bit definitions and registers. patch 2/3 is to implement the switching mode init function. patch 3/3 is to add related mode init function in board code. mx6slevk board is not included in this patch set, since power and i2c interface are not implemented for it. Future patch will cover this to add PAD setting, power_init_board and etc. Peng Fan (3): pmic:pfuz100 add switch mode and more registers pmic:pfuze implement pmic_mode_init imx:mx6 set normal APS and standby PFM mode board/freescale/common/pfuze.c| 36 ++ board/freescale/common/pfuze.h| 1 + board/freescale/mx6qsabreauto/mx6qsabreauto.c | 5 +++ board/freescale/mx6sabresd/mx6sabresd.c | 6 ++- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 6 ++- include/power/pfuze100_pmic.h | 53 +++ 6 files changed, 105 insertions(+), 2 deletions(-) -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] pmic:pfuze implement pmic_mode_init
This patch is to implement pmic_mode_init function, and add prototype
in header file.
This function is to set switching mode for pmic buck regulators to
improve system efficiency.
Mode:
OFF: The regulator is switched off and the output voltage is discharged.
PFM: In this mode, the regulator is always in PFM mode, which
is useful at light loads for optimized efficiency.
PWM: In this mode, the regulator is always in PWM mode operation
regardless of load conditions.
APS: In this mode, the regulator moves automatically between
pulse skipping mode and PWM mode depending on load conditions.
Signed-off-by: Peng Fan peng@freescale.com
---
board/freescale/common/pfuze.c | 36
board/freescale/common/pfuze.h | 1 +
2 files changed, 37 insertions(+)
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 2cd1794..74df69c 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -8,6 +8,42 @@
#include power/pmic.h
#include power/pfuze100_pmic.h
+int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+ unsigned char offset, i, switch_num;
+ u32 id, ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, id);
+ id = id 0xf;
+
+ if (id == 0) {
+ switch_num = 6;
+ offset = PFUZE100_SW1CMODE;
+ } else if (id == 1) {
+ switch_num = 4;
+ offset = PFUZE100_SW2MODE;
+ } else {
+ printf(Not supported, id=%d\n, id);
+ return -1;
+ }
+
+ ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+ if (ret 0) {
+ printf(Set SW1AB mode error!\n);
+ return ret;
+ }
+
+ for (i = 0; i switch_num - 1; i++) {
+ ret = pmic_reg_write(p, offset + i * 7, mode);
+ if (ret 0) {
+ printf(Set switch%x mode error!\n, offset + i * 7);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
struct pmic *pfuze_common_init(unsigned char i2cbus)
{
struct pmic *p;
diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h
index 7a4126c..53cfc99 100644
--- a/board/freescale/common/pfuze.h
+++ b/board/freescale/common/pfuze.h
@@ -8,5 +8,6 @@
#define __PFUZE_BOARD_HELPER__
struct pmic *pfuze_common_init(unsigned char i2cbus);
+int pfuze_mode_init(struct pmic *p, u32 mode);
#endif
--
1.8.4
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Re: [U-Boot] [PATCH 1/3] sunxi: video: Add lvds support
On Wed, 2015-01-07 at 20:58 +0100, Hans de Goede wrote: Hi, On 07-01-15 19:56, Ian Campbell wrote: On Sun, 2015-01-04 at 21:05 +0100, Hans de Goede wrote: diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 8782394..fdb18a4 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -345,6 +345,20 @@ config VIDEO_LCD_BL_PWM Set the backlight pwm pin for the LCD panel. This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +choice + prompt LCD panel support + depends on VIDEO + ---help--- + Select which type of LCD panel to support. + +config VIDEO_LCD_PANEL_PARALLEL + bool Generic parallel interface LCD panel I don't see any use of this choice, I suppose it is the #else case? Right, it is the else case in the actual code (for now). Are there other (third) options for LCDs? Yes, see the second patch in this series, I've replied to the second patch again because it doesn't seem right to put the specific choice of panel under the class of panel choice label. and Sairhei has a tablet which needs something similar (but different) to the second patch. I can't find a reference for this, but I suppose it might imply that the choice of panel should be a Kconfig choice too, just not the same one as the general class of panel Kconfig choice (IYSWIM). Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Fix repeated USB scans problems
Hi, On 08-01-15 01:19, Stephen Warren wrote: On 01/07/2015 04:35 PM, Marek Vasut wrote: On Tuesday, January 06, 2015 at 06:02:57 PM, Stephen Warren wrote: snip Should we rename usb reset to usb restart? No, let's not mess with the UI any more than we already did. Well, it might not be such a bad idea if the semantics are changing, to give people a heads-up? Only the semantics of usb start are changing, and you are suggesting renaming usb reset which remains unchanged ... Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Nokia RX-51 (N900) board broken
On Thursday 08 January 2015 01:16:22 Nishanth Menon wrote:
On 01/07/2015 03:12 AM, Pali Rohár wrote:
@Tom, Nishanth, or anybody from TI: how to check if omap
device type is HS in uboot? In linux kernel it is possible
by:
if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { ... }
it should be.
CONTROL_STATUS register exists in almost all omap2+ devices.
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
/tree/arch/arm/mach-omap2/id.c#n53
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git
/tree/arch/arm/mach-omap2/soc.h#n120
omap3 u-boot implements get_device_type
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/o
map3/sys_info.c;h=bbb65bbe7263674c2b47b97ee05a9f588ed1c58f;hb=
HEAD#l265
Macro HS_DEVICE could be used?
--
Regards,
Nishanth Menon
Thanks, condition if (get_device_type() == HS_DEVICE) fixed
problem with qemu. I will send patch to ML.
--
Pali Rohár
pali.ro...@gmail.com
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Re: [U-Boot] [PATCH 2/2] sunxi: Enable pre-console buffer
On Thu, 2015-01-08 at 09:02 +0200, Siarhei Siamashka wrote: This allows to always have a complete log on the VGA/HDMI/LCD console. Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com --- include/configs/sunxi-common.h | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b4324ee..5ddcc42 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -272,10 +272,15 @@ #ifndef CONFIG_SPL_BUILD #include config_distro_defaults.h +/* Enable pre-console buffer to get complete log on the VGA console */ +#define CONFIG_PRE_CONSOLE_BUFFER +#define CONFIG_PRE_CON_BUF_SZ(1024 * 1024) +#define CONFIG_PRE_CON_BUF_ADDR (0x4300 - CONFIG_PRE_CON_BUF_SZ) + /* * 240M RAM (256M minimum minus space for the framebuffer), - * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, - * 1M script, 1M pxe and the ramdisk at the end. + * 32M uncompressed kernel, 15M compressed kernel, 1M pre-console + * buffer, 1M fdt, 1M script, 1M pxe and the ramdisk at the end. Am I correct in thinking that the pre-console buffer is long gone (replaced by the actual console) by the time any of these mem layout choices come into play (i.e. long before anything might load a kernel, initrd or fdt)? If yes then I think it is confusing to modify this comment, and the comment before the pre-console #defines should mention that the buffer is boottime only/short lived etc. If no then I'm not sure putting a u-boot managed buffer in the middle of the user managed load space is a good idea, since it could lead to odd/hard to debug corruptions etc if the kernel was 15M. Either way I think it would be better to put this buffer somewhere else entirely since it isn't really the same as these things. */ #define MEM_LAYOUT_ENV_SETTINGS \ bootm_size=0xf00\0 \ Both u-boot-sunxi#master and #next still have 0x1000 here, which tree is this patch on? Some branch of Hans' tree (with sunxi: sunxi-common.h: Reduce bootm_size to take the framebuffer into account in it) I suppose? Perhaps a better place for the pre-console buffer would be right before the framebuffer (or at the top of RAM if no video on the board), with modifications to bootm_size or not depending on the answer to the original question above. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Nokia RX-51: Do not call secure PPA routine on non secure devices
Since commit 41623c91b09a0c865fab41acdaff30f060f29ad6 u-boot running in qemu is crashing in function do_omap3_emu_romcode_call(). RX-51 board uses this function for Cortex-A8 errata 430973 workaround (Set IBE bit in ACR) which is needed only on real secure device and not in qemu. This board patch just disable calling secure PPA routine on non secure devices. Qemu implements GP device and with this patch u-boot is working in qemu again. Signed-off-by: Pali Rohár pali.ro...@gmail.com --- board/nokia/rx51/rx51.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index b6b8ad6..08fcaf2 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -422,8 +422,12 @@ int misc_init_r(void) /* * Cortex-A8(r1p0..r1p2) errata 430973 workaround * Set IBE bit in Auxiliary Control Register +* +* Call this routine only on real secure device +* Qemu does not implement secure PPA and crash */ - omap3_update_aux_cr_secure_rx51(1 6, 0); + if (get_device_type() == HS_DEVICE) + omap3_update_aux_cr_secure_rx51(1 6, 0); return 0; } -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/1] marvell: kirkwood: guruplug refresh for newer kernel
Hi Prafulla, On Wed, Jan 07, 2015 at 08:48:17PM -0800, Prafulla Wadaskar wrote: May you lease pull these too? Will do. Let me know if there are any other ones left. Luka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] usb: gadget: pxa25x_udc: fix use-before-initialized bug
Hi! Can you please fix From: and Signed-off-by: fields Oh, it looks like I have to accept this requirement. Ok, I'll fix it. Should I also change tag in subject to '[PATCH v2]' in a fixed patch? Thank you for kind answer! Best regards, Alex Sadovsky. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 2/5] i2c: UniPhier: add driver for UniPhier i2c controller
This commit adds on-chip I2C driver used on some old Panasonic
UniPhier SoCs.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Reviewed-by: Simon Glass s...@chromium.org
Acked-by: Heiko Schocher h...@denx.de
---
Changes in v5:
- Drop unnecessary __packed
Changes in v4:
- Use a structure instead of macros for register access
Changes in v3: None
Changes in v2:
- Fix a typo. s/freqency/frequency/
- Add some comments to explain the formula calculating
wait time.
- add comments on every register
- skip stop condition if the next message is read
drivers/i2c/Kconfig| 8 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-uniphier.c | 235 +
3 files changed, 244 insertions(+)
create mode 100644 drivers/i2c/i2c-uniphier.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 96715d0..6a479ef 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -4,3 +4,11 @@ config DM_I2C
help
If you want to use driver model for I2C drivers, say Y.
To use legacy I2C drivers, say N.
+
+config SYS_I2C_UNIPHIER
+ bool UniPhier I2C driver
+ depends on ARCH_UNIPHIER DM_I2C
+ default y
+ help
+ Support for Panasonic UniPhier I2C controller driver. This I2C
+ controller is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 6f3c86c..e2fcd24 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -31,4 +31,5 @@ obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o
i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
+obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
new file mode 100644
index 000..32dca15
--- /dev/null
+++ b/drivers/i2c/i2c-uniphier.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada yamad...@jp.panasonic.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include linux/types.h
+#include asm/io.h
+#include asm/errno.h
+#include dm/device.h
+#include dm/root.h
+#include i2c.h
+#include fdtdec.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct uniphier_i2c_regs {
+ u32 dtrm; /* data transmission */
+#define I2C_DTRM_STA (1 10)
+#define I2C_DTRM_STO (1 9)
+#define I2C_DTRM_NACK (1 8)
+#define I2C_DTRM_RD(1 0)
+ u32 drec; /* data reception */
+#define I2C_DREC_STS (1 12)
+#define I2C_DREC_LRB (1 11)
+#define I2C_DREC_LAB (1 9)
+ u32 myad; /* slave address */
+ u32 clk;/* clock frequency control */
+ u32 brst; /* bus reset */
+#define I2C_BRST_FOEN (1 1)
+#define I2C_BRST_BRST (1 0)
+ u32 hold; /* hold time control */
+ u32 bsts; /* bus status monitor */
+ u32 noise; /* noise filter control */
+ u32 setup; /* setup time control */
+};
+
+#define IOBUS_FREQ 1
+
+struct uniphier_i2c_dev {
+ struct uniphier_i2c_regs __iomem *regs; /* register base */
+ unsigned long input_clk;/* master clock (Hz) */
+ unsigned long wait_us; /* wait for every byte transfer (us) */
+};
+
+static int uniphier_i2c_probe(struct udevice *dev)
+{
+ fdt_addr_t addr;
+ fdt_size_t size;
+ struct uniphier_i2c_dev *priv = dev_get_priv(dev);
+
+ addr = fdtdec_get_addr_size(gd-fdt_blob, dev-of_offset, reg, size);
+
+ priv-regs = map_sysmem(addr, size);
+
+ if (!priv-regs)
+ return -ENOMEM;
+
+ priv-input_clk = IOBUS_FREQ;
+
+ /* deassert reset */
+ writel(0x3, priv-regs-brst);
+
+ return 0;
+}
+
+static int uniphier_i2c_remove(struct udevice *dev)
+{
+ struct uniphier_i2c_dev *priv = dev_get_priv(dev);
+
+ unmap_sysmem(priv-regs);
+
+ return 0;
+}
+
+static int uniphier_i2c_child_pre_probe(struct udevice *dev)
+{
+ struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
+
+ if (dev-of_offset == -1)
+ return 0;
+ return i2c_chip_ofdata_to_platdata(gd-fdt_blob, dev-of_offset,
+ i2c_chip);
+}
+
+static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm)
+{
+ writel(dtrm, dev-regs-dtrm);
+
+ /*
+* This controller only provides interruption to inform the completion
+* of each byte transfer. (No status register to poll it.)
+* Unfortunately, U-Boot does not have a good support of interrupt.
+* Wait for a while.
+*/
+ udelay(dev-wait_us);
+
+ return readl(dev-regs-drec);
+}
+
+static int send_byte(struct
[U-Boot] [PATCH v5 5/5] ARM: UniPhier: enable CONFIG_I2C_EEPROM
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None include/configs/uniphier.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 5a53c50..9ad47f6 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -43,6 +43,9 @@ #define CONFIG_SDRAM1_SIZE 0x1000 #endif +#define CONFIG_I2C_EEPROM +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + /* * Support card address map */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 0/5] i2c: UniPhier: add I2C drivers based on driver model
Masahiro Yamada (5): i2c: add CONFIG_DM_I2C to Kconfig i2c: UniPhier: add driver for UniPhier i2c controller i2c: UniPhier: add driver for UniPhier FIFO-builtin i2c controller ARM: UniPhier: enable I2C for UniPhier SoCs ARM: UniPhier: enable CONFIG_I2C_EEPROM configs/ph1_ld4_defconfig| 2 + configs/ph1_pro4_defconfig | 2 + configs/ph1_sld8_defconfig | 2 + drivers/i2c/Kconfig | 22 +++ drivers/i2c/Makefile | 2 + drivers/i2c/i2c-uniphier-f.c | 380 +++ drivers/i2c/i2c-uniphier.c | 235 ++ include/configs/uniphier.h | 3 + 8 files changed, 648 insertions(+) create mode 100644 drivers/i2c/i2c-uniphier-f.c create mode 100644 drivers/i2c/i2c-uniphier.c -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 3/5] i2c: UniPhier: add driver for UniPhier FIFO-builtin i2c controller
This commit adds on-chip I2C driver used on newer SoCs of Panasonic
UniPhier platform.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Reviewed-by: Simon Glass s...@chromium.org
Acked-by: Heiko Schocher h...@denx.de
---
Changes in v5:
- Drop unnecessary __packed
Changes in v4:
- Use a structure instead of macros for register access
Changes in v3:
- Fix a bug in that device busy is checked even if the stop
condition is not issued.
Changes in v2:
- Fix a typo. s/freqency/frequency/
- Rename the struct member for clarification. s/wait_us/timeout/
- Add comments on all the registers
- Skip stop condition if the next message is read
drivers/i2c/Kconfig | 8 +
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-uniphier-f.c | 380 +++
3 files changed, 389 insertions(+)
create mode 100644 drivers/i2c/i2c-uniphier-f.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 6a479ef..202ea5d 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -12,3 +12,11 @@ config SYS_I2C_UNIPHIER
help
Support for Panasonic UniPhier I2C controller driver. This I2C
controller is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
+
+config SYS_I2C_UNIPHIER_F
+ bool UniPhier FIFO-builtin I2C driver
+ depends on ARCH_UNIPHIER DM_I2C
+ default y
+ help
+ Support for Panasonic UniPhier FIFO-builtin I2C controller driver.
+ This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e2fcd24..0e4c9f4 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -32,4 +32,5 @@ obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
+obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
new file mode 100644
index 000..7bd524c
--- /dev/null
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada yamad...@jp.panasonic.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include linux/types.h
+#include asm/io.h
+#include asm/errno.h
+#include dm/device.h
+#include dm/root.h
+#include i2c.h
+#include fdtdec.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct uniphier_fi2c_regs {
+ u32 cr; /* control register */
+#define I2C_CR_MST (1 3)/* master mode */
+#define I2C_CR_STA (1 2)/* start condition */
+#define I2C_CR_STO (1 1)/* stop condition */
+#define I2C_CR_NACK(1 0)/* not ACK */
+ u32 dttx; /* send FIFO (write-only) */
+#define dtrx dttx/* receive FIFO (read-only) */
+#define I2C_DTTX_CMD (1 8)/* send command (slave addr) */
+#define I2C_DTTX_RD(1 0)/* read */
+ u32 __reserved; /* no register at offset 0x08 */
+ u32 slad; /* slave address */
+ u32 cyc;/* clock cycle control */
+ u32 lctl; /* clock low period control */
+ u32 ssut; /* restart/stop setup time control */
+ u32 dsut; /* data setup time control */
+ u32 intr; /* interrupt status */
+ u32 ie; /* interrupt enable */
+ u32 ic; /* interrupt clear */
+#define I2C_INT_TE (1 9)/* TX FIFO empty */
+#define I2C_INT_RB (1 4)/* received specified bytes */
+#define I2C_INT_NA (1 2)/* no answer */
+#define I2C_INT_AL (1 1)/* arbitration lost */
+ u32 sr; /* status register */
+#define I2C_SR_DB (1 12) /* device busy */
+#define I2C_SR_BB (1 8)/* bus busy */
+#define I2C_SR_RFF (1 3)/* Rx FIFO full */
+#define I2C_SR_RNE (1 2)/* Rx FIFO not empty */
+#define I2C_SR_TNF (1 1)/* Tx FIFO not full */
+#define I2C_SR_TFE (1 0)/* Tx FIFO empty */
+ u32 __reserved2;/* no register at offset 0x30 */
+ u32 rst;/* reset control */
+#define I2C_RST_TBRST (1 2)/* clear Tx FIFO */
+#define I2C_RST_RBRST (1 1)/* clear Rx FIFO */
+#define I2C_RST_RST(1 0)/* forcible bus reset */
+ u32 bm; /* bus monitor */
+ u32 noise; /* noise filter control */
+ u32 tbc;/* Tx byte count setting */
+ u32 rbc;/* Rx byte count setting */
+ u32 tbcm; /* Tx byte count monitor */
+
[U-Boot] [PATCH v5 1/5] i2c: add CONFIG_DM_I2C to Kconfig
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Reviewed-by: Simon Glass s...@chromium.org Acked-by: Heiko Schocher h...@denx.de --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None drivers/i2c/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index e69de29..96715d0 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -0,0 +1,6 @@ +config DM_I2C + bool Enable Driver Model for I2C drivers + depends on DM + help + If you want to use driver model for I2C drivers, say Y. + To use legacy I2C drivers, say N. -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 4/5] ARM: UniPhier: enable I2C for UniPhier SoCs
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None configs/ph1_ld4_defconfig | 2 ++ configs/ph1_pro4_defconfig | 2 ++ configs/ph1_sld8_defconfig | 2 ++ 3 files changed, 6 insertions(+) diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 2e9dd00..86b4b15 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_LOADB=y CONFIG_CMD_LOADS=y CONFIG_CMD_FLASH=y CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_ECHO=y CONFIG_CMD_ITEST=y @@ -34,6 +35,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y CONFIG_UNIPHIER_SERIAL=y +CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 5dca64b..242bcf9 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_LOADB=y CONFIG_CMD_LOADS=y CONFIG_CMD_FLASH=y CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_ECHO=y CONFIG_CMD_ITEST=y @@ -34,6 +35,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y CONFIG_UNIPHIER_SERIAL=y +CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 2a6e334..8e95f17 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_LOADB=y CONFIG_CMD_LOADS=y CONFIG_CMD_FLASH=y CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_ECHO=y CONFIG_CMD_ITEST=y @@ -34,6 +35,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y CONFIG_UNIPHIER_SERIAL=y +CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: remove __packed that causes a problem on GCC 4.9
On Wed, 7 Jan 2015 14:00:05 -0500
Tom Rini tr...@ti.com wrote:
On Wed, Jan 07, 2015 at 07:41:38PM +0900, Masahiro Yamada wrote:
The DDR PHY training function, ddrphy_prepare_training() would not
work if compiled with GCC 4.9.
The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h)
is specified with __packed because it represents a hardware register
mapping, but it turned out to cause a problem on GCC 4.9.
If -mno-unaligned-access is specified (actually it is in
arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the
__attribute__((packed)) and generates extra instructions to perform
the memory access in a way that does not cause unaligned access.
(Actually it is bogus here because the register base, the first
argument of the ddrphy_prepare_training(), is always given with a
4-byte aligned address.)
Anyway, as a result, readl() / writel() is divided into byte-wise
accesses. The problem is that this hardware only accepts 4-byte
register access. Byte-wise accesses lead to unexpected behavior.
There are some options to avoid this problem.
[1] Remove -mno-unaligned-access
[2] Add __aligned(4) along with __packed to struct ddrphy
[3] Remove __packed from struct ddrphy
[1] solves the problem for ARMv7, but it does not for pre-ARMv6 and
ARMv6-M architectures where -mno-unaligned-access is default.
So, [1] does not seem reasonable in terms of code portability.
Both [2] and [3] work well, but [2] seems too much. All the members
of struct ddrphy have the u32 type. No padding would be inserted
even if __packed is dropped.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
I wanted to think about this for a minute. I argued with myself a bit
about [2] being the best choice, and lost. I'm fairly sure that
__packed on an struct of all u32 (on a 32bit platform) is in fact the
wrong thing to do so yes, [3] is right.
Reviewed-by: Tom Rini tr...@ti.com
There is another (and I think the best) option:
[4] Sync writeb(), writew(), writel(), readlb(), readw(), readl() with Linux
This pitfall does not occur on Linux
because ARM Linux hard-codes writel()/readl() etc.
Linux:
#define __raw_writel __raw_writel
static inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
asm volatile(str %1, %0
: +Qo (*(volatile u32 __force *)addr)
: r (val));
}
U-Boot:
#define __arch_putl(v,a)(*(volatile unsigned int *)(a) = (v))
#define __raw_writel(v,a) __arch_putl(v,a)
On Linux, writel() is always converted to str instruction.
On U-Boot, it depends on compiler's decesion.
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 2/3] sunxi: video: Add support for Hitachi tx18d42vm LCD panels
On Thu, 2015-01-08 at 09:39 +0100, Hans de Goede wrote: Hi, On 08-01-15 09:32, Ian Campbell wrote: On Sun, 2015-01-04 at 21:05 +0100, Hans de Goede wrote: Hitachi tx18d42vm LCD panels have an onboard controller which needs some initialization via spi for the panel to become functional as a regular LVDS panel. Signed-off-by: Hans de Goede hdego...@redhat.com --- board/sunxi/Kconfig | 3 ++ drivers/video/Makefile | 2 +- drivers/video/sunxi_display.c | 9 ++ drivers/video/sunxi_lcd_panel.c | 68 + drivers/video/sunxi_lcd_panel.h | 9 ++ 5 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 drivers/video/sunxi_lcd_panel.c create mode 100644 drivers/video/sunxi_lcd_panel.h diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index fdb18a4..e9f62b9 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -357,6 +357,9 @@ config VIDEO_LCD_PANEL_PARALLEL config VIDEO_LCD_PANEL_LVDS bool Generic lvds interface LCD panel +config VIDEO_LCD_PANEL_HITACHI_TX18D42VM + bool Hitachi tx18d42vm LCD panel + endchoice config USB_KEYBOARD diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 42b1eaa..d4fe1aa 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -39,7 +39,7 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o -obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o +obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o sunxi_lcd_panel.o videomodes.o obj-$(CONFIG_VIDEO_TEGRA) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_X86) += x86_fb.o diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 4b63b01..f087c2c 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -19,8 +19,13 @@ #include fdtdec.h #include fdt_support.h #include video_fb.h +#include sunxi_lcd_panel.h #include videomodes.h +#ifdef CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM +#define CONFIG_VIDEO_LCD_PANEL_LVDS +#endif Your reply to 1/3 made me notice this, which I somehow missed before, I don't think this is the right way to go about this. It seems to me that LCD_PANEL_HITACHI does not belong under the PARALLEL vs LVDS Kconfig choice, rather it should be an independent bool option which depends on PANEL_LVDS. Technically you are correct, but from a user pov it seems easier to tell the user to select which panel he has, and then the user can chose between a bunch of generic ones (generic parallel, generic lvds) and a bunch of specific panels which need some extra setup. Hrm, true. If you insist I can live with doing things your way though, either way let me know how you want to handle this. Perhaps have hidden Kconfig options for the baseline LVDS vs PARALLEL support and then a choice of GENERIC //, GENERIC LVDS, HITACHI TX.., OTHER MAGIC PANEL with appropriate selects on the hidden options? Then the generic code would use the hidden options, no need for a weird #ifdef/#define pair for each non-standard panel (which depending on how many panels are normal vs. needing magic could get unwieldy). Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] config_distro_bootcmd: Scan all partitions for boot files
On Wed, 2015-01-07 at 13:22 -0700, Stephen Warren wrote: On 01/07/2015 04:17 AM, Ian Campbell wrote: On Wed, 2015-01-07 at 12:01 +0100, Sjoerd Simons wrote: On Wed, 2015-01-07 at 10:22 +, Ian Campbell wrote: This is about the default setup though, it would be really nice to get consistent behaviour. I would be inclined to say that the defaults should conservatively try the internal/main storage first (assuming there will be an OS is installed there) and only fallback to other options later. I'm inclined the other way, which is to boot of a removable media first if someone has gone to the effort to plug one in. People building kiosks etc who want to lock it down to internal only can still do so. Yes, I agree. This means that if you already have a (perhaps broken or old) distro installed on the internal media, you can place boot media into the external slot and boot that without having to fiddle with modifying the boot configuration variables. If that behaviour isn't what a particular user wants, they can just edit $boot_targets. Each platform can make their own decision if they want though; the order of entries in BOOT_TARGET_DEVICES (part of the U-Boot config header file) determines the default order of entries in $boot_targets. Fair enough. One thing i would like to mention though that respective of the preference here, It would be nice to have some guidelines here. One thing which always irks me is that for every new ARM i get on my desk, I need to re-discover how this particular one happens to boot.. The distro bootcmd stuff goes a very long way here, but would be even nicer if the sequence was predictable as well (e.g. always external, internal, network boots unless the board has a boot selector switch). (One can wish right :p) -- Sjoerd Simons sjoerd.sim...@collabora.co.uk Collabora Ltd. smime.p7s Description: S/MIME cryptographic signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] sunxi: video: Add support for Hitachi tx18d42vm LCD panels
On Sun, 2015-01-04 at 21:05 +0100, Hans de Goede wrote: Hitachi tx18d42vm LCD panels have an onboard controller which needs some initialization via spi for the panel to become functional as a regular LVDS panel. Signed-off-by: Hans de Goede hdego...@redhat.com --- board/sunxi/Kconfig | 3 ++ drivers/video/Makefile | 2 +- drivers/video/sunxi_display.c | 9 ++ drivers/video/sunxi_lcd_panel.c | 68 + drivers/video/sunxi_lcd_panel.h | 9 ++ 5 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 drivers/video/sunxi_lcd_panel.c create mode 100644 drivers/video/sunxi_lcd_panel.h diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index fdb18a4..e9f62b9 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -357,6 +357,9 @@ config VIDEO_LCD_PANEL_PARALLEL config VIDEO_LCD_PANEL_LVDS bool Generic lvds interface LCD panel +config VIDEO_LCD_PANEL_HITACHI_TX18D42VM + bool Hitachi tx18d42vm LCD panel + endchoice config USB_KEYBOARD diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 42b1eaa..d4fe1aa 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -39,7 +39,7 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o -obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o +obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o sunxi_lcd_panel.o videomodes.o obj-$(CONFIG_VIDEO_TEGRA) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_X86) += x86_fb.o diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 4b63b01..f087c2c 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -19,8 +19,13 @@ #include fdtdec.h #include fdt_support.h #include video_fb.h +#include sunxi_lcd_panel.h #include videomodes.h +#ifdef CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM +#define CONFIG_VIDEO_LCD_PANEL_LVDS +#endif Your reply to 1/3 made me notice this, which I somehow missed before, I don't think this is the right way to go about this. It seems to me that LCD_PANEL_HITACHI does not belong under the PARALLEL vs LVDS Kconfig choice, rather it should be an independent bool option which depends on PANEL_LVDS. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] sunxi: video: Add support for Hitachi tx18d42vm LCD panels
On Wed, 2015-01-07 at 21:04 +0100, Hans de Goede wrote: Hi, On 07-01-15 19:59, Ian Campbell wrote: On Sun, 2015-01-04 at 21:05 +0100, Hans de Goede wrote: Hitachi tx18d42vm LCD panels have an onboard controller which needs some initialization via spi for the panel to become functional as a regular LVDS panel. This doesn't sound terribly sunxi specific, shouldn't sunxi_lcd_panel_hitachi_tx18d42vm_init be generic but making use of some sort of arch-provided interface for actually talking SPI to the device (which may or may not use the generic SPI infra, as your code comment talked about)? You're right it is not sunxi specific, but for now sunxi is the only user (I've checked) so this seemed simplest, with the idea that it is always much easier to make something properly generic when there is more then one user. I think we are more likely to simply end up with N versions of this code because no one notices that it already exists under some other name. If Anatolij is OK with it then I have no objections. I guess I should have put something about this in the commit message :) Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] sunxi: video: Add support for Hitachi tx18d42vm LCD panels
Hi, On 08-01-15 09:32, Ian Campbell wrote: On Sun, 2015-01-04 at 21:05 +0100, Hans de Goede wrote: Hitachi tx18d42vm LCD panels have an onboard controller which needs some initialization via spi for the panel to become functional as a regular LVDS panel. Signed-off-by: Hans de Goede hdego...@redhat.com --- board/sunxi/Kconfig | 3 ++ drivers/video/Makefile | 2 +- drivers/video/sunxi_display.c | 9 ++ drivers/video/sunxi_lcd_panel.c | 68 + drivers/video/sunxi_lcd_panel.h | 9 ++ 5 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 drivers/video/sunxi_lcd_panel.c create mode 100644 drivers/video/sunxi_lcd_panel.h diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index fdb18a4..e9f62b9 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -357,6 +357,9 @@ config VIDEO_LCD_PANEL_PARALLEL config VIDEO_LCD_PANEL_LVDS bool Generic lvds interface LCD panel +config VIDEO_LCD_PANEL_HITACHI_TX18D42VM + bool Hitachi tx18d42vm LCD panel + endchoice config USB_KEYBOARD diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 42b1eaa..d4fe1aa 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -39,7 +39,7 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o -obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o +obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o sunxi_lcd_panel.o videomodes.o obj-$(CONFIG_VIDEO_TEGRA) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_X86) += x86_fb.o diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 4b63b01..f087c2c 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -19,8 +19,13 @@ #include fdtdec.h #include fdt_support.h #include video_fb.h +#include sunxi_lcd_panel.h #include videomodes.h +#ifdef CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM +#define CONFIG_VIDEO_LCD_PANEL_LVDS +#endif Your reply to 1/3 made me notice this, which I somehow missed before, I don't think this is the right way to go about this. It seems to me that LCD_PANEL_HITACHI does not belong under the PARALLEL vs LVDS Kconfig choice, rather it should be an independent bool option which depends on PANEL_LVDS. Technically you are correct, but from a user pov it seems easier to tell the user to select which panel he has, and then the user can chose between a bunch of generic ones (generic parallel, generic lvds) and a bunch of specific panels which need some extra setup. If you insist I can live with doing things your way though, either way let me know how you want to handle this. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] scripts: fix binutils-version.sh for 'as' without a package.
On Wed, 7 Jan 2015 10:34:15 -0500
Bill Pringlemeir bpringlem...@nbsps.com wrote:
Commit 73c25753 fixed the common issue that binutil packages
(tool/organization
that packaged or built the bin-utils) are included in brackets and this may
falsely be recognized as a version. However, some tools do not provide a
'package' and previously we add the 'Gnu assembler..' to the version.
Strip out the '(package version text)' and then look for a ##.## string.
Signed-off-by: Bill Pringlemeir bpringlem...@nbsps.com
---
scripts/binutils-version.sh | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/binutils-version.sh b/scripts/binutils-version.sh
index 0bc26cf..a343681 100755
--- a/scripts/binutils-version.sh
+++ b/scripts/binutils-version.sh
@@ -14,7 +14,8 @@ if [ ${#gas} -eq 0 ]; then
exit 1
fi
-version_string=$($gas --version | head -1 | sed -e 's/.*)
*\([0-9.]*\).*/\1/' )
+version_string=$($gas --version | head -1 | \
+ sed -e 's/(.*)//; s/[^0-9.]*\([0-9.]*\).*/\1/')
MAJOR=$(echo $version_string | cut -d . -f 1)
MINOR=$(echo $version_string | cut -d . -f 2)
--
1.8.0.2
Tested-by: Masahiro Yamada yamad...@jp.panasonic.com
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Re: [U-Boot] [PATCH 0/2] Fix repeated USB scans problems
Hi, On 06-01-15 18:02, Stephen Warren wrote: On 01/06/2015 06:27 AM, Hans de Goede wrote: Hi Marek Stephen, As discussed before we've a problem where our standard bootcmds sometimes scan usb more then once, causing a large boot delay. Marek, as discussed with you before, this patch-set tackles this differently then previous sets, by simply making usb start a oneshot command (atleast until usb stop is called). Stephen the second patch then modifies config_distro_bootcmd.h to simply call usb start unconditionally, since calling it repeatedly now can be done without side-effects. Assuming you both like these patches, that leaves the question of how to merge them, they can be merged individually each through your own trees, or one of you can pick up both of them, I'll leave that to you. Users will have to get used to running usb reset rather than usb start, but I guess that's fine. Should we rename usb reset to usb restart? Either way, the series, Acked-by: Stephen Warren swar...@nvidia.com Will you do something similar for SCSI? I think it would probably make sense to do something similar for SCSI, but I'm not all that familiar with the SCSI code, and I really don't have time to work on this for SCSI, so atm I do not plan to work that. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spl: spl_nor: surround Linux-load code with #ifdef CONFIG_SPL_OS_BOOT
On Wed, 7 Jan 2015 14:47:36 -0500
Tom Rini tr...@ti.com wrote:
On Thu, Dec 18, 2014 at 04:13:48PM +0900, Masahiro Yamada wrote:
Hi Tom,
On Wed, 10 Dec 2014 20:34:03 -0500
Tom Rini tr...@ti.com wrote:
On Thu, Dec 11, 2014 at 10:01:38AM +0900, Masahiro Yamada wrote:
If CONFIG_SPL_NOR_SUPPORT is defined, spl_nor_load_image() requires
spl_start_uboot(), CONFIG_SYS_OS_BASE, CONFIG_SYS_SPL_ARGS_ADDR,
CONFIG_SYS_FDT_BASE to be defined even if users just want to run
U-Boot, not Linux. This is inconvenient.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
Good idea, but the function to check on U-Boot or Linux should be called
spl_start_uboot to match the other load methods :)
I think I am following this way.
+#if defined(CONFIG_SPL_OS_BOOT)
+int load_linux(void)
+{
+ if (spl_start_uboot())
+ return -1;
Here.
Any problem?
Yes, it should look like spl_nand_load_image().
OK.
I generally prefer to dividing shorter helper functions and shaller nests,
but common/spl/spl_nand.c is what you want, v2 is here:
http://patchwork.ozlabs.org/patch/426558/
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[U-Boot] [PATCH 3/5] i2c: imx: Optimize the i2c device recovery solution
From: Fugang Duan b38...@freescale.com
From i2c spec, if device pull down the SDA line that causes
i2c bus dead, host can send out 9 clock to let device release
SDA.
But for some special device like pfuze100, it pull down SDA line
and the solution cannot take effort.
The patch just add NACK and STOP signal after 8 dummy clock, and pmic
can release SDA line after the recovery. Test case catch 375 times of
i2c hang, and all are recovered.
Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Fugang Duan b38...@freescale.com
---
arch/arm/imx-common/i2c-mxv7.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c
index 1a632e7..b1d4ec4 100644
--- a/arch/arm/imx-common/i2c-mxv7.c
+++ b/arch/arm/imx-common/i2c-mxv7.c
@@ -33,13 +33,36 @@ static int force_idle_bus(void *priv)
printf(%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n, __func__,
sda, scl, p-sda.gp, p-scl.gp);
+ gpio_direction_output(p-scl.gp, 1);
+ udelay(1000);
/* Send high and low on the SCL line */
for (i = 0; i 9; i++) {
- gpio_direction_output(p-scl.gp, 0);
+ gpio_direction_output(p-scl.gp, 1);
udelay(50);
- gpio_direction_input(p-scl.gp);
+ gpio_direction_output(p-scl.gp, 0);
udelay(50);
}
+
+ /* Simulate the NACK */
+ gpio_direction_output(p-sda.gp, 1);
+ udelay(50);
+ gpio_direction_output(p-scl.gp, 1);
+ udelay(50);
+ gpio_direction_output(p-scl.gp, 0);
+ udelay(50);
+
+ /* Simulate the STOP signal */
+ gpio_direction_output(p-sda.gp, 0);
+ udelay(50);
+ gpio_direction_output(p-scl.gp, 1);
+ udelay(50);
+ gpio_direction_output(p-sda.gp, 1);
+ udelay(50);
+
+ /* Get the bus status */
+ gpio_direction_input(p-sda.gp);
+ gpio_direction_input(p-scl.gp);
+
start_time = get_timer(0);
for (;;) {
sda = gpio_get_value(p-sda.gp);
--
1.8.4
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Re: [U-Boot] [PATCH] MAINTAINERS: add me as a co-maintainer of KIRKWOOD
On 08.01.2015 05:14, Prafulla Wadaskar wrote: From: Luka Perkov [mailto:luka.per...@sartura.hr] Sent: 08 January 2015 05:02 To: u-boot@lists.denx.de Cc: Luka Perkov; Prafulla Wadaskar; Wolfgang Denk Subject: [PATCH] MAINTAINERS: add me as a co-maintainer of KIRKWOOD Signed-off-by: Luka Perkov luka.per...@sartura.hr CC: Prafulla Wadaskar prafu...@marvell.com CC: Wolfgang Denk w...@denx.de --- I'd like to help the U-Boot project as a Kirkwood co-maintainer and assist Prafulla with the Kirkwood maintenance. I'm maintaining U-Boot in OpenWrt project for Kirkwood and other platforms and have been sending patches to U-Boot project. By doing this I hope to shorten the time needed to get Kirkwood related patches merged in mainline. Hi Luka, Welcome... You cooperation will definitely help all of us. Luka, thanks for stepping up. Really appreciated: Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] scripts: fix binutils-version.sh for 'as' without a package.
Hi, On 07-01-15 16:34, Bill Pringlemeir wrote: Commit 73c25753 fixed the common issue that binutil packages (tool/organization that packaged or built the bin-utils) are included in brackets and this may falsely be recognized as a version. However, some tools do not provide a 'package' and previously we add the 'Gnu assembler..' to the version. Strip out the '(package version text)' and then look for a ##.## string. Signed-off-by: Bill Pringlemeir bpringlem...@nbsps.com Thanks, this fixes the errors I was seeing: Tested-by: Hans de Goede hdego...@redhat.com Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] qspi:fsl implement AHB read
Hi, Jagan
On 1/8/2015 2:20 PM, Jagan Teki wrote:
On 8 January 2015 at 08:10, Peng Fan peng@freescale.com wrote:
The QSPI controller in i.MX 6SoloX and Vybrid supports reading data using
IP register and AHB bus.
The original driver only supports reading data from IP interface. The IC
team suggests to use AHB read which is faster then IP read. Using AHB read,
we can directly memcpy, a missed access to the buffer will cause the
controller to clear the buffer and use the SEQID stored in bfgencr register
to initiate a read from flash device.
So for the read connections - controller is connected through IP and
AHB interface
is it? and I'm thinking these two are bus protocols which can use any
peripheral unlike
qspi.
Yeah. fsl qspi controller is connected through IP and AHB interface.
register access through IP interface, Data access can use IP interface
or AHB interface. There is a memory mapped region for AHB data read. If
want to use AHB data read for QSPI, the controller should be
configured by IP interface, and then can use memcpy to read data. This
patch adds the configuration for using QSPI AHB read, this configuration
is dedicated for qspi.
Since AHB bus is 64 bit width, we can not set MCR register using 32bit. In
order to minimize code change, redefine QSPI_MCR_END_CFD_LE to 64bit Little
endian but not 32bit Little endia.
Introduce a new configuration option CONFIG_SYS_FSL_QSPI_AHB. If want to
use AHB read, just define CONFIG_SYS_FSL_QSPI_AHB. If not, just ignore it.
Actually if Vybrid is migrated to use AHB read, this option can be removed and
IP read function can be discared. The reason to introduce this option
is that only i.MX SOC is tested in my side, no Vybrid platform for me.
So, where did you define?
The configuration is defined in board header file in mx6sxsabresd.h,
using #define CONFIG_SYS_FSL_QSPI_AHB.
In spi_setup_slave, the original piece code to set AHB is deleted, since
Vybrid platform does not use this to intiate AHB read. Instead, add
qspi_init_ahb_read function if defined CONFIG_SYS_FSL_QSPI_AHB.
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/spi/fsl_qspi.c | 137 +
drivers/spi/fsl_qspi.h | 15 ++
2 files changed, 142 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ad4f4ce..5e0b069 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -263,6 +263,110 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lckcr, QSPI_LCKCR_LOCK);
}
+#if defined(CONFIG_SYS_FSL_QSPI_AHB)
+/*
+ * If we have changed the content of the flash by writing or erasing,
+ * we need to invalidate the AHB buffer. If we do not do so, we may read out
+ * the wrong data. The spec tells us reset the AHB domain and Serial Flash
+ * domain at the same time.
+ */
+static inline void qspi_ahb_invalid(struct fsl_qspi *q)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q-reg_base;
+ u32 reg;
+
+ reg = qspi_read32(regs-mcr);
+ reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
+ qspi_write32(regs-mcr, reg);
+
+ /*
+* The minimum delay : 1 AHB + 2 SFCK clocks.
+* Delay 1 us is enough.
+*/
+ udelay(1);
+
+ reg = ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
+ qspi_write32(regs-mcr, reg);
+}
+
+/* Read out the data from the AHB buffer. */
+static inline void qspi_ahb_read(struct fsl_qspi *q, u8 *rxbuf, int len)
+{
+ struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q-reg_base;
+ u32 mcr_reg;
+
+ mcr_reg = qspi_read32(regs-mcr);
+
+ qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+
+ /* Read out the data directly from the AHB buffer. */
+ memcpy(rxbuf, (u8 *)(q-amba_base + q-sf_addr), len);
+
+ qspi_write32(regs-mcr, mcr_reg);
+}
+
+static void qspi_enable_ddr_mode(struct fsl_qspi_regs *regs)
+{
+ u32 reg, reg2;
+
+ reg = qspi_read32(regs-mcr);
+ /* Disable the module */
+ qspi_write32(regs-mcr, reg | QSPI_MCR_MDIS_MASK);
+
+ /* Set the Sampling Register for DDR */
+ reg2 = qspi_read32(regs-smpr);
+ reg2 = ~QSPI_SMPR_DDRSMP_MASK;
+ reg2 |= (2 QSPI_SMPR_DDRSMP_SHIFT);
+ qspi_write32(regs-smpr, reg2);
+
+ /* Enable the module again (enable the DDR too) */
+ reg |= QSPI_MCR_DDR_EN_MASK;
+ /* Enable bit 29 for imx6sx */
+ reg |= (1 29);
+
+ qspi_write32(regs-mcr, reg);
+}
+
+/*
+ * There are two different ways to read out the data from the flash:
+ * the IP Command Read and the AHB Command Read.
+ *
+ * The IC guy suggests we use the AHB Command Read which is faster
+ * then the IP Command Read. (What's more is that there is a bug in
+ * the IP Command Read in the Vybrid.)
+ *
+ * After we set up the registers for the AHB
[U-Boot] [PATCH v2] spl: spl_nor: surround Linux-load code with #ifdef CONFIG_SPL_OS_BOOT
If CONFIG_SPL_NOR_SUPPORT is defined, spl_nor_load_image() requires
spl_start_uboot(), CONFIG_SYS_OS_BASE, CONFIG_SYS_SPL_ARGS_ADDR,
CONFIG_SYS_FDT_BASE to be defined even if users just want to run
U-Boot, not Linux. This is inconvenient.
This patch is following the codying style of common/spl/spl_nand.c.
Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com
---
Changes in v2:
- follow the coding style of common/spl/spl_nand.c
common/spl/spl_nor.c | 64
1 file changed, 39 insertions(+), 25 deletions(-)
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index b444a3e..2c0e8e0 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -15,37 +15,51 @@ void spl_nor_load_image(void)
*/
spl_image.flags |= SPL_COPY_PAYLOAD_ONLY;
- if (spl_start_uboot()) {
- /*
-* Load real U-Boot from its location in NOR flash to its
-* defined location in SDRAM
-*/
- spl_parse_image_header(
- (const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+#ifdef CONFIG_SPL_OS_BOOT
+ if (!spl_start_uboot()) {
+ struct image_header *header;
- memcpy((void *)spl_image.load_addr,
- (void *)(CONFIG_SYS_UBOOT_BASE +
- sizeof(struct image_header)),
- spl_image.size);
- } else {
/*
* Load Linux from its location in NOR flash to its defined
* location in SDRAM
*/
- spl_parse_image_header(
- (const struct image_header *)CONFIG_SYS_OS_BASE);
+ header = (const struct image_header *)CONFIG_SYS_OS_BASE;
- memcpy((void *)spl_image.load_addr,
- (void *)(CONFIG_SYS_OS_BASE +
- sizeof(struct image_header)),
- spl_image.size);
+ if (image_get_os(header) == IH_OS_LINUX) {
+ /* happy - was a Linux */
- /*
-* Copy DT blob (fdt) to SDRAM. Passing pointer to flash
-* doesn't work (16 KiB should be enough for DT)
-*/
- memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
- (void *)(CONFIG_SYS_FDT_BASE),
- (16 10));
+ spl_parse_image_header(header);
+
+ memcpy((void *)spl_image.load_addr,
+ (void *)(CONFIG_SYS_OS_BASE +
+ sizeof(struct image_header)),
+ spl_image.size);
+
+ /*
+* Copy DT blob (fdt) to SDRAM. Passing pointer to
+* flash doesn't work (16 KiB should be enough for DT)
+*/
+ memcpy((void *)CONFIG_SYS_SPL_ARGS_ADDR,
+ (void *)(CONFIG_SYS_FDT_BASE),
+ (16 10));
+
+ return;
+ } else {
+ puts(The Expected Linux image was not found.\n
+Please check your NOR configuration.\n
+Trying to start u-boot now...\n);
+ }
}
+#endif
+
+ /*
+* Load real U-Boot from its location in NOR flash to its
+* defined location in SDRAM
+*/
+ spl_parse_image_header(
+ (const struct image_header *)CONFIG_SYS_UBOOT_BASE);
+
+ memcpy((void *)spl_image.load_addr,
+ (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)),
+ spl_image.size);
}
--
1.9.1
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[U-Boot] [PATCH] watchdog: omap: Add handling for CONFIG_WATCHDOG_TIMEOUT_MSECS
This change add possibility to change watchdog timeout compile time. Previous default value is kept when CONFIG_WATCHDOG_TIMEOUT_MSECS is not defined in config file. Signed-off-by: Marek Belisko marek.beli...@gmail.com --- drivers/watchdog/omap_wdt.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7ea4b60..26774d6 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -44,9 +44,6 @@ #include asm/processor.h #include asm/arch/cpu.h -/* Hardware timeout in seconds */ -#define WDT_HW_TIMEOUT 60 - static unsigned int wdt_trgr_pattern = 0x1234; void hw_watchdog_reset(void) @@ -92,8 +89,15 @@ void hw_watchdog_init(void) writel(WDT_WCLR_PRE | (PTV WDT_WCLR_PTV_OFF), wdt-wdtwclr); while (readl(wdt-wdtwwps) WDT_WWPS_PEND_WCLR) ; + /* +* If timeuot is not defined in config file +* use default 60 seconds +*/ +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6 +#endif - omap_wdt_set_timeout(WDT_HW_TIMEOUT); + omap_wdt_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); /* Sequence to enable the watchdog */ writel(0x, wdt-wdtwspr); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] doc: watchdog: Add documentation for omap watchdog
Signed-off-by: Marek Belisko marek.beli...@gmail.com --- doc/README.watchdog |3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/README.watchdog b/doc/README.watchdog index 59f306b..b1b8d84 100644 --- a/doc/README.watchdog +++ b/doc/README.watchdog @@ -33,3 +33,6 @@ CONFIG_XILINX_TB_WATCHDOG CONFIG_BFIN_WATCHDOG Available for bf5xx and bf6xx to service the watchdog. + +CONFIG_OMAP_WATCHDOG + Available for various TI OMAP 16xx, 24xx, 3xx, am33xx to service the watchdog. -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Nokia RX-51: Do not call secure PPA routine on non secure devices
On Thu 2015-01-08 10:11:40, Pali Rohár wrote: Since commit 41623c91b09a0c865fab41acdaff30f060f29ad6 u-boot running in qemu is crashing in function do_omap3_emu_romcode_call(). RX-51 board uses this function for Cortex-A8 errata 430973 workaround (Set IBE bit in ACR) which is needed only on real secure device and not in qemu. This board patch just disable calling secure PPA routine on non secure devices. Qemu implements GP device and with this patch u-boot is working in qemu again. Signed-off-by: Pali Rohár pali.ro...@gmail.com Acked-by: Pavel Machek pa...@ucw.cz --- board/nokia/rx51/rx51.c |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index b6b8ad6..08fcaf2 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -422,8 +422,12 @@ int misc_init_r(void) /* * Cortex-A8(r1p0..r1p2) errata 430973 workaround * Set IBE bit in Auxiliary Control Register + * + * Call this routine only on real secure device + * Qemu does not implement secure PPA and crash */ - omap3_update_aux_cr_secure_rx51(1 6, 0); + if (get_device_type() == HS_DEVICE) + omap3_update_aux_cr_secure_rx51(1 6, 0); return 0; } -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: fix SRAM size on support card
2015-01-06 14:18 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: The max size of available memories on slot0 and slot1 is 32MB because - EA[25] signal is not output on the save-pin mode which is used PH1-LD4 or later SoCs. - EA[25] signal is not connected by the limitation (or bug?) of the PLD logic of DCC support card. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: enable output of system bus
2015-01-06 14:20 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs, the output of the system bus is disabled by default. It must be enabled by software to have access to the system bus. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: UniPhier: add UART initialization routine for low-level debug
2015-01-06 14:28 GMT+09:00 Masahiro Yamada yamad...@jp.panasonic.com: The low-level debugging functions are useful to debug the early boot stage where the full UART driver is not available. UniPhier SoCs need to initialize the UART port 0 to use this feature. The initialization routine is called at the very entry of the lowlevel_init(). Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Applied to u-boot-uniphier/master -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-uniphier
Hi Tom, Please pull some Panasonic SoC specific updates. The following changes since commit 40ad4c4b1fea2497bc019ee82163b76d4b076730: Kconfig: move EXPERT option under General setup menu (2015-01-07 14:48:47 -0500) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to b4ad44baab713af371b1113dd63dd222ba73ba13: ARM: UniPhier: add UART initialization routine for low-level debug (2015-01-08 23:01:56 +0900) Masahiro Yamada (3): ARM: UniPhier: fix SRAM size on support card ARM: UniPhier: enable output of system bus ARM: UniPhier: add UART initialization routine for low-level debug arch/arm/cpu/armv7/uniphier/lowlevel_init.S | 4 arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S | 29 + arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c| 7 +++ arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S | 39 +++ arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile | 1 + arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S | 29 + arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 7 +++ arch/arm/cpu/armv7/uniphier/support_card.c| 6 +++--- arch/arm/include/asm/arch-uniphier/debug-uart.S | 24 arch/arm/include/asm/arch-uniphier/sbc-regs.h | 1 + 12 files changed, 146 insertions(+), 3 deletions(-) create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S create mode 100644 arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S create mode 100644 arch/arm/include/asm/arch-uniphier/debug-uart.S -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 18/18] trats2: config: disable i2c peripherals if testing dm i2c
On 08/01/15 20:33, Przemyslaw Marczak wrote: Most i2c peripherals for this board doesn't support new i2c api. So CONFIG_DM_I2C on this board can be enabled for test only. The i2c command works fine with it. This is the first step before adding support to the new power framework soon. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Lukasz Majewski l.majew...@samsung.com Cc: Jaehoon Chung jh80.ch...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/trats2.h | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 42481ab..8b099dd 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -159,15 +159,18 @@ #define CONFIG_RANDOM_UUID /* I2C */ -#include asm/arch/gpio.h - +#if 0 /* For test */ +#define CONFIG_DM_I2C +#endif please remove test code. #define CONFIG_CMD_I2C - -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 10 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C #define CONFIG_MAX_I2C_NUM 8 + #define CONFIG_SYS_I2C_SOFT #define CONFIG_SYS_I2C_SOFT_SPEED5 #define CONFIG_SYS_I2C_SOFT_SLAVE0x00 @@ -177,6 +180,8 @@ #define CONFIG_SOFT_I2C_READ_REPEATED_START #define CONFIG_SYS_I2C_INIT_BOARD +#include asm/arch/gpio.h + #ifndef __ASSEMBLY__ int get_soft_i2c_scl_pin(void); int get_soft_i2c_sda_pin(void); @@ -192,6 +197,7 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_POWER_MUIC_MAX77693 #define CONFIG_POWER_FG_MAX77693 #define CONFIG_POWER_BATTERY_TRATS2 +#endif /* ifndef CONFIG_DM_I2C */ /* Security subsystem - enable hw_rand() */ #define CONFIG_EXYNOS_ACE_SHA @@ -203,11 +209,13 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_MISC_INIT_R /* Download menu - Samsung common */ +#ifndef CONFIG_DM_I2C #define CONFIG_LCD_MENU #define CONFIG_LCD_MENU_BOARD /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ +#include power/pmic.h #include power/max77686_pmic.h #define KEY_PWR_PMIC_NAMEMAX77686_PMIC @@ -219,6 +227,7 @@ int get_soft_i2c_sda_pin(void); #define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 #define KEY_VOL_DOWN_GPIOEXYNOS4X12_GPIO_X33 #endif /* __ASSEMBLY__ */ +#endif /* LCD console */ #define LCD_BPP LCD_COLOR16 Thanks, Minkyu Kang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 08/18] exynos5: config: prepare for dm i2c support
Hi, On 08/01/15 20:33, Przemyslaw Marczak wrote: This commit allows for test i2c drivers with new i2c api on Exynos5xxx based boards. The S3C24X0 I2C driver supports driver model I2C api, but i2c peripherials drivers on exynos5 boards doesn't. So this commit allows for test ported driver before switch the Exynos5 boards to DM I2C at all. Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com Cc: Akshay Saraswat aksha...@samsung.com Cc: Simon Glass s...@chromium.org Cc: Minkyu Kang mk7.k...@samsung.com --- include/configs/exynos5-common.h | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ad63f3c..b7af8a5 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -54,13 +54,6 @@ #define CONFIG_CMD_DTT #define CONFIG_TMU_CMD_DTT -/* TPM */ -#define CONFIG_TPM -#define CONFIG_CMD_TPM -#define CONFIG_TPM_TIS_I2C -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER3 -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR0x20 - /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 #define CONFIG_SUPPORT_EMMC_BOOT @@ -126,15 +119,29 @@ #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) /* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C +#if 0 /* For test */ +#define CONFIG_DM_I2C +#endif please remove test code #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0_SLAVE0x0 +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C +#define CONFIG_I2C_MULTI_BUS +#endif /* ifndef CONFIG_DM_I2C */ #define CONFIG_I2C_EDID +/* TPM */ +#ifndef CONFIG_DM_I2C +#define CONFIG_TPM +#define CONFIG_CMD_TPM +#define CONFIG_TPM_TIS_I2C +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER3 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR0x20 +#endif + /* SPI */ #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Fix repeated USB scans problems
Hi, On 08-01-15 18:06, Marek Vasut wrote: On Thursday, January 08, 2015 at 05:16:53 PM, Stephen Warren wrote: On 01/08/2015 01:34 AM, Hans de Goede wrote: Hi, Hi! On 08-01-15 01:19, Stephen Warren wrote: On 01/07/2015 04:35 PM, Marek Vasut wrote: On Tuesday, January 06, 2015 at 06:02:57 PM, Stephen Warren wrote: snip Should we rename usb reset to usb restart? No, let's not mess with the UI any more than we already did. Well, it might not be such a bad idea if the semantics are changing, to give people a heads-up? Only the semantics of usb start are changing, and you are suggesting renaming usb reset which remains unchanged ... Yes, that's true. So I suppose we should indeed not rename anything. OK, let's go with this approach now. So we are all in agreement, good, so through who's tree are these 2 patches going to go upstream ? Note I can take them upstream through the sunxi tree, but the usb tree seems better to me ... Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Fix repeated USB scans problems
On Thursday, January 08, 2015 at 06:23:55 PM, Hans de Goede wrote: Hi, On 08-01-15 18:06, Marek Vasut wrote: On Thursday, January 08, 2015 at 05:16:53 PM, Stephen Warren wrote: On 01/08/2015 01:34 AM, Hans de Goede wrote: Hi, Hi! On 08-01-15 01:19, Stephen Warren wrote: On 01/07/2015 04:35 PM, Marek Vasut wrote: On Tuesday, January 06, 2015 at 06:02:57 PM, Stephen Warren wrote: snip Should we rename usb reset to usb restart? No, let's not mess with the UI any more than we already did. Well, it might not be such a bad idea if the semantics are changing, to give people a heads-up? Only the semantics of usb start are changing, and you are suggesting renaming usb reset which remains unchanged ... Yes, that's true. So I suppose we should indeed not rename anything. OK, let's go with this approach now. So we are all in agreement, good, so through who's tree are these 2 patches going to go upstream ? Note I can take them upstream through the sunxi tree, but the usb tree seems better to me ... I can pick them, shall I pick them as they are ? Are they for -next or current ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/2] Fix repeated USB scans problems
Hi, On 08-01-15 18:36, Marek Vasut wrote: On Thursday, January 08, 2015 at 06:23:55 PM, Hans de Goede wrote: Hi, On 08-01-15 18:06, Marek Vasut wrote: On Thursday, January 08, 2015 at 05:16:53 PM, Stephen Warren wrote: On 01/08/2015 01:34 AM, Hans de Goede wrote: Hi, Hi! On 08-01-15 01:19, Stephen Warren wrote: On 01/07/2015 04:35 PM, Marek Vasut wrote: On Tuesday, January 06, 2015 at 06:02:57 PM, Stephen Warren wrote: snip Should we rename usb reset to usb restart? No, let's not mess with the UI any more than we already did. Well, it might not be such a bad idea if the semantics are changing, to give people a heads-up? Only the semantics of usb start are changing, and you are suggesting renaming usb reset which remains unchanged ... Yes, that's true. So I suppose we should indeed not rename anything. OK, let's go with this approach now. So we are all in agreement, good, so through who's tree are these 2 patches going to go upstream ? Note I can take them upstream through the sunxi tree, but the usb tree seems better to me ... I can pick them, shall I pick them as they are ? Yes, AFAIK there were no requests for changes. Are they for -next or current ? They are intended for -next, the double usb scan when using a usb keyboard *and* booting from usb is a nuisance, but not fatal, and very few people actually use the combo, so given that current is about to be released in a couple of days lets play it safe :) Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/17] videomodes: Add support for refresh and pclk_khz to video_get_params()
On Wed, 24 Dec 2014 20:06:13 +0100 Hans de Goede hdego...@redhat.com wrote: Add support to video_get_params() for setting the new refresh and pixclock_khz struct ctfb_res_modes members. Signed-off-by: Hans de Goede hdego...@redhat.com Acked-by: Anatolij Gustschin ag...@denx.de ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: vf610: fix boot from SD-card
On 8 Jan 2015, ste...@agner.ch wrote: Boot from SD-card (and probably also from NAND) was broken since commit d6d07a9bec (arm: vf610: add NAND support for vf610twr). It looks like the increased size of U-Boot lead to a situation where the boot ROM overwrote its own stack/heap while loading U-Boot from the SD-card to the SRAM. However, U-Boot worked fine when loaded through USB serial loader directly into SRAM. It looks like loading from SD-card uses other stack/heap location then the serial loader (or maybe no stack or heap at all). This fix moves U-Boot to gfxRAM, which is 512kB in size and is not used by the boot ROM nor the SD-card loader of it. Signed-off-by: Stefan Agner ste...@agner.ch --- We use U-Boot from gfxRAM on Vybrid since quite a while for the Colibri VF50/VF61 modules in our downstream U-Boot branch. Hence this is quite well tested. Just today I discovered that this is broken on the Tower module. Back then, when I made the offending change, I only tested on the Tower board using the serial loader, since I thought the behaviour should be exactly the same. But now, I know better... :-) If still possible, it would be great to get this into v2015.01... include/configs/vf610twr.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 6fd0b17..bd79e81 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -125,7 +125,10 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x8200 -#define CONFIG_SYS_TEXT_BASE 0x3f008000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_SYS_TEXT_BASE 0x3f408000 +#define CONFIG_BOARD_SIZE_LIMIT 524288 #define CONFIG_EXTRA_ENV_SETTINGS \ script=boot.scr\0 \ Acked-by: Bill Pringlemeir bpringlem...@nbsps.com See also: http://lists.denx.de/pipermail/u-boot/2014-December/197641.html It seems since v2014.04 u-boot on the Vybrid Tower SD card has not booted. Most users will probably boot this way. https://community.freescale.com/docs/DOC-95248 Thanks, Bill Pringlemeir. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
