[U-Boot] ARMv8 targets are broken on 2015.04-rc3
Guys, I found these targets are broken on tag 2015.04-rc3 ls2085a_emu_D4 vexpress_aemv8a vexpress_aemv8a_juno ls2085a_emu vexpress_aemv8a_semi xilinx_zynqmp ls2085a_simu git bisect points to this commit a389531439a7d5cea2829054edcf438dc76e79a9. However it is really caused by this one commit e771a3d538a4fbe235864061ff3c81a8acb11082 Author: Marc Zyngier marc.zyng...@arm.com AuthorDate: Sat Jul 12 14:24:07 2014 +0100 Commit: Albert ARIBAUD albert.u.b...@aribaud.net CommitDate: Mon Jul 28 17:19:52 2014 +0200 ARM: HYP/non-sec/PSCI: emit DT nodes Generate the PSCI node in the device tree. Also add a reserve section for the secure code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Ian Campbell i...@hellion.org.uk This commit add armv7.h to bootm-fdt.c file. --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,13 +17,14 @@ #include common.h #include fdt_support.h +#include asm/armv7.h Shouldn't this line be architecture dependent? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/22] dm: core: Add a uclass pre_probe() method for devices
Some uclasses want to set up a device before it is probed. Add a method
for this.
An example is with PCI, where a PCI uclass wants to set up its private
data for later use. This allows the device's uclass() method to make calls
whcih use that data (for example, read PCI memory regions from device
tree, set up bus numbers).
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/core/device.c| 2 +-
drivers/core/uclass.c| 10 +-
include/dm/test.h| 1 +
include/dm/uclass-internal.h | 7 ---
include/dm/uclass.h | 2 ++
test/dm/core.c | 7 ++-
test/dm/test-uclass.c| 12
7 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 6bd4b26..7483405 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -227,7 +227,7 @@ int device_probe_child(struct udevice *dev, void
*parent_priv)
}
dev-seq = seq;
- ret = uclass_pre_probe_child(dev);
+ ret = uclass_pre_probe_device(dev);
if (ret)
goto fail;
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 289a5d2..98c15e5 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -391,9 +391,17 @@ int uclass_resolve_seq(struct udevice *dev)
return seq;
}
-int uclass_pre_probe_child(struct udevice *dev)
+int uclass_pre_probe_device(struct udevice *dev)
{
struct uclass_driver *uc_drv;
+ int ret;
+
+ uc_drv = dev-uclass-uc_drv;
+ if (uc_drv-pre_probe) {
+ ret = uc_drv-pre_probe(dev);
+ if (ret)
+ return ret;
+ }
if (!dev-parent)
return 0;
diff --git a/include/dm/test.h b/include/dm/test.h
index 707c69e..b310e5f 100644
--- a/include/dm/test.h
+++ b/include/dm/test.h
@@ -44,6 +44,7 @@ enum {
/* For uclass */
DM_TEST_OP_POST_BIND,
DM_TEST_OP_PRE_UNBIND,
+ DM_TEST_OP_PRE_PROBE,
DM_TEST_OP_POST_PROBE,
DM_TEST_OP_PRE_REMOVE,
DM_TEST_OP_INIT,
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
index f2f254a..ae2a93d 100644
--- a/include/dm/uclass-internal.h
+++ b/include/dm/uclass-internal.h
@@ -44,15 +44,16 @@ int uclass_bind_device(struct udevice *dev);
int uclass_unbind_device(struct udevice *dev);
/**
- * uclass_pre_probe_child() - Deal with a child that is about to be probed
+ * uclass_pre_probe_device() - Deal with a device that is about to be probed
*
* Perform any pre-processing that is needed by the uclass before it can be
- * probed.
+ * probed. This includes the uclass' pre-probe() method and the parent
+ * uclass' child_pre_probe() method.
*
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
-int uclass_pre_probe_child(struct udevice *dev);
+int uclass_pre_probe_device(struct udevice *dev);
/**
* uclass_post_probe_device() - Deal with a device that has just been probed
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index d6c40c6..d57d804 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -53,6 +53,7 @@ struct udevice;
* @id: ID number of this uclass
* @post_bind: Called after a new device is bound to this uclass
* @pre_unbind: Called before a device is unbound from this uclass
+ * @pre_probe: Called before a new device is probed
* @post_probe: Called after a new device is probed
* @pre_remove: Called before a device is removed
* @child_post_bind: Called after a child is bound to a device in this uclass
@@ -80,6 +81,7 @@ struct uclass_driver {
enum uclass_id id;
int (*post_bind)(struct udevice *dev);
int (*pre_unbind)(struct udevice *dev);
+ int (*pre_probe)(struct udevice *dev);
int (*post_probe)(struct udevice *dev);
int (*pre_remove)(struct udevice *dev);
int (*child_post_bind)(struct udevice *dev);
diff --git a/test/dm/core.c b/test/dm/core.c
index 7be28e4..990d390 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -141,6 +141,7 @@ static int dm_test_autoprobe(struct dm_test_state *dms)
ut_assert(uc);
ut_asserteq(1, dm_testdrv_op_count[DM_TEST_OP_INIT]);
+ ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_PRE_PROBE]);
ut_asserteq(0, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
/* The root device should not be activated until needed */
@@ -167,8 +168,12 @@ static int dm_test_autoprobe(struct dm_test_state *dms)
ut_assert(dms-root-flags DM_FLAG_ACTIVATED);
}
- /* Our 3 dm_test_infox children should be passed to post_probe */
+ /*
+* Our 3 dm_test_info children should be passed to pre_probe and
+* post_probe
+*/
ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_POST_PROBE]);
+ ut_asserteq(3, dm_testdrv_op_count[DM_TEST_OP_PRE_PROBE]);
/* Also we can check the
[U-Boot] Please pull u-boot-marvell master
Hi Tom, this series contains small kirkwood/marvell fixes. Please pull when you find the time. The following changes since commit 694cc87b76b1063a2a7a8bd1809e990df0a469f8: arm, da8xx: convert ipam390 board to generic board support (2015-03-05 10:08:13 -0500) are available in the git repository at: git://git.denx.de/u-boot-marvell.git for you to fetch changes up to dbfc4c93f4d8cb495a4fd83b7edbbc3db1e04816: dreamplug: set CONFIG_BUILD_TARGET to build u-boot.kwb (2015-03-05 22:09:00 +0100) Ajay Bhargav (2): arm: gplugd: convert to generic board arm: aspenite: convert to generic board Chris Packham (1): kwbimage: align v1 binary header to 4B Ian Campbell (2): dreamplug: switch to GENERIC_BOARD dreamplug: set CONFIG_BUILD_TARGET to build u-boot.kwb include/configs/aspenite.h | 5 + include/configs/dreamplug.h | 4 include/configs/gplugd.h| 5 + tools/kwbimage.c| 1 + 4 files changed, 15 insertions(+) Regards, Luka ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/22] x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/cpu/baytrail/early_uart.c | 5 ++-
arch/x86/cpu/ivybridge/bd82x6x.c | 32 +++---
arch/x86/cpu/ivybridge/cpu.c | 38
arch/x86/cpu/ivybridge/early_init.c | 58 +
arch/x86/cpu/ivybridge/early_me.c| 12 +++---
arch/x86/cpu/ivybridge/gma.c | 4 +-
arch/x86/cpu/ivybridge/lpc.c | 74
arch/x86/cpu/ivybridge/northbridge.c | 6 +--
arch/x86/cpu/ivybridge/pch.c | 4 +-
arch/x86/cpu/ivybridge/pci.c | 4 +-
arch/x86/cpu/ivybridge/report_platform.c | 4 +-
arch/x86/cpu/ivybridge/sata.c| 61 +-
arch/x86/cpu/ivybridge/sdram.c | 20 -
arch/x86/cpu/ivybridge/usb_ehci.c| 4 +-
arch/x86/cpu/ivybridge/usb_xhci.c| 8 ++--
arch/x86/cpu/pci.c | 12 +++---
arch/x86/cpu/quark/quark.c | 4 +-
arch/x86/cpu/queensbay/tnc.c | 4 +-
arch/x86/include/asm/pci.h | 12 +++---
arch/x86/lib/bios_interrupts.c | 12 +++---
drivers/gpio/intel_ich6_gpio.c | 16 +++
21 files changed, 199 insertions(+), 195 deletions(-)
diff --git a/arch/x86/cpu/baytrail/early_uart.c
b/arch/x86/cpu/baytrail/early_uart.c
index 4199210..b64a3a9 100644
--- a/arch/x86/cpu/baytrail/early_uart.c
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -50,7 +50,7 @@ static void score_select_func(int pad, int func)
writel(reg, pconf0_addr);
}
-static void pci_write_config32(int dev, unsigned int where, u32 value)
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
{
unsigned long addr;
@@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where,
u32 value)
int setup_early_uart(void)
{
/* Enable the legacy UART hardware. */
- pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+ x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
+ 1);
/*
* Set up the pads to the UART function. This allows the signals to
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 65a17d3..56b19e3 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -22,36 +22,36 @@ void bd82x6x_pci_init(pci_dev_t dev)
debug(bd82x6x PCI init.\n);
/* Enable Bus Master */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
+ reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_MASTER;
- pci_write_config16(dev, PCI_COMMAND, reg16);
+ x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
- pci_write_config8(dev, INTR, 0xff);
+ x86_pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
+ reg16 = x86_pci_read_config16(dev, BCTRL);
reg16 = ~(1 0);
reg16 = ~(1 1);
- pci_write_config16(dev, BCTRL, reg16);
+ x86_pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
- reg8 = pci_read_config8(dev, SMLT);
+ reg8 = x86_pci_read_config8(dev, SMLT);
reg8 = 0x07;
reg8 |= (0x04 3);
- pci_write_config8(dev, SMLT, reg8);
+ x86_pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
- pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+ x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
- reg16 = pci_read_config16(dev, PSTS);
+ reg16 = x86_pci_read_config16(dev, PSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, PSTS, reg16);
+ x86_pci_write_config16(dev, PSTS, reg16);
- reg16 = pci_read_config16(dev, SECSTS);
+ reg16 = x86_pci_read_config16(dev, SECSTS);
/* reg16 |= 0xf900; */
- pci_write_config16(dev, SECSTS, reg16);
+ x86_pci_write_config16(dev, SECSTS, reg16);
}
#define PCI_BRIDGE_UPDATE_COMMAND
@@ -59,7 +59,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
{
uint16_t command;
- command = pci_read_config16(dev, PCI_COMMAND);
+ command = x86_pci_read_config16(dev, PCI_COMMAND);
command |= PCI_COMMAND_IO;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/*
@@ -67,7 +67,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
* ROM and APICs to become invisible.
[U-Boot] [PATCH v2 04/22] dm: Add a new CPU init function which can use driver model
Since driver model is set up after arch_cpu_init(), that function cannot
use drivers. Add a new arch_cpu_init_dm() function which is called
immediately after driver model is ready, and can reference devices.
This can be used to probe essential devices for the CPU.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add a new patch with a CPU init function which can use driver model
common/board_f.c | 6 ++
include/common.h | 11 +++
2 files changed, 17 insertions(+)
diff --git a/common/board_f.c b/common/board_f.c
index 4d8b8a6..8bbece2 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -787,6 +787,11 @@ __weak int reserve_arch(void)
return 0;
}
+__weak int arch_cpu_init_dm(void)
+{
+ return 0;
+}
+
static init_fnc_t init_sequence_f[] = {
#ifdef CONFIG_SANDBOX
setup_ram_buf,
@@ -807,6 +812,7 @@ static init_fnc_t init_sequence_f[] = {
fdtdec_check_fdt,
#endif
initf_dm,
+ arch_cpu_init_dm,
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f,
#endif
diff --git a/include/common.h b/include/common.h
index 77c55c6..f95 100644
--- a/include/common.h
+++ b/include/common.h
@@ -253,6 +253,17 @@ int update_flash_size(int flash_size);
int arch_early_init_r(void);
/**
+ * arch_cpu_init_dm() - init CPU after driver model is available
+ *
+ * This is called immediately after driver model is available before
+ * relocation. This is similar to arch_cpu_init() but is able to reference
+ * devices
+ *
+ * @return 0 if OK, -ve on error
+ */
+int arch_cpu_init_dm(void);
+
+/**
* Reserve all necessary stacks
*
* This is used in generic board init sequence in common/board_f.c. Each
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 15/22] dm: sandbox: Add a simple PCI driver
Add a driver which can access emulations of devices and make them available
in sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/pci/Kconfig | 10 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_sandbox.c | 79 +++
3 files changed, 90 insertions(+)
create mode 100644 drivers/pci/pci_sandbox.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 8b7e2ee..167d405 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -9,4 +9,14 @@ config DM_PCI
available PCI devices, allows scanning of PCI buses and provides
device configuration support.
+config PCI_SANDBOX
+ bool Sandbox PCI support
+ depends on SANDBOX DM_PCI
+ help
+ Support PCI on sandbox, as an emulated bus. This permits testing of
+ PCI feature such as bus scanning, device configuration and device
+ access. The available (emulated) devices are defined statically in
+ the device tree but the normal PCI scan technique is used to find
+ then.
+
endmenu
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index db82786..9e2e5f9 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -7,6 +7,7 @@
ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o
+obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
else
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c
new file mode 100644
index 000..6de5130
--- /dev/null
+++ b/drivers/pci/pci_sandbox.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Written by Simon Glass s...@chromium.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include inttypes.h
+#include pci.h
+#include dm/root.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ struct dm_pci_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ ret = sandbox_pci_get_emul(bus, devfn, emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ ops = pci_get_emul_ops(emul);
+ if (!ops || !ops-write_config)
+ return -ENOSYS;
+
+ return ops-write_config(emul, offset, value, size);
+}
+
+static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct dm_pci_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ /* Prepare the default response */
+ *valuep = pci_get_ff(size);
+ ret = sandbox_pci_get_emul(bus, devfn, emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ ops = pci_get_emul_ops(emul);
+ if (!ops || !ops-read_config)
+ return -ENOSYS;
+
+ return ops-read_config(emul, offset, valuep, size);
+}
+
+static int sandbox_pci_child_post_bind(struct udevice *dev)
+{
+ /* Attach an emulator if we can */
+ return dm_scan_fdt_node(dev, gd-fdt_blob, dev-of_offset, false);
+}
+
+static const struct dm_pci_ops sandbox_pci_ops = {
+ .read_config = sandbox_pci_read_config,
+ .write_config = sandbox_pci_write_config,
+};
+
+static const struct udevice_id sandbox_pci_ids[] = {
+ { .compatible = sandbox,pci },
+ { }
+};
+
+U_BOOT_DRIVER(pci_sandbox) = {
+ .name = pci_sandbox,
+ .id = UCLASS_PCI,
+ .of_match = sandbox_pci_ids,
+ .ops= sandbox_pci_ops,
+ .child_post_bind = sandbox_pci_child_post_bind,
+ .per_child_platdata_auto_alloc_size =
+ sizeof(struct pci_child_platdata),
+};
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 07/22] fdt: Tighten up error handling in fdtdec_get_pci_addr()
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).
Update the error return value to allow these different situations to be
distinguished.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Add -ve sign before ENXIO
include/fdtdec.h | 4 +++-
lib/fdtdec.c | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 21bd6bb..6944048 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -327,7 +327,9 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
* @param type pci address type (FDT_PCI_SPACE_xxx)
* @param prop_namename of property to find
* @param addr returns pci address in the form of fdt_pci_addr
- * @return 0 if ok, negative on error
+ * @return 0 if ok, -ENOENT if the property did not exist, -EINVAL if the
+ * format of the property was invalid, -ENXIO if the requested
+ * address type was not found
*/
int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
const char *prop_name, struct fdt_pci_addr *addr);
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index e47fa96..9212f03 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -160,8 +160,10 @@ int fdtdec_get_pci_addr(const void *blob, int node, enum
fdt_pci_space type,
}
}
- if (i == num)
+ if (i == num) {
+ ret = -ENXIO;
goto fail;
+ }
return 0;
} else {
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 08/22] dm: core: Add dev_get_uclass_priv() to access uclass private data
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cmd_sf.c| 2 +-
common/cros_ec.c | 2 +-
drivers/core/device.c | 10 ++
drivers/gpio/at91_gpio.c | 2 +-
drivers/gpio/bcm2835_gpio.c| 2 +-
drivers/gpio/gpio-uclass.c | 22 +++---
drivers/gpio/intel_ich6_gpio.c | 2 +-
drivers/gpio/mxc_gpio.c| 2 +-
drivers/gpio/omap_gpio.c | 2 +-
drivers/gpio/s5p_gpio.c| 2 +-
drivers/gpio/sandbox.c | 6 +++---
drivers/gpio/sunxi_gpio.c | 2 +-
drivers/gpio/tegra_gpio.c | 2 +-
drivers/i2c/i2c-uclass.c | 6 +++---
drivers/i2c/sandbox_i2c.c | 2 +-
drivers/misc/cros_ec.c | 6 +++---
drivers/misc/cros_ec_i2c.c | 2 +-
drivers/misc/cros_ec_sandbox.c | 2 +-
drivers/misc/cros_ec_spi.c | 4 ++--
drivers/mtd/spi/sf-uclass.c| 2 +-
drivers/mtd/spi/sf_probe.c | 8
drivers/serial/serial-uclass.c | 4 ++--
drivers/spi/spi-uclass.c | 4 ++--
include/dm/device.h| 10 ++
include/i2c.h | 8
test/dm/core.c | 2 +-
test/dm/test-uclass.c | 4 ++--
27 files changed, 71 insertions(+), 51 deletions(-)
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 5c788e9..20f14d3 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -130,7 +130,7 @@ static int do_spi_flash_probe(int argc, char * const argv[])
return 1;
}
- flash = new-uclass_priv;
+ flash = dev_get_uclass_priv(new);
#else
new = spi_flash_probe(bus, cs, speed, mode);
if (!new) {
diff --git a/common/cros_ec.c b/common/cros_ec.c
index bb299bc..64b4679 100644
--- a/common/cros_ec.c
+++ b/common/cros_ec.c
@@ -35,7 +35,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void)
debug(%s: Error %d\n, __func__, ret);
return NULL;
}
- return dev-uclass_priv;
+ return dev_get_uclass_priv(dev);
#else
return local.cros_ec_dev;
#endif
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 73c3e07..92e8a57 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -305,6 +305,16 @@ void *dev_get_priv(struct udevice *dev)
return dev-priv;
}
+void *dev_get_uclass_priv(struct udevice *dev)
+{
+ if (!dev) {
+ dm_warn(%s: null device\n, __func__);
+ return NULL;
+ }
+
+ return dev-uclass_priv;
+}
+
void *dev_get_parentdata(struct udevice *dev)
{
if (!dev) {
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 22fbd63..75a32ee 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -511,7 +511,7 @@ static int at91_gpio_probe(struct udevice *dev)
{
struct at91_port_priv *port = dev_get_priv(dev);
struct at91_port_platdata *plat = dev_get_platdata(dev);
- struct gpio_dev_priv *uc_priv = dev-uclass_priv;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv-bank_name = plat-bank_name;
uc_priv-gpio_count = GPIO_PER_BANK;
diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c
index 0244c01..fbc641d 100644
--- a/drivers/gpio/bcm2835_gpio.c
+++ b/drivers/gpio/bcm2835_gpio.c
@@ -105,7 +105,7 @@ static int bcm2835_gpio_probe(struct udevice *dev)
{
struct bcm2835_gpios *gpios = dev_get_priv(dev);
struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
- struct gpio_dev_priv *uc_priv = dev-uclass_priv;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv-bank_name = GPIO;
uc_priv-gpio_count = BCM2835_GPIO_COUNT;
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index a69bbd2..b6e1058 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -34,7 +34,7 @@ static int gpio_to_device(unsigned int gpio, struct gpio_desc
*desc)
for (ret = uclass_first_device(UCLASS_GPIO, dev);
dev;
ret = uclass_next_device(dev)) {
- uc_priv = dev-uclass_priv;
+ uc_priv = dev_get_uclass_priv(dev);
if (gpio = uc_priv-gpio_base
gpio uc_priv-gpio_base + uc_priv-gpio_count) {
desc-dev = dev;
@@ -65,7 +65,7 @@ int gpio_lookup_name(const char *name, struct udevice **devp,
ret = uclass_next_device(dev)) {
int len;
- uc_priv = dev-uclass_priv;
+ uc_priv = dev_get_uclass_priv(dev);
if (numeric != -1) {
offset = numeric - uc_priv-gpio_base;
/* Allow GPIOs to be numbered from 0 */
@@ -116,7 +116,7 @@ static int dm_gpio_request(struct
Re: [U-Boot] [PATCH 1/4][v3] fsl_sfp : Move ccsr_sfp_regs definition to common include
On 02/26/2015 08:13 PM, Gaurav Rana wrote: Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Gaurav Rana gaurav.r...@freescale.com --- Changes in v3: Modify copyright in include/fsl_sfp.h. Changes in v2: No change. Change in other patches of the patch set. Applied to u-boot-mpc85xx master after fixing commit message indentation, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
On Thursday, March 05, 2015 at 05:47:01 PM, Stefan Roese wrote: [...] Please don't mention platforms in the help for what I think of as IP-block-vendor drivers. The Cadence QSPI block will be reused by others and I can see someone needing to patch the help text. How about: Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this Cadence IP core. Even better. Thanks Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 1/2] spi: Add Designware SPI controller Kconfig entry
Add DWC SPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com --- drivers/spi/Kconfig | 8 1 file changed, 8 insertions(+) V2: Improve the help text. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7ae2727..0f1d740 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -10,3 +10,11 @@ config DM_SPI as 'parent data' to every slave on each bus. Slaves typically use driver-private data instead of extending the spi_slave structure. + +config DESIGNWARE_SPI + bool Designware SPI driver + depends on DM_SPI + help + Enable the Designware SPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Designware + IP core. -- 2.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 12/22] dm: pci: Move common PCI functions into their own file
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/pci/Makefile | 2 +-
drivers/pci/pci.c| 281 +
drivers/pci/pci_common.c | 292 +++
include/pci.h| 14 +++
4 files changed, 313 insertions(+), 276 deletions(-)
create mode 100644 drivers/pci/pci_common.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 50b7be5..856a5f5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -6,7 +6,7 @@
#
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
-obj-$(CONFIG_PCI) += pci.o pci_auto.o pci_rom.o
+obj-$(CONFIG_PCI) += pci.o pci_common.o pci_auto.o pci_rom.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e1296ca..3babd94 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -101,25 +101,6 @@ PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x00ff)
PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x)
-/* Get a virtual address associated with a BAR region */
-void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
-{
- pci_addr_t pci_bus_addr;
- u32 bar_response;
-
- /* read BAR address */
- pci_read_config_dword(pdev, bar, bar_response);
- pci_bus_addr = (pci_addr_t)(bar_response ~0xf);
-
- /*
-* Pass 0 as the length argument to pci_bus_to_virt. The arg
-* isn't actualy used on any platform because u-boot assumes a static
-* linear mapping. In the future, this could read the BAR size
-* and pass that as the size if needed.
-*/
- return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
-}
-
/*
*
*/
@@ -187,106 +168,22 @@ int pci_last_busno(void)
pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
struct pci_controller * hose;
- u16 vendor, device;
- u8 header_type;
pci_dev_t bdf;
- int i, bus, found_multi = 0;
+ int bus;
for (hose = pci_get_hose_head(); hose; hose = hose-next) {
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
- for (bus = hose-last_busno; bus = hose-first_busno; bus--)
+ for (bus = hose-last_busno; bus = hose-first_busno; bus--) {
#else
- for (bus = hose-first_busno; bus = hose-last_busno; bus++)
+ for (bus = hose-first_busno; bus = hose-last_busno; bus++) {
#endif
- for (bdf = PCI_BDF(bus, 0, 0);
-bdf PCI_BDF(bus + 1, 0, 0);
-bdf += PCI_BDF(0, 0, 1)) {
- if (pci_skip_dev(hose, bdf))
- continue;
-
- if (!PCI_FUNC(bdf)) {
- pci_read_config_byte(bdf,
-PCI_HEADER_TYPE,
-header_type);
-
- found_multi = header_type 0x80;
- } else {
- if (!found_multi)
- continue;
- }
-
- pci_read_config_word(bdf,
-PCI_VENDOR_ID,
-vendor);
- pci_read_config_word(bdf,
-PCI_DEVICE_ID,
-device);
-
- for (i = 0; ids[i].vendor != 0; i++) {
- if (vendor == ids[i].vendor
- device == ids[i].device) {
- if (index = 0)
- return bdf;
-
- index--;
- }
- }
- }
- }
-
- return -1;
-}
-
-pci_dev_t pci_find_class(uint find_class, int index)
-{
- int bus;
- int devnum;
- pci_dev_t bdf;
- uint32_t class;
-
- for (bus = 0; bus = pci_last_busno(); bus++) {
- for (devnum = 0; devnum PCI_MAX_PCI_DEVICES - 1; devnum++) {
- pci_read_config_dword(PCI_BDF(bus, devnum, 0),
- PCI_CLASS_REVISION, class);
- if (class 16 == 0x)
- continue;
-
-
[U-Boot] [PATCH v2 02/22] fdt: Export fdtdec_get_number() for general use
This function is missing a prototype but is more widey useful. Add it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
include/fdtdec.h | 11 +++
lib/fdtdec.c | 2 +-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1233dfb..21bd6bb 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -386,6 +386,17 @@ s32 fdtdec_get_int(const void *blob, int node, const char
*prop_name,
s32 default_val);
/**
+ * Get a variable-sized number from a property
+ *
+ * This reads a number from one or more cells.
+ *
+ * @param ptr Pointer to property
+ * @param cellsNumber of cells containing the number
+ * @return the value in the cells
+ */
+u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells);
+
+/**
* Look up a 64-bit integer property in a node and return it. The property
* must have at least 8 bytes of data (2 cells). The first two cells are
* concatenated to form a 8 bytes value, where the first cell is top half and
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 21933e4..e47fa96 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -918,7 +918,7 @@ int fdtdec_read_fmap_entry(const void *blob, int node,
const char *name,
return 0;
}
-static u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
+u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
{
u64 number = 0;
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 11/22] dm: Show both allocated and requested seq numbers in 'dm uclass'
Both of these values are useful for understanding what is going on, so show them both. The requested number comes from a device tree alias. The allocated one is set up when the device is activated, and is unique throughout the uclass. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: None test/dm/cmd_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/dm/cmd_dm.c b/test/dm/cmd_dm.c index 79a674e..507f260 100644 --- a/test/dm/cmd_dm.c +++ b/test/dm/cmd_dm.c @@ -77,8 +77,8 @@ static void dm_display_line(struct udevice *dev) printf(- %c %s @ %08lx, dev-flags DM_FLAG_ACTIVATED ? '*' : ' ', dev-name, (ulong)map_to_sysmem(dev)); - if (dev-req_seq != -1) - printf(, %d, dev-req_seq); + if (dev-seq != -1 || dev-req_seq != -1) + printf(, seq-%d, (req=%d), dev-seq, dev-req_seq); puts(\n); } -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 09/22] dm: core: Mark device as active before calling its probe() method
At present the device is not active when the probe() method is called. But
some probe() methods want to set up the device and this can involve
accessing it through normal methods. For example a PCI bus may wish to
set up its PCI parameters using calls to pci_hose_write_config_dword() and
similar.
At present this does not work because every such call within the probe()
method sees that the device is not active and attempts to probe it.
Already we mark the device as probed before calling the uclass post_probe()
method. This is a subtle change but I believe the new approach is better.
Since the scope of the change is only the probe() method and all its callees
it should still be within the control of the board author.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/core/device.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 92e8a57..6bd4b26 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -243,14 +243,15 @@ int device_probe_child(struct udevice *dev, void
*parent_priv)
goto fail;
}
+ dev-flags |= DM_FLAG_ACTIVATED;
if (drv-probe) {
ret = drv-probe(dev);
- if (ret)
+ if (ret) {
+ dev-flags = ~DM_FLAG_ACTIVATED;
goto fail;
+ }
}
- dev-flags |= DM_FLAG_ACTIVATED;
-
ret = uclass_post_probe_device(dev);
if (ret) {
dev-flags = ~DM_FLAG_ACTIVATED;
--
2.2.0.rc0.207.ga3a616c
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Re: [U-Boot] [PATCH] arm: socfpga: Enable DM and DM_SPI
On 5 March 2015 at 03:56, Pavel Machek pa...@denx.de wrote: On Wed 2015-03-04 23:22:25, Marek Vasut wrote: Enable DM and DM_SPI support for both Cyclone 5 and Arria 5 boards, since they use drivers which require those. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Pavel Machek pa...@denx.de -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html Acked-by: Simon Glass s...@chromium.org (Marek I guess you will pick this up, but if not let me know) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4][v3] SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.
On 02/26/2015 08:16 PM, Gaurav Rana wrote: esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana gaurav.r...@freescale.com --- Changes in v3: No change. Change in other patches of the patch set. Changes in v2: Merge patches of enablement for powerpc and enablement for arm. Applied to u-boot-mpc85xx master, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4][v3] SECURE BOOT: Add command for validation of images
On 02/26/2015 08:15 PM, Gaurav Rana wrote: 1. esbc_validate command is meant for validating header and signature of images (Boot Script and ESBC uboot client). SHA-256 and RSA operations are performed using SEC block in HW. This command works on both PBL based and Non PBL based Freescale platforms. Command usage: esbc_validate img_hdr_addr [pub_key_hash] 2. ESBC uboot client can be linux. Additionally, rootfs and device tree blob can also be signed. 3. In the event of header or signature failure in validation, ITS and ITF bits determine further course of action. 4. In case of soft failure, appropriate error is dumped on console. 5. In case of hard failure, SoC is issued RESET REQUEST after dumping error on the console. 6. KEY REVOCATION Feature: QorIQ platforms like B4/T4 have support of srk key table and key revocation in ISBC code in Silicon. The srk key table allows the user to have a key table with multiple keys and revoke any key in case of particular key gets compromised. In case the ISBC code uses the key revocation and srk key table to verify the u-boot code, the subsequent chain of trust should also use the same. 6. ISBC KEY EXTENSION Feature: This feature allows large number of keys to be used for esbc validation of images. A set of public keys is being signed and validated by ISBC which can be further used for esbc validation of images. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Gaurav Rana gaurav.r...@freescale.com --- Changes in v3: No change. Change in other patches of the patch set. Changes in v2: Copyright is changed in all the files in the patch. Applied to u-boot-mpc85xx master after fixing commit message indentation, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpc85xx/t104xrdb : remove raw timing parameter
On 02/03/2015 05:02 AM, Vijay Rai wrote: This board actually uses DIMM, so removing unnecessary raw timing parameter code. Signed-off-by: Vijay Rai vijay@freescale.com --- Applied to u-boot-mpc85xx master after fixing commit message, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 02/20] arm: socfpga: spl: Add SRAM section
On Wednesday, March 04, 2015 at 10:34:30 PM, Dinh Nguyen wrote: On 03/04/2015 01:39 PM, Marek Vasut wrote: On Wednesday, March 04, 2015 at 07:52:04 PM, Dinh Nguyen wrote: On 03/04/2015 06:39 AM, Marek Vasut wrote: On Monday, March 02, 2015 at 05:27:50 PM, dingu...@opensource.altera.com wrote: From: Dinh Nguyen dingu...@opensource.altera.com Add a section of SRAM to the SPL linker file. Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com Hi! Can we not use the generic SPL stuff ( ./arch/arm/cpu/u-boot-spl.lds ) here instead please ? I looked at this, but I didn't see way to overlay in an SRAM section. Do you have an example of how to do this? Hi! Is it really needed at all in the first place ? Why ? Isn't this need to specify the SPL to be located in the sram section? I see other platforms doing the same thing, ie. zynq, sunxi. CONFIG_SPL_TEXT_BASE is what specifies the address to which the SPL is linked. This is the address where the BootROM should place the SPL and jump to it's first instruction. I don't think you explicitly need to hack linker scripts to add this section. btw. Tom Rini has a different email address (@konsulko) now. btw2. is there any way I can help you with hacking on the SPL please ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 16/22] dm: sandbox: pci: Add a PCI emulation uclass
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/pci/Makefile | 1 +
drivers/pci/pci-emul-uclass.c | 67 ++
include/dm/uclass-id.h| 1 +
include/pci.h | 108 ++
4 files changed, 177 insertions(+)
create mode 100644 drivers/pci/pci-emul-uclass.c
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 9e2e5f9..c1c2ae3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -8,6 +8,7 @@
ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
+obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
else
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/drivers/pci/pci-emul-uclass.c b/drivers/pci/pci-emul-uclass.c
new file mode 100644
index 000..0f8e3c9
--- /dev/null
+++ b/drivers/pci/pci-emul-uclass.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Written by Simon Glass s...@chromium.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include fdtdec.h
+#include libfdt.h
+#include pci.h
+#include dm/lists.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sandbox_pci_priv {
+ int dev_count;
+};
+
+int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
+struct udevice **emulp)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pci_bus_find_devfn(bus, find_devfn, dev);
+ if (ret) {
+ debug(%s: Could not find emulator for dev %x\n, __func__,
+ find_devfn);
+ return ret;
+ }
+
+ ret = device_find_first_child(dev, emulp);
+ if (ret)
+ return ret;
+
+ return *emulp ? 0 : -ENODEV;
+}
+
+static int sandbox_pci_emul_post_probe(struct udevice *dev)
+{
+ struct sandbox_pci_priv *priv = dev-uclass-priv;
+
+ priv-dev_count++;
+ sandbox_set_enable_pci_map(true);
+
+ return 0;
+}
+
+static int sandbox_pci_emul_pre_remove(struct udevice *dev)
+{
+ struct sandbox_pci_priv *priv = dev-uclass-priv;
+
+ priv-dev_count--;
+ sandbox_set_enable_pci_map(priv-dev_count 0);
+
+ return 0;
+}
+
+UCLASS_DRIVER(pci_emul) = {
+ .id = UCLASS_PCI_EMUL,
+ .name = pci_emul,
+ .post_probe = sandbox_pci_emul_post_probe,
+ .pre_remove = sandbox_pci_emul_pre_remove,
+ .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv),
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index b984407..0b6e850 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -20,6 +20,7 @@ enum uclass_id {
UCLASS_TEST_BUS,
UCLASS_SPI_EMUL,/* sandbox SPI device emulator */
UCLASS_I2C_EMUL,/* sandbox I2C device emulator */
+ UCLASS_PCI_EMUL,/* sandbox PCI device emulator */
UCLASS_SIMPLE_BUS,
/* U-Boot uclasses start here */
diff --git a/include/pci.h b/include/pci.h
index 07345fd..07b1e9a 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -992,6 +992,114 @@ static inline int pci_read_config_byte(pci_dev_t pcidev,
int offset,
return pci_read_config8(pcidev, offset, valuep);
}
+/**
+ * struct dm_pci_emul_ops - PCI device emulator operations
+ */
+struct dm_pci_emul_ops {
+ /**
+* get_devfn(): Check which device and function this emulators
+*
+* @dev:device to check
+* @return the device and function this emulates, or -ve on error
+*/
+ int (*get_devfn)(struct udevice *dev);
+ /**
+* read_config() - Read a PCI configuration value
+*
+* @dev:Emulated device to read from
+* @offset: Byte offset within the device's configuration space
+* @valuep: Place to put the returned value
+* @size: Access size
+* @return 0 if OK, -ve on error
+*/
+ int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
+ enum pci_size_t size);
+ /**
+* write_config() - Write a PCI configuration value
+*
+* @dev:Emulated device to write to
+* @offset: Byte offset within the device's configuration space
+* @value: Value to write
+* @size: Access size
+* @return 0 if OK, -ve on error
+*/
+ int (*write_config)(struct udevice *dev, uint offset, ulong value,
+ enum pci_size_t size);
+ /**
+* read_io() - Read a PCI I/O value
+*
+* @dev:Emulated device to read from
+* @addr: I/O address to read
+* @valuep: Place to put the returned value
+
[U-Boot] [PATCH v2 01/22] sandbox: Update device tree 'reg' properties for I2C and SPI
We should have a size value for these. Add one in each case. This will
be needed for PCI.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Update root node #size=cells to 1 in this patch
arch/sandbox/dts/sandbox.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 9ce31bf..d090ba8 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -2,7 +2,7 @@
/ {
#address-cells = 1;
- #size-cells = 0;
+ #size-cells = 1;
chosen {
stdout-path = /serial;
@@ -144,7 +144,7 @@
i2c@0 {
#address-cells = 1;
#size-cells = 0;
- reg = 0;
+ reg = 0 0;
compatible = sandbox,i2c;
clock-frequency = 40;
eeprom@2c {
@@ -161,7 +161,7 @@
spi@0 {
#address-cells = 1;
#size-cells = 0;
- reg = 0;
+ reg = 0 0;
compatible = sandbox,spi;
cs-gpios = 0, gpio_a 0;
flash@0 {
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 21/22] dm: x86: pci: Convert chromebook_link to use driver model for pci
Move chromebook_link over to driver model for PCI.
This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)
This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/ivybridge/bd82x6x.c | 24 +++-
arch/x86/cpu/ivybridge/cpu.c | 16 +++---
arch/x86/cpu/ivybridge/lpc.c | 1 +
arch/x86/cpu/ivybridge/pci.c | 81 ---
arch/x86/dts/chromebook_link.dts | 3 +-
arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 -
configs/chromebook_link_defconfig | 1 +
configs/chromebox_panther_defconfig | 1 +
lib/fdtdec.c | 2 +-
9 files changed, 62 insertions(+), 68 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 56b19e3..7b74282 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include fdtdec.h
#include malloc.h
@@ -86,7 +87,7 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
bd82x6x_pci_dev_enable_resources(dev);
}
-int bd82x6x_init_pci_devices(void)
+static int bd82x6x_probe(struct udevice *dev)
{
const void *blob = gd-fdt_blob;
struct pci_controller *hose;
@@ -144,3 +145,24 @@ int bd82x6x_init(void)
return 0;
}
+
+static const struct udevice_id bd82x6x_ids[] = {
+ { .compatible = intel,bd82x6x },
+ { }
+};
+
+U_BOOT_DRIVER(bd82x6x_drv) = {
+ .name = bd82x6x,
+ .id = UCLASS_PCH,
+ .of_match = bd82x6x_ids,
+ .probe = bd82x6x_probe,
+};
+
+/*
+ * TODO(s...@chromium.org): Move this to arch/x86/lib or similar when other
+ * boards also use a PCH
+ */
+UCLASS_DRIVER(pch) = {
+ .id = UCLASS_PCH,
+ .name = pch,
+};
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index e6ef481..2639ec2 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include fdtdec.h
#include asm/cpu.h
@@ -126,19 +127,20 @@ int arch_cpu_init_dm(void)
{
const void *blob = gd-fdt_blob;
struct pci_controller *hose;
+ struct udevice *bus;
int node;
int ret;
- post_code(POST_CPU_INIT);
- timer_set_base(rdtsc());
-
- ret = x86_cpu_init_f();
+ post_code(0x70);
+ ret = uclass_get_device(UCLASS_PCI, 0, bus);
+ post_code(0x71);
if (ret)
return ret;
+ post_code(0x72);
+ hose = dev_get_uclass_priv(bus);
- ret = pci_early_init_hose(hose);
- if (ret)
- return ret;
+ /* TODO(s...@chromium.org): Get rid of gd-hose */
+ gd-hose = hose;
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
if (node 0)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 33b11a1..c20e180 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -7,6 +7,7 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include fdtdec.h
#include rtc.h
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index 7f62a86..5e90f30 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -10,63 +10,24 @@
*/
#include common.h
+#include dm.h
#include pci.h
#include asm/pci.h
+#include asm/post.h
#include asm/arch/bd82x6x.h
#include asm/arch/pch.h
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *table)
-{
- u8 secondary;
-
- hose-read_byte(hose, dev, PCI_SECONDARY_BUS, secondary);
- if (secondary != 0)
- pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_ivybridge_config_table[] = {
- /* vendor, device, class, bus, dev, func */
- { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, config_pci_bridge },
- {}
-};
-
-void board_pci_setup_hose(struct pci_controller *hose)
-{
- hose-config_table = pci_ivybridge_config_table;
- hose-first_busno = 0;
- hose-last_busno = 0;
-
- /* PCI memory space */
- pci_set_region(hose-regions + 0,
- CONFIG_PCI_MEM_BUS,
- CONFIG_PCI_MEM_PHYS,
- CONFIG_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
-
[U-Boot] [PATCH v2 19/22] dm: x86: pci: Add a PCI driver for driver model
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/pci.c | 40
arch/x86/include/asm/pci.h | 8
arch/x86/lib/Makefile | 2 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_x86.c | 24
5 files changed, 75 insertions(+)
create mode 100644 drivers/pci/pci_x86.c
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index c6c5267..e23b233 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -10,9 +10,11 @@
*/
#include common.h
+#include dm.h
#include errno.h
#include malloc.h
#include pci.h
+#include asm/io.h
#include asm/pci.h
DECLARE_GLOBAL_DATA_PTR;
@@ -111,3 +113,41 @@ void x86_pci_write_config32(pci_dev_t dev, unsigned where,
unsigned value)
{
pci_hose_write_config_dword(get_hose(), dev, where, value);
}
+
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ ulong *valuep, enum pci_size_t size)
+{
+ outl(bdf | (offset 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = inb(PCI_REG_DATA + (offset 3));
+ break;
+ case PCI_SIZE_16:
+ *valuep = inw(PCI_REG_DATA + (offset 2));
+ break;
+ case PCI_SIZE_32:
+ *valuep = inl(PCI_REG_DATA);
+ break;
+ }
+
+ return 0;
+}
+
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ulong value, enum pci_size_t size)
+{
+ outl(bdf | (offset 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+ switch (size) {
+ case PCI_SIZE_8:
+ outb(value, PCI_REG_DATA + (offset 3));
+ break;
+ case PCI_SIZE_16:
+ outw(value, PCI_REG_DATA + (offset 2));
+ break;
+ case PCI_SIZE_32:
+ outl(value, PCI_REG_DATA);
+ break;
+ }
+
+ return 0;
+}
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index b277b3d..a1969ed 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -8,6 +8,8 @@
#ifndef _PCI_I386_H_
#define _PCI_I386_H_
+#include pci.h
+
/* bus mapping constants (used for PCI core initialization) */
#define PCI_REG_ADDR 0xcf8
#define PCI_REG_DATA 0xcfc
@@ -56,6 +58,12 @@ void x86_pci_write_config8(pci_dev_t dev, unsigned where,
unsigned value);
void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ ulong *valuep, enum pci_size_t size);
+
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+ulong value, enum pci_size_t size);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_I386_H_ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index c17f7f0..67a34d8 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -17,7 +17,9 @@ obj-y += interrupts.o
obj-y += cmd_mtrr.o
obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
+ifndef CONFIG_DM_PCI
obj-$(CONFIG_PCI) += pci_type1.o
+endif
obj-y += relocate.o
obj-y += physmem.o
obj-$(CONFIG_X86_RAMTEST) += ramtest.o
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c1c2ae3..adc238f 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -9,6 +9,7 @@ ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
+obj-$(CONFIG_X86) += pci_x86.o
else
obj-$(CONFIG_PCI) += pci.o
endif
diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
new file mode 100644
index 000..901bdca
--- /dev/null
+++ b/drivers/pci/pci_x86.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include pci.h
+
+static const struct dm_pci_ops x86_pci_ops = {
+};
+
+static const struct udevice_id x86_pci_ids[] = {
+ { .compatible = x86,pci },
+ { }
+};
+
+U_BOOT_DRIVER(pci_x86) = {
+ .name = pci_x86,
+ .id = UCLASS_PCI,
+ .of_match = x86_pci_ids,
+ .ops= x86_pci_ops,
+};
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 22/22] dm: pci: Add driver model tests for PCI
Add some basic tests to check that things work as expected with sandbox.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
test/dm/Makefile | 1 +
test/dm/pci.c| 59
test/dm/test.dts | 17
3 files changed, 77 insertions(+)
create mode 100644 test/dm/pci.c
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 612aa95..8281779 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -21,4 +21,5 @@ obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_SPI) += spi.o
obj-$(CONFIG_DM_SPI_FLASH) += sf.o
obj-$(CONFIG_DM_I2C) += i2c.o
+obj-$(CONFIG_DM_PCI) += pci.o
endif
diff --git a/test/dm/pci.c b/test/dm/pci.c
new file mode 100644
index 000..6c63fa4
--- /dev/null
+++ b/test/dm/pci.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include asm/io.h
+#include dm/test.h
+#include dm/ut.h
+
+/* Test that sandbox PCI works correctly */
+static int dm_test_pci_base(struct dm_test_state *dms)
+{
+ struct udevice *bus;
+
+ ut_assertok(uclass_get_device(UCLASS_PCI, 0, bus));
+
+ return 0;
+}
+DM_TEST(dm_test_pci_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can use the swapcase device correctly */
+static int dm_test_pci_swapcase(struct dm_test_state *dms)
+{
+ pci_dev_t pci_dev = PCI_BDF(0, 0x1f, 0);
+ struct pci_controller *hose;
+ struct udevice *bus, *swap;
+ ulong io_addr, mem_addr;
+ char *ptr;
+
+ /* Check that asking for the device automatically fires up PCI */
+ ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, swap));
+
+ ut_assertok(uclass_get_device(UCLASS_PCI, 0, bus));
+ hose = dev_get_uclass_priv(bus);
+
+ /* First test I/O */
+ io_addr = pci_read_bar32(hose, pci_dev, 0);
+ outb(2, io_addr);
+ ut_asserteq(2, inb(io_addr));
+
+ /*
+* Now test memory mapping - note we must unmap and remap to cause
+* the swapcase emulation to see our data and response.
+*/
+ mem_addr = pci_read_bar32(hose, pci_dev, 1);
+ ptr = map_sysmem(mem_addr, 20);
+ strcpy(ptr, This is a TesT);
+ unmap_sysmem(ptr);
+
+ ptr = map_sysmem(mem_addr, 20);
+ ut_asserteq_str(tHIS IS A tESt, ptr);
+ unmap_sysmem(ptr);
+
+ return 0;
+}
+DM_TEST(dm_test_pci_swapcase, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/test.dts b/test/dm/test.dts
index 84024a4..96775e1 100644
--- a/test/dm/test.dts
+++ b/test/dm/test.dts
@@ -10,6 +10,7 @@
console = uart0;
i2c0 = /i2c@0;
spi0 = /spi@0;
+ pci0 = pci;
testfdt6 = /e-test;
testbus3 = /some-bus;
testfdt0 = /some-bus/c-test@0;
@@ -135,6 +136,22 @@
};
};
+ pci: pci-controller {
+ compatible = sandbox,pci;
+ device_type = pci;
+ #address-cells = 3;
+ #size-cells = 2;
+ ranges = 0x0200 0 0x1000 0x1000 0 0x2000
+ 0x0100 0 0x2000 0x2000 0 0x2000;
+ pci@1f,0 {
+ compatible = pci-generic;
+ reg = 0xf800 0 0 0 0;
+ emul@1f,0 {
+ compatible = sandbox,swap-case;
+ };
+ };
+ };
+
spi@0 {
#address-cells = 1;
#size-cells = 0;
--
2.2.0.rc0.207.ga3a616c
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 14/22] dm: sandbox: pci: Add PCI support for sandbox
Add the required header information, device tree nodes and I/O accessor
functions to support PCI on sandbox. All devices are emulated by drivers
which can be added as required for testing or development.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/sandbox/Kconfig | 7 ++
arch/sandbox/cpu/cpu.c| 37 +++-
arch/sandbox/dts/sandbox.dts | 20 +
arch/sandbox/include/asm/io.h | 16 +++-
arch/sandbox/include/asm/processor.h | 12 +++
arch/sandbox/include/asm/test.h | 7 +-
arch/sandbox/include/asm/u-boot-sandbox.h | 48 +++
arch/sandbox/lib/Makefile | 2 +-
arch/sandbox/lib/pci_io.c | 138 ++
9 files changed, 280 insertions(+), 7 deletions(-)
create mode 100644 arch/sandbox/include/asm/processor.h
create mode 100644 arch/sandbox/lib/pci_io.c
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 2098b9c..477a20a 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -34,4 +34,11 @@ config DM_I2C
config DM_TEST
default y
+config PCI
+ bool PCI support
+ help
+ Enable support for PCI (Peripheral Interconnect Bus), a type of bus
+ used on some devices to allow the CPU to communicate with its
+ peripherals.
+
endmenu
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 1aa397c..1e67a31 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -2,7 +2,7 @@
* Copyright (c) 2011 The Chromium OS Authors.
* SPDX-License-Identifier:GPL-2.0+
*/
-
+#define DEBUG
#include common.h
#include dm/root.h
#include os.h
@@ -10,6 +10,13 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Enable access to PCI memory with map_sysmem() */
+static bool enable_pci_map;
+
+/* Last device that was mapped into memory, and length of mapping */
+static struct udevice *map_dev;
+unsigned long map_len;
+
void reset_cpu(ulong ignored)
{
if (state_uninit())
@@ -59,9 +66,37 @@ int cleanup_before_linux(void)
void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
+#ifdef CONFIG_PCI
+ unsigned long plen = len;
+ void *ptr;
+
+ map_dev = NULL;
+ if (enable_pci_map !pci_map_physmem(paddr, len, map_dev, ptr)) {
+ if (plen != len) {
+ printf(%s: Warning: partial map at %x, wanted %lx, got
%lx\n,
+ __func__, paddr, len, plen);
+ }
+ map_len = len;
+ return ptr;
+ }
+#endif
+
return (void *)(gd-arch.ram_buf + paddr);
}
+void unmap_physmem(const void *vaddr, unsigned long flags)
+{
+ if (map_dev) {
+ pci_unmap_physmem(vaddr, map_len, map_dev);
+ map_dev = NULL;
+ }
+}
+
+void sandbox_set_enable_pci_map(int enable)
+{
+ enable_pci_map = enable;
+}
+
phys_addr_t map_to_sysmem(const void *ptr)
{
return (u8 *)ptr - gd-arch.ram_buf;
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index d090ba8..42a1f21 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -4,6 +4,10 @@
#address-cells = 1;
#size-cells = 1;
+ aliases {
+ pci0 = pci;
+ };
+
chosen {
stdout-path = /serial;
};
@@ -181,4 +185,20 @@
};
};
+ pci: pci-controller {
+ compatible = sandbox,pci;
+ device_type = pci;
+ #address-cells = 3;
+ #size-cells = 2;
+ ranges = 0x0200 0 0x1000 0x1000 0 0x2000
+ 0x0100 0 0x2000 0x2000 0 0x2000;
+ pci@1f,0 {
+ compatible = pci-generic;
+ reg = 0xf800 0 0 0 0;
+ emul@1f,0 {
+ compatible = sandbox,swap-case;
+ };
+ };
+ };
+
};
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 895fcb8..5b87fde 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -22,10 +22,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len,
unsigned long flags);
/*
* Take down a mapping set up by map_physmem().
*/
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
+void unmap_physmem(const void *vaddr, unsigned long flags);
/* For sandbox, we want addresses to point into our RAM buffer */
static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
@@ -33,8 +30,10 @@ static inline void *map_sysmem(phys_addr_t paddr, unsigned
long len)
return map_physmem(paddr, len, MAP_WRBACK);
}
+/* Remove a previous mapping */
static inline void unmap_sysmem(const void *vaddr)
{
+ unmap_physmem(vaddr, MAP_WRBACK);
}
/* Map from a
[U-Boot] [PATCH v2 17/22] dm: sandbox: Add a emulated PCI device as an example
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
drivers/misc/Makefile| 1 +
drivers/misc/swap_case.c | 285 +++
2 files changed, 286 insertions(+)
create mode 100644 drivers/misc/swap_case.c
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index a34972d..7783b72 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -26,5 +26,6 @@ obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
endif
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_STATUS_LED) += status_led.o
+obj-$(CONFIG_SANDBOX) += swap_case.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c
new file mode 100644
index 000..f6028ba
--- /dev/null
+++ b/drivers/misc/swap_case.c
@@ -0,0 +1,285 @@
+/*
+ * PCI emulation device which swaps the case of text
+ *
+ * Copyright (c) 2014 Google, Inc
+ * Written by Simon Glass s...@chromium.org
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include pci.h
+#include asm/test.h
+#include linux/ctype.h
+
+/**
+ * struct swap_case_platdata - platform data for this device
+ *
+ * @command: Current PCI command value
+ * @bar: Current base address values
+ */
+struct swap_case_platdata {
+ u16 command;
+ u32 bar[2];
+};
+
+#define offset_to_barnum(offset) \
+ (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
+
+enum {
+ MEM_TEXT_SIZE = 0x100,
+};
+
+enum swap_case_op {
+ OP_TO_LOWER,
+ OP_TO_UPPER,
+ OP_SWAP,
+};
+
+static struct pci_bar {
+ int type;
+ u32 size;
+} barinfo[] = {
+ { PCI_BASE_ADDRESS_SPACE_IO, 1 },
+ { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+ { 0, 0 },
+};
+
+struct swap_case_priv {
+ enum swap_case_op op;
+ char mem_text[MEM_TEXT_SIZE];
+};
+
+static int sandbox_swap_case_get_devfn(struct udevice *dev)
+{
+ struct pci_child_platdata *plat = dev_get_parent_platdata(dev);
+
+ return plat-devfn;
+}
+
+static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
+ulong *valuep, enum pci_size_t size)
+{
+ struct swap_case_platdata *plat = dev_get_platdata(emul);
+
+ switch (offset) {
+ case PCI_COMMAND:
+ *valuep = plat-command;
+ break;
+ case PCI_HEADER_TYPE:
+ *valuep = 0;
+ break;
+ case PCI_VENDOR_ID:
+ *valuep = SANDBOX_PCI_VENDOR_ID;
+ break;
+ case PCI_DEVICE_ID:
+ *valuep = SANDBOX_PCI_DEVICE_ID;
+ break;
+ case PCI_CLASS_DEVICE:
+ if (size == PCI_SIZE_8) {
+ *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
+ } else {
+ *valuep = (SANDBOX_PCI_CLASS_CODE 8) |
+ SANDBOX_PCI_CLASS_SUB_CODE;
+ }
+ break;
+ case PCI_CLASS_CODE:
+ *valuep = SANDBOX_PCI_CLASS_CODE;
+ break;
+ case PCI_BASE_ADDRESS_0:
+ case PCI_BASE_ADDRESS_1:
+ case PCI_BASE_ADDRESS_2:
+ case PCI_BASE_ADDRESS_3:
+ case PCI_BASE_ADDRESS_4:
+ case PCI_BASE_ADDRESS_5: {
+ int barnum;
+ u32 *bar, result;
+
+ barnum = offset_to_barnum(offset);
+ bar = plat-bar[barnum];
+
+ result = *bar;
+ if (*bar == 0x) {
+ if (barinfo[barnum].type) {
+ result = (~(barinfo[barnum].size - 1)
+ PCI_BASE_ADDRESS_IO_MASK) |
+ PCI_BASE_ADDRESS_SPACE_IO;
+ } else {
+ result = (~(barinfo[barnum].size - 1)
+ PCI_BASE_ADDRESS_MEM_MASK) |
+ PCI_BASE_ADDRESS_MEM_TYPE_32;
+ }
+ }
+ debug(r bar %d=%x\n, barnum, result);
+ *valuep = result;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
+ ulong value, enum pci_size_t size)
+{
+ struct swap_case_platdata *plat = dev_get_platdata(emul);
+
+ switch (offset) {
+ case PCI_COMMAND:
+ plat-command = value;
+ break;
+ case PCI_BASE_ADDRESS_0:
+ case PCI_BASE_ADDRESS_1: {
+ int barnum;
+ u32 *bar;
+
+ barnum =
[U-Boot] [PATCH v2 20/22] dm: x86: pci: Convert coreboot to use driver model for pci
Move coreboot-x86 over to driver model for PCI.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/coreboot/pci.c | 63 ++---
arch/x86/dts/chromebook_link.dts| 7 +
board/google/chromebook_link/link.c | 9 ++
configs/coreboot-x86_defconfig | 1 +
include/dm/uclass-id.h | 1 +
5 files changed, 34 insertions(+), 47 deletions(-)
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index c9983f1..fa415dd 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -10,58 +10,27 @@
*/
#include common.h
+#include dm.h
+#include errno.h
#include pci.h
+#include asm/io.h
#include asm/pci.h
DECLARE_GLOBAL_DATA_PTR;
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *table)
-{
- u8 secondary;
- hose-read_byte(hose, dev, PCI_SECONDARY_BUS, secondary);
- hose-last_busno = max(hose-last_busno, (int)secondary);
- pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_coreboot_config_table[] = {
- /* vendor, device, class, bus, dev, func */
- { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, config_pci_bridge },
- {}
+static const struct dm_pci_ops pci_x86_ops = {
+ .read_config= pci_x86_read_config,
+ .write_config = pci_x86_write_config,
};
-void board_pci_setup_hose(struct pci_controller *hose)
-{
- hose-config_table = pci_coreboot_config_table;
- hose-first_busno = 0;
- hose-last_busno = 0;
-
- /* PCI memory space */
- pci_set_region(hose-regions + 0,
- CONFIG_PCI_MEM_BUS,
- CONFIG_PCI_MEM_PHYS,
- CONFIG_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI IO space */
- pci_set_region(hose-regions + 1,
- CONFIG_PCI_IO_BUS,
- CONFIG_PCI_IO_PHYS,
- CONFIG_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- pci_set_region(hose-regions + 2,
- CONFIG_PCI_PREF_BUS,
- CONFIG_PCI_PREF_PHYS,
- CONFIG_PCI_PREF_SIZE,
- PCI_REGION_PREFETCH);
-
- pci_set_region(hose-regions + 3,
- 0,
- 0,
- gd-ram_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+static const struct udevice_id pci_x86_ids[] = {
+ { .compatible = pci-x86 },
+ { }
+};
- hose-region_count = 4;
-}
+U_BOOT_DRIVER(pci_x86_drv) = {
+ .name = pci_x86,
+ .id = UCLASS_PCI,
+ .of_match = pci_x86_ids,
+ .ops= pci_x86_ops,
+};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 45ada61..cdbdb68 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -172,6 +172,13 @@
};
pci {
+ compatible = intel,pci-ivybridge, pci-x86;
+ #address-cells = 3;
+ #size-cells = 2;
+ u-boot,dm-pre-reloc;
+ ranges = 0x0200 0x0 0xe000 0xe000 0 0x1000
+ 0x4200 0x0 0xd000 0xd000 0 0x1000
+ 0x0100 0x0 0x1000 0x1000 0 0xefff;
sata {
compatible = intel,pantherpoint-ahci;
intel,sata-mode = ahci;
diff --git a/board/google/chromebook_link/link.c
b/board/google/chromebook_link/link.c
index 9978e92..8c04cb8 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -6,6 +6,7 @@
#include common.h
#include cros_ec.h
+#include dm.h
#include asm/gpio.h
#include asm/io.h
#include asm/pci.h
@@ -13,6 +14,14 @@
int arch_early_init_r(void)
{
+ struct udevice *dev;
+ int ret;
+
+ /* Make sure the platform controller hub is up and running */
+ ret = uclass_get_device(UCLASS_PCH, 0, dev);
+ if (ret)
+ return ret;
+
if (cros_ec_board_init())
return -1;
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 3cc034a..0249172 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -2,3 +2,4 @@ CONFIG_SYS_EXTRA_OPTIONS=SYS_TEXT_BASE=0x0111
CONFIG_X86=y
CONFIG_TARGET_COREBOOT=y
CONFIG_OF_CONTROL=y
+CONFIG_DM_PCI=y
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0b6e850..047ac15 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -37,6 +37,7 @@ enum uclass_id {
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_PCI, /* PCI bus */
UCLASS_PCI_GENERIC, /* Generic PCI bus device
Re: [U-Boot] [PATCH v1]dm : spi: Convert Freescale DSPI to driver model
+Tom for the coding style question
Hi,
On 4 March 2015 at 04:22, haikun.w...@freescale.com
haikun.w...@freescale.com wrote:
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Tuesday, March 03, 2015 2:56 AM
To: Wang Haikun-B53464
Cc: u-boot@lists.denx.de; Jagan Teki
Subject: Re: [U-Boot] [PATCH v1]dm : spi: Convert Freescale DSPI to
driver model
Hi,
On 28 February 2015 at 03:54, haikun.w...@freescale.com
haikun.w...@freescale.com wrote:
Move the Freescale DSPI driver over to driver model.
Signed-off-by: Haikun Wang b53...@freescale.com
---
This patch adds two new files drivers/spi/fsl_dspi.c and
include/fsl_dspi.h.
They will replace files drivers/spi/cf_spi.c and
arch/m68k/include/asm/coldfire/dspi.h.
I need submit patch to remove them later.
Board dts files are also needed to make this change work.
Apart from one thing (the chip selects) this all looks correct to me.
Some style comments below. Also the patch seems to be in Courier font!
I'm interested in your thoughts on what is missing from the SPI uclass
too.
Changes in v1: None
drivers/spi/Makefile | 1 +
drivers/spi/fsl_dspi.c | 461
+
include/fsl_dspi.h | 156 +
3 files changed, 618 insertions(+)
create mode 100644 drivers/spi/fsl_dspi.c create mode 100644
include/fsl_dspi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index
edbd520..9c2b8de 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
+obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c new file
mode 100644 index 000..69c037b
--- /dev/null
+++ b/drivers/spi/fsl_dspi.c
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ * Chao Fu (b44...@freescale.com)
+ * Haikun Wang (b53...@freescale.com)
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include dm.h
+#include errno.h
+#include common.h
+#include spi.h
+#include malloc.h
+#include asm/io.h
+#include fdtdec.h
+#include asm/arch/clock.h
+#include fsl_dspi.h
+
+
Remove extract blank line
+DECLARE_GLOBAL_DATA_PTR;
+
+/* fsl_dspi_platdata flag */
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG(1 0)
+
+/* idle data value */
+#define DSPI_IDLE_VAL (0x0)
Please no brackets around simple constants (I understand if they are -ve,
but this serves no purpose).
[] fine.
+
+/* max chipselect signals number */
+#define FSL_DSPI_MAX_CHIPSELECT(6)
+
+/* CTAR register pre-configure value */
+#define DSPI_CTAR_DEFAULT_VALUE(DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(0))
+
+/* CTAR register pre-configure mask */
+#define DSPI_CTAR_SET_MODE_MASK(DSPI_CTAR_TRSZ(15) | \
+ DSPI_CTAR_PCSSCK(3) | \
+ DSPI_CTAR_PASC(3) | \
+ DSPI_CTAR_PDT(3) | \
+ DSPI_CTAR_CSSCK(15) | \
+ DSPI_CTAR_ASC(15) | \
+ DSPI_CTAR_DT(15))
+
Please comment these things below:
[] fine.
/**
* struct fsl_dspi_platdata - platform data for ...
*
* @flag:some sort of flag and you can find the enum here...
...
+struct fsl_dspi_platdata {
+ uint flag;
+ uint baudrate;
+ uint num_chipselect;
+ uint regs;
+};
+
+struct fsl_dspi_priv {
+ uint mode;
+ uint mcr_val;
+ uint bus_clk;
+ uint baudrate;
+ uint charbit;
+ uint num_chipselect;
+ uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
+ uint regs;
+ struct dm_spi_slave_platdata *cur_slave_plat;
What is that for?
+};
+
+static uint dspi_read32(struct udevice *bus, uint offset) {
+ struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
blank line between declarations and code (throughout)
+ return plat-flag DSPI_FLAG_REGMAP_ENDIAN_BIG ?
+ in_be32(plat-regs + offset) : in_le32(plat-regs +
+ offset);
I think it is better to put regs in your private data rather than
Re: [U-Boot] [PATCH] x86: Add queensbay fsp patch information in README.x86
On 4 March 2015 at 20:21, Bin Meng bmeng...@gmail.com wrote: The FSP release version 001 for Intel Queensbay has a bug which could cause random endless loop during the FspInit call. This bug was published by Intel although Intel did not describe any details. Describe this information in the x86 doc so that U-Boot Queensbay support is invulnerable. Signed-off-by: Bin Meng bmeng...@gmail.com --- doc/README.x86 | 7 +++ 1 file changed, 7 insertions(+) diff --git a/doc/README.x86 b/doc/README.x86 index fb87682..0355d1c 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -105,6 +105,13 @@ in this FSP package too. Rename the first one to fsp.bin and second one to cmc.bin and put them in the board directory. +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig -- 1.8.2.1 Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fdtdec: Improve fdtdec_get_pci_bdf() documentation
On 4 March 2015 at 00:08, Bin Meng bmeng...@gmail.com wrote: Add the description that how the compatible property is involved in the fdtdec_get_pci_bdf() documentation. Signed-off-by: Bin Meng bmeng...@gmail.com --- include/fdtdec.h | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 1bc70db..eef78a7 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -346,7 +346,10 @@ int fdtdec_get_pci_vendev(const void *blob, int node, /** * Look at the pci address of a device node that represents a PCI device - * and parse the bus, device and function number from it. + * and parse the bus, device and function number from it. For some cases + * like the bus number encoded in reg property is not correct after pci + * enumeration, this function looks through the node's compatible strings + * to get these numbers extracted instead. * * @param blob FDT blob * @param node node to examine -- 1.8.2.1 Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] spi: Add Designware SPI controller Kconfig entry
Hi, On 4 March 2015 at 15:22, Marek Vasut ma...@denx.de wrote: Add DWC SPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com --- drivers/spi/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7ae2727..c0b2570 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -10,3 +10,9 @@ config DM_SPI as 'parent data' to every slave on each bus. Slaves typically use driver-private data instead of extending the spi_slave structure. + +config DESIGNWARE_SPI + bool Designware SPI driver + depends on DM_SPI + help + Enable the Designware SPI driver. At least for driver model I'd like to have a nice long help message. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
On 01/18/2015 11:16 PM, Shaveta Leekha wrote: The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420 It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4860QDS: U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45) CPU0: B4860E, Version: 2.2, (0x86880022) Core: e6500, Version: 2.0, (0x80400120) Clock Configuration: CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, CCB:666.667 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz CPRI:600 MHz MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz FMAN1: 666.667 MHz QMAN: 333.333 MHz Top level changes include: (1) Top level CONFIG to identify HETEROGENUOUS clusters (2) CONFIGS for SC3900/DSP components (3) Global structures like cpu_type and MPC85xx_SYS_INFO updated for dsp cores and other components (3) APIs to get DSP num cores and their Mask like: cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC (5) Code to fetch and print SC cores and other heterogenous device's frequencies (6) README added for the same Signed-off-by: Shaveta Leekha shav...@freescale.com --- chnages in v2: Incorporated review comments All DSP aware code is enclosed with #ifdef to not increase the uboot code size for other platforms Tested it on B4860QDS and on T4240QDS Applied to u-boot-mpc85xx master, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4][v3] fsl_sec_mon: Add driver for Security Monitor block of Freescale
On 02/26/2015 08:14 PM, Gaurav Rana wrote: The Security Monitor is the SOC’s central reporting point for security-relevant events such as the success or failure of boot software validation and the detection of potential security compromises. The API's for transition of Security states have been added which will be used in case of SECURE BOOT. Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com Signed-off-by: Gaurav Rana gaurav.r...@freescale.com --- Changes in v3: Modify copyright in include/fsl_sec_mon.h and drivers/misc/fsl_sec_mon.c. Changes in v2: Commit message is changed. Applied to u-boot-mpc85xx master, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-mpc85xx master
Tom, The following changes since commit 8176a874233eb5180701e2811b38c199369975b2: Prepare v2015.04-rc3 (2015-03-03 18:08:39 -0500) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to e04916a721a2069fc770412c57974d02e153ad18: SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. (2015-03-05 12:04:59 -0800) Shaveta Leekha (1): powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs Ying Zhang (1): powerpc: 85xx: Modify CONFIG_USB_MAX_CONTROLLER_COUNT for P1022DS gaurav rana (5): rsa : Compile Modular Exponentiation files based on CONFIG_RSA_SOFTWARE_EXP fsl_sfp : Move ccsr_sfp_regs definition to common include fsl_sec_mon: Add driver for Security Monitor block of Freescale SECURE BOOT: Add command for validation of images SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. vijay rai (1): mpc85xx/t104xrdb : remove raw timing parameter arch/arm/include/asm/arch-ls102xa/config.h | 20 + arch/powerpc/cpu/mpc85xx/cpu.c | 28 + arch/powerpc/cpu/mpc85xx/speed.c | 140 + arch/powerpc/cpu/mpc8xxx/cpu.c | 91 ++- arch/powerpc/include/asm/config_mpc85xx.h | 20 +- arch/powerpc/include/asm/fsl_secure_boot.h | 35 ++ arch/powerpc/include/asm/immap_85xx.h | 22 +- arch/powerpc/include/asm/processor.h |5 + board/freescale/common/Makefile|6 + board/freescale/common/cmd_esbc_validate.c | 34 ++ board/freescale/common/fsl_validate.c | 840 board/freescale/t104xrdb/ddr.c | 15 - board/freescale/t104xrdb/ddr.h | 29 - doc/README.Heterogeneous-SoCs | 105 doc/README.esbc_validate | 41 ++ drivers/crypto/rsa_mod_exp/Makefile|3 +- drivers/misc/Kconfig |8 + drivers/misc/Makefile |1 + drivers/misc/fsl_sec_mon.c | 146 + include/common.h |2 + include/configs/T104xRDB.h |1 - include/e500.h | 11 + include/fsl_sec_mon.h | 58 ++ include/fsl_secboot_err.h | 128 + include/fsl_sfp.h | 85 +++ include/fsl_validate.h | 199 +++ lib/rsa/Makefile |3 +- 27 files changed, 2008 insertions(+), 68 deletions(-) create mode 100644 board/freescale/common/cmd_esbc_validate.c create mode 100644 board/freescale/common/fsl_validate.c create mode 100644 doc/README.Heterogeneous-SoCs create mode 100644 doc/README.esbc_validate create mode 100644 drivers/misc/fsl_sec_mon.c create mode 100644 include/fsl_sec_mon.h create mode 100644 include/fsl_secboot_err.h create mode 100644 include/fsl_sfp.h create mode 100644 include/fsl_validate.h Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc: 85xx: Modify CONFIG_USB_MAX_CONTROLLER_COUNT for P1022DS
On 01/29/2015 10:52 PM, ying.zh...@freescale.com wrote: From: Ying Zhang b40...@freescale.com Modify CONFIG_USB_MAX_CONTROLLER_COUNT value to 1 on P1022DS. As ETSEC2 and USB2 are muxed; thus if ETSEC2 is enabled, the system bus hangs on USB2 if ETSEC2 is enabled but usb start command is issued. Hence making default controller count to 1 to avoid system hang. Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com Reviewed-by: Yusong Sun york...@freescale.com --- Applied to u-boot-mpc85xx master, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH][v2] rsa : Compile Modular Exponentiation files based on CONFIG_RSA_SOFTWARE_EXP
On 02/26/2015 07:40 PM, Gaurav Rana wrote: Remove dependency of rsa_mod_exp from CONFIG_FIT_SIGNATURE. As rsa modular exponentiation is an independent module and can be invoked independently. Signed-off-by: Gaurav Rana gaurav.r...@freescale.com Reviewed-by: Simon Glass s...@chromium.org CC: Simon Glass s...@chromium.org --- Changes in v2: add elaborated commit message. Applied to u-boot-mpc85xx master, awaiting for upstream. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic
On Thu, Mar 05, 2015 at 11:49:05AM -0600, Nishanth Menon wrote:
On 03/05/2015 08:00 AM, Matt Porter wrote:
On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.
While at this, switch over to smc #0 instead of handcoded assembly.
To ensure gcc compatibility, steal the strategy used by Linux kernel
for sec extension builds (NOTE: we no longer use '-march=armv5' as the
legacy comment claims).
Hi Nishanth,
I applied this series with fuzz and fixed a minor conflict on master. I
ran into a build issue for omap3 beagle with the sec extension scheme on
the gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1) toolchain:
arm-linux-gnueabi-gcc
-Wp,-MD,arch/arm/cpu/armv7/omap3/.lowlevel_init.o.d -nostdinc -isystem
/usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude -I../include
-I../arch/arm/include -include ../include/linux/kconfig.h -D__KERNEL__
-D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g
-D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-mword-relocations -march=armv7-a -mno-unaligned-access
-ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float
-pipe -c -o arch/arm/cpu/armv7/omap3/lowlevel_init.o
../arch/arm/cpu/armv7/omap3/lowlevel_init.S
../arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages:
../arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected
processor does not support ARM mode `smc #0'
I've worked around this for the moment by placing an explicit
.arch_extension sec in lowlevel_init.S but hopefully you have some
thoughts on why those flags don't seem to be picked up. I'll continue
to take a look at it in the meantime.
Uggh.. this is weird. I had considered .arch_extension sec in
lowlevel_init.S
Yeah, no worries, I'm not suggesting that. Just a temporary workaround.
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_lowlevel_init.o :=-Wa,-march=armv7-a$(plus_sec)
seems to be what we have in kernel and seems to do the job for me on
right
$ arm-linux-gnueabi-gcc --version
arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3
$ git clean -fdx; make omap3_beagle_defconfig;
make V=1 arch/arm/cpu/armv7/omap-common/lowlevel_init.o
with gcc 4.6:
arm-linux-gnueabi-gcc
-Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc
-isystem /usr/lib/gcc/arm-linux-gnueabi/4.6/include -Iinclude
-I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__
-D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g
-D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-mword-relocations -march=armv7-a -mno-unaligned-access
-ffunction-sections -fdata-sections -fno-common -ffixed-r9
-msoft-float -pipe -Wa,-march=armv7-a+sec -c -o
arch/arm/cpu/armv7/omap-common/lowlevel_init.o
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
I also succeed here..and on a gcc 4.8.2 toolchain
with gcc 4.7:
arm-linux-gnueabi-gcc
-Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc
-isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude
-I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__
-D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g
-D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux
-mword-relocations -march=armv7-a -mno-unaligned-access
-ffunction-sections -fdata-sections -fno-common -ffixed-r9
-msoft-float -pipe -Wa,-march=armv7-a -c -o
arch/arm/cpu/armv7/omap-common/lowlevel_init.o
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages:
arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected
processor does not support ARM mode `smc #0'
make[1]: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 1
make: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 2
I thought I stole the exact code from kernel, but as you can probably
see -march=armv7-a+sec was generated for gcc 4.6 but -march=armv7-a
without +sec for gcc 4.7!
Yeah, so I played a bit with the low-level checks and noted the
following results.
gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1):
$ printf %b\n .arch_extension sec | arm-linux-gnueabi-gcc -c -x
assembler -; echo $?
{standard input}: Assembler messages:
{standard input}:1: Error: architectural extension `sec' is not allowed
for the current base architecture
1
gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4)
$ printf %b\n
[U-Boot] [PATCH v2 05/22] x86: Split up arch_cpu_init()
At present we do more in this function than we should. Split out the
post-driver-model part into a separate function.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2:
- Use the new arch_cpu_init_dm() function instead of something x86-specific
arch/x86/cpu/ivybridge/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 5fd3753..e6ef481 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -116,6 +116,14 @@ static void set_spi_speed(void)
int arch_cpu_init(void)
{
+ post_code(POST_CPU_INIT);
+ timer_set_base(rdtsc());
+
+ return x86_cpu_init_f();
+}
+
+int arch_cpu_init_dm(void)
+{
const void *blob = gd-fdt_blob;
struct pci_controller *hose;
int node;
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 18/22] dm: sandbox: pci: Enable PCI for sandbox
Enable PCI options so that sandbox can be used for testing this bus with driver model. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v2: None configs/sandbox_defconfig | 3 +++ include/configs/sandbox.h | 4 2 files changed, 7 insertions(+) diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 70f5b86..e23b959 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -12,3 +12,6 @@ CONFIG_DM_CROS_EC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_KEYB=y CONFIG_CMD_CROS_EC=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_SANDBOX=y diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index febbfb6..c12c538 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -34,6 +34,10 @@ #define CONFIG_CMD_FDT #define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_CMD_IO + #define CONFIG_FS_FAT #define CONFIG_FAT_WRITE #define CONFIG_FS_EXT4 -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/22] Correct map_sysmem() logic in do_mem_mw()
This function does not unmap what it maps. Correct it.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/cmd_mem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bcb3ee3..855aa57 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -165,7 +165,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#endif
ulong addr, count;
int size;
- void *buf;
+ void *buf, *start;
ulong bytes;
if ((argc 3) || (argc 4))
@@ -197,7 +197,8 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
}
bytes = size * count;
- buf = map_sysmem(addr, bytes);
+ start = map_sysmem(addr, bytes);
+ buf = start;
while (count-- 0) {
if (size == 4)
*((u32 *)buf) = (u32)writeval;
@@ -211,7 +212,7 @@ static int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
*((u8 *)buf) = (u8)writeval;
buf += size;
}
- unmap_sysmem(buf);
+ unmap_sysmem(start);
return 0;
}
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 13/22] dm: pci: Add a uclass for PCI
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.
TODO: Add more header file comments to the new parts of pci.h
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
common/board_r.c | 2 +
common/cmd_pci.c | 14 +-
doc/driver-model/pci-info.txt | 70 +
drivers/pci/Kconfig | 12 +
drivers/pci/Makefile | 8 +-
drivers/pci/pci-uclass.c | 639 ++
drivers/pci/pci_auto.c| 16 +-
drivers/pci/pci_compat.c | 43 +++
include/dm/uclass-id.h| 2 +
include/pci.h | 289 ++-
10 files changed, 1081 insertions(+), 14 deletions(-)
create mode 100644 doc/driver-model/pci-info.txt
create mode 100644 drivers/pci/pci-uclass.c
create mode 100644 drivers/pci/pci_compat.c
diff --git a/common/board_r.c b/common/board_r.c
index 4fcd4f6..82fbc1d 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -227,7 +227,9 @@ static int initr_unlock_ram_in_cache(void)
#ifdef CONFIG_PCI
static int initr_pci(void)
{
+#ifndef CONFIG_DM_PCI
pci_init();
+#endif
return 0;
}
diff --git a/common/cmd_pci.c b/common/cmd_pci.c
index e3a77e3..dcecef8 100644
--- a/common/cmd_pci.c
+++ b/common/cmd_pci.c
@@ -48,6 +48,7 @@ void pciinfo(int BusNum, int ShortPCIListing)
unsigned char HeaderType;
unsigned short VendorID;
pci_dev_t dev;
+ int ret;
if (!hose)
return;
@@ -74,7 +75,10 @@ void pciinfo(int BusNum, int ShortPCIListing)
if (pci_skip_dev(hose, dev))
continue;
- pci_read_config_word(dev, PCI_VENDOR_ID, VendorID);
+ ret = pci_read_config_word(dev, PCI_VENDOR_ID,
+ VendorID);
+ if (ret)
+ goto error;
if ((VendorID == 0x) || (VendorID == 0x))
continue;
@@ -91,8 +95,12 @@ void pciinfo(int BusNum, int ShortPCIListing)
BusNum, Device, Function);
pci_header_show(dev);
}
- }
-}
+ }
+ }
+
+ return;
+error:
+ printf(Cannot read bus configuration: %d\n, ret);
}
diff --git a/doc/driver-model/pci-info.txt b/doc/driver-model/pci-info.txt
new file mode 100644
index 000..63efcb7
--- /dev/null
+++ b/doc/driver-model/pci-info.txt
@@ -0,0 +1,70 @@
+PCI with Driver Model
+=
+
+How busses are scanned
+--
+
+Any config read will end up at pci_read_config(). This uses
+uclass_get_device_by_seq() to get the PCI bus for a particular bus number.
+Bus number 0 will need to be requested first, and the alias in the device
+tree file will point to the correct device:
+
+
+ aliases {
+ pci0 = pci;
+ };
+
+ pci: pci-controller {
+ compatible = sandbox,pci;
+ ...
+ };
+
+
+If there is no alias the devices will be numbered sequentially in the device
+tree.
+
+The call to uclass_get_device by seq() will cause the PCI bus to be probed.
+This does a scan of the bus to locate available devices. These devices are
+bound to their appropriate driver if available. If there is no driver, then
+they are bound to a generic PCI driver which does nothing.
+
+After probing a bus, the available devices will appear in the device tree
+under that bus.
+
+Note that this is all done on a lazy basis, as needed, so until something is
+touched on PCI it will not be probed.
+
+PCI devices can appear in the device tree. If they do this serves to specify
+the driver to use for the device. In this case they will be bound at
+start-up.
+
+
+Sandbox
+---
+
+With sandbox we need a device emulator for each device on the bus since there
+is no real PCI bus. This works by looking in the device tree node for a
+driver. For example:
+
+
+ pci@1f,0 {
+ compatible = pci-generic;
+ reg = 0xf800 0 0 0 0;
+ emul@1f,0 {
+ compatible = sandbox,swap-case;
+ };
+ };
+
+This means that there is a 'sandbox,swap-case' driver at that bus position.
+Note that the first cell in the 'reg' value is the bus/device/function. See
+PCI_BDF() for the encoding (it is also specified in the IEEE Std 1275-1994
+PCI bus binding document, v2.1)
+
+When this bus is scanned we will end up with something like this:
+
+`- * pci-controller @ 05c660c8, 0
+ `- pci@1f,0 @ 05c661c8, 63488
+ `- emul@1f,0 @ 05c662c8
+
+When accesses go to the pci@1f,0 device they are forwarded to its child, the
[U-Boot] [PATCH v2 0/22] Add driver model support for PCI
This series is a collection of changes in core DM, sandbox, x86 and PCI code to implement a PCI uclass and associated operations. Some basic tests are provided as well. As is becoming common with DM conversions, the existing structure (here struct pci_controller) becomes per-bus uclass data. This allows the concept of a 'hose' (generally a PCI host controller and a bus) to continue to exist in the interim, even if it should not be needed in the end. This makes it much easier to convert over existing code. PCI buses are not scanned in the bind() method but only later when probe() is called. This will be automatic if you access a bus, but it does mean that if PCI is not used it will not be touched, in keeping with U-Boot's lazy- init philosophy. The existing 'pciauto' bus configuration code is still used, although it now uses DM underneath. It works exclusively by reading and writing PCI config and does not refer to DM data structures. The one change is to drop use of the hose-current_busno field which is no longer required. The fact that file works largely as before is an indication that a good level of compatibility is achieved between DM and legacy PCI. In order to support testing of PCI I/O and memory space, support has been added to sandbox to allow mapping of these. This allows commands like 'md' and 'iod' to display data from mapped PCI devices. Similarly, it is possible to make changes to this space. This support relies on the existing map_sysmem() and unmap_sysmem() calls which are now fairly widespread in U-Boot. Apart from the driver model tests (run with ./test/dm/test-dm.sh) you can try out these commands which use the new 'swap_case' test device: ../u-boot -d b/sandbox/u-boot.dtb = iow.b 2000 2 = iod.b 2000 : 02 = mw.l 1000 64436241 = md.l 1000 1 1000: 44634261 aBcD = This shows an I/O access to 2000, setting the value 2 which means to swap the case. Then 'AbCd' is written to the memory space at 1000 and 'aBcD' is read back. The 'pci' command can be used as before. Most existing PCI functions (in pci.h) still work, but route through driver model. The file drivers/pci/pci.c is replaced when driver model is enabled so not everything is present. A new pci_common.c file holds functions common to driver model and the old system, and pci_compat.c contains functions I would like to eventually deprecate. Two x86 boards (coreboot and chromebook_link) are converted over to use driver model for PCI. Core driver model changes include: - Addition of a new pre_probe() method for the uclass to set up devices just before the device's probe() method is called - A change in the ordering of when a device is marked as probed - A dev_get_uclass_priv() accessor - A tweak to the 'dm uclass' command to improve sequence number display Notably missing from this series are functions to access PCI devices using a 'struct udevice *'. Where there is no device tree entry for a bus device, a generic PCI device is created in driver model to mirror the device, as with I2C and SPI. Future work could add more real devices to x86 and create a demand for these sorts of functions. Also we might store things like the PCI base address registers (BARs) in data structures if there is a need. These things are probably best developed as a need arises to avoid creating infrastructure and overhead that may not be used. This series is available at u-boot-dm.git branch pci-working. Changes in v2: - Update root node #size=cells to 1 in this patch - Add a new patch with a CPU init function which can use driver model - Use the new arch_cpu_init_dm() function instead of something x86-specific - Add -ve sign before ENXIO Simon Glass (22): sandbox: Update device tree 'reg' properties for I2C and SPI fdt: Export fdtdec_get_number() for general use x86: Add a x86_ prefix to the x86-specific PCI functions dm: Add a new CPU init function which can use driver model x86: Split up arch_cpu_init() Correct map_sysmem() logic in do_mem_mw() fdt: Tighten up error handling in fdtdec_get_pci_addr() dm: core: Add dev_get_uclass_priv() to access uclass private data dm: core: Mark device as active before calling its probe() method dm: core: Add a uclass pre_probe() method for devices dm: Show both allocated and requested seq numbers in 'dm uclass' dm: pci: Move common PCI functions into their own file dm: pci: Add a uclass for PCI dm: sandbox: pci: Add PCI support for sandbox dm: sandbox: Add a simple PCI driver dm: sandbox: pci: Add a PCI emulation uclass dm: sandbox: Add a emulated PCI device as an example dm: sandbox: pci: Enable PCI for sandbox dm: x86: pci: Add a PCI driver for driver model dm: x86: pci: Convert coreboot to use driver model for pci dm: x86: pci: Convert chromebook_link to use driver model for pci dm: pci: Add driver model tests for PCI arch/sandbox/Kconfig | 7 + arch/sandbox/cpu/cpu.c
Re: [U-Boot] [PULL] u-boot-socfpga/master
Fixed PR follows.
The following changes since commit 8176a874233eb5180701e2811b38c199369975b2:
Prepare v2015.04-rc3 (2015-03-03 18:08:39 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-socfpga.git HEAD
for you to fetch changes up to 053ae0a363276324aebbbdb1c2056a9380209f4b:
arm: socfpga: Enable DM and DM_SPI (2015-03-05 21:05:34 +0100)
Marek Vasut (11):
arm: socfpga: Minor coding style fix
arm: socfpga: Sync Cyclone V DK pinmux configuration
arm: socfpga: Sync Cyclone V DK PLL configuration
arm: socfpga: Add USB and UDC support for Cyclone V DK
arm: socfpga: Drop cyclone5 suffix from board file name
arm: socfpga: Zap checkboard()
arm: socfpga: Zap board_early_init_f()
arm: socfpga: Add Altera Arria V DK support
dt: socfpga: Import and enable Cyclone V DK DTS
dt: socfpga: Import and enable Arria V DK DTS
arm: socfpga: Enable DM and DM_SPI
arch/arm/Kconfig | 5 +
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/socfpga_arria5.dtsi | 34 +
arch/arm/dts/socfpga_arria5_socdk.dts | 74 +
arch/arm/dts/socfpga_cyclone5_socdk.dts| 79 ++
board/altera/socfpga/Kconfig | 16 ++
board/altera/socfpga/Makefile | 2 +-
board/altera/socfpga/iocsr_config.c| 688
+++
board/altera/socfpga/iocsr_config.h| 17 ++-
board/altera/socfpga/pinmux_config.c | 403
+
board/altera/socfpga/pinmux_config.h | 14 +-
board/altera/socfpga/pll_config.h | 34 ++---
board/altera/socfpga/{socfpga_cyclone5.c = socfpga.c} | 17 ---
configs/socfpga_arria5_defconfig | 8 +
configs/socfpga_cyclone5_defconfig | 5 +
include/configs/socfpga_arria5.h | 107 +
include/configs/socfpga_common.h | 3 +-
include/configs/socfpga_cyclone5.h | 9 ++
18 files changed, 1371 insertions(+), 149 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria5.dtsi
create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts
create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts
rename board/altera/socfpga/{socfpga_cyclone5.c = socfpga.c} (86%)
create mode 100644 configs/socfpga_arria5_defconfig
create mode 100644 include/configs/socfpga_arria5.h
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Re: [U-Boot] [PATCH] arm: socfpga: Enable DM and DM_SPI
On Thursday, March 05, 2015 at 08:46:44 PM, Simon Glass wrote: On 5 March 2015 at 03:56, Pavel Machek pa...@denx.de wrote: On Wed 2015-03-04 23:22:25, Marek Vasut wrote: Enable DM and DM_SPI support for both Cyclone 5 and Arria 5 boards, since they use drivers which require those. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Acked-by: Pavel Machek pa...@denx.de -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html Acked-by: Simon Glass s...@chromium.org (Marek I guess you will pick this up, but if not let me know) I will pick it, yep. Thanks. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 2/2] spi: Add Cadence QSPI controller Kconfig entry
Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com --- drivers/spi/Kconfig | 8 1 file changed, 8 insertions(+) V2: Improve the help text. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0f1d740..5a415be 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -18,3 +18,11 @@ config DESIGNWARE_SPI Enable the Designware SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Designware IP core. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence Quad-SPI (QSPI) driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Cadence IP core. -- 2.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable DM for Cadence and DW SPI
On Thursday, February 19, 2015 at 07:28:00 PM, Simon Glass wrote: Hi Marek, Hi Simon, On 19 February 2015 at 02:44, Marek Vasut ma...@denx.de wrote: On Thursday, February 19, 2015 at 02:07:13 AM, Simon Glass wrote: Hi Marek, On 18 February 2015 at 14:36, Marek Vasut ma...@denx.de wrote: Enable DM in case these two drivers are enabled, since these two drivers depend on DM. Signed-off-by: Marek Vasut ma...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@ti.com --- include/configs/socfpga_common.h | 4 1 file changed, 4 insertions(+) This should use Kconfig now. Hi, there's still no Cadence SPI nor DW SPI controller entry in drivers/spi/Kconfig, shall I add those then ? Yes, more Kconfig is good. Yep :) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] DWC2 driver issues
On Tuesday, March 03, 2015 at 12:33:41 AM, Stephen Warren wrote: [...] although it hangs pretty quickly. I assume one of the busy loops in dwc2.c without a time out isn't completing. Oh, dang. Those should certainly be fixed. Looking at the patch, could it be that CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP support in usb_kbd.c is broken altogether ? Well, once I applied that patch I did manage to type a few characters into the U-Boot shell via usbkbd one of the two times I tested, so it's not *completely* broken. It's still possible it's quite broken though, given the hangs:-) Well, that's a good progress all right :) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] dm: Protect device_unbind() with CONFIG_DM_DEVICE_REMOVE
On Friday, February 20, 2015 at 08:31:20 PM, Simon Glass wrote: Hi Marek, Hi Simon, things are starting to settle down a bit finally. [...] In case I base those patches on v2015.04-rc1 , I don't see this error, but in case I base those patches on top of v2015.04-rc2, I do see it. Do you have any hint which changes between these two points can cause this breakage please ? It is probably the Kconfig conversion - now there will be extra options enabled. Also, about the Kconfig, shall I introduce the entries for those two drivers or what is the plan here ? I would like to get these patches into the current release. Yes please. Should be all taken care of now :) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic
On Thu, Mar 05, 2015 at 11:49:05AM -0600, Nishanth Menon wrote: On 03/05/2015 08:00 AM, Matt Porter wrote: On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote: set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, switch over to smc #0 instead of handcoded assembly. To ensure gcc compatibility, steal the strategy used by Linux kernel for sec extension builds (NOTE: we no longer use '-march=armv5' as the legacy comment claims). Hi Nishanth, I applied this series with fuzz and fixed a minor conflict on master. I ran into a build issue for omap3 beagle with the sec extension scheme on the gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1) toolchain: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap3/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude -I../include -I../arch/arm/include -include ../include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -c -o arch/arm/cpu/armv7/omap3/lowlevel_init.o ../arch/arm/cpu/armv7/omap3/lowlevel_init.S ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages: ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' I've worked around this for the moment by placing an explicit .arch_extension sec in lowlevel_init.S but hopefully you have some thoughts on why those flags don't seem to be picked up. I'll continue to take a look at it in the meantime. Uggh.. this is weird. I had considered .arch_extension sec in lowlevel_init.S +plus_sec := $(call as-instr,.arch_extension sec,+sec) +AFLAGS_lowlevel_init.o :=-Wa,-march=armv7-a$(plus_sec) seems to be what we have in kernel and seems to do the job for me on $ arm-linux-gnueabi-gcc --version arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3 $ git clean -fdx; make omap3_beagle_defconfig; make V=1 arch/arm/cpu/armv7/omap-common/lowlevel_init.o with gcc 4.6: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc/arm-linux-gnueabi/4.6/include -Iinclude -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -Wa,-march=armv7-a+sec -c -o arch/arm/cpu/armv7/omap-common/lowlevel_init.o arch/arm/cpu/armv7/omap-common/lowlevel_init.S with gcc 4.7: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -Wa,-march=armv7-a -c -o arch/arm/cpu/armv7/omap-common/lowlevel_init.o arch/arm/cpu/armv7/omap-common/lowlevel_init.S arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages: arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' make[1]: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 1 make: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 2 I thought I stole the exact code from kernel, but as you can probably see -march=armv7-a+sec was generated for gcc 4.6 but -march=armv7-a without +sec for gcc 4.7! https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-omap2/Makefile#n44 It will be nice to have a solution that works on gcc 4.4 and above.. if we want to ignore gcc 4.4, then we can embed .arch_extension sec in lowlevel_init.S https://gcc.gnu.org/ml/gcc-help/2012-07/msg00181.html Sigh. I guess I'll give up on getting rid of the hand-crafted smc #0 call, it's being more troulbe than it's worth. Thanks for digging into it tho! -- Tom signature.asc Description: Digital signature
Re: [U-Boot] [PATCH V4 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic
On Thu, Mar 5, 2015 at 3:36 PM, Tom Rini tr...@konsulko.com wrote: On Thu, Mar 05, 2015 at 11:49:05AM -0600, Nishanth Menon wrote: On 03/05/2015 08:00 AM, Matt Porter wrote: On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote: set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, switch over to smc #0 instead of handcoded assembly. To ensure gcc compatibility, steal the strategy used by Linux kernel for sec extension builds (NOTE: we no longer use '-march=armv5' as the legacy comment claims). Hi Nishanth, I applied this series with fuzz and fixed a minor conflict on master. I ran into a build issue for omap3 beagle with the sec extension scheme on the gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1) toolchain: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap3/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude -I../include -I../arch/arm/include -include ../include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -c -o arch/arm/cpu/armv7/omap3/lowlevel_init.o ../arch/arm/cpu/armv7/omap3/lowlevel_init.S ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages: ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' I've worked around this for the moment by placing an explicit .arch_extension sec in lowlevel_init.S but hopefully you have some thoughts on why those flags don't seem to be picked up. I'll continue to take a look at it in the meantime. Uggh.. this is weird. I had considered .arch_extension sec in lowlevel_init.S +plus_sec := $(call as-instr,.arch_extension sec,+sec) +AFLAGS_lowlevel_init.o :=-Wa,-march=armv7-a$(plus_sec) seems to be what we have in kernel and seems to do the job for me on $ arm-linux-gnueabi-gcc --version arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3 $ git clean -fdx; make omap3_beagle_defconfig; make V=1 arch/arm/cpu/armv7/omap-common/lowlevel_init.o with gcc 4.6: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc/arm-linux-gnueabi/4.6/include -Iinclude -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -Wa,-march=armv7-a+sec -c -o arch/arm/cpu/armv7/omap-common/lowlevel_init.o arch/arm/cpu/armv7/omap-common/lowlevel_init.S with gcc 4.7: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -Wa,-march=armv7-a -c -o arch/arm/cpu/armv7/omap-common/lowlevel_init.o arch/arm/cpu/armv7/omap-common/lowlevel_init.S arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages: arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' make[1]: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 1 make: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 2 I thought I stole the exact code from kernel, but as you can probably see -march=armv7-a+sec was generated for gcc 4.6 but -march=armv7-a without +sec for gcc 4.7! https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-omap2/Makefile#n44 It will be nice to have a solution that works on gcc 4.4 and above.. if we want to ignore gcc 4.4, then we can embed .arch_extension sec in lowlevel_init.S https://gcc.gnu.org/ml/gcc-help/2012-07/msg00181.html Sigh. I guess I'll give up on getting rid of the hand-crafted smc #0 call, it's being more troulbe than it's worth. Thanks for digging into it tho! Alright, I will handcraft the smc code back in
Re: [U-Boot] [PATCH] tegra: Remove tegra_spl_gpio_direction_output declaration from header file
On 5 March 2015 at 09:58, Stephen Warren swar...@wwwdotorg.org wrote:
On 03/05/2015 03:40 AM, Axel Lin wrote:
This function is deleted by commit 2fccd2d96bad
tegra: Convert tegra GPIO driver to use driver model.
I think you want to send this to Tom Warren (who as Tegra maintainer would
apply it) and whoever wrote the commit you're fixing (Simon Glass I would
assume given the description). I've CC'd them so they see the patch.
Signed-off-by: Axel Lin axel@ingics.com
---
arch/arm/include/asm/arch-tegra/gpio.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h
b/arch/arm/include/asm/arch-tegra/gpio.h
index 7334e0c..daf5698 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -28,15 +28,6 @@ struct tegra_gpio_config {
};
/**
- * tegra_spl_gpio_direction_output() - set the output value of a GPIO
- *
- * This function is only used from SPL on seaboard, which needs to enable
a
- * GPIO to get the UART running. It could be done in U-Boot rather than
SPL,
- * but for now, this gets it working
- */
-int tegra_spl_gpio_direction_output(int gpio, int value);
-
-/**
* Configure a list of GPIOs
*
* @param config List of GPIO configurations
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Re: [U-Boot] Hi Simon, Problems about RSA public exponents for verified boot
Hi Michael, On 5 March 2015 at 06:29, Michael van der Westhuizen mich...@smart-africa.com wrote: Resurrecting this old thread… Jason, We’re presently getting CONFIG_OF_EMBED up on a 32 bit PPC target and hit a problem that made me think of this thread. What we’re seeing (in v2014.07) is that the FDT pointer is not necessarily aligned in the wrapper assembly file. We’ve worked around this with the following patch. You may want to try a similar patch to see if it resolves your problem. This was fixed in mainline around November. You could cherry-pick 5c30bf4 into your branch. Regards, Simon Michael diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 072abaa..987298f 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -251,6 +251,7 @@ quiet_cmd_dt_S_dtb= DTB $@ cmd_dt_S_dtb= \ ( \ echo '.section .dtb.init.rodata,a'; \ + echo '.align 4';\ echo '.global __dtb_$(*F)_begin'; \ echo '__dtb_$(*F)_begin:'; \ echo '.incbin $ '; \ On 09 Dec 2014, at 4:17 PM, Simon Glass s...@chromium.org wrote: (sorry, forgot to cc list) On 9 December 2014 at 07:17, Simon Glass s...@chromium.org wrote: Hi, On 8 December 2014 at 01:54, Duxiaoqiang duxiaoqi...@huawei.com wrote: Hi Michael, Thanks for your information. My working result show that public exponent is not the only problem caused by 64bit alignment, there are also some other problems caused by it, for example: load image after verify step. If you post your console output then perhaps we might be able to suggest a fix. May be we should add a patch to cover all 64 bit platform's alignment. For we need verified boot feature to solve some problems, I also spent some time trying to solve the problem. But I am not very familiar with uboot FDT'S design, it may spend me long time so not very convenient for me to solve this problem. So I want to know do you have time to fix this problem recently, and what's your plan. I haven't tried this on 64-bit ARM. I may be able to do so later in the month. Thanks very much. Sincerely Jason Hi All, Apologies for the delayed response, I’ve been on vacation. Since this was working for you (Duxiaoqiang) previously it suggests that you are using the default public exponent. If this is still the case you could, as a temporary workaround, remove the public exponent from your public key data to avoid executing the code causing the abort. Simon: Yes, we’ll need an alignment-safe version of fdt64_to_cpu. Michael On 02 Dec 2014, at 12:31 AM, Simon Glass s...@chromium.org wrote: +Michael, U-Boot mailing list Hi, On 30 November 2014 at 19:26, Duxiaoqiang duxiaoqi...@huawei.com wrote: Hi Simon When I test verified boot with new version of U-boot and new version of mkimage, I encountered a alignment problem about RSA public key exponents. I tested verified boot successful few months ago with version of 2014.07-rc4, but failed with the same configuration and operations this time. Problem logs as below: I debug this problem and noticed that the problem was caused by pulic_exponent’s address: 0xff78a04c, this address was not aligned to 8 byte, but this address was pointed by a uint64 * type of pointer. Panic happened in function rsa_verify_with_keynode, just as below: By compared the u-boot.dtb file that signed with RSA public key, I noticed that there are differences about PUBLIC_EXPONENT. With the older version of mkimage, there’s no public exponent section. And this problem only happens when I use the new version of mkimage tool. I also checked uboot’s code, it seems that there’s lack of mechanism to guarantee the alignment about public exponent section. Can you give some suggestions about this problem. Appreciate your time. Copying Michael. Perhaps we need a safer version of fdt64_to_cpu()? But you might be the first to run this on aarch64. I have not tried it yet, but I do now have a platform. REgards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/6] buildman: Add a space before the list of boards
On 5 February 2015 at 22:06, Simon Glass s...@chromium.org wrote: Tweak the output slightly so we don't get things like: - board1 board2+ board3 board4 There should be a space before the '+'. Signed-off-by: Simon Glass s...@chromium.org --- tools/buildman/builder.py | 2 +- tools/buildman/test.py| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 1b0ad99..54f3292 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -664,7 +664,7 @@ class Builder: arch = 'unknown' str = self.col.Color(color, ' ' + target) if not arch in done_arch: -str = self.col.Color(color, char) + ' ' + str +str = ' %s %s' % (self.col.Color(color, char), str) done_arch[arch] = True if not arch in arch_list: arch_list[arch] = str diff --git a/tools/buildman/test.py b/tools/buildman/test.py index c0ad5d0..7642d94 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -169,7 +169,7 @@ class TestBuild(unittest.TestCase): expected_colour = col.GREEN if ok else col.RED expect = '%10s: ' % arch # TODO(s...@chromium.org): If plus is '', we shouldn't need this -expect += col.Color(expected_colour, plus) +expect += ' ' + col.Color(expected_colour, plus) expect += ' ' for board in boards: expect += col.Color(expected_colour, ' %s' % board) -- 2.2.0.rc0.207.ga3a616c Applied u-boot-x86/buildman. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARMv8 targets are broken on 2015.04-rc3
On Thu, Mar 05, 2015 at 11:11:16AM -0800, York Sun wrote: Guys, I found these targets are broken on tag 2015.04-rc3 ls2085a_emu_D4 vexpress_aemv8a vexpress_aemv8a_juno ls2085a_emu vexpress_aemv8a_semi xilinx_zynqmp ls2085a_simu git bisect points to this commit a389531439a7d5cea2829054edcf438dc76e79a9. However it is really caused by this one commit e771a3d538a4fbe235864061ff3c81a8acb11082 Author: Marc Zyngier marc.zyng...@arm.com AuthorDate: Sat Jul 12 14:24:07 2014 +0100 Commit: Albert ARIBAUD albert.u.b...@aribaud.net CommitDate: Mon Jul 28 17:19:52 2014 +0200 ARM: HYP/non-sec/PSCI: emit DT nodes Generate the PSCI node in the device tree. Also add a reserve section for the secure code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Ian Campbell i...@hellion.org.uk This commit add armv7.h to bootm-fdt.c file. --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,13 +17,14 @@ #include common.h #include fdt_support.h +#include asm/armv7.h Shouldn't this line be architecture dependent? Looking at the whole commit, how is this breaking things? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARMv8 targets are broken on 2015.04-rc3
On Thu, Mar 05, 2015 at 03:27:59PM -0800, York Sun wrote: On 03/05/2015 03:26 PM, Tom Rini wrote: On Thu, Mar 05, 2015 at 11:11:16AM -0800, York Sun wrote: Guys, I found these targets are broken on tag 2015.04-rc3 ls2085a_emu_D4 vexpress_aemv8a vexpress_aemv8a_juno ls2085a_emu vexpress_aemv8a_semi xilinx_zynqmp ls2085a_simu git bisect points to this commit a389531439a7d5cea2829054edcf438dc76e79a9. However it is really caused by this one commit e771a3d538a4fbe235864061ff3c81a8acb11082 Author: Marc Zyngier marc.zyng...@arm.com AuthorDate: Sat Jul 12 14:24:07 2014 +0100 Commit: Albert ARIBAUD albert.u.b...@aribaud.net CommitDate: Mon Jul 28 17:19:52 2014 +0200 ARM: HYP/non-sec/PSCI: emit DT nodes Generate the PSCI node in the device tree. Also add a reserve section for the secure code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Ian Campbell i...@hellion.org.uk This commit add armv7.h to bootm-fdt.c file. --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,13 +17,14 @@ #include common.h #include fdt_support.h +#include asm/armv7.h Shouldn't this line be architecture dependent? Looking at the whole commit, how is this breaking things? Shall this include armv7.h regardless which architecture is compiled? This didn't cause any problem until a recent commit a389531 changes armv7.h. Yes, the include looks safe. This is one of those cryptic bisects, can you poke it a bit more and see what's causing the failure inside of the file? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] fastboot: add support for reboot-bootloader command
On 15-02-25 06:10 AM, Alexey Firago wrote:
The fastboot reboot-bootloader command is defined to
re-enter into fastboot mode after rebooting into
bootloader. This command is usually used after updating
bootloader via fastboot.
This commit implements only a generic side of the
command - setting of the reset flag and then resetting.
Setting of the reset flag is implemented using __weak
fb_set_reboot_flag() function. The actual setting and
checking of the reset flag should be implemented by
a boot script and/or board/SoC specific code.
Signed-off-by: Alexey Firago alexey_fir...@mentor.com
---
Changes in v3:
- return -ENOSYS from default fb_set_reboot_flag()
Changes in v2:
- return error in default fb_set_reboot_flag()
drivers/usb/gadget/f_fastboot.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 310175a..a000c25 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -122,6 +122,7 @@ static struct usb_gadget_strings *fastboot_strings[] = {
};
static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
+static int strcmp_l1(const char *s1, const char *s2);
static void fastboot_complete(struct usb_ep *ep, struct usb_request *req)
{
@@ -317,8 +318,20 @@ static void compl_do_reset(struct usb_ep *ep, struct
usb_request *req)
do_reset(NULL, 0, 0, NULL);
}
+int __weak fb_set_reboot_flag(void)
+{
+ return -ENOSYS;
+}
+
static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
{
+ char *cmd = req-buf;
+ if (!strcmp_l1(reboot-bootloader, cmd)) {
+ if (fb_set_reboot_flag()) {
+ fastboot_tx_write_str(FAILCannot set reboot flag);
+ return;
+ }
+ }
fastboot_func-in_req-complete = compl_do_reset;
fastboot_tx_write_str(OKAY);
}
Tested-by: Steve Rae s...@broadcom.com
(on bcm28155_ap board)
Thanks!
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Re: [U-Boot] [PATCH V2 2/2] spi: Add Cadence QSPI controller Kconfig entry
On Thursday, March 05, 2015 at 10:46:08 PM, Simon Glass wrote: Thanks. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0f1d740..5a415be 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -18,3 +18,11 @@ config DESIGNWARE_SPI Enable the Designware SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Designware IP core. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence Quad-SPI (QSPI) driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Cadence IP core. -- 2.1.3 Acked-by: Simon Glass s...@chromium.org Jagan seems to be busy with his marriage, so ... how do we handle these two patches ? Do you want them in for this MW or the next one (either way is fine by me) ? Also, I can push them through the socfpga tree, even though they should probably go through -spi tree. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-x86 branch 'buildman'
HI Tom, Here are a few bug fixes. Note they are in branch 'buildman'. The following changes since commit 7ae8350f67eea861280a4cbd2d06a0e87153: ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACK (2015-03-04 14:55:04 -0500) are available in the git repository at: http://git.denx.de/u-boot-x86.git for you to fetch changes up to 63c619eefde619731370b42ae2a2c16a86b23597: buildman: Add a space before the list of boards (2015-03-05 16:14:32 -0700) Simon Glass (2): buildman: Correct toolchain download feature buildman: Add a space before the list of boards tools/buildman/builder.py | 2 +- tools/buildman/test.py | 2 +- tools/buildman/toolchain.py | 10 +++--- 3 files changed, 9 insertions(+), 5 deletions(-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/2] spi: Add Cadence QSPI controller Kconfig entry
On 5 March 2015 at 13:51, Marek Vasut ma...@denx.de wrote: Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com --- drivers/spi/Kconfig | 8 1 file changed, 8 insertions(+) V2: Improve the help text. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0f1d740..5a415be 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -18,3 +18,11 @@ config DESIGNWARE_SPI Enable the Designware SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Designware IP core. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence Quad-SPI (QSPI) driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Cadence IP core. -- 2.1.3 Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARMv8 targets are broken on 2015.04-rc3
On 03/05/2015 03:26 PM, Tom Rini wrote: On Thu, Mar 05, 2015 at 11:11:16AM -0800, York Sun wrote: Guys, I found these targets are broken on tag 2015.04-rc3 ls2085a_emu_D4 vexpress_aemv8a vexpress_aemv8a_juno ls2085a_emu vexpress_aemv8a_semi xilinx_zynqmp ls2085a_simu git bisect points to this commit a389531439a7d5cea2829054edcf438dc76e79a9. However it is really caused by this one commit e771a3d538a4fbe235864061ff3c81a8acb11082 Author: Marc Zyngier marc.zyng...@arm.com AuthorDate: Sat Jul 12 14:24:07 2014 +0100 Commit: Albert ARIBAUD albert.u.b...@aribaud.net CommitDate: Mon Jul 28 17:19:52 2014 +0200 ARM: HYP/non-sec/PSCI: emit DT nodes Generate the PSCI node in the device tree. Also add a reserve section for the secure code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Ian Campbell i...@hellion.org.uk This commit add armv7.h to bootm-fdt.c file. --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,13 +17,14 @@ #include common.h #include fdt_support.h +#include asm/armv7.h Shouldn't this line be architecture dependent? Looking at the whole commit, how is this breaking things? Shall this include armv7.h regardless which architecture is compiled? This didn't cause any problem until a recent commit a389531 changes armv7.h. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/2] spi: Add Cadence QSPI controller Kconfig entry
On 05.03.2015 21:51, Marek Vasut wrote: Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 1/2] spi: Add Designware SPI controller Kconfig entry
On 05.03.2015 21:51, Marek Vasut wrote: Add DWC SPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] tegra: Remove tegra_spl_gpio_direction_output declaration from header file
On 5 March 2015 at 14:45, Simon Glass s...@chromium.org wrote:
On 5 March 2015 at 09:58, Stephen Warren swar...@wwwdotorg.org wrote:
On 03/05/2015 03:40 AM, Axel Lin wrote:
This function is deleted by commit 2fccd2d96bad
tegra: Convert tegra GPIO driver to use driver model.
I think you want to send this to Tom Warren (who as Tegra maintainer would
apply it) and whoever wrote the commit you're fixing (Simon Glass I would
assume given the description). I've CC'd them so they see the patch.
Signed-off-by: Axel Lin axel@ingics.com
---
arch/arm/include/asm/arch-tegra/gpio.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h
b/arch/arm/include/asm/arch-tegra/gpio.h
index 7334e0c..daf5698 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -28,15 +28,6 @@ struct tegra_gpio_config {
};
/**
- * tegra_spl_gpio_direction_output() - set the output value of a GPIO
- *
- * This function is only used from SPL on seaboard, which needs to enable
a
- * GPIO to get the UART running. It could be done in U-Boot rather than
SPL,
- * but for now, this gets it working
- */
-int tegra_spl_gpio_direction_output(int gpio, int value);
-
-/**
* Configure a list of GPIOs
*
* @param config List of GPIO configurations
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Re: [U-Boot] [PATCH V2 1/2] spi: Add Designware SPI controller Kconfig entry
On 5 March 2015 at 13:51, Marek Vasut ma...@denx.de wrote: Add DWC SPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com --- drivers/spi/Kconfig | 8 1 file changed, 8 insertions(+) V2: Improve the help text. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7ae2727..0f1d740 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -10,3 +10,11 @@ config DM_SPI as 'parent data' to every slave on each bus. Slaves typically use driver-private data instead of extending the spi_slave structure. + +config DESIGNWARE_SPI + bool Designware SPI driver + depends on DM_SPI + help + Enable the Designware SPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Designware + IP core. -- 2.1.3 Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 2/2] spi: Add Cadence QSPI controller Kconfig entry
Hi Marek, On 5 March 2015 at 14:51, Marek Vasut ma...@denx.de wrote: On Thursday, March 05, 2015 at 10:46:08 PM, Simon Glass wrote: Thanks. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0f1d740..5a415be 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -18,3 +18,11 @@ config DESIGNWARE_SPI Enable the Designware SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Designware IP core. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence Quad-SPI (QSPI) driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Cadence IP core. -- 2.1.3 Acked-by: Simon Glass s...@chromium.org Jagan seems to be busy with his marriage, so ... how do we handle these two patches ? Do you want them in for this MW or the next one (either way is fine by me) ? Also, I can push them through the socfpga tree, even though they should probably go through -spi tree. How about you pick them up? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] buildman: Correct toolchain download feature
On 4 March 2015 at 23:15, Heiko Schocher h...@denx.de wrote: Hello Simon, Am 03.03.2015 01:05, schrieb Simon Glass: Commit d908898 updated the ScanPath() function but not its documentation and not all its callers. This breaks the toolchain check after it is downloaded. Fix it. Signed-off-by: Simon Glass s...@chromium.org --- tools/buildman/toolchain.py | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) Thanks! Acked-by: Heiko Schocher h...@denx.de Applied to u-boot-x86/buildman. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARMv8 targets are broken on 2015.04-rc3
On 03/05/2015 03:33 PM, Tom Rini wrote:
On Thu, Mar 05, 2015 at 03:27:59PM -0800, York Sun wrote:
On 03/05/2015 03:26 PM, Tom Rini wrote:
On Thu, Mar 05, 2015 at 11:11:16AM -0800, York Sun wrote:
Guys,
I found these targets are broken on tag 2015.04-rc3
ls2085a_emu_D4
vexpress_aemv8a
vexpress_aemv8a_juno
ls2085a_emu
vexpress_aemv8a_semi
xilinx_zynqmp
ls2085a_simu
git bisect points to this commit a389531439a7d5cea2829054edcf438dc76e79a9.
However it is really caused by this one
commit e771a3d538a4fbe235864061ff3c81a8acb11082
Author: Marc Zyngier marc.zyng...@arm.com
AuthorDate: Sat Jul 12 14:24:07 2014 +0100
Commit: Albert ARIBAUD albert.u.b...@aribaud.net
CommitDate: Mon Jul 28 17:19:52 2014 +0200
ARM: HYP/non-sec/PSCI: emit DT nodes
Generate the PSCI node in the device tree.
Also add a reserve section for the secure code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Ian Campbell i...@hellion.org.uk
This commit add armv7.h to bootm-fdt.c file.
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -17,13 +17,14 @@
#include common.h
#include fdt_support.h
+#include asm/armv7.h
Shouldn't this line be architecture dependent?
Looking at the whole commit, how is this breaking things?
Shall this include armv7.h regardless which architecture is compiled? This
didn't cause any problem until a recent commit a389531 changes armv7.h.
Yes, the include looks safe. This is one of those cryptic bisects, can
you poke it a bit more and see what's causing the failure inside of the
file?
You mean it is safe to include armv7.h even if I am building armv8 targets?
When compiling armv8 targets, I have these warnings
/home/u-boot-upstream-85xx/arch/arm/include/asm/armv7.h: In function
‘v7_enable_smp’:
/home/u-boot-upstream-85xx/arch/arm/include/asm/io.h:72:28: warning: cast to
pointer from integer of different size [-Wint-to-pointer-cast]
#define __arch_getl(a) (*(volatile unsigned int *)(a))
^
/home/u-boot-upstream-85xx/arch/arm/include/asm/io.h:151:31: note: in expansion
of macro ‘__arch_getl’
#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
^
/home/u-boot-upstream-85xx/arch/arm/include/asm/armv7.h:105:9: note: in
expansion of macro ‘readl’
temp = readl(address);
^
The readl was added into armv7.h by commit a389531.
York
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Re: [U-Boot] ARMv8 targets are broken on 2015.04-rc3
On Thu, Mar 05, 2015 at 03:45:24PM -0800, York Sun wrote:
On 03/05/2015 03:33 PM, Tom Rini wrote:
On Thu, Mar 05, 2015 at 03:27:59PM -0800, York Sun wrote:
On 03/05/2015 03:26 PM, Tom Rini wrote:
On Thu, Mar 05, 2015 at 11:11:16AM -0800, York Sun wrote:
Guys,
I found these targets are broken on tag 2015.04-rc3
ls2085a_emu_D4
vexpress_aemv8a
vexpress_aemv8a_juno
ls2085a_emu
vexpress_aemv8a_semi
xilinx_zynqmp
ls2085a_simu
git bisect points to this commit
a389531439a7d5cea2829054edcf438dc76e79a9.
However it is really caused by this one
commit e771a3d538a4fbe235864061ff3c81a8acb11082
Author: Marc Zyngier marc.zyng...@arm.com
AuthorDate: Sat Jul 12 14:24:07 2014 +0100
Commit: Albert ARIBAUD albert.u.b...@aribaud.net
CommitDate: Mon Jul 28 17:19:52 2014 +0200
ARM: HYP/non-sec/PSCI: emit DT nodes
Generate the PSCI node in the device tree.
Also add a reserve section for the secure code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Acked-by: Ian Campbell i...@hellion.org.uk
This commit add armv7.h to bootm-fdt.c file.
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -17,13 +17,14 @@
#include common.h
#include fdt_support.h
+#include asm/armv7.h
Shouldn't this line be architecture dependent?
Looking at the whole commit, how is this breaking things?
Shall this include armv7.h regardless which architecture is compiled? This
didn't cause any problem until a recent commit a389531 changes armv7.h.
Yes, the include looks safe. This is one of those cryptic bisects, can
you poke it a bit more and see what's causing the failure inside of the
file?
You mean it is safe to include armv7.h even if I am building armv8 targets?
When compiling armv8 targets, I have these warnings
/home/u-boot-upstream-85xx/arch/arm/include/asm/armv7.h: In function
‘v7_enable_smp’:
/home/u-boot-upstream-85xx/arch/arm/include/asm/io.h:72:28: warning: cast to
pointer from integer of different size [-Wint-to-pointer-cast]
#define __arch_getl(a) (*(volatile unsigned int *)(a))
^
/home/u-boot-upstream-85xx/arch/arm/include/asm/io.h:151:31: note: in
expansion
of macro ‘__arch_getl’
#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
^
/home/u-boot-upstream-85xx/arch/arm/include/asm/armv7.h:105:9: note: in
expansion of macro ‘readl’
temp = readl(address);
^
The readl was added into armv7.h by commit a389531.
Ah well now we're getting somewhere :) Let me try and whip up a patch..
--
Tom
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Re: [U-Boot] [PATCH V4 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements
On 03/05/2015 11:56 AM, Nishanth Menon wrote: On 03/05/2015 10:21 AM, Matt Porter wrote: On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote: The fourth incarnation of this series to address review comments on V3 With all the usual disclaimers and request to see V1 of the series for a detailed blurb.. As usual additional testing preferred.. Sorry, I dont have access to all possible variants atm.. changes since v3: - few corrections - i have tried to do a push-pop of register params. hopefully, they should do the job - smc with a makefile handling of secure-ext enablement.. (stolen from kernel). V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307 V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174 Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch) BeagleBoard-X15: http://pastebin.ubuntu.com/10518934/ Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x L2PFR=0x09b0 ACTLR=0x0040 After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 L2PFR=0x09b0 ACTLR=0x0040 OMAP5uEVM: http://pastebin.ubuntu.com/10518958/ Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x L2PFR=0x09b0 ACTLR=0x0040 After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 L2PFR=0x09b0 ACTLR=0x0040 Beagle-XM: http://pastebin.ubuntu.com/10519417/ (this is a r2p3 device) Before: CPUID=0x413fc082 ACR=0x00e2 L2AUXCR=0x0042 After: CPUID=0x413fc082 ACR=0x0042 L2AUXCR=0x0042 I also got the same results on a Beagle-XM Rev. C1 I dont have access to other omap3 platforms to give a better coverage Beagle Rev. C2 (OMAP3530): http://pastebin.com/f5JcvRf4 Before: CPUID=0x411fc083 ACR=0x00e2 L2AUXCR=0x0042 After: CPUID=0x411fc083 ACR=0x0042 L2AUXCR=0x0042 Tested-by: Matt Porter mpor...@konsulko.com Thanks for testing. [With build workaround I noted elsewhere in the thread] that should have been a r1p3 device(needs errata), right and mine should really be a r3p2? Did i get the code wrong here? Need some additional eyes here :( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/Bhccjgga.html mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) mov r3, r1, lsr #20 @ get variant field and r3, r3, #0xf@ r3 has CPU variant and r4, r1, #0xf@ r4 has CPU revision mov r2, r3, lsl #4 @ shift variant field for combined value orr r2, r4, r2 @ r2 has combined CPU variant + revision cmp r2, #0x21 @ Only on r2p1 bge skip_errata_621766 Alright, thanks to Jtag debugger and replaced 'bgt skip_errata' with 'blt skip_errata (forcing errata flow on my non-errata beagleboard-xm board) found the issue. (A bit embarrassed to be staring at it and not recollecting).. I should have s/b v7_arch_cp15_set_acr/bl v7_arch_cp15_set_acr/ Since I was not branching and linking (just branching), I was returning back to the caller of cpu_init_cp15 when the call from v7_arch_cp15_set_acr was returning, instead of returning back to v7_arch_cp15_set_acr! elementary error! Sorry, did not see it previously with A15 erratum since it was a single one to walk down and follow on errata never took place. Please standby for a v5 with proper code flow. Apologies on requesting testing again.. -- Uggh... very very embarrassedely yours, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements
On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote:
The fourth incarnation of this series to address review comments on V3
With all the usual disclaimers and request to see V1 of the series for a
detailed blurb.. As usual additional testing preferred.. Sorry, I dont have
access to all possible variants atm..
changes since v3:
- few corrections - i have tried to do a push-pop of register params.
hopefully, they should do the job
- smc with a makefile handling of secure-ext enablement.. (stolen from
kernel).
V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)
BeagleBoard-X15: http://pastebin.ubuntu.com/10518934/
Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x
L2PFR=0x09b0 ACTLR=0x0040
After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198
L2PFR=0x09b0 ACTLR=0x0040
OMAP5uEVM: http://pastebin.ubuntu.com/10518958/
Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x
L2PFR=0x09b0 ACTLR=0x0040
After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198
L2PFR=0x09b0 ACTLR=0x0040
Beagle-XM: http://pastebin.ubuntu.com/10519417/ (this is a r2p3 device)
Before: CPUID=0x413fc082 ACR=0x00e2 L2AUXCR=0x0042
After: CPUID=0x413fc082 ACR=0x0042 L2AUXCR=0x0042
I also got the same results on a Beagle-XM Rev. C1
I dont have access to other omap3 platforms to give a better coverage
Beagle Rev. C2 (OMAP3530): http://pastebin.com/f5JcvRf4
Before: CPUID=0x411fc083 ACR=0x00e2 L2AUXCR=0x0042
After: CPUID=0x411fc083 ACR=0x0042 L2AUXCR=0x0042
Tested-by: Matt Porter mpor...@konsulko.com
[With build workaround I noted elsewhere in the thread]
-Matt
Sanity check:
OMAP4Panda-ES: http://pastebin.ubuntu.com/10518971/
Nishanth Menon (10):
ARM: Introduce erratum workaround for 798870
ARM: Introduce erratum workaround for 454179
ARM: Introduce erratum workaround for 430973
ARM: Introduce erratum workaround for 621766
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with
omap_smc1
ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
configuration
ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973,
621766
Praveen Rao (1):
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
README |8 +++
arch/arm/cpu/armv7/Makefile|2 +-
arch/arm/cpu/armv7/cp15.c | 29 ++
arch/arm/cpu/armv7/omap-common/Makefile|5 +-
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 19 +++---
arch/arm/cpu/armv7/omap3/board.c | 60 +++
arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11
arch/arm/cpu/armv7/omap4/hwinit.c |4 +-
arch/arm/cpu/armv7/omap5/hwinit.c | 23
arch/arm/cpu/armv7/start.S | 61
.../arm/include/asm/arch-omap3/{omap3.h = omap.h} |0
arch/arm/include/asm/arch-omap3/sys_proto.h|3 +-
arch/arm/include/asm/arch-omap4/sys_proto.h|5 +-
arch/arm/include/asm/arch-omap5/sys_proto.h|4 ++
arch/arm/include/asm/armv7.h |5 ++
board/nokia/rx51/rx51.c| 19 +++---
include/configs/am3517_crane.h |6 +-
include/configs/am3517_evm.h |6 +-
include/configs/cm_t35.h |6 +-
include/configs/cm_t3517.h |6 +-
include/configs/dig297.h |6 +-
include/configs/mcx.h |6 +-
include/configs/nokia_rx51.h |6 +-
include/configs/omap3_evm.h|2 +-
include/configs/omap3_evm_common.h |4 ++
include/configs/omap3_evm_quick_mmc.h |2 +-
include/configs/omap3_evm_quick_nand.h |2 +-
include/configs/omap3_logic.h |6 +-
include/configs/omap3_mvblx.h |6 +-
include/configs/omap3_pandora.h|6 +-
include/configs/omap3_sdp3430.h|6 +-
include/configs/omap3_zoom1.h |2 +-
include/configs/tam3517-common.h |6 +-
include/configs/tao3530.h |
Re: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
On Thu, Mar 05, 2015 at 05:30:26PM +0100, Stefan Roese wrote: On 05.03.2015 17:14, Marek Vasut wrote: diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c0b2570..eaf31ed 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -16,3 +16,9 @@ config DESIGNWARE_SPI depends on DM_SPI help Enable the Designware SPI driver. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. Can we get a bit more detail here? What does QSPI mean? What features does it support? Stefan ? ;-) Its the IP core from Cadence supporting SPI NOR flash and is present on the Altera SoCFPGA. Enabling access to such SPI NOR flash devices. QSPI stands for Quad-SPI and refers to the optional use of up to 4 data lines for flash access. So perhaps something like this: + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this + Cadence IP core (like the Altera SoCFPGA). QSPI stands for + Quad-SPI and refers to the optional use of up to 4 data lines + for flash access. Please don't mention platforms in the help for what I think of as IP-block-vendor drivers. The Cadence QSPI block will be reused by others and I can see someone needing to patch the help text. How about: Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this Cadence IP core. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] API_env_enum behaviour with SPI serial flash
Hi, I have a board with a SPI serial flash which runs u-boot 2011.12 and when I make a call to API_env_enum() it only enumerates through the list of environment variables present in the default_environment table and does not enumerate any user configured variables. Is this behaviour by design or have I missed anything. Any help or pointer to codes will be much appreciated. Thanks, ritu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] u-boot deleted
Hi, Im working on db 120 development board which uses atheros 9344 chip. I was trying to install openwrt on it when u-boot was accidentally deleted. So is there any way to install bootloader on it? Thanks and regard ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
On 05.03.2015 17:39, Tom Rini wrote: On Thu, Mar 05, 2015 at 05:30:26PM +0100, Stefan Roese wrote: On 05.03.2015 17:14, Marek Vasut wrote: diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c0b2570..eaf31ed 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -16,3 +16,9 @@ config DESIGNWARE_SPI depends on DM_SPI help Enable the Designware SPI driver. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. Can we get a bit more detail here? What does QSPI mean? What features does it support? Stefan ? ;-) Its the IP core from Cadence supporting SPI NOR flash and is present on the Altera SoCFPGA. Enabling access to such SPI NOR flash devices. QSPI stands for Quad-SPI and refers to the optional use of up to 4 data lines for flash access. So perhaps something like this: + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this + Cadence IP core (like the Altera SoCFPGA). QSPI stands for + Quad-SPI and refers to the optional use of up to 4 data lines + for flash access. Please don't mention platforms in the help for what I think of as IP-block-vendor drivers. The Cadence QSPI block will be reused by others and I can see someone needing to patch the help text. How about: Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to access the SPI NOR flash on platforms embedding this Cadence IP core. Even better. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
On 05.03.2015 17:14, Marek Vasut wrote: diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c0b2570..eaf31ed 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -16,3 +16,9 @@ config DESIGNWARE_SPI depends on DM_SPI help Enable the Designware SPI driver. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. Can we get a bit more detail here? What does QSPI mean? What features does it support? Stefan ? ;-) Its the IP core from Cadence supporting SPI NOR flash and is present on the Altera SoCFPGA. Enabling access to such SPI NOR flash devices. QSPI stands for Quad-SPI and refers to the optional use of up to 4 data lines for flash access. So perhaps something like this: + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this + Cadence IP core (like the Altera SoCFPGA). QSPI stands for + Quad-SPI and refers to the optional use of up to 4 data lines + for flash access. HTP. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] 4K padding of ARM DT blob
On Thu, Mar 05, 2015 at 08:02:50AM +, Yehuda Yitschak wrote: Hello I was wondering why the default ARM device tree blob is padded by 4K bytes Is this required to align to some storage medium ? Is there a configuration that allows to eliminate this padding to save space ? Can you expand on what you're referring to / code in question? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] tegra: Remove tegra_spl_gpio_direction_output declaration from header file
On 03/05/2015 03:40 AM, Axel Lin wrote:
This function is deleted by commit 2fccd2d96bad
tegra: Convert tegra GPIO driver to use driver model.
I think you want to send this to Tom Warren (who as Tegra maintainer
would apply it) and whoever wrote the commit you're fixing (Simon Glass
I would assume given the description). I've CC'd them so they see the patch.
Signed-off-by: Axel Lin axel@ingics.com
---
arch/arm/include/asm/arch-tegra/gpio.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h
b/arch/arm/include/asm/arch-tegra/gpio.h
index 7334e0c..daf5698 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -28,15 +28,6 @@ struct tegra_gpio_config {
};
/**
- * tegra_spl_gpio_direction_output() - set the output value of a GPIO
- *
- * This function is only used from SPL on seaboard, which needs to enable a
- * GPIO to get the UART running. It could be done in U-Boot rather than SPL,
- * but for now, this gets it working
- */
-int tegra_spl_gpio_direction_output(int gpio, int value);
-
-/**
* Configure a list of GPIOs
*
* @param config List of GPIO configurations
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Re: [U-Boot] [PATCH v3 0/9] sf: Update flash params for supported read commands and sector size
On 4 March 2015 at 09:02, Bin Meng bmeng...@gmail.com wrote: Hi Tom, On Wed, Mar 4, 2015 at 6:52 AM, Tom Rini tr...@konsulko.com wrote: On Tue, Mar 03, 2015 at 04:31:44PM +0800, Bin Meng wrote: +Tom Hi Jagan, On Tue, Jan 27, 2015 at 9:50 PM, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Sat, Jan 24, 2015 at 6:34 PM, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Mon, Jan 12, 2015 at 2:52 PM, Jagan Teki jagannadh.t...@gmail.com wrote: On 12 January 2015 at 09:12, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Wed, Dec 17, 2014 at 4:39 PM, Jagan Teki jagannadh.t...@gmail.com wrote: On 17 December 2014 at 13:32, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Wed, Dec 17, 2014 at 3:59 PM, Jagan Teki jagannadh.t...@gmail.com wrote: On 15 December 2014 at 19:21, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Thu, Dec 11, 2014 at 3:40 PM, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Thu, Dec 11, 2014 at 3:26 PM, Jagan Teki jagannadh.t...@gmail.com wrote: Hi Bin, On 11 December 2014 at 08:34, Bin Meng bmeng...@gmail.com wrote: Hi Jagan, On Thu, Dec 11, 2014 at 2:41 AM, Jagan Teki jagannadh.t...@gmail.com wrote: Hi Bin, On 10 December 2014 at 18:21, Bin Meng bmeng...@gmail.com wrote: This series update SPI flash supported read commands per datasheet in the flash params table, and change flash sector size to 4KiB as long as flash supports sector erase (20h) command, to ensure 'sf erase offset +len' work on 4KiB boundary instead of 64KiB when given SECT_4K. Changes in v3: - Rebase with Jagan's patch series @ http://patchwork.ozlabs.org/patch/419154/ Bin Meng (9): sf: Update SST flash params sf: Update Atmel flash params sf: Update EON flash params sf: Update GigaDevice flash params sf: Update Macronix flash params sf: Update Spansion flash params sf: Update Micron flash params sf: Update Winbond flash params sf: Give proper spacing between flash table params Thanks for the updates - have you verified these changes? I verified some, but not all of these flash parts. The update is based on flash datasheet, so if something is broken, eg before this series the flash advertises only READ_NORM and after my series it is changed to READ_FULL, and let's say QUAD_IO_FAST is not working, it is very likely that the SPI controller driver has some bugs when supporting QUAD_IO_FAST. Since these updates were tested before, I will skip these for this PR. Will test all the rest (except these) and send the PR soon. Let me know your inputs? I am fine, as long as this PR will not contains other commits which modify the same sf_params.c to introduce more flash support. We can test these updates and if everything looks fine, apply these first and ask other commits to rebase on this series to introduce more flash support. Do you have any additional comments about this patch series besides the S25FL128S_64K and S25FL256S_64K sector size? If not, I can send the v4. I'm thinking about the other flashes too, since these params were taken from previous working and Linux mtd. You mean 'thinking about' or 'testing'? I should say previously they might not be 100% working as per datasheet some flash params currently are apparently wrong. Yes - about testing. Ping? What about your test results about this patch series? Some were pending - Will comment, pls- wait. thanks! -- I still don't see any additional comments. Looking at the history this patch series has been sitting there for months. Would you please let me know what you think about this series? Could you respond this? I wonder if this series could be merged in before MW is closed. I feel that you did not work on this. Can you please respond with any comments? Indeed. This looks like a fairly trivial sync-up, can you shoot me all of the patchwork links and I'll take a look? Thanks! -- Thanks for checking. Here you are: http://patchwork.ozlabs.org/patch/419633/ http://patchwork.ozlabs.org/patch/419634/ http://patchwork.ozlabs.org/patch/419635/ http://patchwork.ozlabs.org/patch/419636/ http://patchwork.ozlabs.org/patch/419637/ http://patchwork.ozlabs.org/patch/419638/ http://patchwork.ozlabs.org/patch/419639/ http://patchwork.ozlabs.org/patch/419640/ http://patchwork.ozlabs.org/patch/419641/ They might not be applied cleanly now due to the significant delay since it was originally posted to the mailing list. So far Jagan pointed out only one issue and he said he would continue looking into the patches but I did not receive any feedback for months. Sorry that I'm in long vacations which is less possible in mailing. As these changes are very crucial, I keep waiting the same. I will be back on March, end - if still need an urgent sync-up on these changes Tom or
Re: [U-Boot] [PATCH V4 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic
On 03/05/2015 08:00 AM, Matt Porter wrote: On Tue, Mar 03, 2015 at 04:26:22PM -0600, Nishanth Menon wrote: set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, switch over to smc #0 instead of handcoded assembly. To ensure gcc compatibility, steal the strategy used by Linux kernel for sec extension builds (NOTE: we no longer use '-march=armv5' as the legacy comment claims). Hi Nishanth, I applied this series with fuzz and fixed a minor conflict on master. I ran into a build issue for omap3 beagle with the sec extension scheme on the gcc version 4.7.4 (Ubuntu/Linaro 4.7.4-2ubuntu1) toolchain: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap3/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude -I../include -I../arch/arm/include -include ../include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -c -o arch/arm/cpu/armv7/omap3/lowlevel_init.o ../arch/arm/cpu/armv7/omap3/lowlevel_init.S ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages: ../arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' I've worked around this for the moment by placing an explicit .arch_extension sec in lowlevel_init.S but hopefully you have some thoughts on why those flags don't seem to be picked up. I'll continue to take a look at it in the meantime. Uggh.. this is weird. I had considered .arch_extension sec in lowlevel_init.S +plus_sec := $(call as-instr,.arch_extension sec,+sec) +AFLAGS_lowlevel_init.o :=-Wa,-march=armv7-a$(plus_sec) seems to be what we have in kernel and seems to do the job for me on $ arm-linux-gnueabi-gcc --version arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3 $ git clean -fdx; make omap3_beagle_defconfig; make V=1 arch/arm/cpu/armv7/omap-common/lowlevel_init.o with gcc 4.6: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc/arm-linux-gnueabi/4.6/include -Iinclude -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -Wa,-march=armv7-a+sec -c -o arch/arm/cpu/armv7/omap-common/lowlevel_init.o arch/arm/cpu/armv7/omap-common/lowlevel_init.S with gcc 4.7: arm-linux-gnueabi-gcc -Wp,-MD,arch/arm/cpu/armv7/omap-common/.lowlevel_init.o.d -nostdinc -isystem /usr/lib/gcc-cross/arm-linux-gnueabi/4.7/include -Iinclude -I./arch/arm/include -include ./include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -DCONFIG_SYS_TEXT_BASE=0x8010 -D__ASSEMBLY__ -g -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux -mword-relocations -march=armv7-a -mno-unaligned-access -ffunction-sections -fdata-sections -fno-common -ffixed-r9 -msoft-float -pipe -Wa,-march=armv7-a -c -o arch/arm/cpu/armv7/omap-common/lowlevel_init.o arch/arm/cpu/armv7/omap-common/lowlevel_init.S arch/arm/cpu/armv7/omap-common/lowlevel_init.S: Assembler messages: arch/arm/cpu/armv7/omap-common/lowlevel_init.S:34: Error: selected processor does not support ARM mode `smc #0' make[1]: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 1 make: *** [arch/arm/cpu/armv7/omap-common/lowlevel_init.o] Error 2 I thought I stole the exact code from kernel, but as you can probably see -march=armv7-a+sec was generated for gcc 4.6 but -march=armv7-a without +sec for gcc 4.7! https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-omap2/Makefile#n44 It will be nice to have a solution that works on gcc 4.4 and above.. if we want to ignore gcc 4.4, then we can embed .arch_extension sec in lowlevel_init.S https://gcc.gnu.org/ml/gcc-help/2012-07/msg00181.html any suggestions? [...] -- Regards, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V4 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements
On 03/05/2015 10:21 AM, Matt Porter wrote: On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote: The fourth incarnation of this series to address review comments on V3 With all the usual disclaimers and request to see V1 of the series for a detailed blurb.. As usual additional testing preferred.. Sorry, I dont have access to all possible variants atm.. changes since v3: - few corrections - i have tried to do a push-pop of register params. hopefully, they should do the job - smc with a makefile handling of secure-ext enablement.. (stolen from kernel). V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307 V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174 Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch) BeagleBoard-X15: http://pastebin.ubuntu.com/10518934/ Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x L2PFR=0x09b0 ACTLR=0x0040 After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 L2PFR=0x09b0 ACTLR=0x0040 OMAP5uEVM: http://pastebin.ubuntu.com/10518958/ Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x L2PFR=0x09b0 ACTLR=0x0040 After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x0198 L2PFR=0x09b0 ACTLR=0x0040 Beagle-XM: http://pastebin.ubuntu.com/10519417/ (this is a r2p3 device) Before: CPUID=0x413fc082 ACR=0x00e2 L2AUXCR=0x0042 After: CPUID=0x413fc082 ACR=0x0042 L2AUXCR=0x0042 I also got the same results on a Beagle-XM Rev. C1 I dont have access to other omap3 platforms to give a better coverage Beagle Rev. C2 (OMAP3530): http://pastebin.com/f5JcvRf4 Before: CPUID=0x411fc083 ACR=0x00e2 L2AUXCR=0x0042 After: CPUID=0x411fc083 ACR=0x0042 L2AUXCR=0x0042 Tested-by: Matt Porter mpor...@konsulko.com Thanks for testing. [With build workaround I noted elsewhere in the thread] that should have been a r1p3 device(needs errata), right and mine should really be a r3p2? Did i get the code wrong here? Need some additional eyes here :( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/Bhccjgga.html mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) mov r3, r1, lsr #20 @ get variant field and r3, r3, #0xf@ r3 has CPU variant and r4, r1, #0xf@ r4 has CPU revision mov r2, r3, lsl #4 @ shift variant field for combined value orr r2, r4, r2 @ r2 has combined CPU variant + revision cmp r2, #0x21 @ Only on r2p1 bge skip_errata_621766 -- Regards, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] am33xx, spl, siemens: enable debug uart output again
Hello Tom,
Am 05.03.2015 07:22, schrieb Heiko Schocher:
Hello Tom,
Am 04.03.2015 17:40, schrieb Tom Rini:
On Wed, Mar 04, 2015 at 08:42:58AM +0100, Heiko Schocher wrote:
Hello Tom,
Am 02.03.2015 14:59, schrieb Tom Rini:
On Mon, Mar 02, 2015 at 07:56:41AM +0100, Heiko Schocher wrote:
Hello Simon,
Am 24.02.2015 14:31, schrieb Simon Glass:
Hi Heiko,
On 23 February 2015 at 23:18, Heiko Schocher h...@denx.de wrote:
a6b541b090: TI ARMv7: Don't use GD before crt0.S has set it
moves the init of the debug uart at the very end of SPL code.
Enable it for the siemens board earlier, as they print
ddr settings ... all debug output before board_init_r()
is here currently useless. Maybe we must rework this
globally?
Assuming we are talking about U-Boot proper, the DDR init should
happen in board_init_f(), specifically dram_init(). so I think this
code should be updated.
If it is SPL, then DDR init should happen in SPL's board_init_f().
It is in SPL...
sdram_init() is called from:
./arch/arm/cpu/armv7/am33xx/board.c from s_init() ...
I sent a series a few weeks ago (available at u-boot-dm branch
spl-working) related to this topic:
http://patchwork.ozlabs.org/patch/438581/
Ah ... Hmm... so ./arch/arm/cpu/armv7/am33xx/board.c needs
a rework, right?
Is a simple rename s_init() - board_init_f() correct?
Right so, no, we can't just rename s_init to board_init_f. This is what
I was talking about in the thread about the function Hans wants to add
to enable some bits in CP15 on sunxi, iirc.
In short, armv7 has a different set of abstraction hooks than the
previous ARM cores (armv8 followed what we have for v7) and I'm not
convinced in the end that it really won us anything. See
http://lists.denx.de/pipermail/u-boot/2015-January/202350.html
For today you need to rework the Siemens code to print out the DDR
values (when desired) in spl_board_init() as we do not, or will not
shortly, have gd prior to board_init_f running.
Hmm... first I thought, ok, no problem, move the output from the RAM
parameters to spl_board_init() ... but thats only the half of the
story ... They read the RAM parameters from an i2c eeprom, and if
there are errors, they print this errors ... currently this does
not work, and thats I think the more important case ... and I could
not move this error printfs to somewhere, because if RAM is not
working ... there is no later ...
So I have to enable the console early ... maybe I missed something,
but this worked fine in the past (and I think we should not break
this, as this is an essential feature).
OK, I missed something too. I think this gets better now once I merge
Simon's SPL series as we do all of this from board_init_f() and the
siemens code should just work again.
Yes, just saw your patch ;-)
If they are in mainline (or do you have them somewhere in a git repo?),
I test it again on the dxr2 board, thanks!
If I am correct, all needed patches from you are in mainline, just
tried this on the dxr2 board ... but I still need:
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index a39cbd0..8724604 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -40,6 +40,11 @@ void set_uart_mux_conf(void)
void set_mux_conf_regs(void)
{
+ /* enable early the console */
+ gd-baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ gd-have_console = 1;
+
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_set_bus_num(0);
to see the console output ...
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [PATCH v3] fastboot: add support for reboot-bootloader command
Hi Lukasz,
Hmm, I don't see it applied to u-boot-dfu now. Do I need to add something ?
Thanks,
Alexey
On 26.02.2015 13:22, Lukasz Majewski wrote:
Hi Alexey,
The fastboot reboot-bootloader command is defined to
re-enter into fastboot mode after rebooting into
bootloader. This command is usually used after updating
bootloader via fastboot.
This commit implements only a generic side of the
command - setting of the reset flag and then resetting.
Setting of the reset flag is implemented using __weak
fb_set_reboot_flag() function. The actual setting and
checking of the reset flag should be implemented by
a boot script and/or board/SoC specific code.
Signed-off-by: Alexey Firago alexey_fir...@mentor.com
---
Changes in v3:
- return -ENOSYS from default fb_set_reboot_flag()
Changes in v2:
- return error in default fb_set_reboot_flag()
drivers/usb/gadget/f_fastboot.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/usb/gadget/f_fastboot.c
b/drivers/usb/gadget/f_fastboot.c index 310175a..a000c25 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -122,6 +122,7 @@ static struct usb_gadget_strings
*fastboot_strings[] = { };
static void rx_handler_command(struct usb_ep *ep, struct usb_request
*req); +static int strcmp_l1(const char *s1, const char *s2);
static void fastboot_complete(struct usb_ep *ep, struct usb_request
*req) {
@@ -317,8 +318,20 @@ static void compl_do_reset(struct usb_ep *ep,
struct usb_request *req) do_reset(NULL, 0, 0, NULL);
}
+int __weak fb_set_reboot_flag(void)
+{
+ return -ENOSYS;
+}
+
static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
{
+ char *cmd = req-buf;
+ if (!strcmp_l1(reboot-bootloader, cmd)) {
+ if (fb_set_reboot_flag()) {
+ fastboot_tx_write_str(FAILCannot set reboot
flag);
+ return;
+ }
+ }
fastboot_func-in_req-complete = compl_do_reset;
fastboot_tx_write_str(OKAY);
}
Applied to u-boot-dfu.
Thanks for patch!
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[U-Boot] [PATCH] travis.yml: some adaptions
- adapt to build with eldk-5.4
- add more targets for building with buildman:
- freescale -x arm,m68k,aarch64
- arm1136
- arm1176
- arm720t
- arm920t
- davinci
- kirkwood
Signed-off-by: Heiko Schocher h...@denx.de
---
ti and kirkwood boards show errors, this should be fixed from
the board maintainers, see build here:
https://travis-ci.org/hsdenx/u-boot/builds/53150150
ti boards:
see: https://travis-ci.org/hsdenx/u-boot/jobs/53150166#L466
Building current source for 30 boards (30 threads, 2 jobs per thread)
arm: + am335x_evm_usbspl
+(am335x_evm_usbspl) armv5te-ld.bfd: u-boot-spl section `.rodata' will not fit
in region `.sram'
+(am335x_evm_usbspl) armv5te-ld.bfd: region `.sram' overflowed by 6972 bytes
+(am335x_evm_usbspl) make[2]: *** [spl/u-boot-spl] Error 1
+(am335x_evm_usbspl) make[1]: *** [spl/u-boot-spl] Error 2
+(am335x_evm_usbspl) make: *** [sub-make] Error 2
29 0 1 /30 am335x_evm_nor
The command ${TEST_CMD} exited with 128.
kirkwood boards:
see: https://travis-ci.org/hsdenx/u-boot/jobs/53150172#L466
Building current source for 35 boards (32 threads, 1 job per thread)
arm: + openrd_base
+(openrd_base) u-boot.bin exceeds file size limit:
+(openrd_base) limit: 393216 bytes
+(openrd_base) actual: 411124 bytes
+(openrd_base) excess: 17908 bytes
+(openrd_base) make[1]: *** [u-boot.bin] Error 1
+(openrd_base) make: *** [sub-make] Error 2
arm: + openrd_client
+(openrd_client) u-boot.bin exceeds file size limit:
+(openrd_client) limit: 393216 bytes
+(openrd_client) actual: 411200 bytes
+(openrd_client) excess: 17984 bytes
+(openrd_client) make[1]: *** [u-boot.bin] Error 1
+(openrd_client) make: *** [sub-make] Error 2
arm: + openrd_ultimate
+(openrd_ultimate) u-boot.bin exceeds file size limit:
+(openrd_ultimate) limit: 393216 bytes
+(openrd_ultimate) actual: 411176 bytes
+(openrd_ultimate) excess: 17960 bytes
+(openrd_ultimate) make[1]: *** [u-boot.bin] Error 1
+(openrd_ultimate) make: *** [sub-make] Error 2
32 0 3 /35 sheevaplug
The command ${TEST_CMD} exited with 128.
.travis.yml | 115 ++--
1 file changed, 89 insertions(+), 26 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 923c9dd..1d5c18a 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -10,7 +10,7 @@ cache:
install:
# install U-Boot build dependencies
- - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev
gcc-arm-linux-gnueabi gcc-arm-linux-gnueabihf
+ - sudo apt-get install -qq cppcheck sloccount sparse bc libsdl-dev
build-essential
# install latest device tree compiler
- git clone --depth=1 https://git.kernel.org/pub/scm/utils/dtc/dtc.git
/tmp/dtc
- make -j4 -C /tmp/dtc
@@ -18,11 +18,17 @@ install:
- export BUILDMAN_ROOT=root:
- export BUILDMAN_MIPS=mips:
- export BUILDMAN_PPC=ppc:
- - echo -e [toolchain]\\n${BUILDMAN_ROOT} /\n ~/.buildman
- - echo -e ${BUILDMAN_MIPS}
/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/
~/.buildman
- - echo -e ${BUILDMAN_PPC}
/opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/
~/.buildman
+ - export BUILDMAN_ARM=arm:
+ - export BUILDMAN_SANDBOX=sandbox:
+ - echo -e [toolchain]\n${BUILDMAN_ROOT} /\n ~/.buildman
+ - echo -e ${BUILDMAN_MIPS}
/opt/eldk-5.4/mips/sysroots/i686-eldk-linux/usr/bin/mips32-linux/\n
~/.buildman
+ - echo -e ${BUILDMAN_PPC}
/opt/eldk-5.4/powerpc/sysroots/i686-eldk-linux/usr/bin/powerpc-linux/\n
~/.buildman
+ - echo -e ${BUILDMAN_ARM}
/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi/\n
~/.buildman
+ - echo -e ${BUILDMAN_SANDBOX} /usr/bin/gcc\n ~/.buildman
- export BUILDMAN_ALIAS=x86:
- - echo -e [toolchain-alias]\\n${BUILDMAN_ALIAS} i386 ~/.buildman
+ - export BUILDMAN_ALIAS_ARM=arm:
+ - echo -e \n\n[toolchain-alias]\n${BUILDMAN_ALIAS} i386\n ~/.buildman
+ - echo -e ${BUILDMAN_ALIAS_ARM} armv5te\n ~/.buildman
- cat ~/.buildman
env:
@@ -40,6 +46,10 @@ before_script:
- if [[ ${INSTALL_TOOLCHAIN} == *ppc* ]]; then sh
eldk-eglibc-i686-powerpc-toolchain-gmae-5.4.sh -y ; fi
- if [[ ${INSTALL_TOOLCHAIN} == *mips* ]]; then wget
ftp://ftp.denx.de/pub/eldk/5.4/targets/mips/eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh
; fi
- if [[ ${INSTALL_TOOLCHAIN} == *mips* ]]; then sh
eldk-eglibc-i686-mips-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ ${INSTALL_TOOLCHAIN} == *arm* ]]; then wget
ftp://ftp.denx.de/pub/eldk/5.4/targets/armv5te/eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh
; fi
+ - if [[ ${INSTALL_TOOLCHAIN} == *arm* ]]; then sh
eldk-eglibc-i686-arm-toolchain-gmae-5.4.sh -y ; fi
+ - if [[ ${INSTALL_TOOLCHAIN} == *arm* ]]; then ls -al
/opt/eldk-5.4/armv5te/sysroots/i686-eldk-linux/usr/bin/armv5te-linux-gnueabi ;
fi
+ - if [[ ${INSTALL_TOOLCHAIN} == *i386* ]]; then ./tools/buildman/buildman
sandbox --fetch-arch i386 ; fi
script:
# the execution sequence for each test
@@ -54,19 +64,24 @@ matrix:
# each env setting here is a dedicated build
- env:
- TEST_CMD=./MAKEALL
Re: [U-Boot] [PATCH 3/4] stm32f4: Add serial driver
On Sun, Mar 01, 2015 at 12:44:41PM +0100, Kamil Lulko wrote: Signed-off-by: Kamil Lulko re...@wp.pl Reviewed-by: Tom Rini tr...@konsulko.com -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] stm32f4: Add support for stm32f429-discovery board
On Sun, Mar 01, 2015 at 12:44:42PM +0100, Kamil Lulko wrote: Signed-off-by: Kamil Lulko re...@wp.pl Reviewed-by: Tom Rini tr...@konsulko.com -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
Hi Marek, On 4 March 2015 at 15:22, Marek Vasut ma...@denx.de wrote: Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com --- drivers/spi/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c0b2570..eaf31ed 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -16,3 +16,9 @@ config DESIGNWARE_SPI depends on DM_SPI help Enable the Designware SPI driver. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. Can we get a bit more detail here? What does QSPI mean? What features does it support? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
On Thu, 2015-03-05 at 01:26 -0600, Bansal Aneesh-B39320 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, March 05, 2015 2:41 AM To: Bansal Aneesh-B39320 Cc: u-boot@lists.denx.de; Sun York-R58495; Gupta Ruchika-R66431 Subject: Re: [U-Boot, 1/2, v4] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Where does the 3.5G limitation come from? Even if the physical address needs to be elsewhere due to bootrom constraints, we should be able to map it wherever we want in the TLB once U-Boot takes control. The 3.5G limitation comes from BootROM in case of secure Boot. Initially U-Boot has to run from CPC configured as SRAM with address Within 3.5G. Once U-boot has relocated to DDR, we have removed the Corresponding TLB entry. Again, you could relocate the virtual address of L3 much earlier. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] ARM: Add ARMv7-M support
On Sun, Mar 01, 2015 at 12:44:39PM +0100, Kamil Lulko wrote: Signed-off-by: Kamil Lulko re...@wp.pl [snip] diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S [snip] @@ -66,15 +69,30 @@ ENTRY(_main) #else ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif +#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ + mov r3, sp + bic r3, r3, #7 + mov sp, r3 +#else bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ +#endif There's 4 places where this change comes in. Albert, what do you think about always just doing this in 3 instructions with a comment in the first instance about v7-M support? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
On Thursday, March 05, 2015 at 04:58:19 PM, Simon Glass wrote: Hi Marek, On 4 March 2015 at 15:22, Marek Vasut ma...@denx.de wrote: Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com --- drivers/spi/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c0b2570..eaf31ed 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -16,3 +16,9 @@ config DESIGNWARE_SPI depends on DM_SPI help Enable the Designware SPI driver. + +config CADENCE_QSPI + bool Cadence QSPI driver + depends on DM_SPI + help + Enable the Cadence QSPI driver. Can we get a bit more detail here? What does QSPI mean? What features does it support? Stefan ? ;-) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] usb_storage : scan all interfaces to find a storage device
On Wednesday, March 04, 2015 at 09:07:00 PM, franck.jull...@gmail.com wrote: From: Franck Jullien franck.jull...@gmail.com Mass storage is not necessary present on interface 0. This patch allow usb_stor_scan to look in every available interface. Signed-off-by: Franck Jullien franck.jull...@gmail.com Thanks! Acked-by: Marek Vasut ma...@denx.de Are you OK if I apply this for -next (that is, after 2015.04 is out) ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: pxa: introducing cpuinfo display for marvell pxa270m
On Wednesday, March 04, 2015 at 02:57:31 PM, Marcel Ziswiler wrote: According to table 2-3 on page 87 of Marvell's latest PXA270 Specification Update Rev. I from 2010.04.19 [1] there exists a breed of chips with a new CPU ID for PXA270M A1 stepping which our latest Colibri PXA270 V2.4A modules actually have assembled. This patch helps in correctly identifying those chips upon boot as well which then looks as follows: CPU: Marvell PXA27xM rev. A1 Acked-by: Marek Vasut ma...@denx.de Tom, can you please pick this directly for current ? Or do you want me to cook you a PXA PR with one patch? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] Please pull u-boot-imx
On Thu, Mar 05, 2015 at 10:45:43AM +0100, Stefano Babic wrote: Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit 1606b34aa50804227806971dbb6b82ea0bf81f55: Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq (2015-02-25 18:14:18 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 32df39c741788e8637cffe6633d73594b26d70fb: mx5: fix get_reset_cause (2015-03-05 10:29:27 +0100) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl_sec.h: Fix thinko
On Thu, Mar 05, 2015 at 08:58:27AM -0500, Tom Rini wrote: In 0200020 we added a number of tests for 'if defined(CONFIG_SYS_FSL_SEC_LE) !defined(CONFIG_MX6)' and accidentally did one as 'ifdef defined...' Signed-off-by: Tom Rini tr...@konsulko.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fsl_sec.h: Fix thinko
In 0200020 we added a number of tests for 'if
defined(CONFIG_SYS_FSL_SEC_LE) !defined(CONFIG_MX6)' and
accidentally did one as 'ifdef defined...'
Signed-off-by: Tom Rini tr...@konsulko.com
---
include/fsl_sec.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index dbfae68..ebb1ac6 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -180,7 +180,7 @@ struct jr_regs {
* related information
*/
struct sg_entry {
-#ifdef defined(CONFIG_SYS_FSL_SEC_LE) !defined(CONFIG_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) !defined(CONFIG_MX6)
uint32_t addr_lo; /* Memory Address - lo */
uint16_t addr_hi; /* Memory Address of start of buffer - hi */
uint16_t reserved_zero;
--
1.7.9.5
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Re: [U-Boot] [PATCH v3] usb_storage : scan all interfaces to find a storage device
2015-03-05 14:52 GMT+01:00 Marek Vasut ma...@denx.de: On Wednesday, March 04, 2015 at 09:07:00 PM, franck.jull...@gmail.com wrote: From: Franck Jullien franck.jull...@gmail.com Mass storage is not necessary present on interface 0. This patch allow usb_stor_scan to look in every available interface. Signed-off-by: Franck Jullien franck.jull...@gmail.com Thanks! Acked-by: Marek Vasut ma...@denx.de Are you OK if I apply this for -next (that is, after 2015.04 is out) ? Best regards, Marek Vasut Sure, there is no hurry. Franck. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] flea3: Convert to generic board
Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal from the project. Signed-off-by: Stefano Babic sba...@denx.de --- include/configs/flea3.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/flea3.h b/include/configs/flea3.h index bf02829..6604238 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -22,6 +22,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_GENERIC_BOARD /* Only in case the value is not present in mach-types.h */ #ifndef MACH_TYPE_FLEA3 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] woodburn: Convert to generic board
Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal from the project. Signed-off-by: Stefano Babic sba...@denx.de --- include/configs/woodburn_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index c7a17f7..86fcd14 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_GENERIC_BOARD /* Only in case the value is not present in mach-types.h */ #ifndef MACH_TYPE_FLEA3 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] mx35pdk: Convert to generic board
Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal from the project. Signed-off-by: Stefano Babic sba...@denx.de --- include/configs/mx35pdk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index a145f08..6a41093 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -19,6 +19,7 @@ #define CONFIG_MX35 #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_GENERIC_BOARD /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA000 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry
On 04.03.2015 23:22, Marek Vasut wrote: Add Cadence QSPI controller Kconfig entry. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@opensource.altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Pavel Machek pa...@denx.de Cc: Simon Glass s...@chromium.org Cc: Stefan Roese s...@denx.de Cc: Tom Rini tr...@konsulko.com Cc: Vince Bridgers vbrid...@opensource.altera.com Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
