[U-Boot] [U-Boot 3/7] dts: zynq: Add zynq spi controller nodes
This patch adds zynq spi controller nodes in zynq-7000.dtsi.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-7000.dtsi | 24
doc/device-tree-bindings/spi/spi-zynq.txt | 27 +++
2 files changed, 51 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/spi-zynq.txt
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 2d076f1..f66f8dc 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -109,6 +109,30 @@
interrupts = 0 50 4;
};
+ spi0: spi@e0006000 {
+ compatible = xlnx,zynq-spi;
+ reg = 0xe0006000 0x1000;
+ status = disabled;
+ interrupt-parent = intc;
+ interrupts = 0 26 4;
+ clocks = clkc 25, clkc 34;
+ clock-names = ref_clk, pclk;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ spi1: spi@e0007000 {
+ compatible = xlnx,zynq-spi;
+ reg = 0xe0007000 0x1000;
+ status = disabled;
+ interrupt-parent = intc;
+ interrupts = 0 49 4;
+ clocks = clkc 26, clkc 35;
+ clock-names = ref_clk, pclk;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
gem0: ethernet@e000b000 {
compatible = cdns,gem;
reg = 0xe000b000 0x4000;
diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt
b/doc/device-tree-bindings/spi/spi-zynq.txt
new file mode 100644
index 000..a7c2757
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -0,0 +1,27 @@
+Zynq SPI controller Device Tree Bindings
+
+
+Required properties:
+- compatible : Should be xlnx,spi-zynq.
+- reg : Physical base address and size of SPI registers map.
+- status : Status will be disabled in dtsi and enabled in
required dts.
+- interrupt-parent : Must be core interrupt controller.
+- interrupts : Property with a value describing the interrupt
+ number.
+- clocks : Clock phandles (see clock bindings for details).
+- clock-names : List of input clock names - ref_clk, pclk
+ (See clock bindings for details).
+
+Example:
+
+ spi@e0006000 {
+ compatible = xlnx,zynq-spi;
+ reg = 0xe0006000 0x1000;
+ status = disabled;
+ interrupt-parent = intc;
+ interrupts = 0 26 4;
+ clocks = clkc 25, clkc 34;
+ clock-names = ref_clk, pclk;
+ #address-cells = 1;
+ #size-cells = 0;
+ } ;
--
1.9.1
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[U-Boot] [U-Boot 2/7] zynq: Kconfig: Enable dm spi and spi_flash
Enabled CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH for zynq soc. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Simon Glass s...@chromium.org Cc: Michal Simek michal.si...@xilinx.com Cc: Siva Durga Prasad Paladugu siva...@xilinx.com --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3702bb0..40f1186 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -670,6 +670,8 @@ config ZYNQ select CPU_V7 select SUPPORT_SPL select DM + select DM_SPI + select DM_SPI_FLASH config TARGET_XILINX_ZYNQMP bool Support Xilinx ZynqMP Platform -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] mx6cuboxi: Differentiate Cubox-i and Hummingboard
Hi Fabio, guys,
On 04/23/2015 06:57 AM, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Introduce is_hummingboard() function that reads GPIOs that can distinguish
between Cubox-i and Hummingboard.
Print the board name accordingly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/solidrun/mx6cuboxi/mx6cuboxi.c | 41 +++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 1f240ae..83410b2 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -71,6 +71,12 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
+static iomux_v3_cfg_t const hb_cbi_sense[] = {
+ /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
static void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
@@ -167,9 +173,42 @@ int board_init(void)
return 0;
}
+static bool is_hummingboard(void)
+{
+ int val1, val2;
+
+ SETUP_IOMUX_PADS(hb_cbi_sense);
+
+ gpio_direction_input(IMX_GPIO_NR(4, 9));
+ gpio_direction_input(IMX_GPIO_NR(3, 4));
+
+ val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
+ val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
+
+ /*
+* Machine selection -
+* Machineval1, val2
+* -
+* HB rev 3.x x 0
+* CBi0 1
+* HB 1 1
+*/
+
+ if (val2 == 0)
+ return true;
+ else if (val1 == 0)
+ return false;
+ else
+ return true;
+}
As more and more board variants are supported by unified source files,
functions like is_specificboard() are not scaling well - there's a
repetitive code for extracting hw-specific info, and then there's the
multiple functions that return true/false for each board variant.
Here's one proposal how this can be simplified a bit:
typedef enum
{
BOARD_ALPHA,
BOARD_BRAVO,
BOARD_CHARLIE,
} model_t;
/* Can be also named is_board_variant() or something like this */
static bool is_board_model(model_t m)
{
/* ... Extract HW info */
switch (m)
{
case BOARD_ALPHA:
if (check for this board model)
return true;
break;
/* do same for the other board models */
/* ... */
}
return false;
}
Not sure whether such code can be shared between different boards, but
can be a step towards unifying the handling of board models/variants.
I'm perfectly fine with Fabio's code here, just using the occasion to
share my idea.
+
int checkboard(void)
{
- puts(Board: MX6 Hummingboard\n);
+ if (is_hummingboard())
+ puts(Board: MX6 Hummingboard\n);
+ else
+ puts(Board: MX6 Cubox-i\n);
+
return 0;
}
Kind regards,
Nikolay
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Re: [U-Boot] [PATCH v4 9/9] sandbox: add config_distro_defaults and config_distro_bootcmd
Hi, On 21 April 2015 at 02:13, Sjoerd Simons sjoerd.sim...@collabora.co.uk wrote: Hey Joe, On Mon, 2015-04-20 at 23:31 -0500, Joe Hershberger wrote: Hi Sjoerd, On Mon, Apr 13, 2015 at 3:54 PM, Sjoerd Simons sjoerd.sim...@collabora.co.uk wrote: Make the sandbox setup more generic/examplary by including config_distro_defaults.h and config_distro_bootcmd.h. Among other things this makes it easy to test whether images will boot though with the standard distro bootcmds by running e.g: u-boot -c 'host bind 0 myimage.img ; boot' By default there are 2 target host devices to emulate device with multiple storage devices (e.g. internal (host 0) and external (host 1) and verify that the prioritization and fallbacks do work correctly. Signed-off-by: Sjoerd Simons sjoerd.sim...@collabora.co.uk Reviewed by: Simon Glass s...@chromium.org Acked-by: Simon Glass s...@chromium.org For me this has broken the build of the env target. I get this following error: In file included from /home/joe/u-boot/tools/env/fw_env.c:117: /usr/include/search.h:173: error: expected } before BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX make[2]: *** [tools/env/fw_env.o] Error 1 make[1]: *** [env] Error 2 make: *** [sub-make] Error 2 I haven't looked closely at the header you've added. Any quick thoughts about what's going on? Hrm, the problem seems to be that when running make env CONFIG_SANDBOX isn't defined, so you get the error triggered above. Essentially that error is trying to tell you - You're trying to build a config which will cause your boot environment to have commands not supported by this build.. I haven't dug out what exactly causes this difference in definitions but it does make me wonder whether we should trigger on something more conventional like CONFIG_CMD_HOST (similar to e.g. CONFIG_CMD_MMC) rather then CONFIG_SANDBOX That sounds reasonable. Also I think it would be good to add a flag to enable the distro boot feature. At present I always get the bootdelay message and then an error: U-Boot 2015.04-00423-g183ad88 (Apr 23 2015 - 09:05:12) DRAM: 128 MiB Using default environment In:serial Out: lcd Err: lcd Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 Not bound to a backing file Not bound to a backing file I did a similar thing with LCD since it was similarly invasive. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
Hi Albert, On 8 April 2015 at 00:12, Albert ARIBAUD albert.arib...@3adev.fr wrote: Hi Simon, Le Tue, 7 Apr 2015 21:20:22 -0600, Simon Glass s...@chromium.org a écrit : Well the problem is that we don't have driver model support in rtc, We do have an eeprom uclass, but it is currently implemented only for sandbox. We don't have a hwmon uclass (although there is thermal, and I wonder if that is similar? No idea. :/ I'd be willing to create an rtc uclass and convert over ds1374 if you are happy to test it? I can test ds1374 right now, but that is not a hardware that I can keep. I should be able to test eeprom on some other HW which I own. I posted an RTC conversion series. Are you still able to test ds1374? Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot 6/7] dm: spi: xilinx_spi: Convert to driver model
This converts the xilinx spi driver to use the driver model.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
---
Note: Michal, can you test this, I don't have hardware.
drivers/spi/xilinx_spi.c | 212 +++
1 file changed, 124 insertions(+), 88 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 3803c4c..4acade4 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -4,6 +4,7 @@
* Supports 8 bit SPI transfers only, with or w/o FIFO
*
* Based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2015 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
* Copyright (c) 2012 Stephan Linz l...@li-pro.net
* Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
* Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
@@ -14,6 +15,8 @@
#include config.h
#include common.h
+#include dm.h
+#include errno.h
#include malloc.h
#include spi.h
@@ -79,7 +82,7 @@
#endif
/* xilinx spi register set */
-struct xilinx_spi_reg {
+struct xilinx_spi_regs {
u32 __space0__[7];
u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
u32 ipisr; /* IP Interrupt Status Register (IPISR) */
@@ -97,113 +100,76 @@ struct xilinx_spi_reg {
u32 spirfor;/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
};
-/* xilinx spi slave */
-struct xilinx_spi_slave {
- struct spi_slave slave;
- struct xilinx_spi_reg *regs;
+/* xilinx spi priv */
+struct xilinx_spi_priv {
+ struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+ unsigned int cs;
};
-static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
- struct spi_slave *slave)
-{
- return container_of(slave, struct xilinx_spi_slave, slave);
-}
-
static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int xilinx_spi_probe(struct udevice *bus)
{
- return bus ARRAY_SIZE(xilinx_spi_base_list) cs 32;
-}
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ priv-regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus-seq];
+ priv-cs = spi_chip_select(bus);
- writel(SPISSR_ACT(slave-cs), xilspi-regs-spissr);
-}
+ writel(SPISSR_RESET_VALUE, regs-srr);
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
-
- writel(SPISSR_OFF, xilspi-regs-spissr);
-}
-
-void spi_init(void)
-{
- /* do nothing */
+ return 0;
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static void spi_cs_activate(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi;
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf(XILSPI error: unsupported bus %d / cs %d\n, bus, cs);
- return NULL;
- }
-
- xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
- if (!xilspi) {
- printf(XILSPI error: malloc of SPI structure failed\n);
- return NULL;
- }
- xilspi-regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
- xilspi-freq = max_hz;
- xilspi-mode = mode;
- debug(spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n,
- bus, cs, xilspi-regs, xilspi-mode, xilspi-freq);
-
- writel(SPISSR_RESET_VALUE, xilspi-regs-srr);
+ struct udevice *bus = dev-parent;
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- return xilspi-slave;
+ writel(SPISSR_ACT(priv-cs), regs-spissr);
}
-void spi_free_slave(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ struct udevice *bus = dev-parent;
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- free(xilspi);
+ writel(SPISSR_OFF, regs-spissr);
}
-int spi_claim_bus(struct spi_slave *slave)
+static int xilinx_spi_claim_bus(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
- u32 spicr;
+ struct udevice *bus = dev-parent;
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- debug(spi_claim_bus: bus:%i cs:%i\n, slave-bus, slave-cs);
- writel(SPISSR_OFF, xilspi-regs-spissr);
+ writel(SPISSR_OFF, regs-spissr);
+ writel(XILSPI_SPICR_DFLT_ON,
Re: [U-Boot] [PATCH] net/phy: refactor RTL8211F initialization
On Thu, Apr 23, 2015 at 12:58 AM, shengzhou@freescale.com shengzhou@freescale.com wrote: -Original Message- From: Florian Fainelli [mailto:f.faine...@gmail.com] Sent: Thursday, April 23, 2015 12:39 PM To: Liu Shengzhou-B36685; net...@vger.kernel.org; joe.hershber...@gmail.com Subject: Re: [PATCH] net/phy: refactor RTL8211F initialization Did you mean to submit that against u-boot or Linux? If the latter, there is absolutely no need to have the same file compile under u-boot and Linux without changes, that is too restrictive. There is a genphy_soft_reset() which takes care of waiting for BMCR_RESET to clear, please use it, there is no guarantee otherwise that a PHY has completed a reset. -- Florian This patch is for u-boot, not for kernel. There is no genphy_soft_reset() in u-boot. You sent this patch to the netdev list and not the u-boot list. I've added the u-boot list here, but you should send v2 to the u-boot list. Thanks, -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [dm/next PATCH v1] dm: qspi fix claim bus and release bus
Hi Peng,
On 15 April 2015 at 03:50, Peng Fan peng@freescale.com wrote:
Add missed people.
On 4/14/2015 1:19 PM, Peng Fan wrote:
For fsl_qspi_claim_bus and fsl_qspi_release_bus, the input parameter
struct udevice *dev represents device: qspi[x]: qspi@[address] {...}.
Since dev already represents the qspi controller, use its parent to
get platdata and get 'priv' is wrong.
After applying this patch, qspi flashes can be correctly probed.
Is this patch still needed after this patch?
http://patchwork.ozlabs.org/patch/462595/
CC: Simon Glass s...@chromium.org
CC: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
CC: Haikun Wang haikun.w...@freescale.com
Signed-off-by: Peng Fan peng@freescale.com
---
Hi,
This patch is based on dm/next branch.
Regards,
Peng.
drivers/spi/fsl_qspi.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 868df5f..04f1801 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1044,11 +1044,9 @@ static int fsl_qspi_xfer(struct udevice *dev,
unsigned int bitlen,
static int fsl_qspi_claim_bus(struct udevice *dev)
{
struct fsl_qspi_priv *priv;
- struct udevice *bus;
- struct dm_spi_slave_platdata *slave_plat =
dev_get_parent_platdata(dev);
+ struct dm_spi_slave_platdata *slave_plat = dev_get_platdata(dev);
- bus = dev-parent;
- priv = dev_get_priv(bus);
+ priv = dev_get_priv(dev);
priv-cur_amba_base =
priv-amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat-cs;
@@ -1061,10 +1059,8 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
static int fsl_qspi_release_bus(struct udevice *dev)
{
struct fsl_qspi_priv *priv;
- struct udevice *bus;
- bus = dev-parent;
- priv = dev_get_priv(bus);
+ priv = dev_get_priv(dev);
qspi_module_disable(priv, 1);
Regards,
Simon
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Re: [U-Boot] [PATCH 4/5] mx6cuboxi: Differentiate Cubox-i and Hummingboard
Hi Nikolay,
On 23/04/2015 16:38, Nikolay Dimitrov wrote:
As more and more board variants are supported by unified source files,
functions like is_specificboard() are not scaling well - there's a
repetitive code for extracting hw-specific info, and then there's the
multiple functions that return true/false for each board variant.
ok - let's see what we can do. I have not thinking about it, because how
to get model / version is quite always very specific. Some boards as
this one are reading GPIOs, some other are reading from I2C / SPI, some
other ones check if some hardware is present.
Here's one proposal how this can be simplified a bit:
typedef enum
{
BOARD_ALPHA,
BOARD_BRAVO,
BOARD_CHARLIE,
} model_t;
/* Can be also named is_board_variant() or something like this */
static bool is_board_model(model_t m)
{
/* ... Extract HW info */
switch (m)
{
case BOARD_ALPHA:
if (check for this board model)
return true;
The check must be done in board code, because only the board knows the
details.
break;
/* do same for the other board models */
/* ... */
}
return false;
}
Not sure whether such code can be shared between different boards, but
can be a step towards unifying the handling of board models/variants.
Trying to get further and see if we can factorize it. Maybe not a lot.
We can also think that is_board_model() becomes get_board_model(), or we
generalize what was done in tqma6 with a sort of get_board_name().
Maybe we can factorize just a few code, but at least we could provide a
standard method without having all boards doing the same in different way.
I'm perfectly fine with Fabio's code here, just using the occasion to
share my idea.
Thanks - by sharing ideas we can improve code !
Best regards,
Stefano
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[U-Boot] [U-Boot 1/7] dm: spi: zynq_spi: Convert to driver model
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz - frequency
- req_hz - freq
- base - regs
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
Note: Siva Durga Prasad, can you test this on zc770_xm010
drivers/spi/zynq_spi.c | 305 +
1 file changed, 181 insertions(+), 124 deletions(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index ff1ec6a..62edbbe 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2013 Inc.
+ * (C) Copyright 2015 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
*
* Xilinx Zynq PS SPI controller driver (master mode only)
*
@@ -8,6 +9,8 @@
#include config.h
#include common.h
+#include dm.h
+#include errno.h
#include malloc.h
#include spi.h
#include asm/io.h
@@ -44,180 +47,142 @@ struct zynq_spi_regs {
u32 rxdr; /* 0x20 */
};
-/* zynq spi slave */
-struct zynq_spi_slave {
- struct spi_slave slave;
- struct zynq_spi_regs *base;
- u8 mode;
- u8 fifo_depth;
+
+/* zynq spi platform data */
+struct zynq_spi_platdata {
+ struct zynq_spi_regs *regs;
+ u32 frequency; /* input frequency */
u32 speed_hz;
- u32 input_hz;
- u32 req_hz;
};
-static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct zynq_spi_slave, slave);
-}
+/* zynq spi priv */
+struct zynq_spi_priv {
+ struct zynq_spi_regs *regs;
+ u8 cs;
+ u8 mode;
+ u8 fifo_depth;
+ u32 freq; /* required frequency */
+};
-static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
+static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
{
- if (dev)
+ if (bus-seq)
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
else
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
}
-static void zynq_spi_init_hw(struct zynq_spi_slave *zslave)
+static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct zynq_spi_platdata *plat = bus-platdata;
+
+ plat-regs = get_zynq_spi_regs(bus);
+ plat-frequency = 16700;
+ plat-speed_hz = plat-frequency / 2;
+
+ return 0;
+}
+
+static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
{
+ struct zynq_spi_regs *regs = priv-regs;
u32 confr;
/* Disable SPI */
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, zslave-base-enr);
+ writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, regs-enr);
/* Disable Interrupts */
- writel(ZYNQ_SPI_IXR_ALL_MASK, zslave-base-idr);
+ writel(ZYNQ_SPI_IXR_ALL_MASK, regs-idr);
/* Clear RX FIFO */
- while (readl(zslave-base-isr)
+ while (readl(regs-isr)
ZYNQ_SPI_IXR_RXNEMPTY_MASK)
- readl(zslave-base-rxdr);
+ readl(regs-rxdr);
/* Clear Interrupts */
- writel(ZYNQ_SPI_IXR_ALL_MASK, zslave-base-isr);
+ writel(ZYNQ_SPI_IXR_ALL_MASK, regs-isr);
/* Manual slave select and Auto start */
confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
ZYNQ_SPI_CR_MSTREN_MASK;
confr = ~ZYNQ_SPI_CR_MSA_MASK;
- writel(confr, zslave-base-cr);
+ writel(confr, regs-cr);
/* Enable SPI */
- writel(ZYNQ_SPI_ENR_SPI_EN_MASK, zslave-base-enr);
+ writel(ZYNQ_SPI_ENR_SPI_EN_MASK, regs-enr);
}
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int zynq_spi_probe(struct udevice *bus)
{
- /* 2 bus with 3 chipselect */
- return bus 2 cs 3;
+ struct zynq_spi_platdata *plat = dev_get_platdata(bus);
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+
+ priv-regs = plat-regs;
+ priv-cs = spi_chip_select(bus);
+ priv-fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
+
+ /* init the zynq spi hw */
+ zynq_spi_init_hw(priv);
+
+ return 0;
}
-void spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
+ struct udevice *bus = dev-parent;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv-regs;
u32 cr;
- debug(spi_cs_activate: 0x%08x\n, (u32)slave);
-
- clrbits_le32(zslave-base-cr, ZYNQ_SPI_CR_CS_MASK);
- cr = readl(zslave-base-cr);
+ clrbits_le32(regs-cr, ZYNQ_SPI_CR_CS_MASK);
+ cr = readl(regs-cr);
/*
* CS cal logic: CS[13:10]
* xxx0 - cs0
* xx01 - cs1
* x011 - cs2
*/
- cr |= (~(0x1 slave-cs) 10)
[U-Boot] [U-Boot 7/7] spi: xilinx_spi: Add asm/io.h include file
This patch includes asm/io.h for readl and writel calls. build errors: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe': drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration] drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Michal Simek michal.si...@xilinx.com --- drivers/spi/xilinx_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 4acade4..e9ff804 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -19,6 +19,7 @@ #include errno.h #include malloc.h #include spi.h +#include asm/io.h /* * [0]: http://www.xilinx.com/support/documentation -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot 5/7] dts: zynq: Enable spi1 for zc770_xm010 board
This patch enables spi1 for zynq zc770_xm010 board dts.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-zc770-xm010.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts
b/arch/arm/dts/zynq-zc770-xm010.dts
index 5e66174..e793a61 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -21,3 +21,7 @@
reg = 0 0x4000;
};
};
+
+spi1 {
+ status = okay;
+};
--
1.9.1
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Re: [U-Boot] [PATCH v4] powerpc/t1023rdb: Add T1023 RDB board support
+Masahiro Yamada On 04/23/2015 01:27 AM, Liu Shengzhou-B36685 wrote: -Original Message- From: Sun York-R58495 Sent: Friday, April 17, 2015 3:22 AM To: Liu Shengzhou-B36685; u-boot@lists.denx.de Subject: Re: [PATCH v4] powerpc/t1023rdb: Add T1023 RDB board support On 03/27/2015 12:48 AM, Shengzhou Liu wrote: T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. +++ b/configs/T1023RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y Please do not use CONFIG_SYS_EXTRA_OPTIONS for new boards. York I noted config SYS_EXTRA_OPTIONS string Extra Options (DEPRECATED) in Kconfig. But we still have to use the CONFIG_SYS_EXTRA_OPTIONS in current configuration Infrastructure, unless a newer approach is available in future. Because there are some something like 'SPL_FSL_PBL', 'NAND', 'SPIFLASH''SDCARD' which must be defined dynamically during build u-boot for various boot-mode in those *_defconfig files instead of in static include/config.h I was thinking to use select in Kconfig. But as you said, there are some macros not standardized. Maybe it is too early to enforce that. Let's hear from Masahiro. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations
Hi Stefano,
On 04/22/2015 05:02 PM, Stefano Babic wrote:
Hi Nikolay,
On 22/04/2015 14:22, Nikolay Dimitrov wrote:
Hi Stefano,
On 04/22/2015 03:12 PM, Stefano Babic wrote:
Hi Nikolay,
On 17/04/2015 00:36, Nikolay Dimitrov wrote:
This is proposal for clamping the MMDC/DDR3 clocks to the maximum
supported
frequencies as per imx6 SOC models, and for dynamically calculating
valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600
MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
doesn't take into account DDR3 memory limitations.
Signed-off-by: Nikolay Dimitrov picmas...@mail.bg
Cc: Fabio Estevam feste...@gmail.com
Cc: Stefano Babic sba...@denx.de
Cc: Tim Harvey thar...@gateworks.com
Cc: Eric Nelson eric.nel...@boundarydevices.com
---
arch/arm/cpu/armv7/mx6/ddr.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index fef2231..9daa180 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -265,7 +265,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
*sysinfo,
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
u8 coladdr;
int clkper; /* clock period in picoseconds */
-int clock; /* clock freq in mHz */
+int clock; /* clock freq in MHz */
int cs;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
@@ -273,16 +273,31 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo
*sysinfo,
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
#endif
-/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+/* Limit mem_speed for MX6D/MX6Q */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
-clock = 528;
+if (ddr3_cfg-mem_speed 1066)
+ddr3_cfg-mem_speed = 1066; /* 1066 MT/s */
+
Sorry, but there is an issue. Parameters are const struct *, and you are
setting value here.
By testing I get on most mx6 boards:
+arch/arm/cpu/armv7/mx6/ddr.c: In function 'mx6_dram_cfg':
+arch/arm/cpu/armv7/mx6/ddr.c:279:4: error: assignment of member
'mem_speed' in read-only object
+arch/arm/cpu/armv7/mx6/ddr.c:286:4: error: assignment of member
'mem_speed' in read-only object
+make[4]: *** [spl/arch/arm/cpu/armv7/mx6/ddr.o] Error 1
Sorry for the stupid mistake, I've already sent v2.
Regards,
Nikolay
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[U-Boot] [PATCH 1/4] x86: baytrail: fix the GPIOBASE address
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] x86: support of pin-muxing from device tree
This serie of patches adds the support of pin-muxing from the device tree through different properties. I have put two example to enable the USB Host on the minnowboard max. The support of the call to 'setup_pch_gpios' is still supported and only the minnowboard has been tested with the device tree implementation. Because the GPIO and IO base register ares different, I have also defined some proxy function to set the function/value and direction of the GPIO as the GPIO register can override some registers in the IO. Gabriel Huau (4): x86: baytrail: fix the GPIOBASE address x86: minnowmax: add GPIO banks in the device tree x86: gpio: add pinctrl support from the device tree x86: minnowmax: initialize the pin-muxing from device tree arch/x86/dts/minnowmax.dts| 63 + arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- arch/x86/include/asm/gpio.h | 1 + board/intel/minnowmax/minnowmax.c | 9 ++ drivers/gpio/intel_ich6_gpio.c| 222 ++ include/configs/minnowmax.h | 1 + include/dt-bindings/gpio/gpio.h | 20 +++ 7 files changed, 292 insertions(+), 27 deletions(-) -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
There is 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 8f34369..c73e421 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -21,6 +21,48 @@
silent_console = 0;
};
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x20;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x20 0x20;
+ bank-name = B;
+ };
+
+ gpioc {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x40 0x20;
+ bank-name = C;
+ };
+
+ gpiod {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x60 0x20;
+ bank-name = D;
+ };
+
+ gpioe {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x80 0x20;
+ bank-name = E;
+ };
+
+ gpiof {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0xA0 0x20;
+ bank-name = F;
+ };
+
chosen {
stdout-path = /serial;
};
--
2.1.4
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Re: [U-Boot] [PATCH 02/20] dm: i2c: sandbox: Add debugging to the speed limit
Hi Heiko,
On 20 April 2015 at 23:04, Heiko Schocher h...@denx.de wrote:
Hello Simon,
Am 20.04.2015 20:37, schrieb Simon Glass:
Print a debug() message with the I2C speed is exceeded.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/i2c/sandbox_i2c.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c
index d6adc0f..621caec 100644
--- a/drivers/i2c/sandbox_i2c.c
+++ b/drivers/i2c/sandbox_i2c.c
@@ -73,8 +73,10 @@ static int sandbox_i2c_xfer(struct udevice *bus, struct
i2c_msg *msg,
* 400KHz for reads
*/
is_read = nmsgs 1;
- if (i2c-speed_hz (is_read ? 40 : 10))
+ if (i2c-speed_hz (is_read ? 40 : 10)) {
+ debug(%s: Max speed exceeded\n, __func__);
return -EINVAL;
+ }
Why different speeds for reading/writing?
This is just test code - in fact a later patch adds a flag to enable
it only when running tests. See test/dm/i2c.c.
Regards,
Simon
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[U-Boot] [U-Boot PATCH v2] Revert spi: add config option to enable the WP pin function on st micron flashes
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Note: Even un-reverting this patch couldn't works as expected, based
on the latest testing from Heiko Schocher.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Heiko Schocher h...@denx.de
---
README| 11 ---
drivers/mtd/spi/sf_internal.h | 4
drivers/mtd/spi/sf_probe.c| 30 --
3 files changed, 45 deletions(-)
diff --git a/README b/README
index fc1fd52..82224f7 100644
--- a/README
+++ b/README
@@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections.
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
- SystemACE Support:
CONFIG_SYSTEMACE
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a9..bd834dc 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -97,10 +97,6 @@ enum {
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD(1 7) /* SR write protect */
-#endif
-
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 2ee228d..de8d0b7 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -288,34 +288,6 @@ int spi_flash_decode_fdt(const void *blob, struct
spi_flash *flash)
}
#endif /* CONFIG_OF_CONTROL */
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- u8 status;
- int ret;
-
- ret = spi_flash_cmd_read_status(flash, status);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_disable(flash);
- if (ret 0)
- return ret;
-
- return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- return 0;
-}
-#endif
-
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
@@ -394,8 +366,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct
spi_flash *flash)
puts( Full access #define CONFIG_SPI_FLASH_BAR\n);
}
#endif
- if (spi_enable_wp_pin(flash))
- puts(Enable WP pin failed\n);
/* Release spi bus */
spi_release_bus(spi);
--
1.9.1
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[U-Boot] [PATCH] x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
include/configs/minnowmax.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
2.1.4
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[U-Boot] [U-Boot 4/7] spi: zynq_spi: Add fdt support in driver
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying okay on respective board dts to use
the devicetree generated platdata.
Ex:
spi1 {
status = okay;
};
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-7000.dtsi | 2 ++
arch/arm/include/asm/arch-zynq/hardware.h | 2 --
doc/device-tree-bindings/spi/spi-zynq.txt | 2 ++
drivers/spi/zynq_spi.c| 23 +--
4 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index f66f8dc..9207159 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -117,6 +117,7 @@
interrupts = 0 26 4;
clocks = clkc 25, clkc 34;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
};
@@ -129,6 +130,7 @@
interrupts = 0 49 4;
clocks = clkc 26, clkc 35;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
};
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index e2e0b73..df9b06b 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -19,8 +19,6 @@
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
-#define ZYNQ_SPI_BASEADDR0 0xE0006000
-#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
#define ZYNQ_SMC_BASEADDR 0xE000E000
#define ZYNQ_NAND_BASEADDR 0xE100
diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt
b/doc/device-tree-bindings/spi/spi-zynq.txt
index a7c2757..f397a36 100644
--- a/doc/device-tree-bindings/spi/spi-zynq.txt
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -11,6 +11,7 @@ Required properties:
- clocks : Clock phandles (see clock bindings for details).
- clock-names : List of input clock names - ref_clk, pclk
(See clock bindings for details).
+- spi-max-frequency: Maximum SPI clocking speed of device in Hz
Example:
@@ -22,6 +23,7 @@ Example:
interrupts = 0 26 4;
clocks = clkc 25, clkc 34;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
} ;
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 62edbbe..df4a99e 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -13,9 +13,12 @@
#include errno.h
#include malloc.h
#include spi.h
+#include fdtdec.h
#include asm/io.h
#include asm/arch/hardware.h
+DECLARE_GLOBAL_DATA_PTR;
+
/* zynq spi register bit masks ZYNQ_SPI_REG_BIT_MASK */
#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
@@ -64,22 +67,22 @@ struct zynq_spi_priv {
u32 freq; /* required frequency */
};
-static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
-{
- if (bus-seq)
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
- else
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
-}
-
static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
{
struct zynq_spi_platdata *plat = bus-platdata;
+ const void *blob = gd-fdt_blob;
+ int node = bus-of_offset;
+
+ plat-regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node, reg);
- plat-regs = get_zynq_spi_regs(bus);
- plat-frequency = 16700;
+ /* FIXME: Use 250MHz as a suitable default */
+ plat-frequency = fdtdec_get_int(blob, node, spi-max-frequency,
+ 25000);
plat-speed_hz = plat-frequency / 2;
+ debug(zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n,
+ plat-regs, plat-frequency);
+
return 0;
}
--
1.9.1
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Re: [U-Boot] [U-Boot PATCH v2] Revert spi: add config option to enable the WP pin function on st micron flashes
On 23 April 2015 at 19:57, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Note: Even un-reverting this patch couldn't works as expected, based
on the latest testing from Heiko Schocher.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Heiko Schocher h...@denx.de
---
README| 11 ---
drivers/mtd/spi/sf_internal.h | 4
drivers/mtd/spi/sf_probe.c| 30 --
3 files changed, 45 deletions(-)
diff --git a/README b/README
index fc1fd52..82224f7 100644
--- a/README
+++ b/README
@@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections.
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS
REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
- SystemACE Support:
CONFIG_SYSTEMACE
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a9..bd834dc 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -97,10 +97,6 @@ enum {
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD(1 7) /* SR write protect */
-#endif
-
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 2ee228d..de8d0b7 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -288,34 +288,6 @@ int spi_flash_decode_fdt(const void *blob, struct
spi_flash *flash)
}
#endif /* CONFIG_OF_CONTROL */
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- u8 status;
- int ret;
-
- ret = spi_flash_cmd_read_status(flash, status);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_disable(flash);
- if (ret 0)
- return ret;
-
- return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- return 0;
-}
-#endif
-
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
@@ -394,8 +366,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct
spi_flash *flash)
puts( Full access #define CONFIG_SPI_FLASH_BAR\n);
}
#endif
- if (spi_enable_wp_pin(flash))
- puts(Enable WP pin failed\n);
/* Release spi bus */
spi_release_bus(spi);
--
1.9.1
Applied to u-boot-spi/master
thanks!
--
Jagan.
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Re: [U-Boot] [PATCH] fdt: Fix handling of paths with options in them
Hi Hans,
On 23 April 2015 at 00:55, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 22-04-15 19:20, Simon Glass wrote:
Hi Hans,
On 20 April 2015 at 12:10, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 20-04-15 17:39, Simon Glass wrote:
Hi Hans,
On 20 April 2015 at 03:13, Hans de Goede hdego...@redhat.com wrote:
After syncing the sunxi dts files with the upstream kernel dm/fdt sunxi
builds would no longer boot.
The problem is that stdout-path is now set like this in the upstream
dts
files: stdout-path = serial0:115200n8. The use of options in
of-paths,
either after an alias name, or after a full path, e.g. stdout-path =
/soc@01c0/serial@01c28000:115200, is standard of usage, but
something
which the u-boot dts code so far did not handle.
This commit fixes this, adding support for both path formats.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/dts/sun7i-a20-pcduino3.dts | 2 +-
lib/libfdt/fdt_ro.c | 25 ++---
I haven't looked. but is this change in dtc upstream or just in the
kernel?
This is just a change in the dts files shipped with the kernel not in
dtc,
the dts files for sunxi used to not set stdout-path, and you patched in
a stdout-path setting for u-boot:
In that case, can we change this in the fdt support /fdtdec code,
instead of making a change to libfdt that will never go upstream?
If that doesn't work or is too painful, then we should take this patch.
Actually I started with fixing this the fdtdev level, but then I noticed
that the kernel does this at the of_find_node_by_path level, so if we
fix this for stdout-path only (which a fdtdec patch would do) then we may
get bit by this again later.
Also fixing it at the fdtdec level means adding a strdup + error checking
since then we need to pass a truncated (options removed) copy of the path
to fdt_path_offset(), while with the current patch we can keep using
read only access to the fdt.
So I've a slight preference for going this way. Why would libfdt upstream
not
take this patch ?
I'm not sure, but please go ahead and send it upstream. Thanks for the
explanation, I'll pick this up.
Acked-by: Simon Glass s...@chromium.org
Regards,
Hans
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=1a81cf8399675056beef5e76be8a9380d88c4ebf
+ chosen {
+ stdout-path = uart0;
+ };
But now the upstream dts contains a stdout-path itself, but like this;
alias {
serial0 = uart0;
};
chosen {
stdout-path = serial0:115200n8;
};
And the current u-boot dts parsing does not grok this due to it not
recognizing
the : in there.
Where as the kernel has:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/of/base.c#n713
static struct device_node *__of_find_node_by_path(struct device_node
*parent,
const char *path)
{
struct device_node *child;
int len;
len = strcspn(path, /:);
if (!len)
return NULL;
__for_each_child_of_node(parent, child) {
const char *name = strrchr(child-full_name, '/');
if (WARN(!name, malformed device_node %s\n,
child-full_name))
continue;
name++;
if (strncmp(path, name, len) == 0 (strlen(name) ==
len))
return child;
}
return NULL;
}
Where the strcspn surves the same purpose as the fdt_path_next_seperator
my
patch
introduces find the basename to match for stopping at the first occurence
of
either a '/' or a ':' char.
Regards,
Hans
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts
b/arch/arm/dts/sun7i-a20-pcduino3.dts
index cd05267..624abf2 100644
--- a/arch/arm/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -64,7 +64,7 @@
};
chosen {
- stdout-path = serial0:115200n8;
+ stdout-path = /soc@01c0/serial@01c28000:115200;
};
leds {
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 03733e5..44fc0aa 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -113,6 +113,25 @@ int fdt_subnode_offset(const void *fdt, int
parentoffset,
return fdt_subnode_offset_namelen(fdt, parentoffset, name,
strlen(name));
}
+/*
+ * Find the next of path seperator, note we need to search for both
'/'
and ':'
+ * and then take the first one so that we do the rigth thing for e.g.
+ * foo/bar:option and bar:option/otheroption, both of which
happen,
so
+ * first searching for either ':' or '/' does not work.
+ */
+static const char *fdt_path_next_seperator(const char *path)
+{
+ const char *sep1 = strchr(path,
Re: [U-Boot] [PATCH] net/phy: refactor RTL8211F initialization
Hi Shengzhou Liu,
On Wed, Apr 22, 2015 at 5:22 AM, Shengzhou Liu
shengzhou@freescale.com wrote:
RTL8211F needs to enalbe TXDLY for RGMII during
phy initialization, so move it to rtl8211f_config
for early initialization.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
cc: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/phy/realtek.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 3917c82..d48095b 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -43,6 +43,22 @@ static int rtl8211x_config(struct phy_device *phydev)
return 0;
}
+static int rtl8211f_config(struct phy_device *phydev)
+{
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
Do you not need to disable the phy interrupt here?
+
+ if (phydev-interface == PHY_INTERFACE_MODE_RGMII) {
+ /* enable TXDLY */
+ phy_write(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT, 0xd08);
Why do you not need to change the page back to default? Does it only
apply to one following command or something? I haven't read the data
sheet for this phy to understand its behavior, but want to make sure
it's clear here. Please at least add a comment describing why the
page need not be changed back.
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x11, 0x109);
Is this TX delay board specific? Seems like it would be. Should it be
parameterized to come from a board CONFIG_? If not, at least add a
comment describing these magic numbers.
+ }
+
+ genphy_config_aneg(phydev);
+
+ return 0;
+}
+
static int rtl8211x_parse_status(struct phy_device *phydev)
{
unsigned int speed;
@@ -142,13 +158,6 @@ static int rtl8211f_parse_status(struct phy_device
*phydev)
phydev-speed = SPEED_10;
}
- if (phydev-interface == PHY_INTERFACE_MODE_RGMII) {
- /* enable TXDLY */
- phy_write(phydev, MDIO_DEVAD_NONE,
- MIIM_RTL8211F_PAGE_SELECT, 0xd08);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x11, 0x109);
- }
-
return 0;
}
@@ -209,7 +218,7 @@ static struct phy_driver RTL8211F_driver = {
.uid = 0x1cc916,
.mask = 0xff,
.features = PHY_GBIT_FEATURES,
- .config = rtl8211x_config,
+ .config = rtl8211f_config,
.startup = rtl8211f_startup,
.shutdown = genphy_shutdown,
};
--
2.1.0.27.g96db324
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Re: [U-Boot] [PATCH v4] powerpc/t1023rdb: Add T1023 RDB board support
Resend with corrected email address. +Masahiro Yamada On 04/23/2015 01:27 AM, Liu Shengzhou-B36685 wrote: -Original Message- From: Sun York-R58495 Sent: Friday, April 17, 2015 3:22 AM To: Liu Shengzhou-B36685; u-boot@lists.denx.de Subject: Re: [PATCH v4] powerpc/t1023rdb: Add T1023 RDB board support On 03/27/2015 12:48 AM, Shengzhou Liu wrote: T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. +++ b/configs/T1023RDB_NAND_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS=PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND ++S:CONFIG_PPC=y ++S:CONFIG_MPC85xx=y ++S:CONFIG_TARGET_T102XRDB=y Please do not use CONFIG_SYS_EXTRA_OPTIONS for new boards. York I noted config SYS_EXTRA_OPTIONS string Extra Options (DEPRECATED) in Kconfig. But we still have to use the CONFIG_SYS_EXTRA_OPTIONS in current configuration Infrastructure, unless a newer approach is available in future. Because there are some something like 'SPL_FSL_PBL', 'NAND', 'SPIFLASH''SDCARD' which must be defined dynamically during build u-boot for various boot-mode in those *_defconfig files instead of in static include/config.h I was thinking to use select in Kconfig. But as you said, there are some macros not standardized. Maybe it is too early to enforce that. Let's hear from Masahiro Yamada. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 6e82b16..60dd2bb 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -7,6 +7,7 @@
#include common.h
#include asm/ibmpc.h
#include asm/pnp_def.h
+#include asm/gpio.h
#include netdev.h
#include smsc_lpc47m.h
@@ -14,6 +15,14 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 823e051..3c7b266 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_NR_DRAM_BANKS 1
--
2.1.4
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[U-Boot] [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
+
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
+ tmplong = x86_pci_read_config32(pci_dev, base);
if (tmplong == 0x || tmplong == 0x) {
- debug(%s: unexpected GPIOBASE value\n, __func__);
+ debug(%s: unexpected BASE value\n, __func__);
return -ENODEV;
}
@@ -135,7 +146,138 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice
*dev)
* at the offset that we just read. Bit 0 indicates that it's
* an I/O address, not a memory address, so mask that off.
*/
- gpiobase = tmplong 0xfffe;
+ return tmplong 0xfffc;
+}
+
+int
Re: [U-Boot] [PATCH] spl: descend into lib/ for all the SPL boards
On 21 April 2015 at 10:53, York Sun york...@freescale.com wrote: On 04/20/2015 08:37 PM, Masahiro Yamada wrote: Currently, CONFIG_SPL_LIBGENERIC_SUPPORT must be defined to build under lib/ directory for SPL. This directory contains very basic functions such as memcpy, memset in lib/string.c, so it should be very useful for all the boards. Because SPL always enables compiler's garbage collection, this change should not give impact on its memory footprint. Let's allow SPL to descend into lib/ all the time. As a result, CONFIG_SPL_LIBGENERIC_SUPPORT is no longer necessary. If this macro is not needed, do you want to remove it from README? Four files must be adjusted to avoid multiple definition error. - arch/powerpc/cpu/mpc85xx/spl_minimal.c udelay() is not a weak function. __udelay() is overridable. - arch/powerpc/lib/time.c MPC85xx has its own udelay for CONFIG_SPL_INIT_MINIAL. Enclose the definition with ifdefs. - board/armadeus/apf27/apf27.c - board/vpac270/onenand.c Do not duplicate hang() Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com --- Tested on multiple mpc85xx boards. Most are OK but I see issues with B4860QDS and T4240QDS NAND boot. Probably not caused by this patch. I will ask board maintainers to follow up. Reviewed-by: Simon Glass s...@chromium.org A few more uses to clean up: $ git grep CONFIG_SPL_LIBGENERIC_SUPPORT README: CONFIG_SPL_LIBGENERIC_SUPPORT doc/README.SPL:CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) doc/SPL/README.am335x-network:CONFIG_ETH_SUPPORT, CONFIG_SPL_LIBGENERIC_SUPPORT and Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spl: descend into lib/ for all the SPL boards
Hi Tom, On 22 April 2015 at 08:14, Tom Rini tr...@konsulko.com wrote: On Tue, Apr 21, 2015 at 12:37:18PM +0900, Masahiro Yamada wrote: Currently, CONFIG_SPL_LIBGENERIC_SUPPORT must be defined to build under lib/ directory for SPL. This directory contains very basic functions such as memcpy, memset in lib/string.c, so it should be very useful for all the boards. Because SPL always enables compiler's garbage collection, this change should not give impact on its memory footprint. Since we had a recent reminder about https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54303 did you do a size check before/after and confirm no change? Thanks! With just this patch applied to upstream/master: buildman -b try-masa -sS boards.cfg is up to date. Nothing to do. Summary of 2 commits for 1075 boards (32 threads, 1 job per thread) 01: serial: pl01x: fix PL010 regression blackfin: + bf609-ezkit powerpc: + taihu ocotea taishan katmai ebony alpr sh: + sh7753evb sh7785lcr_32bit sh7785lcr nios2: + nios2-generic microblaze: + microblaze-generic openrisc: + openrisc-generic arm: + openrd_base axm openrd_ultimate openrd_client tricorder tricorder_flash mx53loco taurus 02: spl: descend into lib/ for all the SPL boards powerpc: + P1022DS_36BIT_NAND powerpc: (for 406/411 boards) spl/u-boot-spl:all +1.3 spl/u-boot-spl:data +0.4 spl/u-boot-spl:text +0.9 So I think it looks fine. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot 6/7] dm: spi: xilinx_spi: Convert to driver model
Hi Jagan,
On 23 April 2015 at 08:15, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This converts the xilinx spi driver to use the driver model.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
---
Note: Michal, can you test this, I don't have hardware.
drivers/spi/xilinx_spi.c | 212
+++
1 file changed, 124 insertions(+), 88 deletions(-)
Acked-by: Simon Glass s...@chromium.org
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 3803c4c..4acade4 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -4,6 +4,7 @@
* Supports 8 bit SPI transfers only, with or w/o FIFO
*
* Based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2015 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
* Copyright (c) 2012 Stephan Linz l...@li-pro.net
* Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
* Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
@@ -14,6 +15,8 @@
#include config.h
#include common.h
+#include dm.h
+#include errno.h
#include malloc.h
#include spi.h
@@ -79,7 +82,7 @@
#endif
/* xilinx spi register set */
-struct xilinx_spi_reg {
+struct xilinx_spi_regs {
u32 __space0__[7];
u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
u32 ipisr; /* IP Interrupt Status Register (IPISR) */
@@ -97,113 +100,76 @@ struct xilinx_spi_reg {
u32 spirfor;/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
};
-/* xilinx spi slave */
-struct xilinx_spi_slave {
- struct spi_slave slave;
- struct xilinx_spi_reg *regs;
+/* xilinx spi priv */
+struct xilinx_spi_priv {
+ struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+ unsigned int cs;
};
-static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
- struct spi_slave *slave)
-{
- return container_of(slave, struct xilinx_spi_slave, slave);
-}
-
static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int xilinx_spi_probe(struct udevice *bus)
{
- return bus ARRAY_SIZE(xilinx_spi_base_list) cs 32;
-}
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ priv-regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus-seq];
+ priv-cs = spi_chip_select(bus);
- writel(SPISSR_ACT(slave-cs), xilspi-regs-spissr);
-}
+ writel(SPISSR_RESET_VALUE, regs-srr);
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
-
- writel(SPISSR_OFF, xilspi-regs-spissr);
-}
-
-void spi_init(void)
-{
- /* do nothing */
+ return 0;
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static void spi_cs_activate(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi;
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf(XILSPI error: unsupported bus %d / cs %d\n, bus, cs);
- return NULL;
- }
-
- xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
- if (!xilspi) {
- printf(XILSPI error: malloc of SPI structure failed\n);
- return NULL;
- }
- xilspi-regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
- xilspi-freq = max_hz;
- xilspi-mode = mode;
- debug(spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n,
- bus, cs, xilspi-regs, xilspi-mode, xilspi-freq);
-
- writel(SPISSR_RESET_VALUE, xilspi-regs-srr);
+ struct udevice *bus = dev-parent;
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- return xilspi-slave;
+ writel(SPISSR_ACT(priv-cs), regs-spissr);
}
-void spi_free_slave(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ struct udevice *bus = dev-parent;
dev_get_parent() so we can add pointer checking later perhaps.
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- free(xilspi);
+ writel(SPISSR_OFF, regs-spissr);
}
[snip]
Regards,
Simon
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Re: [U-Boot] [U-Boot 2/7] zynq: Kconfig: Enable dm spi and spi_flash
On 23 April 2015 at 08:15, Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com wrote: Enabled CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH for zynq soc. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Simon Glass s...@chromium.org Cc: Michal Simek michal.si...@xilinx.com Cc: Siva Durga Prasad Paladugu siva...@xilinx.com --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] patman: check git format.subjectprefix setting when generate patches prefix
On 14 April 2015 at 20:25, Josh Wu josh...@atmel.com wrote: For the local project, we may specified format.subjectprefix setting. Then the patch will be formated as [Project_prefix][PATCH]. But patman will not check this setting. It will remove the format.subjectprefix. So This patch will let patman check this setting and add it as a project prefix. Signed-off-by: Josh Wu josh...@atmel.com --- Changes in v2: - Modify README file to document how to use format.subjectprefix. tools/patman/README | 6 +- tools/patman/gitutil.py | 11 +++ tools/patman/series.py | 8 +++- 3 files changed, 23 insertions(+), 2 deletions(-) Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot 3/7] dts: zynq: Add zynq spi controller nodes
On 23 April 2015 at 08:15, Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com wrote: This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Simon Glass s...@chromium.org Cc: Michal Simek michal.si...@xilinx.com Cc: Siva Durga Prasad Paladugu siva...@xilinx.com --- arch/arm/dts/zynq-7000.dtsi | 24 doc/device-tree-bindings/spi/spi-zynq.txt | 27 +++ 2 files changed, 51 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-zynq.txt Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot 5/7] dts: zynq: Enable spi1 for zc770_xm010 board
On 23 April 2015 at 08:15, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This patch enables spi1 for zynq zc770_xm010 board dts.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-zc770-xm010.dts | 4
1 file changed, 4 insertions(+)
Acked-by: Simon Glass s...@chromium.org
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts
b/arch/arm/dts/zynq-zc770-xm010.dts
index 5e66174..e793a61 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -21,3 +21,7 @@
reg = 0 0x4000;
};
};
+
+spi1 {
+ status = okay;
+};
--
1.9.1
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Re: [U-Boot] [U-Boot 4/7] spi: zynq_spi: Add fdt support in driver
Hi Jagan,
On 23 April 2015 at 08:15, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying okay on respective board dts to use
the devicetree generated platdata.
Ex:
spi1 {
status = okay;
};
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-7000.dtsi | 2 ++
arch/arm/include/asm/arch-zynq/hardware.h | 2 --
doc/device-tree-bindings/spi/spi-zynq.txt | 2 ++
drivers/spi/zynq_spi.c| 23 +--
4 files changed, 17 insertions(+), 12 deletions(-)
Acked-by: Simon Glass s...@chromium.org
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index f66f8dc..9207159 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -117,6 +117,7 @@
interrupts = 0 26 4;
clocks = clkc 25, clkc 34;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
};
@@ -129,6 +130,7 @@
interrupts = 0 49 4;
clocks = clkc 26, clkc 35;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
};
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index e2e0b73..df9b06b 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -19,8 +19,6 @@
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
-#define ZYNQ_SPI_BASEADDR0 0xE0006000
-#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
#define ZYNQ_SMC_BASEADDR 0xE000E000
#define ZYNQ_NAND_BASEADDR 0xE100
diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt
b/doc/device-tree-bindings/spi/spi-zynq.txt
index a7c2757..f397a36 100644
--- a/doc/device-tree-bindings/spi/spi-zynq.txt
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -11,6 +11,7 @@ Required properties:
- clocks : Clock phandles (see clock bindings for details).
- clock-names : List of input clock names - ref_clk, pclk
(See clock bindings for details).
+- spi-max-frequency: Maximum SPI clocking speed of device in Hz
Example:
@@ -22,6 +23,7 @@ Example:
interrupts = 0 26 4;
clocks = clkc 25, clkc 34;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
} ;
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 62edbbe..df4a99e 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -13,9 +13,12 @@
#include errno.h
#include malloc.h
#include spi.h
+#include fdtdec.h
#include asm/io.h
#include asm/arch/hardware.h
+DECLARE_GLOBAL_DATA_PTR;
+
/* zynq spi register bit masks ZYNQ_SPI_REG_BIT_MASK */
#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
@@ -64,22 +67,22 @@ struct zynq_spi_priv {
u32 freq; /* required frequency */
};
-static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
-{
- if (bus-seq)
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
- else
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
-}
-
static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
{
struct zynq_spi_platdata *plat = bus-platdata;
+ const void *blob = gd-fdt_blob;
+ int node = bus-of_offset;
+
+ plat-regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node,
reg);
Or dev_get_addr() if you like.
- plat-regs = get_zynq_spi_regs(bus);
- plat-frequency = 16700;
+ /* FIXME: Use 250MHz as a suitable default */
+ plat-frequency = fdtdec_get_int(blob, node, spi-max-frequency,
+ 25000);
plat-speed_hz = plat-frequency / 2;
+ debug(zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n,
+ plat-regs, plat-frequency);
+
return 0;
}
--
1.9.1
Regards,
Simon
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Re: [U-Boot] [U-Boot 1/7] dm: spi: zynq_spi: Convert to driver model
Hi Jagan,
On 23 April 2015 at 08:15, Jagannadha Sutradharudu Teki
jagannadh.t...@gmail.com wrote:
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz - frequency
- req_hz - freq
- base - regs
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
Note: Siva Durga Prasad, can you test this on zc770_xm010
drivers/spi/zynq_spi.c | 305
+
1 file changed, 181 insertions(+), 124 deletions(-)
Acked-by: Simon Glass s...@chromium.org
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index ff1ec6a..62edbbe 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2013 Inc.
+ * (C) Copyright 2015 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
*
* Xilinx Zynq PS SPI controller driver (master mode only)
*
@@ -8,6 +9,8 @@
#include config.h
#include common.h
+#include dm.h
+#include errno.h
#include malloc.h
#include spi.h
#include asm/io.h
@@ -44,180 +47,142 @@ struct zynq_spi_regs {
u32 rxdr; /* 0x20 */
};
-/* zynq spi slave */
-struct zynq_spi_slave {
- struct spi_slave slave;
- struct zynq_spi_regs *base;
- u8 mode;
- u8 fifo_depth;
+
+/* zynq spi platform data */
+struct zynq_spi_platdata {
+ struct zynq_spi_regs *regs;
+ u32 frequency; /* input frequency */
u32 speed_hz;
- u32 input_hz;
- u32 req_hz;
};
-static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave
*slave)
-{
- return container_of(slave, struct zynq_spi_slave, slave);
-}
+/* zynq spi priv */
+struct zynq_spi_priv {
+ struct zynq_spi_regs *regs;
+ u8 cs;
+ u8 mode;
+ u8 fifo_depth;
+ u32 freq; /* required frequency */
+};
-static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
+static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
I see you remove this in a latest patch.
{
- if (dev)
+ if (bus-seq)
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
else
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
}
[snip]
Regards,
Simon
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Re: [U-Boot] [PATCH] buildman: Add gcc 4.9.0 with Microblaze toolchain
On 20 April 2015 at 03:46, Michal Simek michal.si...@xilinx.com wrote: Also read gcc 4.9.0 at kernel.org which also have Microblaze toolchain. Signed-off-by: Michal Simek michal.si...@xilinx.com --- tools/buildman/README | 2 +- tools/buildman/toolchain.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] buildman and multiple toolchains?
Hi Tom, On 23 April 2015 at 07:07, Tom Rini tr...@konsulko.com wrote: Hey, So I'm merging (or rather have merged and will push shortly) the ARMv7-M support. You can't build this with your normal arm-linux toolchain. Is there some way in buildman to be able to say, roughly: [toolchain] arm: /usr/bin/arm-linux-gnueabi armnone: /usr/bin/arm-none-eabi [toolchain-alias] stm32f429-discovery: armnone And have the 'arm' toolchain used normally for arm but 'armnone' used for the stm32f429-discovery board? I don't see why not, or something similar. Are you asking for a patch? :-) I don't have one one of those boards. Maybe I should take a look. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Booting Xen from a FIT - Additional discussion about a refactor
Hi Karl,
On 23 April 2015 at 07:15, Karl Apsite karl.aps...@dornerworks.com wrote:
On 04/22/2015 09:55 PM, Simon Glass wrote:
+Tom
Hi Karl,
On 22 April 2015 at 13:05, Karl Apsite karl.aps...@dornerworks.com wrote:
Hi!
I work at DornerWorks with the Xen Hypervisor. We work with a variety of
embedded systems, and we wanted to facilitate Xen's boot procedure through
U-boot's Flattened Image Tree (FIT) format. I've already prototyped some
of the
functionality we were hoping to see, so we thought it'd be prudent to begin
a
discussion with denx to get your opinion on the matter,
First Objective: (Summary of what was prototyped)
A Flattened Image Tree is capable of holding all of the necessary binaries
already, so we only need to make a quick change to allow u-boot to load an
extra
binary (in this case, a linux kernel) so that Xen can boot and load the
kernel
when it's ready. I started by simply adding a line in the configuration of
my
tree-source (.its) to look like:
config@1 {
description = Xen 4.6.0-unstable configuration;
kernel = xen_kernel@1;
fdt = fdt@1;
gen_bin0 = linux_kernel@1;
};
I investigated what effort would be needed to load the additional binary.
Booting Xen is easy (only a kernel and fdt are required), but Xen will look
at a
hard-coded memory address to try a load a linux kernel. This has to be
placed
in memory by u-boot. The only major addition I needed, was to make u-boot
care
about a config option named generic-binary and load it, no questions
asked. I
chose the name generic binary as I simply needed u-boot to load a [thing]
without any additional behavior. I'm using it to specifically load a linux
kernel at a specific memory address in preparation for xen, but there could
be
potential future uses, hence the ambiguous name.
I wonder whether you should add a new type for the target kernel?
General binary seems a bit vague. Just a thought.
I do agree, I don't really like the term generic binary either.
When preparing to boot Xen, u-boot needs to take a binary, and simply put it
in
place. Unlike the other images/objects (kernel, fdt, ramdisk, etc) u-boot's
role is very simple in this regard: Take these bits, and make sure they go
over
here.
In this scenario, the action taken by u-boot should be agnostic to what the
image actually is. U-boot should simply move a binary, without any additional
behavior. This led me to choose a name just as generic.
What is this additional behaviour you are referring to?
Maybe changing the name to Loadable(s) would sound a bit better, but going
so
far as to name it kernel could be misleading.
The hack is pretty simple, as most everything was in place to boot xen, and
it
took a little extra legwork to make u-boot care about my gen_bin. I added
the
necessary structure to load another object using ramdisk functions as
examples.
By loading a separate binary, Xen was able to boot, and successively boot
Linux
as expected. If you have any thoughts on this process overall, we'd like to
take your concerns into consideration.
For a little more fun, I extended out the configuration to be able to load N
number of generics.
This plan was part of the reason we were trying to keep the name more generic.
Keeping it generic allows for people other than xen users to take advantage of
the new feature in various ways.
Affected Files:
common/bootm.c
common/image-fit.c
common/image.c
doc/uImage.FIT/source_file_format.txt
include/configs/xilinx_zynqmp.h
include/image.h
Second Objective:
While I was there, I noticed that u-boot's binary loading logic isn't as
modular
as I first expected. Most objects eventually boil down to a
boot_get_thing().
Example: boot_get_ramdisk() or boot_get_kernel(). These functions are all
very
similar as they handle the various u-boot image types and load their
specific
binary. The functions appear to have grown similar in structure and
operation
overtime. I don't think it is too much to reduce the duplicated structure
of
the functions into a common boot_get_object() function, while replacing
some of
the extra function wrappings.
Some quick diagrams to explain what I mean
Initial: http://i.imgur.com/H44dXmN.png (29KB)
Refactor: http://i.imgur.com/apEpyWz.png (24KB)
SGTM.
The refactor will likely effect the following files, several of which
contain
trivial name changes, or small changes in a variable type.
arch/arm/lib/bootm.c
arch/avr32/lib/bootm.c
arch/microblaze/lib/bootm.c
arch/mips/lib/bootm.c
arch/nds32/lib/bootm.c
arch/nios2/lib/bootm.c
arch/openrisc/lib/bootm.c
arch/powerpc/lib/bootm.c
arch/sh/lib/bootm.c
arch/sparc/lib/bootm.c
arch/x86/lib/bootm.c
common/bootm.c
common/bootm_os.c
common/cmd_bootm.c
common/image-fdt.c
common/image.c
include/bootm.h
include/image.h
Summary
1.) RFC: What is the opinion on implementing a FIT configuration option to
Re: [U-Boot] [PATCH] buildman: Add gcc 4.9.0 with Microblaze toolchain
On 23 April 2015 at 12:36, Michal Simek michal.si...@xilinx.com wrote:
On 04/23/2015 08:30 PM, Simon Glass wrote:
Hi,
On 23 April 2015 at 12:23, Simon Glass s...@chromium.org wrote:
On 20 April 2015 at 03:46, Michal Simek michal.si...@xilinx.com wrote:
Also read gcc 4.9.0 at kernel.org which also have Microblaze toolchain.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
tools/buildman/README | 2 +-
tools/buildman/toolchain.py | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
However it does cause a test failure.
./tools/buildman/buildman -t
Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
unittest.result.TestResult run=34 errors=0 failures=1
Traceback (most recent call last):
File
/usr/local/google/c/cosarm/src/third_party/u-boot/files/tools/buildman/test.py,
line 415, in testToolchainDownload
self.toolchains.LocateArchUrl('arm'))
AssertionError:
'https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/x86_64-gcc-4.6.3-nolibc_arm-unknown-linux-gnueabi.tar.xz'
!=
'https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/x86_64-gcc-4.9.0-nolibc_arm-unknown-linux-gnueabi.tar.xz'
I'll fix that up when applying.
Thanks. I was curious why you didn't add 4.9.0 there but maybe this was
the reason.
Thanks for fixing it.
Michal
Applied to u-boot-x86 branch 'buildman', thanks!
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Re: [U-Boot] [PATCH v2] patman: check git format.subjectprefix setting when generate patches prefix
On 23 April 2015 at 12:33, Simon Glass s...@chromium.org wrote: On 14 April 2015 at 20:25, Josh Wu josh...@atmel.com wrote: For the local project, we may specified format.subjectprefix setting. Then the patch will be formated as [Project_prefix][PATCH]. But patman will not check this setting. It will remove the format.subjectprefix. So This patch will let patman check this setting and add it as a project prefix. Signed-off-by: Josh Wu josh...@atmel.com --- Changes in v2: - Modify README file to document how to use format.subjectprefix. tools/patman/README | 6 +- tools/patman/gitutil.py | 11 +++ tools/patman/series.py | 8 +++- 3 files changed, 23 insertions(+), 2 deletions(-) Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org Applied to u-boot-x86 branch 'buildman', thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] mx6cuboxi: Load the correct 'fdt_file' variable
Hi Stefano, On Thu, Apr 23, 2015 at 3:13 AM, Stefano Babic sba...@denx.de wrote: I admit I do not like a lot to have C code setting / fixing the environment. This has the drawback that when a user try to set the environment from the console as he wants, he cannot because the code has reverted back and it is not easy to track. I would like to propose another solution. Thanks for the suggestion. What about to export your is_hummingboard() function as U-Boot command ? You can then use it in U-Boot scripts, and the correct fdt name can be set in the bootcmd variable. Something like if is_humming;then ... I am not sure how I can retrieve the returned value from is_hummingboard() as a U-boot command and use it inside a script? Maybe I did not understand your suggestion. Please advise. And if a user wants to use other names, he can because it is not hard-coded. Yes, I understand the concern, but in this specific case we are talking about a DTB file, which is board specific and cannot really change. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] buildman: Add gcc 4.9.0 with Microblaze toolchain
Hi,
On 23 April 2015 at 12:23, Simon Glass s...@chromium.org wrote:
On 20 April 2015 at 03:46, Michal Simek michal.si...@xilinx.com wrote:
Also read gcc 4.9.0 at kernel.org which also have Microblaze toolchain.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
tools/buildman/README | 2 +-
tools/buildman/toolchain.py | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
However it does cause a test failure.
./tools/buildman/buildman -t
Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
unittest.result.TestResult run=34 errors=0 failures=1
Traceback (most recent call last):
File
/usr/local/google/c/cosarm/src/third_party/u-boot/files/tools/buildman/test.py,
line 415, in testToolchainDownload
self.toolchains.LocateArchUrl('arm'))
AssertionError:
'https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/x86_64-gcc-4.6.3-nolibc_arm-unknown-linux-gnueabi.tar.xz'
!=
'https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/x86_64-gcc-4.9.0-nolibc_arm-unknown-linux-gnueabi.tar.xz'
I'll fix that up when applying.
Regards,
Simon
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Re: [U-Boot] [PATCH] buildman: Add gcc 4.9.0 with Microblaze toolchain
On 04/23/2015 08:30 PM, Simon Glass wrote:
Hi,
On 23 April 2015 at 12:23, Simon Glass s...@chromium.org wrote:
On 20 April 2015 at 03:46, Michal Simek michal.si...@xilinx.com wrote:
Also read gcc 4.9.0 at kernel.org which also have Microblaze toolchain.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
tools/buildman/README | 2 +-
tools/buildman/toolchain.py | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
However it does cause a test failure.
./tools/buildman/buildman -t
Checking: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
unittest.result.TestResult run=34 errors=0 failures=1
Traceback (most recent call last):
File
/usr/local/google/c/cosarm/src/third_party/u-boot/files/tools/buildman/test.py,
line 415, in testToolchainDownload
self.toolchains.LocateArchUrl('arm'))
AssertionError:
'https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/x86_64-gcc-4.6.3-nolibc_arm-unknown-linux-gnueabi.tar.xz'
!=
'https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/x86_64-gcc-4.9.0-nolibc_arm-unknown-linux-gnueabi.tar.xz'
I'll fix that up when applying.
Thanks. I was curious why you didn't add 4.9.0 there but maybe this was
the reason.
Thanks for fixing it.
Michal
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[U-Boot] Please pull u-boot-x86 branch 'buildman'
Hi Tom, Note this is branch 'buildman'. The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06: serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400) are available in the git repository at: http://git.denx.de/u-boot-x86.git for you to fetch changes up to 3871cd858fcf8a00e31c2f456409afea03ce8788: patman: check git format.subjectprefix setting when generate patches prefix (2015-04-23 12:35:50 -0600) Michal Simek (1): buildman: Add gcc 4.9.0 with Microblaze toolchain Wu, Josh (1): patman: check git format.subjectprefix setting when generate patches prefix tools/buildman/README | 2 +- tools/buildman/test.py | 2 +- tools/buildman/toolchain.py | 2 +- tools/patman/README | 6 +- tools/patman/gitutil.py | 11 +++ tools/patman/series.py | 8 +++- 6 files changed, 26 insertions(+), 5 deletions(-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/138: [PATCH 3/4] x86: gpio: add pinctrl support from the device tree
A set of properties has been defined for the device tree to select for
each pin the pull/func/default output configuration.
The offset for the PAD needs to be provided and if a GPIO needs to be
configured, his offset needs to be provided as well.
Here is an example:
pin_usb_host_en0@0 {
gpio-offset = 0x80 8;
pad-offset = 0x260;
mode-gpio;
output-value = 1;
direction = PIN_OUTPUT;
};
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Added to GNATS database as unassigned-patches/138
Responsible:patch-coord
Message-Id: 1429805775-1809-4-git-send-email-cont...@huau-gabriel.fr
In-Reply-To:1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr
References: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr
Patch-Date: Thu Apr 23 18:16:14 +0200 2015
---
arch/x86/dts/minnowmax.dts| 21 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 1 +
arch/x86/include/asm/gpio.h | 1 +
drivers/gpio/intel_ich6_gpio.c| 222 ++
include/dt-bindings/gpio/gpio.h | 20 +++
5 files changed, 239 insertions(+), 26 deletions(-)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index c73e421..3936e21 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+
/include/ skeleton.dtsi
/include/ serial.dtsi
@@ -21,6 +23,25 @@
silent_console = 0;
};
+ pch_pinctrl {
+ compatible = intel,ich6-pinctrl;
+ pin_usb_host_en0@0 {
+ gpio-offset = 0x80 8;
+ pad-offset = 0x260;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+
+ pin_usb_host_en1@0 {
+ gpio-offset = 0x80 9;
+ pad-offset = 0x258;
+ mode-gpio;
+ output-value = 1;
+ direction = PIN_OUTPUT;
+ };
+ };
+
gpioa {
compatible = intel,ich6-gpio;
u-boot,dm-pre-reloc;
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h
b/arch/x86/include/asm/arch-baytrail/gpio.h
index 4e8987c..85a65a8 100644
--- a/arch/x86/include/asm/arch-baytrail/gpio.h
+++ b/arch/x86/include/asm/arch-baytrail/gpio.h
@@ -9,5 +9,6 @@
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x48
+#define PCI_CFG_IOBASE 0x4c
#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 1099427..ed85b08 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -147,6 +147,7 @@ struct pch_gpio_map {
} set3;
};
+int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 7e679a0..a110d5b 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -44,21 +44,32 @@ struct ich6_bank_priv {
uint16_t lvl;
};
+#define GPIO_USESEL_OFFSET(x) (x)
+#define GPIO_IOSEL_OFFSET(x) (x + 4)
+#define GPIO_LVL_OFFSET(x) (x + 8)
+
+#define IOPAD_MODE_MASK0x7
+#define IOPAD_PULL_ASSIGN_MASK 0x3
+#define IOPAD_PULL_ASSIGN_SHIFT7
+#define IOPAD_PULL_STRENGTH_MASK 0x3
+#define IOPAD_PULL_STRENGTH_SHIFT 9
+
+static int __ich6_gpio_set_value(uint16_t base, unsigned offset, int value);
+static int __ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir);
+static int __ich6_gpio_set_function(uint16_t base, unsigned offset, int func);
+
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd-arch.gpio_map = map;
}
-static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
+static int gpio_ich6_get_base(unsigned long base)
{
- struct ich6_bank_platdata *plat = dev_get_platdata(dev);
pci_dev_t pci_dev; /* handle for 0:1f:0 */
u8 tmpbyte;
u16 tmpword;
u32 tmplong;
- u16 gpiobase;
- int offset;
/* Where should it be? */
pci_dev = PCI_BDF(0, 0x1f, 0);
@@ -123,9 +134,9 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
- tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
+ tmplong = x86_pci_read_config32(pci_dev, base);
if (tmplong == 0x || tmplong == 0x) {
- debug(%s: unexpected GPIOBASE value\n, __func__);
+ debug(%s: unexpected BASE value\n, __func__);
[U-Boot] unassigned-patches/141: [PATCH] x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Added to GNATS database as unassigned-patches/141
Responsible:patch-coord
Message-Id: 1429805814-1892-1-git-send-email-cont...@huau-gabriel.fr
In-Reply-To:
References:
Patch-Date: Thu Apr 23 18:16:54 +0200 2015
---
include/configs/minnowmax.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 3c7b266..72393fa 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -43,7 +43,7 @@
#define CONFIG_SCSI_DEV_LIST\
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
--
2.1.4
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[U-Boot] [PATCH 2/4][v2]drivers:usb:fsl: Add XHCI driver support
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 6 ++
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-fsl.c | 107 ++
include/linux/usb/xhci-fsl.h | 54 +++
4 files changed, 168 insertions(+)
create mode 100644 drivers/usb/host/xhci-fsl.c
create mode 100644 include/linux/usb/xhci-fsl.h
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 3a64afc..9c1f1ce 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -538,4 +538,10 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x1 - 0xe004];
};
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00
+#define FSL_OTG_WRAPPER_BASE 0x4A02
+
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index c0d95cf..7c94439 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
+obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644
index 000..4ffcd6a
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+#include asm/arch-ls102xa/immap_ls102xa.h
+#include linux/compat.h
+#include linux/usb/xhci-fsl.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
+{
+ /* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs.
+*/
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
+ ctx-dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 000..8eaab2c
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek
Re: [U-Boot] [PATCH v5 2/3] mtd, nand: move common functions from cmd_nand.c to common place
On Thu, 2015-04-23 at 13:12 +0200, Heiko Schocher wrote: Hello Scott, Am 23.04.2015 08:55, schrieb Scott Wood: On Thu, 2015-04-23 at 07:57 +0200, Heiko Schocher wrote: Hello Scott, Am 23.04.2015 00:47, schrieb Scott Wood: On Mon, 2015-04-20 at 07:47 +0200, Heiko Schocher wrote: +int str2off(const char *p, loff_t *num); +int str2long(const char *p, ulong *num); These should be moved somewhere more generic, especially if they're no longer file-local. Hmm... the code is currently in drivers/mtd/mtd_uboot.c ... maybe we add a mtd_ prefix to them? I think these functions are mtd specific ... What is mtd-specific about them? Hmm... I thought: return *p != '\0' *endptr == '\0'; is more or less mtd specific ... but you are right, it is not really mtd specific ... so I move them to ./lib/vsprintf.c ... Ok? OK. Maybe change the return to bool while you're at it, to make it clear that it isn't return-zero-on-success. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot 0/7] dm: spi: Convert few drivers to driver model
Driver model conversion, patches. - drivers/spi/zynq_spi.c and drivers/spi/xilinx_spi.c thanks! -- Jagan. Jagannadha Sutradharudu Teki (7): dm: spi: zynq_spi: Convert to driver model zynq: Kconfig: Enable dm spi and spi_flash dts: zynq: Add zynq spi controller nodes spi: zynq_spi: Add fdt support in driver dts: zynq: Enable spi1 for zc770_xm010 board dm: spi: xilinx_spi: Convert to driver model spi: xilinx_spi: Add asm/io.h include file arch/arm/Kconfig | 2 + arch/arm/dts/zynq-7000.dtsi | 26 +++ arch/arm/dts/zynq-zc770-xm010.dts | 4 + arch/arm/include/asm/arch-zynq/hardware.h | 2 - doc/device-tree-bindings/spi/spi-zynq.txt | 29 +++ drivers/spi/xilinx_spi.c | 213 +++- drivers/spi/zynq_spi.c| 312 ++ 7 files changed, 372 insertions(+), 216 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-zynq.txt -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] arm: mx6: Clamp MMDC and DDR3 clocks for timing calculations
Hi Nikolay, On 23/04/2015 16:26, Nikolay Dimitrov wrote: +arch/arm/cpu/armv7/mx6/ddr.c: In function 'mx6_dram_cfg': +arch/arm/cpu/armv7/mx6/ddr.c:279:4: error: assignment of member 'mem_speed' in read-only object +arch/arm/cpu/armv7/mx6/ddr.c:286:4: error: assignment of member 'mem_speed' in read-only object +make[4]: *** [spl/arch/arm/cpu/armv7/mx6/ddr.o] Error 1 Sorry for the stupid mistake, I've already sent v2. No probblem at all, I have seen it and I'll pick it up soon ! Regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-dm
Hi Tom, This brings in core features to support PMICs (which should come within a week so), core test fixes and most of the SPL device tree support . I'd like to do this in two pieces since this is all somewhat risky. The images sizes mostly drop slightly with these patches which is a good sign (i.e. it would indicate a problem if they increased a lot). 16: dm: Init device tree as well as driver model in SPL blackfin: (for 34/35 boards) all -26.8 data -4.0 rodata -14.4 text -8.5 x86: (for 6/6 boards) all -24.0 bss +216.0 data -4.0 rodata -76.0 text -160.0 avr32: (for 10/10 boards) all -3.6 data -1.6 text -2.0 sandbox: (for 1/1 boards) all -56.0 rodata -96.0 text +40.0 m68k: (for 48/48 boards) all -1.5 data -2.3 text +0.9 powerpc: (for 406/411 boards) all -81.3 bss +0.1 data -3.5 rodata -0.7 spl/u-boot-spl:all +44.7 spl/u-boot-spl:data +50.0 spl/u-boot-spl:rodata +2.2 spl/u-boot-spl:text -7.4 text -77.1 sparc: (for 5/5 boards) all +48.0 text +48.0 sh: (for 21/22 boards) all +53.1 text +53.1 nios2: (for 1/1 boards) data -4.0 text +4.0 mips: (for 24/24 boards) all +0.7 bss -3.3 data -4.3 text +8.3 arm: (for 496/496 boards) all -67.2 bss -0.4 data -0.7 rodata -16.1 spl/u-boot-spl:all +27.6 spl/u-boot-spl:bss -0.0 spl/u-boot-spl:rodata +59.1 spl/u-boot-spl:text -31.5 text -50.0 nds32: (for 3/3 boards) all +84.0 text +84.0 The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06: serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400) are available in the git repository at: http://git.denx.de/u-boot-dm.git for you to fetch changes up to f3d46bd658ef4df575ec26c29e472ac858723159: dm: Init device tree as well as driver model in SPL (2015-04-23 09:05:55 -0600) Przemyslaw Marczak (11): dm: core: add internal functions for getting the device without probe dm: core: Extend struct udevice by '.uclass_platdata' field. dm: test: Add tests for device's uclass platform data dm: test: Add tests for get/find uclass devices dm: core: uclass: add function: uclass_find_device_by_name() dm: core: uclass: add function: uclass_get_device_by_name() dm: core: device: add function: dev_get_driver_ops() dm: core: device: add function: dev_get_uclass_name() dm: core: remove type 'static' of function uclass_get_device_tail() dm: test: Add tests for get/find uclass's device by name dm: core: precise comments for get/find device by name Simon Glass (20): dm: core: Handle recursive unbinding of uclass devices dm: usb: Add a terminator to the string destructor list dm: Update the README to reflect the current test output dm: test: Don't clear global_data in dm_test_uclass_before_ready() exynos: sandbox: ti: Add SPDX license identifiers and notes serial: ns16550: Add an option to specify the debug UART register shift dm: ns16550: Support non-byte register spacing with driver model serial: ns16550: Remove unnecessary init on UART setup dm: core: Allow sequence alias support to be removed for SPL dm: core: Remove unbind operations when not required dm: Add a panic_str() function to reduce code size dm: core: Drop device removal error path when not supported fdt: sandbox: Move setup code from board_f to fdtdec fdt: Rename setup_fdt() and make it prepare also Move initf_malloc() to a common place Correct malloc_limit value for pre-relocation malloc() fdt: Add an option to disable device tree in SPL fdt: Allow FDT functions to be built for SPL dm: core: Select device tree control correctly for SPL dm: Init device tree as well as driver model in SPL arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 2 + arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 2 + arch/arm/dts/exynos5250-pinctrl-uboot.dtsi | 2 + arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi | 2 + arch/arm/dts/s5pc100-pinctrl.dtsi | 2 + arch/arm/dts/s5pc110-pinctrl.dtsi | 2 + arch/sandbox/cpu/cpu.c | 41 ++ arch/sandbox/include/asm/bitops.h | 2 + arch/sandbox/include/asm/u-boot-sandbox.h | 8 common/board_f.c | 84 ++--- common/dlmalloc.c | 11 + common/spl/spl.c | 22 -- doc/driver-model/README.txt| 58 + drivers/core/Kconfig | 9 drivers/core/device-remove.c | 4 ++ drivers/core/device.c | 103 + drivers/core/root.c| 14 --- drivers/core/uclass.c | 122
[U-Boot] unassigned-patches/142: [PATCH 0/4] x86: support of pin-muxing from device tree
This serie of patches adds the support of pin-muxing from the device tree through different properties. I have put two example to enable the USB Host on the minnowboard max. The support of the call to 'setup_pch_gpios' is still supported and only the minnowboard has been tested with the device tree implementation. Because the GPIO and IO base register ares different, I have also defined some proxy function to set the function/value and direction of the GPIO as the GPIO register can override some registers in the IO. Gabriel Huau (4): x86: baytrail: fix the GPIOBASE address x86: minnowmax: add GPIO banks in the device tree x86: gpio: add pinctrl support from the device tree x86: minnowmax: initialize the pin-muxing from device tree arch/x86/dts/minnowmax.dts| 63 + arch/x86/include/asm/arch-baytrail/gpio.h | 3 +- arch/x86/include/asm/gpio.h | 1 + board/intel/minnowmax/minnowmax.c | 9 ++ drivers/gpio/intel_ich6_gpio.c| 222 ++ include/configs/minnowmax.h | 1 + include/dt-bindings/gpio/gpio.h | 20 +++ 7 files changed, 292 insertions(+), 27 deletions(-) -- 2.1.4 --- Added to GNATS database as unassigned-patches/142 Responsible:patch-coord Message-Id: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr In-Reply-To: References: Patch-Date: Thu Apr 23 18:16:11 +0200 2015 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/143: [PATCH 4/4] x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Added to GNATS database as unassigned-patches/143
Responsible:patch-coord
Message-Id: 1429805775-1809-5-git-send-email-cont...@huau-gabriel.fr
In-Reply-To:1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr
References: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr
Patch-Date: Thu Apr 23 18:16:15 +0200 2015
---
board/intel/minnowmax/minnowmax.c | 9 +
include/configs/minnowmax.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/board/intel/minnowmax/minnowmax.c
b/board/intel/minnowmax/minnowmax.c
index 6e82b16..60dd2bb 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -7,6 +7,7 @@
#include common.h
#include asm/ibmpc.h
#include asm/pnp_def.h
+#include asm/gpio.h
#include netdev.h
#include smsc_lpc47m.h
@@ -14,6 +15,14 @@
DECLARE_GLOBAL_DATA_PTR;
+int arch_early_init_r(void)
+{
+ /* do the pin-muxing */
+ gpio_ich6_pinctrl_init();
+
+ return 0;
+}
+
int board_early_init_f(void)
{
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 823e051..3c7b266 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_NR_DRAM_BANKS 1
--
2.1.4
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Re: [U-Boot] [PATCH 5/5] mx6cuboxi: Load the correct 'fdt_file' variable
Hi Fabio, On 23/04/2015 19:18, Fabio Estevam wrote: What about to export your is_hummingboard() function as U-Boot command ? You can then use it in U-Boot scripts, and the correct fdt name can be set in the bootcmd variable. Something like if is_humming;then ... I am not sure how I can retrieve the returned value from is_hummingboard() as a U-boot command and use it inside a script? Maybe I did not understand your suggestion. Please advise. U_BOOT_CMD returns a value that can be evaluated, exactly as we do with if tftp.. or for other commands. So you could implement: U_BOOT_CMD(is_hummingbird, 1, 1, do_is_hummingbird, .. and the do_is_hummingbird can return CMD_RET_SUCCESS or CMD_RET_FAILURE. This is then evaluated in the script as if is_hummingbird;then fdt_file=;else fdt_file=...;fi And if a user wants to use other names, he can because it is not hard-coded. Yes, I understand the concern, but in this specific case we are talking about a DTB file, which is board specific and cannot really change. Well, maybe I am alone, but I am used to have several DTB files during the developmnet phase - I agree with you that at the end there should be only one DTB file. Anyway, my was only a proposal - it is also fine if you decide to maintain the current implementation. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] mx6cuboxi: Load the correct 'fdt_file' variable
On Thu, Apr 23, 2015 at 08:13:05AM +0200, Stefano Babic wrote:
Hi Fabio,
On 23/04/2015 05:57, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Instead of hardcoding the 'fdt_file' variable, let's introduce a new
function - build_dts_name(), that can build the dtb filename on the fly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/solidrun/mx6cuboxi/mx6cuboxi.c | 24
include/configs/mx6cuboxi.h | 3 +--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 83410b2..1c24a55 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -212,6 +212,30 @@ int checkboard(void)
return 0;
}
+static const char *build_dts_name(void)
+{
+ char *dt_prefix = unknown;
+ char *dt_suffix = unknown;
+
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ dt_prefix = imx6q;
+ else if (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+ dt_prefix = imx6dl;
+
+ if (is_hummingboard())
+ dt_suffix = -hummingboard.dtb;
+ else
+ dt_suffix = -cubox-i.dtb;
+
+ return strcat(dt_prefix, dt_suffix);
+}
+
I admit I do not like a lot to have C code setting / fixing the
environment. This has the drawback that when a user try to set the
environment from the console as he wants, he cannot because the code has
reverted back and it is not easy to track. I would like to propose
another solution.
Yes. Please see how this is done for the various TI boards where we
export into the env enough information to make these kind of decisions
in the shell. This is even more applicable here as we don't have the
dynamic pick a DT for Falcon Mode that the Solid Run tree has where
this originated in.
--
Tom
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Re: [U-Boot] buildman and multiple toolchains?
On Thu, Apr 23, 2015 at 12:44:12PM -0600, Simon Glass wrote: Hi Tom, On 23 April 2015 at 07:07, Tom Rini tr...@konsulko.com wrote: Hey, So I'm merging (or rather have merged and will push shortly) the ARMv7-M support. You can't build this with your normal arm-linux toolchain. Is there some way in buildman to be able to say, roughly: [toolchain] arm: /usr/bin/arm-linux-gnueabi armnone: /usr/bin/arm-none-eabi [toolchain-alias] stm32f429-discovery: armnone And have the 'arm' toolchain used normally for arm but 'armnone' used for the stm32f429-discovery board? I don't see why not, or something similar. Are you asking for a patch? :-) Or a pointer to where to start hacking :) -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] buildman and multiple toolchains?
On Thu, Apr 23, 2015 at 01:22:55PM -0600, Simon Glass wrote: Hi Tom, On 23 April 2015 at 12:57, Tom Rini tr...@konsulko.com wrote: On Thu, Apr 23, 2015 at 12:44:12PM -0600, Simon Glass wrote: Hi Tom, On 23 April 2015 at 07:07, Tom Rini tr...@konsulko.com wrote: Hey, So I'm merging (or rather have merged and will push shortly) the ARMv7-M support. You can't build this with your normal arm-linux toolchain. Is there some way in buildman to be able to say, roughly: [toolchain] arm: /usr/bin/arm-linux-gnueabi armnone: /usr/bin/arm-none-eabi [toolchain-alias] stm32f429-discovery: armnone And have the 'arm' toolchain used normally for arm but 'armnone' used for the stm32f429-discovery board? I don't see why not, or something similar. Are you asking for a patch? :-) Or a pointer to where to start hacking :) The toolchain is selected in builderthread.py: self.toolchain = self.builder.toolchains.Select(brd.arch) brd is a Board object. At present only the arch is passed in, but you could pass in brd.target if you like. You'll then need to enhance toolchain.Select() to check for an alias for that target. Ah, but the first problem is that I can't convince buildman that if I have both /usr/bin/arm-linux-gnueabi-gcc and /usr/bin/arm-none-eabi-gcc to let me set both arm and armnone to something. Or even /somewhere/else/bin/arm-linux-gnueabi-gcc and /usr/bin/arm-none-eabi-gcc Where does that need beating up? :) -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/5] mx6cuboxi: Load the correct 'fdt_file' variable
Instead of hardcoding the 'fdt_file' variable, let's detect the SoC and
board variant on the fly and change the dtb name.
Based on a patch from Rabeeh Khoury.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Attribute the credit to Rabeeh
- Create a U-boot command for checking if the board is hummingboard
board/solidrun/mx6cuboxi/mx6cuboxi.c | 30 ++
include/configs/mx6cuboxi.h | 12 ++--
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 83410b2..4ea6081 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -212,6 +212,36 @@ int checkboard(void)
return 0;
}
+static const char *build_dts_prefix(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ return imx6q;
+ else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ return imx6dl;
+
+ return unknown;
+}
+
+static int do_is_hummingboard(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
+{
+ if (is_hummingboard())
+ return CMD_RET_SUCCESS;
+ else
+ return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMD(
+ is_hummingboard, 1, 1, do_is_hummingboard,
+ detect if it is a Hummingboard or Cubox-i,
+
+);
+
+int misc_init_r(void)
+{
+ setenv(dts_prefix, build_dts_prefix());
+ return 0;
+}
+
#ifdef CONFIG_SPL_BUILD
#include asm/arch/mx6-ddr.h
static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 5d58b16..c3cf633 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -29,6 +29,7 @@
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_CMD_FUSE
@@ -81,14 +82,19 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV ttymxc0
#define CONFIG_MMCROOT /dev/mmcblk0p2
-#define CONFIG_DEFAULT_FDT_FILEimx6q-hummingboard.dtb
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
#define CONFIG_EXTRA_ENV_SETTINGS \
script=boot.scr\0 \
image=zImage\0 \
- fdt_file= CONFIG_DEFAULT_FDT_FILE \0 \
+ check_suffix= \
+ if is_hummingboard; then \
+ setenv dts_suffix -hummingboard.dtb; \
+ else \
+ setenv dts_suffix -cubox-i.dtb; \
+ fi; \
+ setenv fdt_file ${dts_prefix}${dts_suffix}; \
fdt_addr=0x1800\0 \
boot_fdt=try\0 \
ip_dyn=yes\0 \
@@ -119,6 +125,7 @@
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0 \
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0 \
mmcboot=echo Booting from mmc ...; \
+ run check_suffix; \
run mmcargs; \
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then \
if run loadfdt; then \
@@ -137,6 +144,7 @@
root=/dev/nfs \
ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0 \
netboot=echo Booting from net ...; \
+ run check_suffix; \
run netargs; \
if test ${ip_dyn} = yes; then \
setenv get_cmd dhcp; \
--
1.9.1
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[U-Boot] [PATCH v2 2/5] mx6cuboxi: Prepare for multi SoC support
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad.
Use IOMUX_PADS() macro in order to prepare for the multi-SoC support.
Also pass 'MX6QDL' in the defconfig to indicate it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- None
board/solidrun/mx6cuboxi/mx6cuboxi.c | 60 ++--
configs/mx6cuboxi_defconfig | 2 +-
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index b696dcb..0377dc4 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -28,7 +28,6 @@
#include asm/arch/crm_regs.h
#include asm/io.h
#include asm/arch/sys_proto.h
-#include asm/arch/mx6-ddr.h
#include spl.h
DECLARE_GLOBAL_DATA_PTR;
@@ -59,22 +58,22 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ SETUP_IOMUX_PADS(uart1_pads);
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
@@ -88,7 +87,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd-arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
@@ -97,33 +96,33 @@ int board_mmc_init(bd_t *bis)
}
static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8035 reset */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
/* AR8035 interrupt */
- MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* GPIO16 - AR8035 25MHz */
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8035 CLK_25M -- ENET_REF_CLK (V22) */
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD2__RGMII_RD2 |
[U-Boot] [PATCH v2 3/5] mx6cuboxi: Introduce multi-SoC support
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad. Add support for the different SoC/memory sizes
combinations.
DDR initialization values were extracted from Solid-run internal U-boot.
Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Mention that the DDR init came from Solid-run
board/solidrun/mx6cuboxi/mx6cuboxi.c | 134 ---
1 file changed, 125 insertions(+), 9 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 0377dc4..1f240ae 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -175,7 +175,7 @@ int checkboard(void)
#ifdef CONFIG_SPL_BUILD
#include asm/arch/mx6-ddr.h
-static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
@@ -204,7 +204,36 @@ static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm7 = 0x00020030,
};
-static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
+ .dram_sdclk_0 = 0x0028,
+ .dram_sdclk_1 = 0x0028,
+ .dram_cas = 0x0028,
+ .dram_ras = 0x0028,
+ .dram_reset = 0x000c0028,
+ .dram_sdcke0 = 0x3000,
+ .dram_sdcke1 = 0x3000,
+ .dram_sdba2 = 0x,
+ .dram_sdodt0 = 0x3030,
+ .dram_sdodt1 = 0x3030,
+ .dram_sdqs0 = 0x0028,
+ .dram_sdqs1 = 0x0028,
+ .dram_sdqs2 = 0x0028,
+ .dram_sdqs3 = 0x0028,
+ .dram_sdqs4 = 0x0028,
+ .dram_sdqs5 = 0x0028,
+ .dram_sdqs6 = 0x0028,
+ .dram_sdqs7 = 0x0028,
+ .dram_dqm0 =0x0028,
+ .dram_dqm1 =0x0028,
+ .dram_dqm2 =0x0028,
+ .dram_dqm3 =0x0028,
+ .dram_dqm4 =0x0028,
+ .dram_dqm5 =0x0028,
+ .dram_dqm6 =0x0028,
+ .dram_dqm7 =0x0028,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
.grp_ddr_type = 0x000C,
.grp_ddrmode_ctl = 0x0002,
.grp_ddrpke = 0x,
@@ -221,7 +250,25 @@ static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
.grp_b7ds = 0x0030,
};
-static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c,
+ .grp_ddrmode_ctl = 0x0002,
+ .grp_ddrpke = 0x,
+ .grp_addds = 0x0028,
+ .grp_ctlds = 0x0028,
+ .grp_ddrmode = 0x0002,
+ .grp_b0ds = 0x0028,
+ .grp_b1ds = 0x0028,
+ .grp_b2ds = 0x0028,
+ .grp_b3ds = 0x0028,
+ .grp_b4ds = 0x0028,
+ .grp_b5ds = 0x0028,
+ .grp_b6ds = 0x0028,
+ .grp_b7ds = 0x0028,
+};
+
+/* microSOM with Dual processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
.p0_mpwldectrl0 = 0x,
.p0_mpwldectrl1 = 0x,
.p1_mpwldectrl0 = 0x,
@@ -236,7 +283,49 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p1_mpwrdlctl =0x422a423c,
};
-static struct mx6_ddr3_cfg mem_ddr = {
+/* microSOM with Quad processor and 2GB memory */
+static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x,
+ .p0_mpwldectrl1 = 0x,
+ .p1_mpwldectrl0 = 0x,
+ .p1_mpwldectrl1 = 0x,
+ .p0_mpdgctrl0 =0x0314031c,
+ .p0_mpdgctrl1 =0x023e0304,
+ .p1_mpdgctrl0 =0x03240330,
+ .p1_mpdgctrl1 =0x03180260,
+ .p0_mprddlctl =0x3630323c,
+ .p1_mprddlctl =0x3436283a,
+ .p0_mpwrdlctl =0x36344038,
+ .p1_mpwrdlctl =0x422a423c,
+};
+
+/* microSOM with Solo processor and 512MB memory */
+static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0045004D,
+ .p0_mpwldectrl1 = 0x003A0047,
+ .p0_mpdgctrl0 = 0x023C0224,
+ .p0_mpdgctrl1 = 0x02000220,
+ .p0_mprddlctl = 0x4846,
+ .p0_mpwrdlctl = 0x32343032,
+};
+
+/* microSOM with Dual lite processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0045004D,
+ .p0_mpwldectrl1 = 0x003A0047,
+ .p1_mpwldectrl0 = 0x001F001F,
+ .p1_mpwldectrl1 = 0x00210035,
+ .p0_mpdgctrl0 =0x023C0224,
+ .p0_mpdgctrl1 =0x02000220,
+ .p1_mpdgctrl0 =0x02200220,
+ .p1_mpdgctrl1 =0x02000220,
+ .p0_mprddlctl =0x4846,
+
[U-Boot] [PATCH v2 1/5] mx6cuboxi: Fix the defconfig name
The correct name of the defconfig file is 'mx6cuboxi_defconfig'. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- Changes since v1: - None board/solidrun/mx6cuboxi/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS index 3d468ed..a3506c2 100644 --- a/board/solidrun/mx6cuboxi/MAINTAINERS +++ b/board/solidrun/mx6cuboxi/MAINTAINERS @@ -3,4 +3,4 @@ M: Fabio Estevam fabio.este...@freescale.com S: Maintained F: board/solidrun/mx6cuboxi/ F: include/configs/mx6cuboxi.h -F: configs/mx6cuboxi_spl_defconfig +F: configs/mx6cuboxi_defconfig -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/5] mx6cuboxi: Differentiate Cubox-i and Hummingboard
Introduce is_hummingboard() function that reads GPIOs that can distinguish
between Cubox-i and Hummingboard.
Print the board name accordingly.
Based on a patch from Rabeeh Khoury.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
Changes since v1:
- Attribute the credit to Rabeeh
board/solidrun/mx6cuboxi/mx6cuboxi.c | 41 +++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 1f240ae..83410b2 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -71,6 +71,12 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
+static iomux_v3_cfg_t const hb_cbi_sense[] = {
+ /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
static void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
@@ -167,9 +173,42 @@ int board_init(void)
return 0;
}
+static bool is_hummingboard(void)
+{
+ int val1, val2;
+
+ SETUP_IOMUX_PADS(hb_cbi_sense);
+
+ gpio_direction_input(IMX_GPIO_NR(4, 9));
+ gpio_direction_input(IMX_GPIO_NR(3, 4));
+
+ val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
+ val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
+
+ /*
+* Machine selection -
+* Machineval1, val2
+* -
+* HB rev 3.x x 0
+* CBi0 1
+* HB 1 1
+*/
+
+ if (val2 == 0)
+ return true;
+ else if (val1 == 0)
+ return false;
+ else
+ return true;
+}
+
int checkboard(void)
{
- puts(Board: MX6 Hummingboard\n);
+ if (is_hummingboard())
+ puts(Board: MX6 Hummingboard\n);
+ else
+ puts(Board: MX6 Cubox-i\n);
+
return 0;
}
--
1.9.1
___
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Re: [U-Boot] buildman and multiple toolchains?
Hi Tom, On 23 April 2015 at 12:57, Tom Rini tr...@konsulko.com wrote: On Thu, Apr 23, 2015 at 12:44:12PM -0600, Simon Glass wrote: Hi Tom, On 23 April 2015 at 07:07, Tom Rini tr...@konsulko.com wrote: Hey, So I'm merging (or rather have merged and will push shortly) the ARMv7-M support. You can't build this with your normal arm-linux toolchain. Is there some way in buildman to be able to say, roughly: [toolchain] arm: /usr/bin/arm-linux-gnueabi armnone: /usr/bin/arm-none-eabi [toolchain-alias] stm32f429-discovery: armnone And have the 'arm' toolchain used normally for arm but 'armnone' used for the stm32f429-discovery board? I don't see why not, or something similar. Are you asking for a patch? :-) Or a pointer to where to start hacking :) The toolchain is selected in builderthread.py: self.toolchain = self.builder.toolchains.Select(brd.arch) brd is a Board object. At present only the arch is passed in, but you could pass in brd.target if you like. You'll then need to enhance toolchain.Select() to check for an alias for that target. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] buildman and multiple toolchains?
Hi Tom, On 23 April 2015 at 13:26, Tom Rini tr...@konsulko.com wrote: On Thu, Apr 23, 2015 at 01:22:55PM -0600, Simon Glass wrote: Hi Tom, On 23 April 2015 at 12:57, Tom Rini tr...@konsulko.com wrote: On Thu, Apr 23, 2015 at 12:44:12PM -0600, Simon Glass wrote: Hi Tom, On 23 April 2015 at 07:07, Tom Rini tr...@konsulko.com wrote: Hey, So I'm merging (or rather have merged and will push shortly) the ARMv7-M support. You can't build this with your normal arm-linux toolchain. Is there some way in buildman to be able to say, roughly: [toolchain] arm: /usr/bin/arm-linux-gnueabi armnone: /usr/bin/arm-none-eabi [toolchain-alias] stm32f429-discovery: armnone And have the 'arm' toolchain used normally for arm but 'armnone' used for the stm32f429-discovery board? I don't see why not, or something similar. Are you asking for a patch? :-) Or a pointer to where to start hacking :) The toolchain is selected in builderthread.py: self.toolchain = self.builder.toolchains.Select(brd.arch) brd is a Board object. At present only the arch is passed in, but you could pass in brd.target if you like. You'll then need to enhance toolchain.Select() to check for an alias for that target. Ah, but the first problem is that I can't convince buildman that if I have both /usr/bin/arm-linux-gnueabi-gcc and /usr/bin/arm-none-eabi-gcc to let me set both arm and armnone to something. Or even /somewhere/else/bin/arm-linux-gnueabi-gcc and /usr/bin/arm-none-eabi-gcc Where does that need beating up? :) Ah, well at present there is only one toolchain per arch. Toolchains.Add() relies on toolchain.arch as a key for its dictionary. Public members: toolchains: Dict of Toolchain objects, keyed by architecture name So this is a problem. I suppose you need to allow more than one toolchain for each arch - e.g. change the valuers in that dict from being a single Toolchain to being a list of Toolchain objects. But you need a label for each toolchain - thatt could be kept in the Toolchain object. At present Toolchain.arch tells you everything you need to know about which toolchain to use. But if you add Toolchain.target (for example) then Toolchains.Select() could look for that first. I think that list-tool-chains should be enhanced to list all tool chains in that case. Happy hacking. Let me know if you want me to take a look. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-dm
On Thu, Apr 23, 2015 at 10:24:32AM -0600, Simon Glass wrote: Hi Tom, This brings in core features to support PMICs (which should come within a week so), core test fixes and most of the SPL device tree support . I'd like to do this in two pieces since this is all somewhat risky. The images sizes mostly drop slightly with these patches which is a good sign (i.e. it would indicate a problem if they increased a lot). 16: dm: Init device tree as well as driver model in SPL blackfin: (for 34/35 boards) all -26.8 data -4.0 rodata -14.4 text -8.5 x86: (for 6/6 boards) all -24.0 bss +216.0 data -4.0 rodata -76.0 text -160.0 avr32: (for 10/10 boards) all -3.6 data -1.6 text -2.0 sandbox: (for 1/1 boards) all -56.0 rodata -96.0 text +40.0 m68k: (for 48/48 boards) all -1.5 data -2.3 text +0.9 powerpc: (for 406/411 boards) all -81.3 bss +0.1 data -3.5 rodata -0.7 spl/u-boot-spl:all +44.7 spl/u-boot-spl:data +50.0 spl/u-boot-spl:rodata +2.2 spl/u-boot-spl:text -7.4 text -77.1 sparc: (for 5/5 boards) all +48.0 text +48.0 sh: (for 21/22 boards) all +53.1 text +53.1 nios2: (for 1/1 boards) data -4.0 text +4.0 mips: (for 24/24 boards) all +0.7 bss -3.3 data -4.3 text +8.3 arm: (for 496/496 boards) all -67.2 bss -0.4 data -0.7 rodata -16.1 spl/u-boot-spl:all +27.6 spl/u-boot-spl:bss -0.0 spl/u-boot-spl:rodata +59.1 spl/u-boot-spl:text -31.5 text -50.0 nds32: (for 3/3 boards) all +84.0 text +84.0 The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06: serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400) are available in the git repository at: http://git.denx.de/u-boot-dm.git for you to fetch changes up to f3d46bd658ef4df575ec26c29e472ac858723159: dm: Init device tree as well as driver model in SPL (2015-04-23 09:05:55 -0600) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] gpio: mvmfp: support newer MFP bit definitions
On Mon, Mar 23, 2015 at 05:56:58PM -0500, Rob Herring wrote: From: Xiang Wang wa...@marvell.com 1. The bits 11..10 for mfp driver strength is only valid for aspen and old xscale family, for newer Marvell chip, this range has been moved to 12..11. 2. add sleep bit support Signed-off-by: Xiang Wang wa...@marvell.com [robh: rebase to current mainline] Signed-off-by: Rob Herring r...@kernel.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] cmd_led: Extend led command to support blinking and more leds
On Wed, Mar 11, 2015 at 09:51:39AM +0100, Stefan Roese wrote: This patch extends the U-Boot led command to support automatic blinking by setting a blink frequency in milliseconds. Additionally the number of supported LEDs is increased to 6 (0...5). This will be used by the PCA9551 LED driver. Signed-off-by: Stefan Roese s...@denx.de Reviewed-by: Tom Rini tr...@konsulko.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-x86 branch 'buildman'
On Thu, Apr 23, 2015 at 12:39:41PM -0600, Simon Glass wrote: Hi Tom, Note this is branch 'buildman'. The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06: serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400) are available in the git repository at: http://git.denx.de/u-boot-x86.git for you to fetch changes up to 3871cd858fcf8a00e31c2f456409afea03ce8788: patman: check git format.subjectprefix setting when generate patches prefix (2015-04-23 12:35:50 -0600) Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] davinci: add support for omapl138-lcdk board
On Mon, Mar 23, 2015 at 09:19:56AM +1100, Peter Howard wrote: Signed-off-by: Peter Howard phow...@gme.net.au Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Booting Xen from a FIT - Additional discussion about a refactor
On 04/23/2015 01:06 PM, Simon Glass wrote:
Hi Karl,
On 23 April 2015 at 07:15, Karl Apsite karl.aps...@dornerworks.com wrote:
On 04/22/2015 09:55 PM, Simon Glass wrote:
+Tom
Hi Karl,
On 22 April 2015 at 13:05, Karl Apsite karl.aps...@dornerworks.com wrote:
Hi!
I work at DornerWorks with the Xen Hypervisor. We work with a variety of
embedded systems, and we wanted to facilitate Xen's boot procedure through
U-boot's Flattened Image Tree (FIT) format. I've already prototyped some
of the
functionality we were hoping to see, so we thought it'd be prudent to
begin a
discussion with denx to get your opinion on the matter,
First Objective: (Summary of what was prototyped)
A Flattened Image Tree is capable of holding all of the necessary binaries
already, so we only need to make a quick change to allow u-boot to load an
extra
binary (in this case, a linux kernel) so that Xen can boot and load the
kernel
when it's ready. I started by simply adding a line in the configuration
of my
tree-source (.its) to look like:
config@1 {
description = Xen 4.6.0-unstable configuration;
kernel = xen_kernel@1;
fdt = fdt@1;
gen_bin0 = linux_kernel@1;
};
I investigated what effort would be needed to load the additional binary.
Booting Xen is easy (only a kernel and fdt are required), but Xen will
look at a
hard-coded memory address to try a load a linux kernel. This has to be
placed
in memory by u-boot. The only major addition I needed, was to make u-boot
care
about a config option named generic-binary and load it, no questions
asked. I
chose the name generic binary as I simply needed u-boot to load a [thing]
without any additional behavior. I'm using it to specifically load a linux
kernel at a specific memory address in preparation for xen, but there
could be
potential future uses, hence the ambiguous name.
I wonder whether you should add a new type for the target kernel?
General binary seems a bit vague. Just a thought.
I do agree, I don't really like the term generic binary either.
When preparing to boot Xen, u-boot needs to take a binary, and simply put it
in
place. Unlike the other images/objects (kernel, fdt, ramdisk, etc) u-boot's
role is very simple in this regard: Take these bits, and make sure they go
over
here.
In this scenario, the action taken by u-boot should be agnostic to what the
image actually is. U-boot should simply move a binary, without any
additional
behavior. This led me to choose a name just as generic.
What is this additional behaviour you are referring to?
In each of the existing boot_get_thing functions, I saw that U-boot stores
various addresses in the images parameter: bootm_headers_t *images. I am making
an assumption that these addresses are used later for any possible additional
behaviors. That could very well be a misunderstanding, but I thought those
addresses are used by u-boot later in the boot process.
Maybe changing the name to Loadable(s) would sound a bit better, but going
so
far as to name it kernel could be misleading.
The hack is pretty simple, as most everything was in place to boot xen,
and it
took a little extra legwork to make u-boot care about my gen_bin. I added
the
necessary structure to load another object using ramdisk functions as
examples.
By loading a separate binary, Xen was able to boot, and successively boot
Linux
as expected. If you have any thoughts on this process overall, we'd like
to
take your concerns into consideration.
For a little more fun, I extended out the configuration to be able to load
N
number of generics.
This plan was part of the reason we were trying to keep the name more
generic.
Keeping it generic allows for people other than xen users to take advantage
of
the new feature in various ways.
Affected Files:
common/bootm.c
common/image-fit.c
common/image.c
doc/uImage.FIT/source_file_format.txt
include/configs/xilinx_zynqmp.h
include/image.h
Second Objective:
While I was there, I noticed that u-boot's binary loading logic isn't as
modular
as I first expected. Most objects eventually boil down to a
boot_get_thing().
Example: boot_get_ramdisk() or boot_get_kernel(). These functions are all
very
similar as they handle the various u-boot image types and load their
specific
binary. The functions appear to have grown similar in structure and
operation
overtime. I don't think it is too much to reduce the duplicated structure
of
the functions into a common boot_get_object() function, while replacing
some of
the extra function wrappings.
Some quick diagrams to explain what I mean
Initial: http://i.imgur.com/H44dXmN.png (29KB)
Refactor: http://i.imgur.com/apEpyWz.png (24KB)
SGTM.
The refactor will likely effect the following files, several of which
contain
trivial name changes, or small changes in a variable type.
arch/arm/lib/bootm.c
arch/avr32/lib/bootm.c
[U-Boot] unassigned-patches/139: [PATCH 1/4] x86: baytrail: fix the GPIOBASE address
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr --- Added to GNATS database as unassigned-patches/139 Responsible:patch-coord Message-Id: 1429805775-1809-2-git-send-email-cont...@huau-gabriel.fr In-Reply-To:1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr References: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr Patch-Date: Thu Apr 23 18:16:12 +0200 2015 --- arch/x86/include/asm/arch-baytrail/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] unassigned-patches/140: [PATCH 2/4] x86: minnowmax: add GPIO banks in the device tree
There is 6 banks:
4 banks for CORE: available in S0 mode
2 banks for SUS (Suspend): available in S0-S5 mode
Signed-off-by: Gabriel Huau cont...@huau-gabriel.fr
---
Added to GNATS database as unassigned-patches/140
Responsible:patch-coord
Message-Id: 1429805775-1809-3-git-send-email-cont...@huau-gabriel.fr
In-Reply-To:1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr
References: 1429805775-1809-1-git-send-email-cont...@huau-gabriel.fr
Patch-Date: Thu Apr 23 18:16:13 +0200 2015
---
arch/x86/dts/minnowmax.dts | 42 ++
1 file changed, 42 insertions(+)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 8f34369..c73e421 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -21,6 +21,48 @@
silent_console = 0;
};
+ gpioa {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0 0x20;
+ bank-name = A;
+ };
+
+ gpiob {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x20 0x20;
+ bank-name = B;
+ };
+
+ gpioc {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x40 0x20;
+ bank-name = C;
+ };
+
+ gpiod {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x60 0x20;
+ bank-name = D;
+ };
+
+ gpioe {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0x80 0x20;
+ bank-name = E;
+ };
+
+ gpiof {
+ compatible = intel,ich6-gpio;
+ u-boot,dm-pre-reloc;
+ reg = 0xA0 0x20;
+ bank-name = F;
+ };
+
chosen {
stdout-path = /serial;
};
--
2.1.4
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[U-Boot] Commands to partition the hw partitions on emmc using uboot 2015-04
Hi !
I am unable to create the hardware (gp1-4) partitions my eMMC on a custom
board using the new Uboot(2015.04). I think i am missing something in my
commands..I was wondering if someone can point at the mistake i am doing..
i am trying to create a gp1 partition with 7009.875 MB and SLC on and wrrel
off..
mmc hwpartition [args...] - does hardware partitioning
arguments (sizes in 512-byte blocks):
[user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes
[gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition
[check|set|complete] - mode, complete set partitioning completed
WARNING: Partitioning is a write-once setting once it is set to complete.
Power cycling is required to initialize partitions after set to complete.
mmc hwpartition gp1 14356224 - did not work
mmc hwpartition gp1 14356224 1 wrrel 0ff - did not work
mmc hwpartition gp1 14356224 [1] wrrel off -- did not work
mmc hwpartition gp1 14356224 1 0 -- did not work
mmc hwpartition gp1 14356224 [enh] off -- did not work
U-Boot# mmc hwpartition check
Partition configuration:
No enhanced user data area
No GP1 partition
No GP2 partition
No GP3 partition
No GP4 partition
Thanks,
Harsha
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Sent from the U-Boot mailing list archive at Nabble.com.
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[U-Boot] [PATCH 3/4][v2]include:configs:ls1021atwr: Enable USB IP support
Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
include/configs/ls1021atwr.h | 36
include/linux/usb/xhci-fsl.h | 5 +
2 files changed, 41 insertions(+)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a13876b..f208638 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -28,6 +28,42 @@
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
+ * USB
+ */
+
+/* EHCI Support - disbaled by default as
+ * there is no signal coming out of soc on
+ * this board for this controller. However,
+ * the silicon still has this controller,
+ * and anyone can use this controller by
+ * taking signals out on their board.
+ */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/* XHCI Support - enabled by default */
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
* Generic Timer Definitions
*/
#define GENERIC_TIMER_CLK 1250
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 8eaab2c..329abf7 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -46,6 +46,11 @@
#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_ENBIT(17)
+#ifdef CONFIG_LS102XA
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#endif
+
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
--
1.8.3.1
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Re: [U-Boot] [PATCH 3/5] mx6cuboxi: Introduce multi-SoC support
On Thu, Apr 23, 2015 at 12:57:04AM -0300, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite, mx6dual and mx6quad. Add support for the different SoC/memory sizes combinations. Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1. Signed-off-by: Fabio Estevam fabio.este...@freescale.com This applies to this patch as well as 4 and 5. This code looks really similar to the solid run tree and as such make sure you credit the original author from that tree. For example, 4/6 looks really really close to: commit c81b43e9e3a5cc206fc7716822362d41e8bcaef4 Author: Rabeeh Khoury rab...@solid-run.com Date: Wed May 21 14:02:52 2014 +0300 Add HummingBoard rev 3.0 detection In the Solid Run tree. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 5/5] mx6cuboxi: Load the correct 'fdt_file' variable
On 2015-04-22, Fabio Estevam wrote:
Instead of hardcoding the 'fdt_file' variable, let's introduce a new
function - build_dts_name(), that can build the dtb filename on the fly.
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 83410b2..1c24a55 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
...
+int misc_init_r(void)
+{
+ setenv(fdt_file, build_dts_name());
+ return 0;
+}
+
Shouldn't this set fdtfile instead of fdt_file?
According to top-level README, several variables are configured:
Image File NameRAM Address Flash Location
- ---- --
u-boot u-boot u-boot_addr_r u-boot_addr
Linux kernelbootfile kernel_addr_r kernel_addr
device tree blobfdtfile fdt_addr_rfdt_addr
ramdisk ramdiskfile ramdisk_addr_rramdisk_addr
FWIW, I'm happy to test and review patches for cubox-i4po, hummingboard
solo and hummingboard i2ex.
live well,
vagrant
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Re: [U-Boot] gpio: mvmfp: support newer MFP bit definitions
On Mon, Mar 23, 2015 at 05:56:58PM -0500, Rob Herring wrote: From: Xiang Wang wa...@marvell.com 1. The bits 11..10 for mfp driver strength is only valid for aspen and old xscale family, for newer Marvell chip, this range has been moved to 12..11. 2. add sleep bit support Signed-off-by: Xiang Wang wa...@marvell.com [robh: rebase to current mainline] Signed-off-by: Rob Herring r...@kernel.org Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/5] mx6cuboxi: Prepare for multi SoC support
Hi Fabio,
On 23/04/2015 05:57, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad.
Use IOMUX_PADS() macro in order to prepare for the multi-SoC support.
Also pass 'MX6QDL' in the defconfig to indicate it.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/solidrun/mx6cuboxi/mx6cuboxi.c | 60
++--
configs/mx6cuboxi_defconfig | 2 +-
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index b696dcb..0377dc4 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -28,7 +28,6 @@
#include asm/arch/crm_regs.h
#include asm/io.h
#include asm/arch/sys_proto.h
-#include asm/arch/mx6-ddr.h
#include spl.h
DECLARE_GLOBAL_DATA_PTR;
@@ -59,22 +58,22 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK| MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD| MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ SETUP_IOMUX_PADS(uart1_pads);
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
@@ -88,7 +87,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd-arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
@@ -97,33 +96,33 @@ int board_mmc_init(bd_t *bis)
}
static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8035 reset */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
/* AR8035 interrupt */
- MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* GPIO16 - AR8035 25MHz */
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8035 CLK_25M -- ENET_REF_CLK (V22) */
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
- MX6_PAD_RGMII_RD1__RGMII_RD1 |
[U-Boot] [PATCH] socfpga: implement socdk SPI flash config in dts
SocDK has same QSPI and SPI flash configuration as Socrates. Add
support for it.
Signed-off-by: Pavel Machek pa...@denx.de
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 8e1f88c..70701f0 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -25,6 +25,10 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = gmac1;
+
+ spi0 = /spi@ff705000; /* QSPI */
+ spi1 = /spi@fff0;
+ spi2 = /spi@fff01000;
};
regulator_3_3v: 3-3-v-regulator {
@@ -77,3 +81,23 @@
usb1 {
status = okay;
};
+
+qspi {
+ status = okay;
+
+ flash0: n25q00@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = n25q00;
+ reg = 0; /* chip select */
+ spi-max-frequency = 5000;
+ m25p,fast-read;
+ page-size = 256;
+ block-size = 16; /* 2^16, 64KB */
+ read-delay = 4; /* delay value in read data capture register
*/
+ tshsl-ns = 50;
+ tsd2d-ns = 50;
+ tchsh-ns = 4;
+ tslch-ns = 4;
+ };
+};
--
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http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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Re: [U-Boot] [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support
-Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: Wednesday, April 22, 2015 5:18 PM To: Mehresh Ramneek-B31383 Cc: u-boot@lists.denx.de Subject: Re: [PATCH 3/4] include:configs:ls1021atwr: Enable USB IP support On Wednesday, April 22, 2015 at 08:49:42 AM, Ramneek Mehresh wrote: Enable USB IP support for both EHCI and XHCI for ls1021atwr platform Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com --- include/configs/ls1021atwr.h | 29 + include/linux/usb/xhci-fsl.h | 5 + 2 files changed, 34 insertions(+) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a13876b..0f59b3c 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -28,6 +28,35 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* + * USB + */ +/* EHCI Support - disbaled by default */ 'disabled' +/*#define CONFIG_HAS_FSL_DR_USB*/ Why is this disabled ? EHCI is disabled because this controller is not exposed via any connector on the board. However, the silicon still has this controller, and anyone can use this controller by taking signals out on their board. XHCI can be used on the board via micro-A usb host connector [...] Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt: Fix handling of paths with options in them
Hi,
On 22-04-15 19:20, Simon Glass wrote:
Hi Hans,
On 20 April 2015 at 12:10, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 20-04-15 17:39, Simon Glass wrote:
Hi Hans,
On 20 April 2015 at 03:13, Hans de Goede hdego...@redhat.com wrote:
After syncing the sunxi dts files with the upstream kernel dm/fdt sunxi
builds would no longer boot.
The problem is that stdout-path is now set like this in the upstream dts
files: stdout-path = serial0:115200n8. The use of options in of-paths,
either after an alias name, or after a full path, e.g. stdout-path =
/soc@01c0/serial@01c28000:115200, is standard of usage, but
something
which the u-boot dts code so far did not handle.
This commit fixes this, adding support for both path formats.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/dts/sun7i-a20-pcduino3.dts | 2 +-
lib/libfdt/fdt_ro.c | 25 ++---
I haven't looked. but is this change in dtc upstream or just in the
kernel?
This is just a change in the dts files shipped with the kernel not in dtc,
the dts files for sunxi used to not set stdout-path, and you patched in
a stdout-path setting for u-boot:
In that case, can we change this in the fdt support /fdtdec code,
instead of making a change to libfdt that will never go upstream?
If that doesn't work or is too painful, then we should take this patch.
Actually I started with fixing this the fdtdev level, but then I noticed
that the kernel does this at the of_find_node_by_path level, so if we
fix this for stdout-path only (which a fdtdec patch would do) then we may
get bit by this again later.
Also fixing it at the fdtdec level means adding a strdup + error checking
since then we need to pass a truncated (options removed) copy of the path
to fdt_path_offset(), while with the current patch we can keep using
read only access to the fdt.
So I've a slight preference for going this way. Why would libfdt upstream not
take this patch ?
Regards,
Hans
http://git.denx.de/?p=u-boot.git;a=commitdiff;h=1a81cf8399675056beef5e76be8a9380d88c4ebf
+ chosen {
+ stdout-path = uart0;
+ };
But now the upstream dts contains a stdout-path itself, but like this;
alias {
serial0 = uart0;
};
chosen {
stdout-path = serial0:115200n8;
};
And the current u-boot dts parsing does not grok this due to it not
recognizing
the : in there.
Where as the kernel has:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/of/base.c#n713
static struct device_node *__of_find_node_by_path(struct device_node
*parent,
const char *path)
{
struct device_node *child;
int len;
len = strcspn(path, /:);
if (!len)
return NULL;
__for_each_child_of_node(parent, child) {
const char *name = strrchr(child-full_name, '/');
if (WARN(!name, malformed device_node %s\n,
child-full_name))
continue;
name++;
if (strncmp(path, name, len) == 0 (strlen(name) == len))
return child;
}
return NULL;
}
Where the strcspn surves the same purpose as the fdt_path_next_seperator my
patch
introduces find the basename to match for stopping at the first occurence of
either a '/' or a ':' char.
Regards,
Hans
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts
b/arch/arm/dts/sun7i-a20-pcduino3.dts
index cd05267..624abf2 100644
--- a/arch/arm/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -64,7 +64,7 @@
};
chosen {
- stdout-path = serial0:115200n8;
+ stdout-path = /soc@01c0/serial@01c28000:115200;
};
leds {
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 03733e5..44fc0aa 100644
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
@@ -113,6 +113,25 @@ int fdt_subnode_offset(const void *fdt, int
parentoffset,
return fdt_subnode_offset_namelen(fdt, parentoffset, name,
strlen(name));
}
+/*
+ * Find the next of path seperator, note we need to search for both '/'
and ':'
+ * and then take the first one so that we do the rigth thing for e.g.
+ * foo/bar:option and bar:option/otheroption, both of which happen,
so
+ * first searching for either ':' or '/' does not work.
+ */
+static const char *fdt_path_next_seperator(const char *path)
+{
+ const char *sep1 = strchr(path, '/');
+ const char *sep2 = strchr(path, ':');
+
+ if (sep1 sep2)
+ return (sep1 sep2) ? sep1 : sep2;
+ else if (sep1)
+ return sep1;
+ else
+ return sep2;
+}
+
int fdt_path_offset(const void *fdt, const char *path)
{
const char *end = path + strlen(path);
@@ -123,7
Re: [U-Boot] [PATCH 4/5] mx6cuboxi: Differentiate Cubox-i and Hummingboard
Hi Fabio,
On 23/04/2015 05:57, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Introduce is_hummingboard() function that reads GPIOs that can distinguish
between Cubox-i and Hummingboard.
Print the board name accordingly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/solidrun/mx6cuboxi/mx6cuboxi.c | 41
+++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 1f240ae..83410b2 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -71,6 +71,12 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
+static iomux_v3_cfg_t const hb_cbi_sense[] = {
+ /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
static void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
@@ -167,9 +173,42 @@ int board_init(void)
return 0;
}
+static bool is_hummingboard(void)
+{
+ int val1, val2;
+
+ SETUP_IOMUX_PADS(hb_cbi_sense);
+
+ gpio_direction_input(IMX_GPIO_NR(4, 9));
+ gpio_direction_input(IMX_GPIO_NR(3, 4));
+
+ val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
+ val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
+
+ /*
+ * Machine selection -
+ * Machineval1, val2
+ * -
+ * HB rev 3.x x 0
+ * CBi0 1
+ * HB 1 1
+ */
+
+ if (val2 == 0)
+ return true;
+ else if (val1 == 0)
+ return false;
+ else
+ return true;
+}
+
int checkboard(void)
{
- puts(Board: MX6 Hummingboard\n);
+ if (is_hummingboard())
+ puts(Board: MX6 Hummingboard\n);
+ else
+ puts(Board: MX6 Cubox-i\n);
+
return 0;
}
Reviewed-by: Stefano Babic sba...@denx.de
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [PATCH 3/5] mx6cuboxi: Introduce multi-SoC support
Hi Fabio,
On 23/04/2015 05:57, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Cubox-i and Hummingboard support several MX6 SoCs: mx6solo, mx6dual-lite,
mx6dual and mx6quad. Add support for the different SoC/memory sizes
combinations.
Tested on a CuBox-i4Pro, HummingBoard-i2eX and HummingBoard-i1.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/solidrun/mx6cuboxi/mx6cuboxi.c | 134
---
1 file changed, 125 insertions(+), 9 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 0377dc4..1f240ae 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -175,7 +175,7 @@ int checkboard(void)
#ifdef CONFIG_SPL_BUILD
#include asm/arch/mx6-ddr.h
-static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
@@ -204,7 +204,36 @@ static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs
= {
.dram_dqm7 = 0x00020030,
};
-static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
+ .dram_sdclk_0 = 0x0028,
+ .dram_sdclk_1 = 0x0028,
+ .dram_cas = 0x0028,
+ .dram_ras = 0x0028,
+ .dram_reset = 0x000c0028,
+ .dram_sdcke0 = 0x3000,
+ .dram_sdcke1 = 0x3000,
+ .dram_sdba2 = 0x,
+ .dram_sdodt0 = 0x3030,
+ .dram_sdodt1 = 0x3030,
+ .dram_sdqs0 = 0x0028,
+ .dram_sdqs1 = 0x0028,
+ .dram_sdqs2 = 0x0028,
+ .dram_sdqs3 = 0x0028,
+ .dram_sdqs4 = 0x0028,
+ .dram_sdqs5 = 0x0028,
+ .dram_sdqs6 = 0x0028,
+ .dram_sdqs7 = 0x0028,
+ .dram_dqm0 =0x0028,
+ .dram_dqm1 =0x0028,
+ .dram_dqm2 =0x0028,
+ .dram_dqm3 =0x0028,
+ .dram_dqm4 =0x0028,
+ .dram_dqm5 =0x0028,
+ .dram_dqm6 =0x0028,
+ .dram_dqm7 =0x0028,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
.grp_ddr_type = 0x000C,
.grp_ddrmode_ctl = 0x0002,
.grp_ddrpke = 0x,
@@ -221,7 +250,25 @@ static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs
= {
.grp_b7ds = 0x0030,
};
-static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c,
+ .grp_ddrmode_ctl = 0x0002,
+ .grp_ddrpke = 0x,
+ .grp_addds = 0x0028,
+ .grp_ctlds = 0x0028,
+ .grp_ddrmode = 0x0002,
+ .grp_b0ds = 0x0028,
+ .grp_b1ds = 0x0028,
+ .grp_b2ds = 0x0028,
+ .grp_b3ds = 0x0028,
+ .grp_b4ds = 0x0028,
+ .grp_b5ds = 0x0028,
+ .grp_b6ds = 0x0028,
+ .grp_b7ds = 0x0028,
+};
+
+/* microSOM with Dual processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
.p0_mpwldectrl0 = 0x,
.p0_mpwldectrl1 = 0x,
.p1_mpwldectrl0 = 0x,
@@ -236,7 +283,49 @@ static const struct mx6_mmdc_calibration mx6_mmcd_calib
= {
.p1_mpwrdlctl =0x422a423c,
};
-static struct mx6_ddr3_cfg mem_ddr = {
+/* microSOM with Quad processor and 2GB memory */
+static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x,
+ .p0_mpwldectrl1 = 0x,
+ .p1_mpwldectrl0 = 0x,
+ .p1_mpwldectrl1 = 0x,
+ .p0_mpdgctrl0 =0x0314031c,
+ .p0_mpdgctrl1 =0x023e0304,
+ .p1_mpdgctrl0 =0x03240330,
+ .p1_mpdgctrl1 =0x03180260,
+ .p0_mprddlctl =0x3630323c,
+ .p1_mprddlctl =0x3436283a,
+ .p0_mpwrdlctl =0x36344038,
+ .p1_mpwrdlctl =0x422a423c,
+};
+
+/* microSOM with Solo processor and 512MB memory */
+static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0045004D,
+ .p0_mpwldectrl1 = 0x003A0047,
+ .p0_mpdgctrl0 = 0x023C0224,
+ .p0_mpdgctrl1 = 0x02000220,
+ .p0_mprddlctl = 0x4846,
+ .p0_mpwrdlctl = 0x32343032,
+};
+
+/* microSOM with Dual lite processor and 1GB memory */
+static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x0045004D,
+ .p0_mpwldectrl1 = 0x003A0047,
+ .p1_mpwldectrl0 = 0x001F001F,
+ .p1_mpwldectrl1 = 0x00210035,
+ .p0_mpdgctrl0 =0x023C0224,
+ .p0_mpdgctrl1 =0x02000220,
+ .p1_mpdgctrl0 =0x02200220,
+ .p1_mpdgctrl1 =0x02000220,
+ .p0_mprddlctl =0x4846,
+ .p1_mprddlctl =0x4042463C,
+ .p0_mpwrdlctl =
Re: [U-Boot] [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support
-Original Message-
From: Marek Vasut [mailto:ma...@denx.de]
Sent: Wednesday, April 22, 2015 5:17 PM
To: Mehresh Ramneek-B31383
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH 2/4] drivers:usb:fsl: Add XHCI driver support
On Wednesday, April 22, 2015 at 08:49:41 AM, Ramneek Mehresh wrote:
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
Hi!
[...]
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
new file mode 100644 index 000..9d89313
--- /dev/null
+++ b/drivers/usb/host/xhci-fsl.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include usb.h
+#include asm-generic/errno.h
+/*#include asm/arch/cpu.h*/
+/*#include asm/arch/sys_proto.h*/
Remove these please .
Oops, my bad, will do
+#include linux/compat.h
+#include linux/usb/xhci-fsl.h
+#include linux/usb/dwc3.h
+#include xhci.h
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fsl_xhci fsl_xhci;
+
This will do:
agreed
__weak int board_usb_init(...)
{
return 0;
}
+inline int __board_usb_init(int index, enum usb_init_type init) {
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+ __attribute__((weak, alias(__board_usb_init)));
Drop the above, just use __weak .
+void usb_phy_reset(struct dwc3 *dwc3_reg) {
+ /* Assert USB3 PHY reset */
+ setbits_le32(dwc3_reg-g_usb3pipectl[0],
+DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Assert USB2 PHY reset */
+ setbits_le32(dwc3_reg-g_usb2phycfg,
DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+ mdelay(200);
+
+ /* Clear USB3 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb3pipectl[0],
+DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+ /* Clear USB2 PHY reset */
+ clrbits_le32(dwc3_reg-g_usb2phycfg,
DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) {
+ int ret = 0;
+
+ ret = dwc3_core_init(fsl_xhci-dwc3_reg);
+ if (ret) {
+ debug(%s:failed to initialize core\n, __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(fsl_xhci-dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) {
+ /* Currently fsl socs do not support PHY shutdown from
+* sw. But this support may be added in future socs */
Multiline comment should be in this form:
Will correct
/*
* foo
* bar
*/
+ return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct
+xhci_hcor
**hcor) +{
+ struct fsl_xhci *ctx = fsl_xhci;
+ int ret = 0;
+
+ ctx-hcd = (struct xhci_hccr *)FSL_XHCI_BASE;
+ ctx-dwc3_reg = (struct dwc3 *)(FSL_XHCI_BASE +
DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts(Failed to initialize board for USB\n);
+ return ret;
+ }
+
+ ret = fsl_xhci_core_init(ctx);
+ if (ret 0) {
+ puts(Failed to initialize xhci\n);
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)(FSL_XHCI_BASE);
+ *hcor = (struct xhci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(xhci_readl((*hccr)-
cr_capbase)));
+
+ debug(fsl-xhci: init hccr %x and hcor %x hc_length %d\n,
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(xhci_readl((*hccr)-cr_capbase)));
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ struct fsl_xhci *ctx = fsl_xhci;
+
+ fsl_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-fsl.h
b/include/linux/usb/xhci-fsl.h new file mode 100644 index
000..1751c7a
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehreshramneek.mehr...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */ #define FSL_XHCI_BASE 0x310
+#define FSL_OCP1_SCP_BASE 0x4a084c00 #define
FSL_OTG_WRAPPER_BASE
+0x4A02
This should be in CPU-specific file I guess, not in IP-specific one.
Agreed, let me check which file can be used for this
[...]
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Re: [U-Boot] [PATCH 1/5] mx6cuboxi: Fix the defconfig name
Hi Fabio, On 23/04/2015 05:57, Fabio Estevam wrote: From: Fabio Estevam fabio.este...@freescale.com The correct name of the defconfig file is 'mx6cuboxi_defconfig'. Signed-off-by: Fabio Estevam fabio.este...@freescale.com --- board/solidrun/mx6cuboxi/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS index 3d468ed..a3506c2 100644 --- a/board/solidrun/mx6cuboxi/MAINTAINERS +++ b/board/solidrun/mx6cuboxi/MAINTAINERS @@ -3,4 +3,4 @@ M:Fabio Estevam fabio.este...@freescale.com S: Maintained F: board/solidrun/mx6cuboxi/ F: include/configs/mx6cuboxi.h -F: configs/mx6cuboxi_spl_defconfig +F: configs/mx6cuboxi_defconfig Reviewed-by: Stefano Babic sba...@denx.de Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] mx6cuboxi: Load the correct 'fdt_file' variable
Hi Fabio,
On 23/04/2015 05:57, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
Instead of hardcoding the 'fdt_file' variable, let's introduce a new
function - build_dts_name(), that can build the dtb filename on the fly.
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
board/solidrun/mx6cuboxi/mx6cuboxi.c | 24
include/configs/mx6cuboxi.h | 3 +--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c
b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 83410b2..1c24a55 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -212,6 +212,30 @@ int checkboard(void)
return 0;
}
+static const char *build_dts_name(void)
+{
+ char *dt_prefix = unknown;
+ char *dt_suffix = unknown;
+
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ dt_prefix = imx6q;
+ else if (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+ dt_prefix = imx6dl;
+
+ if (is_hummingboard())
+ dt_suffix = -hummingboard.dtb;
+ else
+ dt_suffix = -cubox-i.dtb;
+
+ return strcat(dt_prefix, dt_suffix);
+}
+
I admit I do not like a lot to have C code setting / fixing the
environment. This has the drawback that when a user try to set the
environment from the console as he wants, he cannot because the code has
reverted back and it is not easy to track. I would like to propose
another solution.
What about to export your is_hummingboard() function as U-Boot command ?
You can then use it in U-Boot scripts, and the correct fdt name can be
set in the bootcmd variable. Something like if is_humming;then ...
And if a user wants to use other names, he can because it is not hard-coded.
+int misc_init_r(void)
+{
+ setenv(fdt_file, build_dts_name());
+ return 0;
+}
+
#ifdef CONFIG_SPL_BUILD
#include asm/arch/mx6-ddr.h
static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index 5d58b16..504a81c 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -29,6 +29,7 @@
#define CONFIG_SYS_MALLOC_LEN(2 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_CMD_FUSE
@@ -81,14 +82,12 @@
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV ttymxc0
#define CONFIG_MMCROOT /dev/mmcblk0p2
-#define CONFIG_DEFAULT_FDT_FILE imx6q-hummingboard.dtb
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */
#define CONFIG_EXTRA_ENV_SETTINGS \
script=boot.scr\0 \
image=zImage\0 \
- fdt_file= CONFIG_DEFAULT_FDT_FILE \0 \
I do not exclude that the board will switch to distro environment, and
we will have a strong dependency with the code then.
Best regards,
Stefano
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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Re: [U-Boot] [U-Boot PATCH 6/8] spi: xilinx_spi: Driver clean-up
On 22 April 2015 at 18:10, Michal Simek michal.si...@xilinx.com wrote:
On 04/21/2015 08:27 PM, Jagannadha Sutradharudu Teki wrote:
- Zap unneeded macros
- Re-arrange the code
- Removed __attribute__((weak))
- Replace __func__ macro with func names to save macro transition.
- Re-arranged comment lines.
- Arrange driver code in more readable format[1]
[1] http://lists.denx.de/pipermail/u-boot/2013-August/160473.html
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Michal Simek michal.si...@xilinx.com
---
drivers/spi/xilinx_spi.c | 164
---
1 file changed, 57 insertions(+), 107 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8073edc..650e494 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -1,79 +1,31 @@
/*
* Xilinx SPI driver
*
- * supports 8 bit SPI transfers only, with or w/o FIFO
+ * Supports 8 bit SPI transfers only, with or w/o FIFO
*
- * based on bfin_spi.c, by way of altera_spi.c
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
- * Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
+ * Based on bfin_spi.c, by way of altera_spi.c
* Copyright (c) 2012 Stephan Linz l...@li-pro.net
+ * Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
+ * Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* SPDX-License-Identifier: GPL-2.0+
- *
- * [0]: http://www.xilinx.com/support/documentation
- *
- * [S]: [0]/ip_documentation/xps_spi.pdf
- * [0]/ip_documentation/axi_spi_ds742.pdf
*/
+
#include config.h
#include common.h
#include malloc.h
#include spi.h
/*
- * Xilinx SPI Register Definition
+ * [0]: http://www.xilinx.com/support/documentation
*
+ * Xilinx SPI Register Definitions
* [1]: [0]/ip_documentation/xps_spi.pdf
* page 8, Register Descriptions
* [2]: [0]/ip_documentation/axi_spi_ds742.pdf
* page 7, Register Overview Table
*/
-struct xilinx_spi_reg {
- u32 __space0__[7];
- u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
- u32 ipisr; /* IP Interrupt Status Register (IPISR) */
- u32 __space1__;
- u32 ipier; /* IP Interrupt Enable Register (IPIER) */
- u32 __space2__[5];
- u32 srr;/* Softare Reset Register (SRR) */
- u32 __space3__[7];
- u32 spicr; /* SPI Control Register (SPICR) */
- u32 spisr; /* SPI Status Register (SPISR) */
- u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
- u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
- u32 spissr; /* SPI Slave Select Register (SPISSR) */
- u32 spitfor;/* SPI Transmit FIFO Occupancy Register (SPITFOR) */
- u32 spirfor;/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
-};
-
-/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
-#define DGIER_GIE(1 31)
-
-/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
-#define IPISR_DRR_NOT_EMPTY (1 8)
-#define IPISR_SLAVE_SELECT (1 7)
-#define IPISR_TXF_HALF_EMPTY (1 6)
-#define IPISR_DRR_OVERRUN(1 5)
-#define IPISR_DRR_FULL (1 4)
-#define IPISR_DTR_UNDERRUN (1 3)
-#define IPISR_DTR_EMPTY (1 2)
-#define IPISR_SLAVE_MODF (1 1)
-#define IPISR_MODF (1 0)
-
-/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
-#define IPIER_DRR_NOT_EMPTY (1 8)
-#define IPIER_SLAVE_SELECT (1 7)
-#define IPIER_TXF_HALF_EMPTY (1 6)
-#define IPIER_DRR_OVERRUN(1 5)
-#define IPIER_DRR_FULL (1 4)
-#define IPIER_DTR_UNDERRUN (1 3)
-#define IPIER_DTR_EMPTY (1 2)
-#define IPIER_SLAVE_MODF (1 1)
-#define IPIER_MODF (1 0)
-
-/* Softare Reset Register (srr), [1] p9, [2] p8 */
-#define SRR_RESET_CODE 0x000A
/* SPI Control Register (spicr), [1] p9, [2] p8 */
#define SPICR_LSB_FIRST (1 9)
@@ -110,17 +62,42 @@ struct xilinx_spi_reg {
#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
#define SPISSR_OFF ~0UL
-/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
-#define SPITFOR_OCYVAL_POS 0
-#define SPITFOR_OCYVAL_MASK (0xf SPITFOR_OCYVAL_POS)
-
-/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
-#define SPIRFOR_OCYVAL_POS 0
-#define SPIRFOR_OCYVAL_MASK (0xf SPIRFOR_OCYVAL_POS)
-
/* SPI Software Reset Register (ssr) */
#define SPISSR_RESET_VALUE 0x0a
+#define XILSPI_MAX_XFER_BITS 8
+#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
+ SPICR_SPE)
+#define XILSPI_SPICR_DFLT_OFF(SPICR_MASTER_INHIBIT |
SPICR_MANUAL_SS)
+
+#ifndef CONFIG_XILINX_SPI_IDLE_VAL
+#define
Re: [U-Boot] [PATCH v5 2/3] mtd, nand: move common functions from cmd_nand.c to common place
On Thu, 2015-04-23 at 07:57 +0200, Heiko Schocher wrote:
Hello Scott,
Am 23.04.2015 00:47, schrieb Scott Wood:
On Mon, 2015-04-20 at 07:47 +0200, Heiko Schocher wrote:
@@ -322,7 +213,12 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char
*const argv[])
goto usage;
/* We don't care about size, or maxsize. */
- if (arg_off(argv[2], idx, addr, maxsize, maxsize)) {
+ if (arg_off(argv[2], idx, addr, maxsize, maxsize,
+ MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
+ puts(Offset or partition name expected\n);
+ return 1;
+ }
Use only one tab per indentation level.
You mean the line MTD_DEV_TYPE_NAND, nand_info[idx].size)) { ?
I have to move MTD_xx to the opening bracket to avoid checkpatch.pl
errors ...
If you mean the puts ... line ... fixed.
I meant the puts and return lines.
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 8666413..2861af5 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -482,5 +482,12 @@ int add_mtd_device(struct mtd_info *mtd);
int del_mtd_device(struct mtd_info *mtd);
int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *,
int);
int del_mtd_partitions(struct mtd_info *);
+
+int str2off(const char *p, loff_t *num);
+int str2long(const char *p, ulong *num);
These should be moved somewhere more generic, especially if they're no
longer file-local.
Hmm... the code is currently in drivers/mtd/mtd_uboot.c ... maybe
we add a mtd_ prefix to them? I think these functions are mtd specific ...
What is mtd-specific about them?
-Scott
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[U-Boot] [PATCH] Remove non-working address from MAINTAINER
I checked with Detlev, and sadly removing that maintainers entry is right thing to do. Signed-off-by: Pavel Machek pa...@denx.de diff --git a/MAINTAINERS b/MAINTAINERS index 067fb22..a8394f3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -383,11 +383,6 @@ F: drivers/mtd/spi/ F: drivers/spi/ F: include/spi* -TESTING -M: Detlev Zundel d...@denx.de -S: Maintained -T: git git://git.denx.de/u-boot-testing.git - TQ GROUP M: Martin Krause martin.kra...@tq-systems.de S: Maintained -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert spi: add config option to enable the WP pin function on st micron flashes
Hello Jagan, Am 22.04.2015 13:03, schrieb Jagan Teki: On 23 December 2014 at 13:45, Jagan Teki jagannadh.t...@gmail.com wrote: Hi Heiko, On 23 December 2014 at 12:04, Heiko Schocher h...@denx.de wrote: Hello Jagan, Am 22.12.2014 09:58, schrieb Jagan Teki: On 18 December 2014 at 19:21, Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com wrote: This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Heiko Schocher h...@denx.de --- README| 11 --- drivers/mtd/spi/sf_internal.h | 4 drivers/mtd/spi/sf_probe.c| 30 -- 3 files changed, 45 deletions(-) I found this issue on the aristainetos board, there the W#/Vpp signal is connected to a gpio pin. Did you test the same board on Linux? what about the status there? You can revert this patch. It seems it works not as expected, so it is better to revert it, and I maybe get time for reworking it. bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert spi: add config option to enable the WP pin function on st micron flashes
On 23 April 2015 at 18:28, Heiko Schocher h...@denx.de wrote: Hello Jagan, Am 22.04.2015 13:03, schrieb Jagan Teki: On 23 December 2014 at 13:45, Jagan Teki jagannadh.t...@gmail.com wrote: Hi Heiko, On 23 December 2014 at 12:04, Heiko Schocher h...@denx.de wrote: Hello Jagan, Am 22.12.2014 09:58, schrieb Jagan Teki: On 18 December 2014 at 19:21, Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com wrote: This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Heiko Schocher h...@denx.de --- README| 11 --- drivers/mtd/spi/sf_internal.h | 4 drivers/mtd/spi/sf_probe.c| 30 -- 3 files changed, 45 deletions(-) I found this issue on the aristainetos board, there the W#/Vpp signal is connected to a gpio pin. Did you test the same board on Linux? what about the status there? You can revert this patch. It seems it works not as expected, so it is better to revert it, and I maybe get time for reworking it. Ok, Shall I apply this revert patch? thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] buildman and multiple toolchains?
Hey, So I'm merging (or rather have merged and will push shortly) the ARMv7-M support. You can't build this with your normal arm-linux toolchain. Is there some way in buildman to be able to say, roughly: [toolchain] arm: /usr/bin/arm-linux-gnueabi armnone: /usr/bin/arm-none-eabi [toolchain-alias] stm32f429-discovery: armnone And have the 'arm' toolchain used normally for arm but 'armnone' used for the stm32f429-discovery board? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Revert spi: add config option to enable the WP pin function on st micron flashes
Hello Jagan, Am 23.04.2015 15:06, schrieb Jagan Teki: On 23 April 2015 at 18:28, Heiko Schocher h...@denx.de wrote: Hello Jagan, Am 22.04.2015 13:03, schrieb Jagan Teki: On 23 December 2014 at 13:45, Jagan Teki jagannadh.t...@gmail.com wrote: Hi Heiko, On 23 December 2014 at 12:04, Heiko Schocher h...@denx.de wrote: Hello Jagan, Am 22.12.2014 09:58, schrieb Jagan Teki: On 18 December 2014 at 19:21, Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com wrote: This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Never see the issue with N25Q128 flash without need of W#/Vpp signal during probe. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Heiko Schocher h...@denx.de --- README| 11 --- drivers/mtd/spi/sf_internal.h | 4 drivers/mtd/spi/sf_probe.c| 30 -- 3 files changed, 45 deletions(-) I found this issue on the aristainetos board, there the W#/Vpp signal is connected to a gpio pin. Did you test the same board on Linux? what about the status there? You can revert this patch. It seems it works not as expected, so it is better to revert it, and I maybe get time for reworking it. Ok, Shall I apply this revert patch? Yes, please. bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/7] Add support for Colibri Vybrid Modules
On Thu, Apr 23, 2015 at 06:08:43PM +0530, maitysancha...@gmail.com wrote:
Hello,
On 15-04-15 16:24:21, Sanchayan Maity wrote:
Hello,
This is the third version of the patchset which adds support for the
Toradex Colibri Vybrid VF50 and VF61 modules. Boot up has been tested
using the serial loader over UART. Compile tested for vf610twr_defconfig
and vf610twr_nand_defconfig as well.
First patch in the series refactors the DDR related code for use by both
the tower board and colibri modules. It also introduces a DDR3 based
JEDEC timing structure.
Second third and fourth patch in this series are improvement patches
related to RTC, SoC/CPU detection and caches.
Fifth patch introduces USB support for Vybrid modules. Much of the code
is similar to the ehci-mx6 driver. Both host and client modes are working
and DFU has also been tested with client. Currently, we restrict the
ports to be in one of host and client mode.
Sixth patch adds the actual support for the Colibri modules.
Comments and feedback are most welcome. Thanks for the feedback till
now.
The patchset is based and tested on the latest master branch as of
this writing.
Discussion on the version 2 of the patchset can be found at the below
link:
https://www.mail-archive.com/u-boot@lists.denx.de/msg168727.html
Discussion on the version 1 of the patchset can be found at the below
link:
https://www.mail-archive.com/u-boot@lists.denx.de/msg168136.html
Changes since v2:
- Rework the USB driver to use register + offset method in light of
discussion which Fabio Estevam pointed out instead of the regular
struct{} method which v2 used. The discussion is at the below link:
https://www.marc.info/?l=u-bootm=142609602127309w=2
- Reorder the patchset, putting the USB support in the end and add an
additional patch for adding USB support to Colibri modules. By chance
if more discussions happen on the USB support, this allows picking up
of atleast the first patches on which no issues have been reported so
far.
- The register definitions have been moved under arch/arm/include/asm/
imx-common in the regs-usbphy.h file. This was agreed on after
discussion with Marek and some input from Peter Chen. Since it is not
clear if SoC's other than Freescale's use the Sigmatel Phy's which seem
to be use in iMX/VF/MXS, put the USH PHY register definitions in
imx-common rather than include/usb in a chipidea specific file.
- Remove setting of a PLL divisor select which was added for USB but is
actually not required considering default value. It also seems to break
USB after my latest rebase. The file in question concerning the change
is colibri_vf.c. PLL divisor selects the PLL Multiplication factor which
by default is 0, setting Fout = Fref * 20 giving 480MHz. The earlier
patch set this to 1 giving Fout = Fref * 22 where Fref = 24MHz.
- Rebased on the latest master branch.
Changes since v1:
- Rework the USB driver to use register offsets using the regular
struct {} method
- Some cleanups and fixes in the sixth patch for the colibri_vf.h file
which takes care of environment variables in uboot
- Purge some useless defines in the fifth and sixth patch which were
related to USB.
Ping!?
Anything preventing this patch from getting applied?
I'll pick this up soon, thanks!
--
Tom
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Re: [U-Boot] [U-Boot, 2/2] unzip: add gzwrite command to write compressed image to block device
On Sun, Feb 15, 2015 at 04:16:07PM -0700, Eric Nelson wrote: Add gzwrite command to write gzip-compressed images to block devices. Input must be gzip-compressed according to RFC1952, since the crc and file size in the trailer will be confirmed during operation. The decompressed file size must be specified on the command line for images with decompressed sizes = 4GiB because the trailer only contains the low 32 bits of the original file size. Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,3/4] stm32f4: Add serial driver
On Sun, Mar 01, 2015 at 12:44:41PM +0100, re...@wp.pl wrote: Signed-off-by: Kamil Lulko re...@wp.pl Reviewed-by: Tom Rini tr...@konsulko.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, V2, 1/2] gunzip: add gzwrite routine for extracting compresed images to block device
On Tue, Feb 17, 2015 at 11:30:30AM -0700, Eric Nelson wrote: Initial filesystem images are generally highly compressible. Add a routine gzwrite that allows gzip-compressed images to be written to block devices. Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com Reviewed-by: Tom Rini tr...@ti.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/4] ARMv7M: Add STM32F4 support
On Sun, Mar 01, 2015 at 12:44:40PM +0100, re...@wp.pl wrote: Signed-off-by: Kamil Lulko re...@wp.pl Reviewed-by: Tom Rini tr...@konsulko.com Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/4] ARM: Add ARMv7-M support
On Sun, Mar 01, 2015 at 12:44:39PM +0100, re...@wp.pl wrote: Signed-off-by: Kamil Lulko re...@wp.pl Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
