Re: [U-Boot] [PATCH v2 5/5] cgtqmx6eval: Protect the manufacturing information in SPI NOR
On 25 September 2015 at 22:33, Otavio Salvador wrote: > Hello Jagan, > > On Thu, Sep 24, 2015 at 5:03 PM, Jagan Teki wrote: > ... >> "sf protect on off len" then based on the offset and len write the >> protected bits and skips the sectors which are protected by showing >> warning say "protected sectors will not be erased!" [1]" > > What about creating commands doing like this instead? > > "sf protect 000" ---> Write 000 to BP2 BP1 BP0 (do not protect any sector) > "sf protect 001" ---> Write 001 to BP2 BP1 BP0 (protect the last 1/64 sectors) > ... > "sf protect 111" ---> Write 111 to BP2 BP1 BP0" (protect all sectors) This would rather un-obvious implementation, how can use controls register bits, from user point-of-view flash can be accessed in-terms of offset, size. > > Would this method be acceptable? It much simpler. > > I don't think that the proposed "sf protect on off len" would apply to > the SPI NOR protection layout. No, it would apply any flash-layout not only for SPI-NOR, in fact it is much known and acceptable way of implementation - see cfi flash for example(both in Linux, U-Boot) and same case with SPI-NOR on Linux[1] > > Please advise. [1] https://patchwork.ozlabs.org/patch/513041/ -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v7 1/6] spi: cadence_qspi: move trigger base configuration in init
Thanks Wolfgang, > -Original Message- > From: Wolfgang Denk [mailto:w...@denx.de] > Sent: Thursday, September 24, 2015 3:32 PM > To: Jagan Teki > Cc: Vikas MANOCHA; u-boot@lists.denx.de; ma...@denx.de; s...@denx.de; > grmo...@opensource.altera.com > Subject: Re: [U-Boot] [PATCH v7 1/6] spi: cadence_qspi: move trigger base > configuration in init > > Dear Jagan, > > In message gv4...@mail.gmail.com> you wrote: > > > > What if we move Vikas changes now for this release as he stated in > > previous mail "about sending patches later". > > Well, we've been there too many times before. In to many cases, the "later" > just did not happen. To ensure it this time, I can add a patch for the same on top of these patches in next version :-) > > > My idea is someone is trying to clean it up existing code then give > > him a chance to move his code as well because he sent couple times. > > Well, I think it would be better to clean up first, instead of just > reshuffeling > the crappy code. > > Also, I would like to hear a comment about comparing the efforts (and > benefits) of cleaning up this stuff versus doing a clean port of the Linux > version of that driver. I think it makes sense. Although both drivers (uboot, linux) have lot of similarities, there are differences also. It would be good to sync up. Rgds, Vikas > > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de > Eureka! -- Archimedes ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] doc: Complement document about booting VxWorks
On Thu, Sep 24, 2015 at 02:21:24AM -0700, Bin Meng wrote: > Current document about how to boot VxWorks is limited. > Add several chapters in README.vxworks to document this. > > Signed-off-by: Bin Meng > Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/8] cmd: bootvx: Pass E820 information to an x86 VxWorks kernel
On Thu, Sep 24, 2015 at 02:21:23AM -0700, Bin Meng wrote: > E820 is critical to the kernel as it provides system memory map > information. Pass it to an x86 VxWorks kernel. > > Signed-off-by: Bin Meng Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8] cmd: bootvx: Always get VxWorks bootline from env
On Thu, Sep 24, 2015 at 02:21:22AM -0700, Bin Meng wrote: > So far VxWorks bootline can be contructed from various environment > variables, but when these variables do not exist we get these from > corresponding config macros. This is not helpful as it requires > rebuilding U-Boot, and to make sure these config macros take effect > we should not have these environment variables. This is a little > bit complex and confusing. > > Now we change the logic to always contruct the bootline from > environments (the only single source), by adding two new variables > "bootdev" and "othbootargs", and adding some comments about network > related settings mentioning they are optional. The doc about the > bootline handling is also updated. > > Signed-off-by: Bin Meng Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8] cmd: elf: Reorder load_elf_image_phdr() and load_elf_image_shdr()
On Thu, Sep 24, 2015 at 02:21:20AM -0700, Bin Meng wrote: > Move load_elf_image_phdr() and load_elf_image_shdr() to the beginning > of the cmd_elf.c so that forward declaration is not needed. > > Signed-off-by: Bin Meng Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/8] cmd: Clean up cmd_elf a little bit
On Thu, Sep 24, 2015 at 02:21:19AM -0700, Bin Meng wrote: > This commit cleans up cmd_elf.c per U-Boot coding convention, > and removes the unnecessary DECLARE_GLOBAL_DATA_PTR and out-of-date > powerpc comments (it actually supports not only powerpc targets). > > Signed-off-by: Bin Meng Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/8] cmd: Convert CONFIG_CMD_ELF to Kconfig
On Thu, Sep 24, 2015 at 02:21:18AM -0700, Bin Meng wrote: > configs/A10-OLinuXino-Lime_defconfig| 2 +- > configs/Bananapi_defconfig | 2 +- > configs/Bananapro_defconfig | 2 +- > configs/Chuwi_V7_CW0825_defconfig | 2 +- > configs/M5208EVBE_defconfig | 2 +- > configs/M52277EVB_defconfig | 2 +- > configs/M5235EVB_defconfig | 2 +- > configs/M5272C3_defconfig | 2 +- > configs/M5275EVB_defconfig | 2 +- > configs/M5282EVB_defconfig | 2 +- > configs/M53017EVB_defconfig | 2 +- > configs/M5329AFEE_defconfig | 2 +- > configs/M5329BFEE_defconfig | 2 +- > configs/M5373EVB_defconfig | 2 +- > configs/M54418TWR_defconfig | 2 +- > configs/M54418TWR_nand_mii_defconfig| 2 +- > configs/M54418TWR_nand_rmii_defconfig | 2 +- > configs/M54418TWR_nand_rmii_lowfreq_defconfig | 2 +- > configs/M54418TWR_serial_mii_defconfig | 2 +- > configs/M54418TWR_serial_rmii_defconfig | 2 +- > configs/M54451EVB_defconfig | 2 +- > configs/M54455EVB_defconfig | 2 +- > configs/M5475AFE_defconfig | 2 +- > configs/M5475BFE_defconfig | 2 +- > configs/M5475CFE_defconfig | 2 +- > configs/M5475DFE_defconfig | 2 +- > configs/M5475EFE_defconfig | 2 +- > configs/M5475FFE_defconfig | 2 +- > configs/M5475GFE_defconfig | 2 +- > configs/M5485AFE_defconfig | 2 +- > configs/M5485BFE_defconfig | 2 +- > configs/M5485CFE_defconfig | 2 +- > configs/M5485DFE_defconfig | 2 +- > configs/M5485EFE_defconfig | 2 +- > configs/M5485FFE_defconfig | 2 +- > configs/M5485GFE_defconfig | 2 +- > configs/M5485HFE_defconfig | 2 +- > configs/MPC8349ITXGP_defconfig | 2 +- > configs/MPC8349ITX_LOWBOOT_defconfig| 2 +- > configs/MPC8349ITX_defconfig| 2 +- > configs/MSI_Primo81_defconfig | 2 +- > configs/Mini-X_defconfig| 2 +- > configs/PATI_defconfig | 2 +- > configs/UCP1020_defconfig | 2 +- > configs/VCMA9_defconfig | 2 +- > configs/Wexler_TAB7200_defconfig| 2 +- > configs/ac14xx_defconfig| 2 +- > configs/alt_defconfig | 2 +- > configs/am335x_boneblack_defconfig | 2 +- > configs/am335x_gp_evm_defconfig | 1 - > configs/am335x_sl50_defconfig | 1 - > configs/am3517_crane_defconfig | 2 +- > configs/am3517_evm_defconfig| 2 +- > configs/amcore_defconfig| 2 +- > configs/apalis_t30_defconfig| 4 +-- > configs/apf27_defconfig | 2 +- > configs/arcangel4-be_defconfig | 2 +- > configs/arcangel4_defconfig | 4 +-- > configs/arndale_defconfig | 4 +-- > configs/astro_mcf5373l_defconfig| 2 +- > configs/at91rm9200ek_defconfig | 2 +- > configs/at91rm9200ek_ram_defconfig | 2 +- > configs/at91sam9260ek_dataflash_cs0_defconfig | 2 +- > configs/at91sam9260ek_dataflash_cs1_defconfig | 2 +- > configs/at91sam9260ek_nandflash_defconfig | 2 +- > configs/at91sam9261ek_dataflash_cs0_defconfig | 2 +- > configs/at91sam9261ek_dataflash_cs3_defconfig | 2 +- > configs/at91sam9261ek_nandflash_defconfig | 2 +- > configs/at91sam9263ek_dataflash_cs0_defconfig | 2 +- > configs/at91sam9263ek_dataflash_defconfig | 2 +- > configs/at91sam9263ek_nandflash_defconfig | 2 +- > configs/at91sam9263ek_norflash_boot_defconfig | 2 +- > configs/at91sam9263ek_norflash_defconfig| 2 +- > configs/at91sam9g10ek_dataflash_cs0_defconfig | 2 +- > configs/at91sam9g10ek_dataflash_cs3_defconfig | 2 +- > configs/at91sam9g10ek_nandflash_defconfig | 2 +- > configs/at91sam9g20ek_2mmc_defconfig| 2 +- > configs/at91sam9g20ek_2mmc_nandflash_defconfig | 2 +- > configs/at91sam9g20ek_dataflash_cs0_defconfig | 2 +- > configs/at91sam9g20ek_dataflash_cs1_defconfig | 2 +- > configs/at91sam9g20ek_nandflash_defconfig | 2 +- > configs/at91sam9m10g45ek_mmc_defconfig | 2 +- > configs/at91sam9m10g45ek_nandflash_defconfig| 2 +- > configs/at91sam9n12ek_mmc_defconfig
[U-Boot] Improving DRAM settings for Allwinner A10/A13/A20 devices
Hello, This is a reply to an old thread http://lists.denx.de/pipermail/u-boot/2015-February/205761.html On Sat, 21 Feb 2015 10:41:48 +0100 Hans de Goede wrote: > On 20-02-15 19:33, Siarhei Siamashka wrote: > > On Fri, 20 Feb 2015 15:11:04 +0100 > > > > The sun4i/sun5i/sun7i DRAM controller code in u-boot is ready for much > > faster DRAM clock speeds since the v2014.10 release. We are only > > missing the appropriate 'dram_para' settings for the boards, which can > > be prepared/verified according to the instructions from the linux-sunxi > > wiki. But there does not seem to be much interest in the performance > > and reliability for the sunxi boards yet. And participation of the > > hardware vendors (for doing large scale tests on many boards) is > > missing too. > > > > Maybe now after the introduction of the Raspberry Pi 2, the Allwinner > > based devboard manufacturers might become a bit more interested in > > tweaking the performance in order to remain competitive. > > > > I believe that every Cubietruck user had more than enough time to > > try my 'highspeedtruck' branches posted at > > > > http://lists.denx.de/pipermail/u-boot/2014-July/183981.html > > > > That's "the proof of the pudding", which demonstrates what is > > possible with this hardware :-) > > I still believe that the only way to get anywhere wrt getting better > DRAM speeds is to just make the change. As said before if you submit > patches to increase DRAM speed on some boards I'll put them in > my personal sunxi-wip and the official u-boot-sunxi/next asap, Just to make it clear. I'm still not in favour of pushing potentially reliability degrading changes to any repository, where they can be picked up by unsuspecting users. And I'm going to be strict about it, so no compromise is possible. Sorry about this. The users must be well aware of what they are trying, which tests to run and what kind of feedback is expected from them. Otherwise very few will notice anything even if they get unreliable DRAM setup. A good example is the unstable "1008MHz, 1.4V" CPU voltage/frequency configuration on the A10-Lime board. Only a small fraction of boards was affected, and the symptoms were not very obvious (it is not like the board fails to boot). And the users had to unnecessarily play the "guinea pig" role for a very long time. As I said, the best possible scenario would be a participation of the board manufacturers (OLIMEX, CubieTech, LeMaker, ...). So that we could collect sufficient statistics from multiple board samples (preferably from different batches) and check whether we can select the settings, which work fine on all of them. But if there is no interested board manufacturer, then the only option is to ask users for help. Unfortunately the users are not always cooperative and disciplined. So it becomes a real hassle in practice. We already got some interesting results though. For example, Adam Sampson tried to follow the guide from the linux-sunxi wiki and run my DRAM settings bruteforcing scripts on two pcDuino3 Nano boards. He also managed to reach 648MHz DRAM clock speed (though increasing MBUS to anything higher than 300MHz resulted in stability problems). It's surely good that we can potentially get into the 600MHz DRAM clock speed range on one more board model in addition to Cubietruck and A13-OLinuXino-Micro. But the most interesting part is that he had the results updated in real time on a web server as the scripts were progressing (now this link contains the final report): http://stuff.offog.org/tpr3.html The Adam's work also demonstrated that the current scripts do not support efficient handling of multiple boards at one. The html report is a bit messy when there is more than one board. I could try to introduce some improvements in this area. And inspired by Adam's web server usage for real-time progress tracking, in fact it may be beneficial to move from the current NFS based setup to a server in the Internet, which could show statistics in realtime, implement a simple communication protocol and coordinate the DRAM settings bruteforcing process by issuing commands to the connected "slave" devices. Anyone who is interested in participating, would only need to use a special bootable SD card and just let the device out in the Internet... However now I'm really disappointed in the whole idea of relying on anyone else, because this proved to be really inefficient. So I have bought 5 pcDuino V2 boards myself from http://www.exp-tech.de/pcduino-v2-linux-android-arduino-dev-board They are currently available at a discounted price 22.5 euro, which seemed to be a reasonably good deal for me :-) I'm just going to take care of tuning the DRAM settings for pcDuino V2. But I'm not setting any deadline and will do it as time permits. And then we can see what happens. After I'm done experimenting with the DRAM settings, I will probably donate extra boards to other people. And we still do have preliminary DRAM sett
Re: [U-Boot] [PATCH 00/10] Kconfig and ti omap configs tidy up
On Thu, Sep 24, 2015 at 12:53:32PM +0300, Igor Grinberg wrote: > Hi Tom, > > On 08/26/15 17:54, Igor Grinberg wrote: > > The patch set is aimed to transferring several config options > > from the old config.h configuration style to the new Kconfig > > framework and also move some of the existing (in Kconfig) ones > > from config.h style to the defconfig style in the ti-omap land. > > > > It is based on the 7d31c6a (Merge git://git.denx.de/u-boot-pxa) commit > > upstream. > > > > Igor Grinberg (10): > > configs: remove remnants of CONFIG_SYS_NAND_QUIET_TEST > > Kconfig: fix typo in CONFIG_FIT description > > Can the above two be applied please? > I'm going to rework the below ones (once I've got some time...), > but above two can be applied. OK, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/5] cgtqmx6eval: Protect the manufacturing information in SPI NOR
Hello Jagan, On Thu, Sep 24, 2015 at 5:03 PM, Jagan Teki wrote: ... > "sf protect on off len" then based on the offset and len write the > protected bits and skips the sectors which are protected by showing > warning say "protected sectors will not be erased!" [1]" What about creating commands doing like this instead? "sf protect 000" ---> Write 000 to BP2 BP1 BP0 (do not protect any sector) "sf protect 001" ---> Write 001 to BP2 BP1 BP0 (protect the last 1/64 sectors) ... "sf protect 111" ---> Write 111 to BP2 BP1 BP0" (protect all sectors) Would this method be acceptable? It much simpler. I don't think that the proposed "sf protect on off len" would apply to the SPI NOR protection layout. Please advise. -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://code.ossystems.com.br Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] gpio: tegra: remove unused type
From: Stephen Warren These enum values aren't used anywhere. Remove them. Signed-off-by: Stephen Warren --- This series depends on my previous "ARM: tegra: don't enable GPIOs until direction is set" drivers/gpio/tegra_gpio.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 2dfd02d62053..f9c06fe88b71 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -25,13 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -enum { - TEGRA_CMD_INFO, - TEGRA_CMD_PORT, - TEGRA_CMD_OUTPUT, - TEGRA_CMD_INPUT, -}; - struct tegra_gpio_platdata { struct gpio_ctlr_bank *bank; const char *port_name; /* Name of port, e.g. "B" */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] gpio: tegra: use named constants
From: Stephen Warren In order to make it clear what the parameters to set_config() and set_direction() mean, and similarly for the return values from the respective get_*(), define named constants for these values. Disassembly shows no diff in the generated code, except that the order of the code in the branches of tegra_gpio_get_function() gets modified without affecting behaviour. Suggested-by: Tom Warren Signed-off-by: Stephen Warren --- drivers/gpio/tegra_gpio.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index f9c06fe88b71..8e880e276f0a 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -1,6 +1,6 @@ /* * NVIDIA Tegra20 GPIO handling. - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2012,2015 * NVIDIA Corporation * * SPDX-License-Identifier:GPL-2.0+ @@ -25,6 +25,11 @@ DECLARE_GLOBAL_DATA_PTR; +static const int CONFIG_SFIO = 0; +static const int CONFIG_GPIO = 1; +static const int DIRECTION_INPUT = 0; +static const int DIRECTION_OUTPUT = 1; + struct tegra_gpio_platdata { struct gpio_ctlr_bank *bank; const char *port_name; /* Name of port, e.g. "B" */ @@ -37,7 +42,7 @@ struct tegra_port_info { int base_gpio; /* Port number for this port (0, 1,.., n-1) */ }; -/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ +/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */ static int get_config(unsigned gpio) { struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; @@ -46,15 +51,15 @@ static int get_config(unsigned gpio) int type; u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - type = (u >> GPIO_BIT(gpio)) & 1; + type = (u >> GPIO_BIT(gpio)) & 1; debug("get_config: port = %d, bit = %d is %s\n", GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - return type; + return type ? CONFIG_GPIO : CONFIG_SFIO; } -/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ +/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */ static void set_config(unsigned gpio, int type) { struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; @@ -65,7 +70,7 @@ static void set_config(unsigned gpio, int type) GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - if (type) /* GPIO */ + if (type != CONFIG_SFIO) u |= 1 << GPIO_BIT(gpio); else u &= ~(1 << GPIO_BIT(gpio)); @@ -86,7 +91,7 @@ static int get_direction(unsigned gpio) debug("get_direction: port = %d, bit = %d, %s\n", GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); - return dir; + return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT; } /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ @@ -100,7 +105,7 @@ static void set_direction(unsigned gpio, int output) GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); - if (output) + if (output != DIRECTION_INPUT) u |= 1 << GPIO_BIT(gpio); else u &= ~(1 << GPIO_BIT(gpio)); @@ -135,7 +140,7 @@ static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) struct tegra_port_info *state = dev_get_priv(dev); /* Configure GPIO direction as input. */ - set_direction(state->base_gpio + offset, 0); + set_direction(state->base_gpio + offset, DIRECTION_INPUT); /* Enable the pin as a GPIO */ set_config(state->base_gpio + offset, 1); @@ -154,7 +159,7 @@ static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, set_level(gpio, value); /* Configure GPIO direction as output. */ - set_direction(gpio, 1); + set_direction(gpio, DIRECTION_OUTPUT); /* Enable the pin as a GPIO */ set_config(state->base_gpio + offset, 1); @@ -199,18 +204,18 @@ void gpio_config_table(const struct tegra_gpio_config *config, int len) for (i = 0; i < len; i++) { switch (config[i].init) { case TEGRA_GPIO_INIT_IN: - set_direction(config[i].gpio, 0); + set_direction(config[i].gpio, DIRECTION_INPUT); break; case TEGRA_GPIO_INIT_OUT0: set_level(config[i].gpio, 0); - set_direction(config[i].gpio, 1); + set_direction(config[i].gpio, DIRECTION_OUTPUT); break; case TEGRA_GPIO_INIT_OUT1: set_level(config[i].gpio, 1); - set_direction(config[i].gpio, 1); + set_direction(config[i].
[U-Boot] [PATCH] mmc: dw_mmc: Increase timeout to 4 minutes (as in Linux kernel)
The commit: d9dbb97be0e4a550457aec5f11afefb446169c90 "mmc: dw_mmc: Zap endless timeout" removed endless loop waiting for end of dw mmc transfer. For some workloads - dfu test @ Odroid XU3 (sending 8MiB file) - and SD cards (e.g. MicroSD Kingston 4GiB, Adata 4GiB) the default timeout is to short. The new value - 4 minutes (240 seconds) - is the same as the one used in Linux kernel driver. Such fix should be good enough until we come up with better fix for this issue. Signed-off-by: Lukasz Majewski Cc: Marek Vasut Cc: Pantelis Antoniou Cc: Tom Rini --- drivers/mmc/dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index a84c1e1..26d34ae 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -214,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) { start = get_timer(0); - timeout = 1000; + timeout = 24; for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); /* Error during data transfer. */ -- 2.0.0.rc2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 7/9] armv8: cavium: Add ThunderX 88xx board definition
This commit adds basic Cavium ThunderX 88xx board definitions and support. Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla --- Changes in v6: - Added 'u-boot,skip-init' property to the FDT Changes in v5: - Added CONFIG_OF_CONTROL support - Changed memory attributes Changes in v4: - Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig - Added proper DM_SERIAL definitions Changes in v3: - Fixed formatting - Added MAINTAINERS - Moved command definitions to defconfig Changes in v2: None arch/arm/Kconfig | 7 ++ arch/arm/dts/thunderx-88xx.dtsi | 4 +- board/cavium/thunderx/Kconfig | 19 + board/cavium/thunderx/MAINTAINERS | 6 ++ board/cavium/thunderx/Makefile| 8 +++ board/cavium/thunderx/thunderx.c | 75 configs/thunderx_88xx_defconfig | 29 include/configs/thunderx_88xx.h | 146 ++ 8 files changed, 292 insertions(+), 2 deletions(-) create mode 100644 board/cavium/thunderx/Kconfig create mode 100644 board/cavium/thunderx/MAINTAINERS create mode 100644 board/cavium/thunderx/Makefile create mode 100644 board/cavium/thunderx/thunderx.c create mode 100644 configs/thunderx_88xx_defconfig create mode 100644 include/configs/thunderx_88xx.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c4371c7..66625c3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -651,6 +651,10 @@ config ARCH_ROCKCHIP select CPU_V7 select DM +config TARGET_THUNDERX_88XX + bool "Support ThunderX 88xx" + select OF_CONTROL + endchoice source "arch/arm/mach-at91/Kconfig" @@ -781,6 +785,9 @@ source "board/technologic/ts4800/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" +source "board/xaeniax/Kconfig" +source "board/zipitz2/Kconfig" +source "board/cavium/thunderx/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/dts/thunderx-88xx.dtsi b/arch/arm/dts/thunderx-88xx.dtsi index 086652f..56c0d6e 100644 --- a/arch/arm/dts/thunderx-88xx.dtsi +++ b/arch/arm/dts/thunderx-88xx.dtsi @@ -348,7 +348,7 @@ interrupts = <1 21 4>; clocks = <&refclk50mhz>; clock-names = "apb_pclk"; - flags = <1>; + u-boot,skip-init; }; uaa1: serial@87e0,2500 { @@ -357,7 +357,7 @@ interrupts = <1 22 4>; clocks = <&refclk50mhz>; clock-names = "apb_pclk"; - flags = <1>; + u-boot,skip-init; }; }; }; diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig new file mode 100644 index 000..3e62abf --- /dev/null +++ b/board/cavium/thunderx/Kconfig @@ -0,0 +1,19 @@ +if TARGET_THUNDERX_88XX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "thunderx" + +config SYS_VENDOR + string + default "cavium" + +config SYS_CONFIG_NAME + string + default "thunderx_88xx" + +endif diff --git a/board/cavium/thunderx/MAINTAINERS b/board/cavium/thunderx/MAINTAINERS new file mode 100644 index 000..c84d3b5 --- /dev/null +++ b/board/cavium/thunderx/MAINTAINERS @@ -0,0 +1,6 @@ +THUNDERX BOARD +M: Sergey Temerkhanov +S: Maintained +F: board/cavium/thunderx/ +F: include/configs/thunderx_88xx.h +F: configs/thunderx_88xx_defconfig diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile new file mode 100644 index 000..306044a --- /dev/null +++ b/board/cavium/thunderx/Makefile @@ -0,0 +1,8 @@ +# +# +# (C) Copyright 2014, Cavium Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := thunderx.o diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c new file mode 100644 index 000..486374e --- /dev/null +++ b/board/cavium/thunderx/thunderx.c @@ -0,0 +1,75 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier:GPL-2.0+ +**/ + +#include +#include +#include +#include + +#if !CONFIG_IS_ENABLED(OF_CONTROL) +#include +#include + +static const struct pl01x_serial_platdata serial0 = { + .base = CONFIG_SYS_SERIAL0, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial0) = { + .name = "serial_pl01x", + .platdata = &serial0, +}; + +static const struct pl01x_serial_platdata serial1 = { + .base = CONFIG_SYS_SERIAL1, + .type = TYPE_PL011, + .clock = 0, + .skip_init = true, +}; + +U_BOOT_DEVICE(thunderx_serial1) = { + .name = "serial_pl01x", + .platdata = &serial1, +}; +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int timer_init(void) +{ + return 0; +} + +/* + * Boar
[U-Boot] [PATCH v6 9/9] armv8: cavium: Get DRAM size from ATF
Change the dram_init() function on ThunderX to query ATF services for the real installed DRAM size Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla --- Changes in v6: None Changes in v5: - Moved dram_init() from a separate file to thunderx.c Changes in v4: None Changes in v3: None Changes in v2: None board/cavium/thunderx/thunderx.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index 486374e..b926767 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -9,6 +9,8 @@ #include #include +#include + #if !CONFIG_IS_ENABLED(OF_CONTROL) #include #include @@ -50,6 +52,31 @@ int timer_init(void) return 0; } +int dram_init(void) +{ + ssize_t node_count = atf_node_count(); + ssize_t dram_size; + int node; + + printf("Initializing\nNodes in system: %zd\n", node_count); + + gd->ram_size = 0; + + for (node = 0; node < node_count; node++) { + dram_size = atf_dram_size(node); + printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20); + gd->ram_size += dram_size; + } + + gd->ram_size -= MEM_BASE; + + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + puts("DRAM size:"); + + return 0; +} + /* * Board specific reset that is system reset. */ -- 2.2.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 8/9] armv8: cavium: Add an implementation of ATF calling functions
This commit adds functions issuing calls to the product-specific ATF services Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None board/cavium/thunderx/Makefile | 2 +- board/cavium/thunderx/atf.c | 312 include/cavium/atf.h| 22 +++ include/cavium/atf_part.h | 26 include/cavium/thunderx_svc.h | 67 + include/configs/thunderx_88xx.h | 2 + 6 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 board/cavium/thunderx/atf.c create mode 100644 include/cavium/atf.h create mode 100644 include/cavium/atf_part.h create mode 100644 include/cavium/thunderx_svc.h diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile index 306044a..c78c414 100644 --- a/board/cavium/thunderx/Makefile +++ b/board/cavium/thunderx/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := thunderx.o +obj-y := thunderx.o atf.o diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c new file mode 100644 index 000..6ab9de9 --- /dev/null +++ b/board/cavium/thunderx/atf.c @@ -0,0 +1,312 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier:GPL-2.0+ +**/ + +#include +#include + +#include +#include +#include +#include + +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_MMC_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NOR_READ; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_pcount(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_PART_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_get_part(struct storage_partition *part, unsigned int index) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_GET_PART; + regs.regs[1] = (uintptr_t)part; + regs.regs[2] = index; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_erase_nor(uintptr_t offset, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_ERASE; + regs.regs[1] = offset; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_NOR_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size) +{ + struct pt_regs regs; + + regs.regs[0] = THUNDERX_MMC_WRITE; + regs.regs[1] = offset; + regs.regs[2] = size; + regs.regs[3] = (uintptr_t)buffer; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_dram_size(unsigned int node) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_DRAM_SIZE; + regs.regs[1] = node; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_node_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_NODE_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_count(void) +{ + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_COUNT; + + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t atf_env_string(size_t index, char *str) +{ + uint64_t *buf = (void *)str; + struct pt_regs regs; + regs.regs[0] = THUNDERX_ENV_STRING; + regs.regs[1] = index; + + smc_call(®s); + + if (regs.regs > 0) { + buf[0] = regs.regs[0]; + buf[1] = regs.regs[1]; + buf[2] = regs.regs[2]; + buf[3] = regs.regs[3]; + + return 1; + } else { + return regs.regs[0]; + } +} + +#ifdef CONFIG_CMD_ATF + +static void atf_print_ver(void) +{ + struct pt_regs regs; + regs.regs[0] = ARM_STD_SVC_VERSION; + + smc_call(®s); + + printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]); + + regs.regs[0] = THUNDERX_SVC_VERSION; + + smc_call(®s); + + printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]); +} + +static void atf_print_uid(void) +{ +} + +static void atf_print_part_table(void) +{ + size_t pcount; + unsigned long i; + int ret; + char *ptype; + + struct
[U-Boot] [PATCH v6 6/9] armv8: cavium: Add the device tree for ThunderX
This commit adds the FDT for the ThunderX family of SoCs Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla Reviewed-by: Simon Glass --- Changes in v6: - Added /chosen node Changes in v5: - Added FDT for ThunderX 88xx series Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/dts/Makefile | 1 + arch/arm/dts/thunderx-88xx.dts | 31 arch/arm/dts/thunderx-88xx.dtsi | 363 3 files changed, 395 insertions(+) create mode 100644 arch/arm/dts/thunderx-88xx.dts create mode 100644 arch/arm/dts/thunderx-88xx.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5f10243..ef123c50 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb +dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb\ diff --git a/arch/arm/dts/thunderx-88xx.dts b/arch/arm/dts/thunderx-88xx.dts new file mode 100644 index 000..08f2678 --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dts @@ -0,0 +1,31 @@ +/* + * Cavium Thunder DTS file - Thunder board description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier:GPL-2.0+ or X11 + * + */ + +/dts-v1/; + +/include/ "thunderx-88xx.dtsi" + +/ { + model = "Cavium ThunderX CN88XX board"; + compatible = "cavium,thunder-88xx"; + + aliases { + serial0 = &uaa0; + serial1 = &uaa1; + }; + + chosen { +stdout-path = &uaa0; +}; + + memory@ { + device_type = "memory"; + reg = <0x0 0x 0x0 0x8000>; + }; +}; diff --git a/arch/arm/dts/thunderx-88xx.dtsi b/arch/arm/dts/thunderx-88xx.dtsi new file mode 100644 index 000..086652f --- /dev/null +++ b/arch/arm/dts/thunderx-88xx.dtsi @@ -0,0 +1,363 @@ +/* + * Cavium Thunder DTS file - Thunder SoC description + * + * Copyright (C) 2014, Cavium Inc. + * + * SPDX-License-Identifier:GPL-2.0+ or X11 + * + */ + +/ { + compatible = "cavium,thunder-88xx"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@000 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + }; + cpu@001 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "psci"; + }; + cpu@002 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "psci"; + }; + cpu@003 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "psci"; + }; + cpu@004 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x004>; + enable-method = "psci"; + }; + cpu@005 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x005>; + enable-method = "psci"; + }; + cpu@006 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x006>; + enable-method = "psci"; + }; + cpu@007 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x007>; + enable-method = "psci"; + }; + cpu@008 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x008>; + enable-method = "psci"; + }; + cpu@009 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; +
[U-Boot] [PATCH] fdt: fix fdtdec_get_addr_size not to require any size cells
From: Stephen Warren fdtdec_get_addr_size() may be used in two cases: a) With sizep supplied, in which case both an address and a size are parsed from DT. In this case, the DT property must be large enough to contain both values. b) With sizep NULL, in which case only an address is parsed from DT. In this case, the DT property only need be large enough to contain this address value. Commit 02464e386bb5 "fdt: add new fdt address parsing functions" broke this relaxed checking, and required the DT property to contain both an address and a size value in all cases. Fix fdtdec_get_addr_size() to vary ns based on whether the size value is being parsed from the DT or not. This is safe since the function only parses the first entry in the property, so the overall value of (na + ns) need not be accurate, since it is never used to step through the property data to find other entries. Besides, this fixed behaviour essentially matches the original behaviour before the patch this patch fixes. (The original code validated that the property was exactly the length of either na or (na + ns), whereas the current code only validates that the property is at least that long. For non-failure cases, the two behaviours are identical). Cc: Przemyslaw Marczak Cc: Simon Glass Cc: Thierry Reding Cc: Bin Meng Cc: Michal Suchanek Fixes: 02464e386bb5 ("fdt: add new fdt address parsing functions") Reported-by: Przemyslaw Marczak Signed-off-by: Stephen Warren --- lib/fdtdec.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9f0b65de3831..1fdb4f0d9ce9 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -180,10 +180,11 @@ fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node, fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, const char *prop_name, fdt_size_t *sizep) { + int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0; + return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0, sizeof(fdt_addr_t) / sizeof(fdt32_t), - sizeof(fdt_size_t) / sizeof(fdt32_t), - sizep); + ns, sizep); } fdt_addr_t fdtdec_get_addr(const void *blob, int node, -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 5/9] arm: serial: Add ability to use pre-initialized UARTs
On some systems, UART initialization is performed before running U-Boot. This commit allows to skip UART re-initializaion on those systems Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla Reviewed-by: Simon Glass --- Changes in v6: - Changed the 'PL0X_PREINITIALIZED' flag to the 'skip-init' bool Changes in v5: - Added OF control support Changes in v4: - Fixed build warnings - Moved to DM_SERIAL Changes in v3: - Added __used keyword Changes in v2: None doc/device-tree-bindings/serial/pl01x.txt | 3 +++ drivers/serial/serial_pl01x.c | 14 -- include/dm/platform_data/serial_pl01x.h | 2 ++ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/doc/device-tree-bindings/serial/pl01x.txt b/doc/device-tree-bindings/serial/pl01x.txt index 61c27d1..0591497 100644 --- a/doc/device-tree-bindings/serial/pl01x.txt +++ b/doc/device-tree-bindings/serial/pl01x.txt @@ -5,3 +5,6 @@ Required properties: - reg: exactly one register range with length 0x1000 - clock: input clock frequency for the UART (used to calculate the baud rate divisor) + +Optional properties: +- u-boot,skip-init: skip UART initialization at start. diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 3a5c1d0..de9f642 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -103,7 +103,7 @@ static int pl011_set_line_control(struct pl01x_regs *regs) } static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, - int clock, int baudrate) + int clock, int baudrate) { switch (type) { case TYPE_PL010: { @@ -273,7 +273,6 @@ __weak struct serial_device *default_serial_console(void) #endif /* nCONFIG_DM_SERIAL */ #ifdef CONFIG_DM_SERIAL - struct pl01x_priv { struct pl01x_regs *regs; enum pl01x_type type; @@ -284,9 +283,9 @@ static int pl01x_serial_setbrg(struct udevice *dev, int baudrate) struct pl01x_serial_platdata *plat = dev_get_platdata(dev); struct pl01x_priv *priv = dev_get_priv(dev); - pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate); - - return 0; + return plat->skip_init ? 0 : + pl01x_generic_setbrg(priv->regs, priv->type, +plat->clock, baudrate); } static int pl01x_serial_probe(struct udevice *dev) @@ -296,7 +295,8 @@ static int pl01x_serial_probe(struct udevice *dev) priv->regs = (struct pl01x_regs *)plat->base; priv->type = plat->type; - return pl01x_generic_serial_init(priv->regs, priv->type); + return plat->skip_init ? 0 : + pl01x_generic_serial_init(priv->regs, priv->type); } static int pl01x_serial_getc(struct udevice *dev) @@ -350,6 +350,8 @@ static int pl01x_serial_ofdata_to_platdata(struct udevice *dev) plat->base = addr; plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1); plat->type = dev_get_driver_data(dev); + plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "uboot,skip-init"); return 0; } #endif diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h index 5e068f3..10e9572 100644 --- a/include/dm/platform_data/serial_pl01x.h +++ b/include/dm/platform_data/serial_pl01x.h @@ -17,11 +17,13 @@ enum pl01x_type { * @base: Register base address * @type: Port type * @clock: Input clock rate, used for calculating the baud rate divisor + * @flags: Port flags */ struct pl01x_serial_platdata { unsigned long base; enum pl01x_type type; unsigned int clock; + bool skip_init; }; #endif -- 2.2.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 3/9] armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure
This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov Signed-off-by: Corey Minyard Signed-off-by: Radha Mohan Chintakuntla Reviewed-by: Simon Glass --- Changes in v6: None Changes in v5: None Changes in v4: - Document FW calls Changes in v3: - Fixed clobber lists (thanks to Corey) Changes in v2: None arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/fwcall.c | 75 +++ arch/arm/include/asm/system.h | 21 3 files changed, 97 insertions(+) create mode 100644 arch/arm/cpu/armv8/fwcall.c diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index adb11b3..7579ea7 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -14,6 +14,7 @@ obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o obj-y += transition.o +obj-y += fwcall.o obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c new file mode 100644 index 000..9efcc5a --- /dev/null +++ b/arch/arm/cpu/armv8/fwcall.c @@ -0,0 +1,75 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier:GPL-2.0+ +**/ + +#include +#include +#include +#include +#include + +/* + * Issue the hypervisor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ +void hvc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "ldr x7, %7\n" + "hvc#0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]), "m" (args->regs[7]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} + +/* + * void smc_call(arg0, arg1...arg7) + * + * issue the secure monitor call + * + * x0~x7: input arguments + * x0~x3: output arguments + */ + +void smc_call(struct pt_regs *args) +{ + asm volatile( + "ldr x0, %0\n" + "ldr x1, %1\n" + "ldr x2, %2\n" + "ldr x3, %3\n" + "ldr x4, %4\n" + "ldr x5, %5\n" + "ldr x6, %6\n" + "smc#0\n" + "str x0, %0\n" + "str x1, %1\n" + "str x2, %2\n" + "str x3, %3\n" + : "+m" (args->regs[0]), "+m" (args->regs[1]), + "+m" (args->regs[2]), "+m" (args->regs[3]) + : "m" (args->regs[4]), "m" (args->regs[5]), + "m" (args->regs[6]) + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17"); +} diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9288541..f3e2d1b 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -1,6 +1,9 @@ #ifndef __ASM_ARM_SYSTEM_H #define __ASM_ARM_SYSTEM_H +#include +#include + #ifdef CONFIG_ARM64 /* @@ -104,6 +107,24 @@ void smp_kick_all_cpus(void); void flush_l3_cache(void); +/* + *Issue a hypervisor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void hvc_call(struct pt_regs *args); + +/* + *Issue a secure monitor call in accordance with ARM "SMC Calling convention", + * DEN0028A + * + * @args: input and output arguments + * + */ +void smc_call(struct pt_regs *args); + #endif /* __ASSEMBLY__ */ #else /* CONFIG_ARM64 */ -- 2.2.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 4/9] armv8: Add psci.h from the Linux kernel
This commit adds the psci.h header file from Linux kernel which contains definitions related to the PSCI interface provided by firmware Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None include/linux/psci.h | 90 1 file changed, 90 insertions(+) create mode 100644 include/linux/psci.h diff --git a/include/linux/psci.h b/include/linux/psci.h new file mode 100644 index 000..310d83e --- /dev/null +++ b/include/linux/psci.h @@ -0,0 +1,90 @@ +/* + * ARM Power State and Coordination Interface (PSCI) header + * + * This header holds common PSCI defines and macros shared + * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. + * + * Copyright (C) 2014 Linaro Ltd. + * Author: Anup Patel + */ + +#ifndef _UAPI_LINUX_PSCI_H +#define _UAPI_LINUX_PSCI_H + +/* + * PSCI v0.1 interface + * + * The PSCI v0.1 function numbers are implementation defined. + * + * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, + * INVALID_PARAMS, and DENIED defined below are applicable + * to PSCI v0.1. + */ + +/* PSCI v0.2 interface */ +#define PSCI_0_2_FN_BASE 0x8400 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x4000 +#define PSCI_0_2_FN64_BASE \ + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) + +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPENDPSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFFPSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATEPSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPUPSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFOPSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) + +/* PSCI v0.2 power state encoding for CPU_SUSPEND function */ +#define PSCI_0_2_POWER_STATE_ID_MASK 0x +#define PSCI_0_2_POWER_STATE_ID_SHIFT 0 +#define PSCI_0_2_POWER_STATE_TYPE_SHIFT16 +#define PSCI_0_2_POWER_STATE_TYPE_MASK \ + (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) +#define PSCI_0_2_POWER_STATE_AFFL_SHIFT24 +#define PSCI_0_2_POWER_STATE_AFFL_MASK \ + (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) + +/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ +#define PSCI_0_2_AFFINITY_LEVEL_ON 0 +#define PSCI_0_2_AFFINITY_LEVEL_OFF1 +#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 + +/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ +#define PSCI_0_2_TOS_UP_MIGRATE0 +#define PSCI_0_2_TOS_UP_NO_MIGRATE 1 +#define PSCI_0_2_TOS_MP2 + +/* PSCI version decoding (independent of PSCI version) */ +#define PSCI_VERSION_MAJOR_SHIFT 16 +#define PSCI_VERSION_MINOR_MASK\ + ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) +#define PSCI_VERSION_MAJOR_MASK~PSCI_VERSION_MINOR_MASK +#define PSCI_VERSION_MAJOR(ver)\ + (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) +#define PSCI_VERSION_MINOR(ver)\ + ((ver) & PSCI_VERSION_MINOR_MASK) + +/* PSCI return values (inclusive of all PSCI versions) */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS-2 +#define PSCI_RET_DENIED-3 +#define PSCI_RET_ALREADY_ON-4 +#define PSCI_RET_ON_PENDING-5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 + +#endif /* _UAPI_LINUX_PSCI_H */ -- 2.2.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 2/9] armv8: New MMU setup code allowing to use 48+ bits PA/VA
This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla --- Changes in v6: - Fixed lack of protection in global_data.h Changes in v5: - Allow setting of different memory attributes in the memory map Changes in v4: - Use ALIGN macro for address alignment Changes in v3: - Reduced code duplication - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS - Moved 'reset_sctrl' call to the 'reset' label - Rebased to the actual upstream tree - Documented newly added config options Changes in v2: - Changed code licensing - Completed the patchset arch/arm/cpu/armv8/cache_v8.c | 79 arch/arm/cpu/armv8/start.S | 36 + arch/arm/include/asm/armv8/mmu.h | 82 +++--- arch/arm/include/asm/global_data.h | 3 ++ arch/arm/include/asm/system.h | 7 arch/arm/lib/board.c | 6 ++- doc/README.arm64 | 35 +--- 7 files changed, 234 insertions(+), 14 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6bde1cf..989b17e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,6 +12,69 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_SYS_FULL_VA +static void set_ptl1_entry(u64 index, u64 ptl2_entry) +{ + u64 *pgd = (u64 *)gd->arch.tlb_addr; + u64 value; + + value = ptl2_entry | PTL1_TYPE_TABLE; + pgd[index] = value; +} + +static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs) +{ + u64 *pmd = (u64 *)ptl1; + u64 value; + + value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF; + value |= memory_attrs; + pmd[bfn] = value; +} + +static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP; + +#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES + +static void setup_pgtables(void) +{ + int l1_e, l2_e; + unsigned long pmd = 0; + unsigned long address; + + /* Setup the PMD pointers */ + for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) { + gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr + + PTL1_ENTRIES * sizeof(u64); + gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e; + gd->arch.pmd_addr[l1_e] = ALIGN(gd->arch.pmd_addr[l1_e], + 0x1UL); + } + + /* Setup the page tables */ + for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) { + if (mem_map[pmd].base == + (uintptr_t)l1_e << PTL2_BITS) { + set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]); + + for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) { + address = mem_map[pmd].base + + (uintptr_t)l2_e * BLOCK_SIZE; + set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e, + address, mem_map[pmd].attrs); + } + + pmd++; + } else { + set_ptl1_entry(l1_e, 0); + } + } +} + +#else + inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type, u64 share) { @@ -31,13 +94,25 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) page_table[index] = value; } +#endif + + /* to activate the MMU we need to set up virtual memory */ static void mmu_setup(void) { +#ifndef CONFIG_SYS_FULL_VA bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; +#endif int el; +#ifdef CONFIG_SYS_FULL_VA + unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK; + + /* Set up page tables only on BSP */ + if (coreid == BSP_COREID) + setup_pgtables(); +#else /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, @@ -55,6 +130,7 @@ static void mmu_setup(void) } } +#endif /* load TTBR0 */ el = current_el(); if (el == 1) { @@ -154,6 +230,7 @@ u64 *__weak arch_get_page_table(void) { return NULL; } +#ifndef CONFIG_SYS_FULL_VA void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option)
[U-Boot] [PATCH v6 1/9] armv8: Add read_mpidr() function
This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov Signed-off-by: Radha Mohan Chintakuntla Reviewed-by: Simon Glass --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/include/asm/system.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 868ea54..323c43e 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -71,6 +71,17 @@ static inline void set_sctlr(unsigned int val) asm volatile("isb"); } +static inline unsigned long read_mpidr(void) +{ + unsigned long val; + + asm volatile("mrs %0, mpidr_el1" : "=r" (val)); + + return val; +} + +#define BSP_COREID 0 + void __asm_flush_dcache_all(void); void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); -- 2.2.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] fix: s5p_gpio: call: dev_get_addr() instead of fdtdec_get_addr()
On 09/25/2015 02:36 AM, Przemyslaw Marczak wrote: Hello Stephen, On 09/24/2015 07:29 PM, Stephen Warren wrote: On 09/24/2015 09:29 AM, Przemyslaw Marczak wrote: After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property, set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Migrating everything to dev_get_addr() is the correct long-term fix, so this patch, Acked-by: Stephen Warren ... although I'd have liked to see a smaller diff that didn't both re-order all the code /and/ call a different function, but I suppose that's not possible given the need to pass the device object to dev_get_addr(). You could have used fdtdec_get_addr_size_auto_parent() directly. Yes, it's not a single line diff, but the driver supports driver-model, so it's natural that it should use driver model API if can, instead of fdtdec API. This approach makes things easier to test and catch mistakes in the future. I think it'd be good to fix fdtdec_get_addr_size() to have the same semantics that it previously did. There might be other code in U-Boot that's affected by the same issue, and fixing fdtdec_get_addr_size() would make sure that all got fixed too. Are you willing to send that patch too? Essentially, fdtdec_get_addr_size() used to assume: #address-cells == sizeof(fdt_addr_t) if sizep == NULL: #size-cells == 0 else: #size-cells == sizeof(fdt_addr_t) However, it now assumes: #address-cells == sizeof(fdt_addr_t) #size-cells == sizeof(fdt_addr_t) Let's just add that condition back by doing something like the following in fdtdec_get_addr_size(): u32 ns; if (sizep) ns = sizeof(fdt_size_t) / sizeof(fdt32_t); else ns = 0; ... and replacing the ns parameter that's passed to fdtdec_get_addr_size_fixed() with that variable, rather than hard-coding it. Sorry, currently I have some other things to do, and I wouldn't prefer fixing this without proper testing. Such core things should be tested in sandbox by couple of unit tests. OK, I'll take a stab at it. This seem to be okay, but is still wrong. We should always call fdtdec_get_addr_size_fixed() with arguments, which fits to the dtb, instead of hardcoded values. So, only the implementation of function fdtdec_get_addr_size_auto_parent() seem to be correct. It check the real #address-cells and #size-cells. Right. All "client" code should be migrated to call function which look at #address-cells and #size-cells. That's what fdtdec_get_addr_size_auto_parent(), fdtdec_get_addr_size_auto_noparent(), and dev_get_addr() do. However, there is code in U-Boot which (incorrectly) used fdtdec_get_addr() to parse properties other than reg. Those properties aren't affected by #address-cells and #size-cells. Hence, the hard-coding of na and ns inside fdtdec_get_addr_size() is required to support those use-case. Hopefully once everything that parses reg is migrated to the functions that look at #address-cells and #size-cells, fdtdec_get_addr_size() can be renamed to make it obvious it shouldn't be used for parsing reg. If this is slow, then maybe we need some cache with nodes, its parents/childs and its size/addr cells to be checked only once? Hopefully all (or almost all) use-cases can use dev_get_addr(). There's no slowness there, since there's no searching of the DT to find the parent; it's already known directly. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] fix: fdtdec: allow parse 'reg' property with zero value in '#size-cells'
On 09/25/2015 02:35 AM, Przemyslaw Marczak wrote: Hello Stephen, On 09/24/2015 07:14 PM, Stephen Warren wrote: On 09/24/2015 09:29 AM, Przemyslaw Marczak wrote: After rework of lib/fdtdec.c by commit: commit 02464e386bb5f0a022c121f95ae75cf583759d95 Author: Stephen Warren Date: Thu Aug 6 15:31:02 2015 -0600 That'd usually be abbreviated as: Commit 02464e386bb5 "fdt: add new fdt address parsing functions". Ok, I will update the commit message. Of course, if you want to shame me that's justified too:-) Tracking down regressions sucks:-( Oh no no... maybe a little :) the function fdtdec_get_addr() doesn't work as previous, because the implementation assumes that properties '#address-cells' and '#size-cells' are equal to 1, which can be not true sometimes. "are equal to" should be "is at least"; the purpose of that rework was to support values greater than one. But it describe the fdtdec_get_addr(), which calls fdtdec_get_addr_size_fixed(...) and for this call we have: na = sizeof(fdt_addr_t) / sizeof(fdt32_t) == 1 ns = sizeof(fdt_size_t) / sizeof(fdt32_t) == 1 This is consistent with the description for this function in include/fdtdec.h. Ah yes; I was thinking of the core function fdtdec_get_addr_size_fixed(). The description you gave seems correct. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] common: add CMD_GPIO to Kconfig
Hi Thomas, On 24 September 2015 at 01:44, Thomas Chou wrote: > > Add CMD_GPIO to Kconfig. > > Signed-off-by: Thomas Chou > --- > common/Kconfig | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/common/Kconfig b/common/Kconfig > index 2c42b8e..f2034c2 100644 > --- a/common/Kconfig > +++ b/common/Kconfig > @@ -344,6 +344,11 @@ config CMD_FPGA > help > FPGA support. > > +config CMD_GPIO > + bool "gpio" > + help > + GPIO support. > + > endmenu You can use the moveconfig.py tool to move configs into Kconfig. You could do that with your patch applied, and create a patch to remove the old #defines from board configs. I think this should be done at the same time as we add new Kconfigs, to avoid confusion. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
On 09/25/2015 05:28 AM, Hu Mingkai-B21284 wrote: > > >> -Original Message- >> From: Sun York-R58495 >> Sent: Tuesday, September 22, 2015 1:27 AM >> To: Gong Qianyu-B52263; u-boot@lists.denx.de >> Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Song Wenbin- >> B53747; Xie Shaohui-B21989; Wood Scott-B07421; Li Yang-Leo-R58472 >> Subject: Re: [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC >> >> >> >> On 09/17/2015 12:06 AM, Gong Qianyu wrote: >>> From: Mingkai Hu >>> >>> Freescale LayerScape with Chassis Generation 2 is a set of SoCs with >>> ARMv8 cores and 2rd generation of Chassis. >>> >>> Signed-off-by: Li Yang >>> Signed-off-by: Hou Zhiqiang >>> Signed-off-by: Mingkai Hu >>> Signed-off-by: Gong Qianyu >>> --- >>> V2: >>> remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h >>> >>> arch/arm/cpu/armv8/Makefile | 1 + >>> arch/arm/cpu/armv8/fsl-lsch2/Makefile | 12 + >>> arch/arm/cpu/armv8/fsl-lsch2/README | 10 + >>> arch/arm/cpu/armv8/fsl-lsch2/cpu.c| 414 >> ++ >> >> Too much duplication. Please work with Alison/Prabhakar to move out the >> common code in cpu.c. >> > > I agree, there are too much duplications between lsch2 and lsch3: > > arch/arm/cpu/armv8/fsl-lsch* > arch/arm/include/asm/arch-fsl-lsch* > > I am considering to consolidate the code between lsch2 and lsch3 using > arch-layerscape. The basic idea is to add the following directory for ARMv8 > layerscape for the common files and use CONFIG_FSL_LSCH2/ CONFIG_FSL_LSCH3 to > differentiate the difference between these two chassis in the same file if > necessary. > > arch/arm/cpu/armv8/fsl-layerscape > arch/arm/include/asm/arch-fsl-layerscape/ > > what is your suggestion? > I think it is worth a try. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V3 11/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
On 09/25/2015 05:32 AM, Gong Qianyu wrote: > From: Mingkai Hu > > Freescale LayerScape with Chassis Generation 2 is a set of SoCs with > ARMv8 cores and 2rd generation of Chassis. > > Signed-off-by: Li Yang > Signed-off-by: Hou Zhiqiang > Signed-off-by: Mingkai Hu > Signed-off-by: Gong Qianyu > --- > V3: > - Update MMU table initialization to match the latest code. > - Remove some dead code > - Rename #include to #include > > arch/arm/cpu/armv8/Makefile | 1 + > arch/arm/cpu/armv8/fsl-lsch2/Makefile | 12 + > arch/arm/cpu/armv8/fsl-lsch2/README | 10 + > arch/arm/cpu/armv8/fsl-lsch2/cpu.c| 527 > ++ NACK. Do NOT duplicate massive code. Please consolidate fsl-lsch3 and fsl-lsc2 and move common code out. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] U-boot hang on Renesas porter
Hey all, I recently got a Renesas Porter board, obviously one of the first things i wanted to do is replace its u-boot with a somewhat more recent version. Unfortunately upstream u-boot simply hangs during initialisation. Some printf debugging showed that the board_init_r test sequence is successful, but the board_init_f sequence never starts? Curiously, u-boot master *does* starts when chainloaded from the NOR loader (iotw tftp new u-boot to the expected CONFIG_SYS_TEXT_BASE and jump into it). Which makes me suspect there is some initialisation missing. FWIW, to prevent toolchain issues, i've both tried gcc 4.9 (as downloaded by buildman) as well as the gcc 5 cross-compilers from Debian. I've also updated the QSPI loader with the latest one from the elinux bage (PORTER_SPI_LOADER_V019_DDR3L.bin) Current u-boot output: PORTER SPI_LOADER(DDR3L) V0.19 2015.02.12 DEVICE S25FL512 U-Boot 2015.10-rc3-00297-g1a9c229 (Sep 25 2015 - 16:25:46 +0200) CPU: Renesas Electronics R8A7791 rev 2.0 Board: Porter I2C: ready DRAM: 1 GiB (At this point the board hangs) -- Sjoerd Simons Collabora Ltd. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
> -Original Message- > From: Sun York-R58495 > Sent: Tuesday, September 22, 2015 1:27 AM > To: Gong Qianyu-B52263; u-boot@lists.denx.de > Cc: Hu Mingkai-B21284; Sun York-R58495; Hou Zhiqiang-B48286; Song Wenbin- > B53747; Xie Shaohui-B21989; Wood Scott-B07421; Li Yang-Leo-R58472 > Subject: Re: [Patch v2 09/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC > > > > On 09/17/2015 12:06 AM, Gong Qianyu wrote: > > From: Mingkai Hu > > > > Freescale LayerScape with Chassis Generation 2 is a set of SoCs with > > ARMv8 cores and 2rd generation of Chassis. > > > > Signed-off-by: Li Yang > > Signed-off-by: Hou Zhiqiang > > Signed-off-by: Mingkai Hu > > Signed-off-by: Gong Qianyu > > --- > > V2: > > remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h > > > > arch/arm/cpu/armv8/Makefile | 1 + > > arch/arm/cpu/armv8/fsl-lsch2/Makefile | 12 + > > arch/arm/cpu/armv8/fsl-lsch2/README | 10 + > > arch/arm/cpu/armv8/fsl-lsch2/cpu.c| 414 > ++ > > Too much duplication. Please work with Alison/Prabhakar to move out the > common code in cpu.c. > I agree, there are too much duplications between lsch2 and lsch3: arch/arm/cpu/armv8/fsl-lsch* arch/arm/include/asm/arch-fsl-lsch* I am considering to consolidate the code between lsch2 and lsch3 using arch-layerscape. The basic idea is to add the following directory for ARMv8 layerscape for the common files and use CONFIG_FSL_LSCH2/ CONFIG_FSL_LSCH3 to differentiate the difference between these two chassis in the same file if necessary. arch/arm/cpu/armv8/fsl-layerscape arch/arm/include/asm/arch-fsl-layerscape/ what is your suggestion? We will send out version 3 to address the other comments and use it as the base for such consolidation. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 12/16] armv8/ls1043ardb: Add LS1043ARDB board support
From: Mingkai Hu LS1043ARDB Specification: - Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang Signed-off-by: Li Yang Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- V3: - Fix message typos. - Add ddr model number in comments. - Fix boot options in README. - Remove some dead code. arch/arm/Kconfig| 7 ++ board/freescale/ls1043ardb/Kconfig | 16 +++ board/freescale/ls1043ardb/MAINTAINERS | 7 ++ board/freescale/ls1043ardb/Makefile | 9 ++ board/freescale/ls1043ardb/README | 85 ++ board/freescale/ls1043ardb/cpld.c | 115 +++ board/freescale/ls1043ardb/cpld.h | 43 +++ board/freescale/ls1043ardb/ddr.c| 191 board/freescale/ls1043ardb/ddr.h| 45 board/freescale/ls1043ardb/ls1043ardb.c | 134 ++ configs/ls1043ardb_defconfig| 3 + drivers/i2c/mxc_i2c.c | 2 +- include/configs/ls1043a_common.h| 134 ++ include/configs/ls1043ardb.h| 191 14 files changed, 981 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c4371c7..5faf8c8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -616,6 +616,12 @@ config TARGET_LS1021ATWR select CPU_V7 select SUPPORT_SPL +config TARGET_LS1043ARDB + bool "Support ls1043ardb" + select ARM64 + help + Support for Freescale LS1043ARDB platform. + config TARGET_H2200 bool "Support h2200" select CPU_PXA @@ -730,6 +736,7 @@ source "board/freescale/ls2085aqds/Kconfig" source "board/freescale/ls2085ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig new file mode 100644 index 000..eb6a12a --- /dev/null +++ b/board/freescale/ls1043ardb/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS1043ARDB + +config SYS_BOARD + default "ls1043ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-lsch2" + +config SYS_CONFIG_NAME + default "ls1043ardb" + +endif diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS new file mode 100644 index 000..b8f6be2 --- /dev/null +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -0,0 +1,7 @@ +LS1043A BOARD +M: Mingkai Hu +S: Maintained +F: board/freescale/ls1043ardb/ +F: board/freescale/ls1043ardb/ls1043ardb.c +F: include/configs/ls1043ardb.h +F: configs/ls1043ardb_defconfig diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile new file mode 100644 index 000..dd17e2e --- /dev/null +++ b/board/freescale/ls1043ardb/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2015 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpld.o +obj-y += ddr.o +obj-y += ls1043ardb.o diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README new file mode 100644 index 000..d5925a9 --- /dev/null +++ b/board/freescale/ls1043ardb/README @@ -0,0 +1,85 @@ +Overview + +The LS1043A Reference Design Board (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1043A +LayerScape Architecture processor. The LS1043ARDB provides SW development +platform for the Freescale LS1043A processor series, with a complete +debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. + +LS1043A SoC Overview + +The LS1043A integrated multicore processor combines four ARM Cortex-A53 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1043A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A53 CPUs + - 1 MB unified L2 Cache + - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestio
[U-Boot] [Patch V3 13/16] armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu Signed-off-by: Hou Zhiqiang Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu --- arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/fsl-lsch2/Makefile | 1 + arch/arm/cpu/armv8/fsl-lsch2/spl.c | 79 ++ board/freescale/ls1043ardb/README | 1 + board/freescale/ls1043ardb/cpld.c | 18 + board/freescale/ls1043ardb/cpld.h | 1 + board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 ++ configs/ls1043ardb_nand_defconfig | 4 ++ include/configs/ls1043a_common.h | 27 include/configs/ls1043ardb.h | 46 + 11 files changed, 199 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5faf8c8..f487d13 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -619,6 +619,7 @@ config TARGET_LS1021ATWR config TARGET_LS1043ARDB bool "Support ls1043ardb" select ARM64 + select SUPPORT_SPL help Support for Freescale LS1043ARDB platform. diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile b/arch/arm/cpu/armv8/fsl-lsch2/Makefile index 9d2ac43..12d0b5a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch2/Makefile +++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile @@ -10,3 +10,4 @@ obj-y += soc.o obj-y += speed.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv8/fsl-lsch2/spl.c b/arch/arm/cpu/armv8/fsl-lsch2/spl.c new file mode 100644 index 000..cd667e5 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch2/spl.c @@ -0,0 +1,79 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_SPI_SUPPORT + return BOOT_DEVICE_SPI; +#endif +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif +#ifdef CONFIG_SPL_NAND_SUPPORT + return BOOT_DEVICE_NAND; +#endif + return 0; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + break; + case BOOT_DEVICE_NAND: + case BOOT_DEVICE_SPI: + return 0; + break; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + /* Set global data pointer */ + gd = &gdata; + + timer_init(); + + get_clocks(); + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + dram_init(); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + board_init_r(NULL, 0); +} +#endif diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index d5925a9..4f15557 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -83,3 +83,4 @@ Start Address End Address Description Size Booting Options --- a) NOR boot +b) NAND boot diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 3f1101e..5acb97d 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -45,6 +45,21 @@ void cpld_set_defbank(void) CPLD_WRITE(global_rst, 1); } +void cpld_set_nand(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_NAND; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} + #ifdef DEBUG static void cpld_dump_regs(void) { @@ -91,6 +106,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strcmp(argv[1], "reset") == 0) { if (strcmp(argv[2], "altbank") == 0) cpld_set_altbank(); + else if (strcmp(argv[2], "nand") == 0) + cpld_set_nand(); else cpld_set_defbank(); #ifdef DEBUG @@ -109,6 +126,7 @@ U_BOOT_CMD( "Reset the board or alternate bank", "reset: reset to default bank\n" "cpld reset altbank: reset to alternate bank\n" + "cpld reset nand: reset to boot from NAND flash\n" #ifdef DEBUG "cpld dump - display the CPLD registers
[U-Boot] [Patch V3 16/16] armv8/ls1043ardb: Add sd boot support
Signed-off-by: Gong Qianyu --- board/freescale/ls1043ardb/README| 1 + board/freescale/ls1043ardb/cpld.c| 17 ++ board/freescale/ls1043ardb/cpld.h| 1 + board/freescale/ls1043ardb/ls1043ardb.c | 6 + board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 ++ configs/ls1043ardb_sdcard_defconfig | 4 include/configs/ls1043a_common.h | 30 include/configs/ls1043ardb.h | 13 -- 8 files changed, 77 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 4f15557..0556e73 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -84,3 +84,4 @@ Booting Options --- a) NOR boot b) NAND boot +c) SD boot diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 5acb97d..faa0de8 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -60,6 +60,20 @@ void cpld_set_nand(void) CPLD_WRITE(system_rst, 1); } +void cpld_set_sd(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_SD; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} #ifdef DEBUG static void cpld_dump_regs(void) { @@ -108,6 +122,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) cpld_set_altbank(); else if (strcmp(argv[2], "nand") == 0) cpld_set_nand(); + else if (strcmp(argv[2], "sd") == 0) + cpld_set_sd(); else cpld_set_defbank(); #ifdef DEBUG @@ -127,6 +143,7 @@ U_BOOT_CMD( "reset: reset to default bank\n" "cpld reset altbank: reset to alternate bank\n" "cpld reset nand: reset to boot from NAND flash\n" + "cpld reset sd: reset to boot from SD card\n" #ifdef DEBUG "cpld dump - display the CPLD registers\n" #endif diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index 5f43a8a..bd59c0e 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -41,4 +41,5 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_ALTBANK 0x04 #define CPLD_CFG_RCW_SRC_NAND 0x106 +#define CPLD_CFG_RCW_SRC_SD0x040 #endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index de6682a..37846ff 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -26,12 +26,17 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { static const char *freq[3] = {"100.00MHZ", "156.25MHZ"}; +#ifndef CONFIG_SD_BOOT u8 cfg_rcw_src1, cfg_rcw_src2; u32 cfg_rcw_src; +#endif u32 sd1refclk_sel; printf("Board: LS1043ARDB, boot from "); +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); cpld_rev_bit(&cfg_rcw_src1); @@ -44,6 +49,7 @@ int checkboard(void) puts("NAND\n"); else printf("Invalid setting of SW4\n"); +#endif printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg new file mode 100644 index 000..28cd958 --- /dev/null +++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +081f 0c00 +14550002 80004012 6004 61002000 + 00038800 + 1100 0096 0001 diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig new file mode 100644 index 000..5fe0470 --- /dev/null +++ b/configs/ls1043ardb_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4" +CONFIG_ARM=y +CONFIG_TARGET_LS1043ARDB=y diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index d3ba4a3..565acf5 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -57,6 +57,36 @@ #define CONFIG_BAUDRATE115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* SD boot SPL */ +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT"arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_S
[U-Boot] [Patch V3 15/16] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
From: Yangbo Lu This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu Signed-off-by: Gong Qianyu --- arch/arm/cpu/armv8/fsl-lsch2/cpu.c | 10 ++ arch/arm/cpu/armv8/fsl-lsch2/fdt.c | 6 ++ arch/arm/cpu/armv8/fsl-lsch2/speed.c| 18 +- board/freescale/ls1043ardb/ls1043ardb.c | 1 + drivers/mmc/fsl_esdhc.c | 13 +++-- include/configs/ls1043a_common.h| 11 +++ include/fsl_esdhc.h | 2 +- 7 files changed, 53 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c index ef63770..63b74d0 100644 --- a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c @@ -13,6 +13,9 @@ #include #include #include +#ifdef CONFIG_FSL_ESDHC +#include +#endif #include "speed.h" DECLARE_GLOBAL_DATA_PTR; @@ -495,6 +498,13 @@ int print_cpuinfo(void) } #endif +#ifdef CONFIG_FSL_ESDHC +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c index a646faa..f1ae1f1 100644 --- a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c @@ -8,6 +8,9 @@ #include #include #include +#ifdef CONFIG_FSL_ESDHC +#include +#endif int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -17,4 +20,7 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) void ft_cpu_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_FSL_ESDHC) + fdt_fixup_esdhc(blob, bd); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.c b/arch/arm/cpu/armv8/fsl-lsch2/speed.c index 3bc6401..4c59baa 100644 --- a/arch/arm/cpu/armv8/fsl-lsch2/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.c @@ -25,7 +25,7 @@ void get_sys_info(struct sys_info *sys_info) struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -105,6 +105,11 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M2_CLK_SEL 0x0007 #define HWA_CGA_M2_CLK_SHIFT 0 +#if defined(CONFIG_FSL_ESDHC) + rcw_tmp = in_be32(&gur->rcwsr[15]); + rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT; + sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp; +#endif #if defined(CONFIG_FSL_IFC) ccr = in_le32(&ifc_regs.gregs->ifc_ccr); @@ -123,6 +128,10 @@ int get_clocks(void) gd->bus_clk = sys_info.freq_systembus; gd->mem_clk = sys_info.freq_ddrbus; +#if defined(CONFIG_FSL_ESDHC) + gd->arch.sdhc_clk = sys_info.freq_sdhc; +#endif + if (gd->cpu_clk != 0) return 0; else @@ -139,6 +148,11 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; } +int get_sdhc_freq(ulong dummy) +{ + return gd->arch.sdhc_clk; +} + int get_serial_clock(void) { return gd->bus_clk; @@ -149,6 +163,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_bus_freq(0); + case MXC_ESDHC_CLK: + return get_sdhc_freq(0); case MXC_DSPI_CLK: return get_bus_freq(0); case MXC_UART_CLK: diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 5a2f3bd..de6682a 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002..0a22874 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) xfertyp |= XFERTYP_RSPTYP_48; #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) + defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) || \ + defined(CONFIG_LS1043A) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif @@ -184,7 +185,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) int timeout; struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; -#ifdef CONFIG_LS2085A +#if defined(CONFIG_LS2085A) || defined(CONFIG_LS1043A) dma_addr_t addr; #endif uint wml_value; @@ -197,7 +198,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrset
[U-Boot] [Patch V3 14/16] armv8/ls1043a: Add Fman support
From: Shaohui Xie Signed-off-by: Hou Zhiqiang Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- arch/arm/cpu/armv8/fsl-lsch2/cpu.c | 19 + arch/arm/cpu/armv8/fsl-lsch2/fdt.c | 7 ++ arch/arm/cpu/armv8/fsl-lsch2/speed.c| 23 ++ board/freescale/common/fman.c | 6 +- board/freescale/ls1043ardb/Makefile | 1 + board/freescale/ls1043ardb/eth.c| 77 + board/freescale/ls1043ardb/ls1043ardb.c | 4 ++ doc/README.fsl-dpaa | 4 +- drivers/net/fm/Makefile | 1 + drivers/net/fm/init.c | 10 ++- drivers/net/fm/ls1043.c | 119 include/configs/ls1043a_common.h| 12 include/configs/ls1043ardb.h| 25 +++ 13 files changed, 303 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c index ef11c1c..ef63770 100644 --- a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "speed.h" DECLARE_GLOBAL_DATA_PTR; @@ -471,6 +472,9 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); +#ifdef CONFIG_SYS_DPAA_FMAN + printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); +#endif puts("\n"); /* @@ -491,11 +495,26 @@ int print_cpuinfo(void) } #endif +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + fm_standard_init(bis); +#endif + return 0; +} + int arch_early_init_r(void) { #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif +#ifdef CONFIG_FMAN_ENET + fman_enet_init(); +#endif return 0; } diff --git a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c index 015ad76..a646faa 100644 --- a/arch/arm/cpu/armv8/fsl-lsch2/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch2/fdt.c @@ -7,6 +7,13 @@ #include #include #include +#include + +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) +{ + return fdt_setprop_string(blob, offset, "phy-connection-type", +phy_string_for_interface(phyc)); +} void ft_cpu_setup(void *blob, bd_t *bd) { diff --git a/arch/arm/cpu/armv8/fsl-lsch2/speed.c b/arch/arm/cpu/armv8/fsl-lsch2/speed.c index 68cb5c2..3bc6401 100644 --- a/arch/arm/cpu/armv8/fsl-lsch2/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch2/speed.c @@ -25,6 +25,9 @@ void get_sys_info(struct sys_info *sys_info) struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif +#ifdef CONFIG_SYS_DPAA_FMAN + u32 rcw_tmp; +#endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[8] = { @@ -79,6 +82,26 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe000 #define HWA_CGA_M1_CLK_SHIFT 29 +#ifdef CONFIG_SYS_DPAA_FMAN + rcw_tmp = in_be32(&gur->rcwsr[7]); + switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { + case 2: + sys_info->freq_fman[0] = freq_c_pll[0] / 2; + break; + case 3: + sys_info->freq_fman[0] = freq_c_pll[0] / 3; + break; + case 6: + sys_info->freq_fman[0] = freq_c_pll[1] / 2; + break; + case 7: + sys_info->freq_fman[0] = freq_c_pll[1] / 3; + break; + default: + printf("Error: Unknown FMan1 clock select!\n"); + break; + } +#endif #define HWA_CGA_M2_CLK_SEL 0x0007 #define HWA_CGA_M2_CLK_SHIFT 0 diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 9dc5402..e491064 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier:GPL-2.0+ */ @@ -10,7 +10,11 @@ #include #include +#ifdef CONFIG_FSL_LSCH2 +#include +#else #include +#endif /* * Given the following ... diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile index dd17e2e..5fe1cc9 100644 --- a/board/freescale/ls1043ardb/Makefile +++ b/board/freescale/ls1043ardb/Makefile @@ -7,3 +7,4 @@ obj-y += cpld.o obj-y += ddr.o obj-y += ls1043ardb.o +obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c new file mode 100644 index 000..61f2b5d --- /dev/null +++ b/board/freescale/ls1043ardb/eth.c @@ -0,0 +
[U-Boot] [Patch V3 10/16] net/fm: fix MDIO controller base on FMAN2
From: Shaohui Xie MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two FMANs, so we should only define MDIO controller base on FMAN2 when there is FMAN2. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- include/fm_eth.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/fm_eth.h b/include/fm_eth.h index 3e1b9f4..d43f801 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -45,8 +45,10 @@ enum fm_eth_type { #ifdef CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) +#endif #else #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR(CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) @@ -89,6 +91,7 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } #else +#if (CONFIG_SYS_NUM_FMAN == 2) #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -101,6 +104,20 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } +#else +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num= n - 1,\ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE + n - 1, \ + .tx_port_id = TX_PORT_10G_BASE + n - 1, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1+8]),\ +} +#endif #endif #if (CONFIG_SYS_NUM_FM1_10GEC >= 3) -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 09/16] net/fm: Add QSGMII PCS init
From: Shaohui Xie QSGMII PCS needed to be programmed same as SGMII PCS, and there are four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared port 0's MDIO controller, so when programming port 0, we continue to program other three ports. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- drivers/net/fm/eth.c | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index a241d27..f3ac7d0 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -41,28 +41,39 @@ static void dtsec_configure_serdes(struct fm_eth *priv) bus.priv = priv->mac->phyregs; bool sgmii_2500 = (priv->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ? true : false; + int i = 0; + +qsgmii_loop: + if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && + ((priv->phyaddr % 4) != 0)) + return; /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ value = PHY_SGMII_IF_MODE_SGMII; if (!sgmii_2500) value |= PHY_SGMII_IF_MODE_AN; - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value); /* Dev ability according to SGMII specification */ value = PHY_SGMII_DEV_ABILITY_SGMII; - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value); /* Adjust link timer for SGMII - 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */ - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3); - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40); /* Restart AN */ value = PHY_SGMII_CR_DEF_VAL; if (!sgmii_2500) value |= PHY_SGMII_CR_RESET_AN; - memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value); + + if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) { + i++; + goto qsgmii_loop; + } #else struct dtsec *regs = priv->mac->base; struct tsec_mii_mng *phyregs = priv->mac->phyregs; @@ -91,6 +102,7 @@ static void dtsec_init_phy(struct eth_device *dev) #endif if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || + fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII || fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) dtsec_configure_serdes(fm_eth); } -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 11/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC
From: Mingkai Hu Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang Signed-off-by: Hou Zhiqiang Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- V3: - Update MMU table initialization to match the latest code. - Remove some dead code - Rename #include to #include arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/fsl-lsch2/Makefile | 12 + arch/arm/cpu/armv8/fsl-lsch2/README | 10 + arch/arm/cpu/armv8/fsl-lsch2/cpu.c| 527 ++ arch/arm/cpu/armv8/fsl-lsch2/fdt.c| 13 + arch/arm/cpu/armv8/fsl-lsch2/fsl_lsch2_serdes.c | 116 + arch/arm/cpu/armv8/fsl-lsch2/lowlevel.S | 122 + arch/arm/cpu/armv8/fsl-lsch2/ls1043a_serdes.c | 86 arch/arm/cpu/armv8/fsl-lsch2/soc.c| 36 ++ arch/arm/cpu/armv8/fsl-lsch2/speed.c | 137 ++ arch/arm/cpu/armv8/fsl-lsch2/speed.h | 7 + arch/arm/include/asm/arch-fsl-lsch2/clock.h | 24 + arch/arm/include/asm/arch-fsl-lsch2/config.h | 151 +++ arch/arm/include/asm/arch-fsl-lsch2/fsl_serdes.h | 105 + arch/arm/include/asm/arch-fsl-lsch2/immap_lsch2.h | 490 arch/arm/include/asm/arch-fsl-lsch2/imx-regs.h| 52 +++ arch/arm/include/asm/arch-fsl-lsch2/mmu.h | 10 + arch/arm/include/asm/arch-fsl-lsch2/ns_access.h | 158 +++ arch/arm/include/asm/arch-fsl-lsch2/soc.h | 7 + arch/arm/include/asm/arch-fsl-lsch2/spl.h | 20 + arch/arm/include/asm/armv8/mmu.h | 1 + include/common.h | 3 + 22 files changed, 2088 insertions(+) diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index adb11b3..eee8344 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -15,6 +15,7 @@ obj-y += cache.o obj-y += tlb.o obj-y += transition.o +obj-$(CONFIG_FSL_LSCH2) += fsl-lsch2/ obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile b/arch/arm/cpu/armv8/fsl-lsch2/Makefile new file mode 100644 index 000..9d2ac43 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2015, Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += lowlevel.o +obj-y += soc.o +obj-y += speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch2/README b/arch/arm/cpu/armv8/fsl-lsch2/README new file mode 100644 index 000..a6ef830 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch2/README @@ -0,0 +1,10 @@ +# +# Copyright 2015 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Freescale LayerScape with Chassis Generation 2 + +This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, +for example LS1043A. diff --git a/arch/arm/cpu/armv8/fsl-lsch2/cpu.c b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c new file mode 100644 index 000..10edc8c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-lsch2/cpu.c @@ -0,0 +1,527 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "speed.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DCACHE_OFF +#define SECTION_SHIFT_L0 39UL +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x80 +#define BLOCK_SIZE_L1 0x4000 +#define BLOCK_SIZE_L2 0x20 + +#define NUM_OF_ENTRY 512 +#define TCR_EL2_PS_40BIT (2 << 16) +#define LSCH2_VA_BITS (40) +#define LSCH2_TCR (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT| \ + TCR_SHARED_NON | \ + TCR_ORGN_NC | \ + TCR_IRGN_NC | \ + TCR_T0SZ(LSCH2_VA_BITS)) +#define LSCH2_TCR_FINAL(TCR_TG0_4K | \ + TCR_EL2_PS_40BIT| \ + TCR_SHARED_OUTER| \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(LSCH2_VA_BITS)) + +#define CONFIG_SYS_FSL_BOOTROM_BASE0x0 +#define CONFIG_SYS_FSL_BOOTROM_SIZE0x100 +#define CONFIG_SYS_FSL_CCSR_BASE 0x100 +#define CONFIG_SYS_FSL_CCSR_SIZE 0xf00 +#define CONFIG_SYS_FSL_DCSR_BASE 0x2000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x400 +#define CONFIG_SYS_FSL_QSPI_BASE 0x4000 +#define CONFIG_SYS_FSL_QSPI_SIZE
[U-Boot] [Patch V3 05/16] net/fm: Add support for 64-bit platforms
From: Hou Zhiqiang The FMan IM driver is developed for 32-bit platfroms and isn't friendly to 64-bit platforms, so do the minimal refactor: 1. Refine the MURAM management and access. 2. Correct the initialization and operations for QDs and BDs. Signed-off-by: Hou Zhiqiang Signed-off-by: Gong Qianyu --- V3: - New patch drivers/net/fm/eth.c | 61 drivers/net/fm/fm.c | 20 ++--- drivers/net/fm/fm.h | 12 +-- 3 files changed, 60 insertions(+), 33 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 5b860cc..a5c 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -108,12 +108,12 @@ static int tgec_is_fibre(struct eth_device *dev) static u16 muram_readw(u16 *addr) { - u32 base = (u32)addr & ~0x3; - u32 val32 = in_be32((u32 *)base); + ulong base = (ulong)addr & ~0x3UL; + u32 val32 = in_be32((void *)base); int byte_pos; u16 ret; - byte_pos = (u32)addr & 0x3; + byte_pos = (ulong)addr & 0x3UL; if (byte_pos) ret = (u16)(val32 & 0x); else @@ -124,18 +124,18 @@ static u16 muram_readw(u16 *addr) static void muram_writew(u16 *addr, u16 val) { - u32 base = (u32)addr & ~0x3; - u32 org32 = in_be32((u32 *)base); + ulong base = (ulong)addr & ~0x3UL; + u32 org32 = in_be32((void *)base); u32 val32; int byte_pos; - byte_pos = (u32)addr & 0x3; + byte_pos = (ulong)addr & 0x3UL; if (byte_pos) val32 = (org32 & 0x) | val; else val32 = (org32 & 0x) | ((u32)val << 16); - out_be32((u32 *)base, val32); + out_be32((void *)base, val32); } static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port) @@ -199,6 +199,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) u32 pram_page_offset; void *rx_bd_ring_base; void *rx_buf_pool; + u32 bd_ring_base_lo, bd_ring_base_hi; + u32 buf_lo, buf_hi; struct fm_port_bd *rxbd; struct fm_port_qd *rxqd; struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port; @@ -207,10 +209,15 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* alloc global parameter ram at MURAM */ pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index, FM_PRAM_SIZE, FM_PRAM_ALIGN); + if (!pram) { + printf("%s: No muram for Rx global parameter\n", __func__); + return 0; + } + fm_eth->rx_pram = pram; /* parameter page offset to MURAM */ - pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); + pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index); /* enable global mode- snooping data buffers and BDs */ out_be32(&pram->mode, PRAM_MODE_GLOBAL); @@ -234,6 +241,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) if (!rx_buf_pool) return 0; memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); + debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool); /* save them to fm_eth */ fm_eth->rx_bd_ring = rx_bd_ring_base; @@ -245,17 +253,22 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) for (i = 0; i < RX_BD_RING_SIZE; i++) { muram_writew(&rxbd->status, RxBD_EMPTY); muram_writew(&rxbd->len, 0); - muram_writew(&rxbd->buf_ptr_hi, 0); - out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool + - i * MAX_RXBUF_LEN); + buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool + + i * MAX_RXBUF_LEN)); + buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool + + i * MAX_RXBUF_LEN)); + muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi); + out_be32(&rxbd->buf_ptr_lo, buf_lo); rxbd++; } /* set the Rx queue descriptor */ rxqd = &pram->rxqd; muram_writew(&rxqd->gen, 0); - muram_writew(&rxqd->bd_ring_base_hi, 0); - out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base); + bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base)); + bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base)); + muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi); + out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo); muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd) * RX_BD_RING_SIZE); muram_writew(&rxqd->offset_in, 0); @@ -272,6 +285,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) struct fm_port_global_pram *pram; u32 pram_page_offset; void *tx_bd_ring_base; + u32 bd_ring_base_lo, bd_ring_base
[U-Boot] [Patch V3 04/16] net/fm/eth: Use mb() to be compatible for both ARM and PowerPC
From: Shaohui Xie Use mb() instead of sync() to be compatible for both ARM and PowerPC. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- V3: - Separated from patch 'net: Move some header files to include/' drivers/net/fm/eth.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 946b591..5b860cc 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -371,7 +371,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth) pram = fm_eth->tx_pram; /* graceful stop transmission of frames */ setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP); - sync(); + mb(); } static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) @@ -381,7 +381,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) pram = fm_eth->tx_pram; /* re-enable transmission of frames */ clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP); - sync(); + mb(); } static int fm_eth_open(struct eth_device *dev, bd_t *bd) @@ -483,9 +483,9 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len) muram_writew(&txbd->buf_ptr_hi, 0); out_be32(&txbd->buf_ptr_lo, (u32)buf); muram_writew(&txbd->len, len); - sync(); + mb(); muram_writew(&txbd->status, TxBD_READY | TxBD_LAST); - sync(); + mb(); /* update TxQD, let RISC to send the packet */ offset_in = muram_readw(&pram->txqd.offset_in); @@ -493,7 +493,7 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len) if (offset_in >= muram_readw(&pram->txqd.bd_ring_size)) offset_in = 0; muram_writew(&pram->txqd.offset_in, offset_in); - sync(); + mb(); /* wait for buffer to be transmitted */ for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) { @@ -544,7 +544,7 @@ static int fm_eth_recv(struct eth_device *dev) /* clear the RxBDs */ muram_writew(&rxbd->status, RxBD_EMPTY); muram_writew(&rxbd->len, 0); - sync(); + mb(); /* advance RxBD */ rxbd++; @@ -560,7 +560,7 @@ static int fm_eth_recv(struct eth_device *dev) if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size)) offset_out = 0; muram_writew(&pram->rxqd.offset_out, offset_out); - sync(); + mb(); } fm_eth->cur_rxbd = (void *)rxbd; -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 07/16] net/fm: bug fix when CONFIG_PHYLIB not defined
From: Shaohui Xie phy_shutdown should be wrapped by CONFIG_PHYLIB. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- drivers/net/fm/eth.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index de32814..131902b 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -483,8 +483,10 @@ static void fm_eth_halt(struct eth_device *dev) /* disable bmi Rx port */ bmi_rx_port_disable(fm_eth->rx_port); +#ifdef CONFIG_PHYLIB if (fm_eth->phydev) phy_shutdown(fm_eth->phydev); +#endif } static int fm_eth_send(struct eth_device *dev, void *buf, int len) -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 06/16] net/fm: Make the return value logic consistent with convention
From: Hou Zhiqiang In convention, the '0' is a normal return value indicating there isn't an error. While some functions of FMan IM driver treat '0' as an error return value. Signed-off-by: Hou Zhiqiang Signed-off-by: Gong Qianyu --- V3: - New patch drivers/net/fm/eth.c | 60 +++- 1 file changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index a5c..de32814 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -211,7 +211,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) FM_PRAM_SIZE, FM_PRAM_ALIGN); if (!pram) { printf("%s: No muram for Rx global parameter\n", __func__); - return 0; + return -ENOMEM; } fm_eth->rx_pram = pram; @@ -232,14 +232,16 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) rx_bd_ring_base = malloc(sizeof(struct fm_port_bd) * RX_BD_RING_SIZE); if (!rx_bd_ring_base) - return 0; + return -ENOMEM; + memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd) * RX_BD_RING_SIZE); /* alloc Rx buffer from main memory */ rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE); if (!rx_buf_pool) - return 0; + return -ENOMEM; + memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool); @@ -277,7 +279,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* set IM parameter ram pointer to Rx Frame Queue ID */ out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset); - return 1; + return 0; } static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) @@ -296,7 +298,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) FM_PRAM_SIZE, FM_PRAM_ALIGN); if (!pram) { printf("%s: No muram for Tx global parameter\n", __func__); - return 0; + return -ENOMEM; } fm_eth->tx_pram = pram; @@ -313,7 +315,8 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) tx_bd_ring_base = malloc(sizeof(struct fm_port_bd) * TX_BD_RING_SIZE); if (!tx_bd_ring_base) - return 0; + return -ENOMEM; + memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd) * TX_BD_RING_SIZE); /* save it to fm_eth */ @@ -344,29 +347,35 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */ out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset); - return 1; + return 0; } static int fm_eth_init(struct fm_eth *fm_eth) { + int ret; - if (!fm_eth_rx_port_parameter_init(fm_eth)) - return 0; + ret = fm_eth_rx_port_parameter_init(fm_eth); + if (ret) + return ret; - if (!fm_eth_tx_port_parameter_init(fm_eth)) - return 0; + ret = fm_eth_tx_port_parameter_init(fm_eth); + if (ret) + return ret; - return 1; + return 0; } static int fm_eth_startup(struct fm_eth *fm_eth) { struct fsl_enet_mac *mac; + int ret; + mac = fm_eth->mac; /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */ - if (!fm_eth_init(fm_eth)) - return 0; + ret = fm_eth_init(fm_eth); + if (ret) + return ret; /* setup the MAC controller */ mac->init_mac(mac); @@ -381,7 +390,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth) /* init bmi tx port, IM mode and disable */ bmi_tx_port_init(fm_eth->tx_port); - return 1; + return 0; } static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth) @@ -628,7 +637,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) /* alloc mac controller */ mac = malloc(sizeof(struct fsl_enet_mac)); if (!mac) - return 0; + return -ENOMEM; memset(mac, 0, sizeof(struct fsl_enet_mac)); /* save the mac to fm_eth struct */ @@ -643,7 +652,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); #endif - return 1; + return 0; } static int init_phy(struct eth_device *dev) @@ -696,17 +705,18 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) struct eth_device *dev; struct fm_eth *fm_eth; int i, num = info->num; + int ret; /* alloc eth device */ dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) -
[U-Boot] [Patch V3 08/16] net: Move some header files to include/
From: Shaohui Xie The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie Signed-off-by: Gong Qianyu --- arch/powerpc/include/asm/immap_85xx.h | 2 +- board/freescale/b4860qds/eth_b4860qds.c | 2 +- board/freescale/corenet_ds/eth_hydra.c | 2 +- board/freescale/corenet_ds/eth_p4080.c | 2 +- board/freescale/corenet_ds/eth_superhydra.c | 2 +- board/freescale/p1023rdb/p1023rdb.c | 2 +- board/freescale/p2041rdb/eth.c | 2 +- board/freescale/t102xqds/eth_t102xqds.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- board/freescale/t1040qds/eth.c | 2 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 2 +- board/freescale/t208xrdb/eth_t208xrdb.c | 2 +- board/freescale/t4qds/eth.c | 2 +- board/freescale/t4rdb/eth.c | 2 +- drivers/net/fm/dtsec.c | 2 +- drivers/net/fm/eth.c| 4 ++-- drivers/net/fm/fm.h | 2 +- drivers/net/fm/tgec.c | 2 +- drivers/net/fm/tgec_phy.c | 2 +- 20 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 0c9d85e..101b8db 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include typedef struct ccsr_local { diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 501d4b3..df90476 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include "../common/ngpixis.h" #include "../common/fman.h" diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 396103f..172a55b 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -55,7 +55,7 @@ #include #include #include -#include +#include #include "../common/ngpixis.h" #include "../common/fman.h" diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 5cbec7f..c68dc2c 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -24,7 +24,7 @@ #include "../common/ngpixis.h" #include "../common/fman.h" -#include +#include #define EMI_NONE 0x #define EMI_MASK 0xf000 diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index ad1bffd..62b1635 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -55,7 +55,7 @@ #include #include #include -#include +#include #include "../common/ngpixis.h" #include "../common/fman.h" diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c index 56f561a..074b713 100644 --- a/board/freescale/p1023rdb/p1023rdb.c +++ b/board/freescale/p1023rdb/p1023rdb.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 532eeac..95fe85b 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include "cpld.h" #include "../common/fman.h" diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c index 441d6a3..99c23f7 100644 --- a/board/freescale/t102xqds/eth_t102xqds.c +++ b/board/freescale/t102xqds/eth_t102xqds.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include "../common/qixis.h" #include "../common/fman.h" diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 856ec6e..02b283d 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include "../common/fman.h" diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 8c82934..8bf34fa 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include "../common/fman.h" diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 71d0457..52cd112 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include "../c
[U-Boot] [Patch V3 02/16] common/board_f.c: modify the macro to use get_clocks() more common
get_clocks() should not be limited by ESDHC. Signed-off-by: Gong Qianyu --- V3: -Removed defines in PPC configs that have no need to use. common/board_f.c | 2 +- include/configs/colibri_vf.h | 1 + include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + include/configs/ls2085aqds.h | 1 + include/configs/ls2085ardb.h | 1 + include/configs/m53evk.h | 1 + include/configs/mx25pdk.h | 1 + include/configs/mx35pdk.h | 1 + include/configs/mx51evk.h | 1 + include/configs/mx53ard.h | 1 + include/configs/mx53evk.h | 1 + include/configs/mx53loco.h| 1 + include/configs/mx53smd.h | 1 + include/configs/mx6_common.h | 1 + include/configs/mx7_common.h | 1 + include/configs/usbarmory.h | 1 + include/configs/vf610twr.h| 1 + include/configs/woodburn_common.h | 1 + 19 files changed, 19 insertions(+), 1 deletion(-) diff --git a/common/board_f.c b/common/board_f.c index 613332e..1bb84b3 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -806,7 +806,7 @@ static init_fnc_t init_sequence_f[] = { #if defined(CONFIG_BOARD_POSTCLK_INIT) board_postclk_init, #endif -#ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_CLK get_clocks, #endif #ifdef CONFIG_M68K diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 2583155..5bd742d 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -18,6 +18,7 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_USE_ARCH_MEMCPY #define CONFIG_USE_ARCH_MEMSET +#define CONFIG_FSL_CLK #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARCH_MISC_INIT diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 0234e32..c02cefa 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -12,6 +12,7 @@ #define CONFIG_ARMV7_PSCI #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_FSL_CLK #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f561cbe..66f487d 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -12,6 +12,7 @@ #define CONFIG_ARMV7_PSCI #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_FSL_CLK #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index f7f3870..4cfcf98 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -16,6 +16,7 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif +#define CONFIG_FSL_CLK #define CONFIG_SYS_CLK_FREQget_board_sys_clk() #define CONFIG_DDR_CLK_FREQget_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index a190bc7..583fed5 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -18,6 +18,7 @@ unsigned long get_board_sys_clk(void); #endif +#define CONFIG_FSL_CLK #define CONFIG_SYS_CLK_FREQget_board_sys_clk() #define CONFIG_DDR_CLK_FREQ1 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 35058e2..4d37785 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -18,6 +18,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_REVISION_TAG #define CONFIG_SYS_NO_FLASH +#define CONFIG_FSL_CLK #define CONFIG_FIT diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index bd7216e..105ac6d 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_TEXT_BASE 0x8120 #define CONFIG_MXC_GPIO #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_FSL_CLK #define CONFIG_SYS_TIMER_RATE 32768 #define CONFIG_SYS_TIMER_COUNTER \ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index c9983f3..97527b6 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -20,6 +20,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_FSL_CLK /* Set TEXT at the beginning of the NOR flash */ #define CONFIG_SYS_TEXT_BASE 0xA000 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 2203c15..e3763c1 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -18,6 +18,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_FSL_CLK #define CONFIG_SYS_TEXT_BASE 0x9780 #include diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 0479195..d57e06d 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -24,6 +24,7 @@ #define CONFIG_REVISION_TAG #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_
[U-Boot] [Patch V3 00/16] Add LS1043A platform support
[Patch V3 01/16] armv7/ls1021a: move ns_access to common file [Patch V3 02/16] common/board_f.c: modify the macro to use [Patch V3 03/16] net/fm: Fix the endian issue to support both [Patch V3 04/16] net/fm/eth: Use mb() to be compatible for both ARM [Patch V3 05/16] net/fm: Add support for 64-bit platforms [Patch V3 06/16] net/fm: Make the return value logic consistent with [Patch V3 07/16] net/fm: bug fix when CONFIG_PHYLIB not defined [Patch V3 08/16] net: Move some header files to include/ [Patch V3 09/16] net/fm: Add QSGMII PCS init [Patch V3 10/16] net/fm: fix MDIO controller base on FMAN2 [Patch V3 11/16] ARMv8/FSL_LSCH2: Add FSL_LSCH2 SoC [Patch V3 12/16] armv8/ls1043ardb: Add LS1043ARDB board support [Patch V3 13/16] armv8/ls1043ardb: Add nand boot support [Patch V3 14/16] armv8/ls1043a: Add Fman support [Patch V3 15/16] armv8/ls1043ardb: esdhc: Add esdhc support for [Patch V3 16/16] armv8/ls1043ardb: Add sd boot support ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V3 01/16] armv7/ls1021a: move ns_access to common file
From: Mingkai Hu Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- arch/arm/include/asm/arch-ls102xa/ns_access.h | 103 -- board/freescale/common/Makefile | 2 +- board/freescale/common/ns_access.c| 8 +- board/freescale/ls1021aqds/ls1021aqds.c | 101 ++--- board/freescale/ls1021atwr/ls1021atwr.c | 92 +-- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/fsl_csu.h | 34 + 8 files changed, 136 insertions(+), 208 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h index b53f699..a921fb6 100644 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -7,22 +7,6 @@ #ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ -enum csu_cslx_access { - CSU_NS_SUP_R = 0x08, - CSU_NS_SUP_W = 0x80, - CSU_NS_SUP_RW = 0x88, - CSU_NS_USER_R = 0x04, - CSU_NS_USER_W = 0x40, - CSU_NS_USER_RW = 0x44, - CSU_S_SUP_R = 0x02, - CSU_S_SUP_W = 0x20, - CSU_S_SUP_RW = 0x22, - CSU_S_USER_R = 0x01, - CSU_S_USER_W = 0x10, - CSU_S_USER_RW = 0x11, - CSU_ALL_RW = 0xff, -}; - enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, CSU_CSLX_PCIE1_IO, @@ -108,11 +92,88 @@ enum csu_cslx_ind { CSU_CSLX_MAX, }; -struct csu_ns_dev { - unsigned long ind; - uint32_t val; +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, +
[U-Boot] [Patch V3 03/16] net/fm: Fix the endian issue to support both
From: Hou Zhiqiang The Frame Manager(FMan) is a big-endian peripheral, so the registers, internal MURAM and BDs, which are allocated in main memory and used to communication between core and FMan, should be accessed in big-endian. The big-endian platforms can access them directly as the code implemented so far, while for the little-endian platforms it need to swap the byte-order. Signed-off-by: Hou Zhiqiang Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- V3: - Modify the subject to make the aim clear. drivers/net/fm/eth.c | 70 +++- drivers/net/fm/fm.c | 11 + 2 files changed, 43 insertions(+), 38 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 6702f5a..946b591 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -109,7 +109,7 @@ static int tgec_is_fibre(struct eth_device *dev) static u16 muram_readw(u16 *addr) { u32 base = (u32)addr & ~0x3; - u32 val32 = *(u32 *)base; + u32 val32 = in_be32((u32 *)base); int byte_pos; u16 ret; @@ -125,7 +125,7 @@ static u16 muram_readw(u16 *addr) static void muram_writew(u16 *addr, u16 val) { u32 base = (u32)addr & ~0x3; - u32 org32 = *(u32 *)base; + u32 org32 = in_be32((u32 *)base); u32 val32; int byte_pos; @@ -135,7 +135,7 @@ static void muram_writew(u16 *addr, u16 val) else val32 = (org32 & 0x) | ((u32)val << 16); - *(u32 *)base = val32; + out_be32((u32 *)base, val32); } static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port) @@ -213,10 +213,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); /* enable global mode- snooping data buffers and BDs */ - pram->mode = PRAM_MODE_GLOBAL; + out_be32(&pram->mode, PRAM_MODE_GLOBAL); /* init the Rx queue descriptor pionter */ - pram->rxqd_ptr = pram_page_offset + 0x20; + out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20); /* set the max receive buffer length, power of 2 */ muram_writew(&pram->mrblr, MAX_RXBUF_LOG2); @@ -243,10 +243,11 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* init Rx BDs ring */ rxbd = (struct fm_port_bd *)rx_bd_ring_base; for (i = 0; i < RX_BD_RING_SIZE; i++) { - rxbd->status = RxBD_EMPTY; - rxbd->len = 0; - rxbd->buf_ptr_hi = 0; - rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN; + muram_writew(&rxbd->status, RxBD_EMPTY); + muram_writew(&rxbd->len, 0); + muram_writew(&rxbd->buf_ptr_hi, 0); + out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool + + i * MAX_RXBUF_LEN); rxbd++; } @@ -254,7 +255,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) rxqd = &pram->rxqd; muram_writew(&rxqd->gen, 0); muram_writew(&rxqd->bd_ring_base_hi, 0); - rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base; + out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base); muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd) * RX_BD_RING_SIZE); muram_writew(&rxqd->offset_in, 0); @@ -285,10 +286,10 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index); /* enable global mode- snooping data buffers and BDs */ - pram->mode = PRAM_MODE_GLOBAL; + out_be32(&pram->mode, PRAM_MODE_GLOBAL); /* init the Tx queue descriptor pionter */ - pram->txqd_ptr = pram_page_offset + 0x40; + out_be32(&pram->txqd_ptr, pram_page_offset + 0x40); /* alloc Tx buffer descriptors from main memory */ tx_bd_ring_base = malloc(sizeof(struct fm_port_bd) @@ -304,16 +305,17 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth) /* init Tx BDs ring */ txbd = (struct fm_port_bd *)tx_bd_ring_base; for (i = 0; i < TX_BD_RING_SIZE; i++) { - txbd->status = TxBD_LAST; - txbd->len = 0; - txbd->buf_ptr_hi = 0; - txbd->buf_ptr_lo = 0; + muram_writew(&txbd->status, TxBD_LAST); + muram_writew(&txbd->len, 0); + muram_writew(&txbd->buf_ptr_hi, 0); + out_be32(&txbd->buf_ptr_lo, 0); + txbd++; } /* set the Tx queue decriptor */ txqd = &pram->txqd; muram_writew(&txqd->bd_ring_base_hi, 0); - txqd->bd_ring_base_lo = (u32)tx_bd_ring_base; + out_be32(&txqd->bd_ring_base_lo, (u32)tx_bd_ring_base); muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd) * TX_BD_RING_SIZE); muram
Re: [U-Boot] [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
> -Original Message- > From: Wood Scott-B07421 > Sent: Friday, September 18, 2015 1:13 PM > To: Xie Shaohui-B21989 > Cc: Gong Qianyu-B52263; u-boot@lists.denx.de; Hu Mingkai-B21284; Sun > York-R58495; Hou Zhiqiang-B48286; Song Wenbin-B53747 > Subject: Re: [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2 > > > > doc/README.fsl-dpaa says that CONFIG_FSL_FM_10GEC_REGULAR_NOTATION > > > is for newer SoCs. Presumably this patch is for ls1043a -- is that > > > not considered a newer SoC? Or does the README need to be fixed? > > [S.H] Yes, this is for LS1043A. LS1043A has one FMAN same as T2080. > > A new SoC but has an old DPAA. > > So maybe the README should be changed to more accurately talk about FMan > versions? > Thanks, we will change the README to make it clear. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm, at91: small updates for the smartweb board
- add CONFIG_BOOT_RETRY_TIME to 30 - fex LED colors - fix button pressed combination - add CONFIG_USB_HOST_ETHER CONFIG_USB_ETHER_ASIX CONFIG_USB_ETHER_MCS7830 - change U-Boot prompt to "U-Boot> " Signed-off-by: Heiko Schocher Signed-off-by: Matthias Michel --- $ ./tools/buildman/buildman -b 20150923 at91 WARNING: no status info for 'dra72_evm' WARNING: no maintainers for 'dra72_evm' WARNING: no status info for 'am335x_gp_evm' WARNING: no maintainers for 'am335x_gp_evm' WARNING: no status info for 'hikey' WARNING: no maintainers for 'hikey' Building 5 commits for 61 boards (8 threads, 1 job per thread) Cloning repo for thread 0 Cloning repo for thread 1 Cloning repo for thread 2 Cloning repo for thread 3 Cloning repo for thread 4 Cloning repo for thread 5 Cloning repo for thread 6 Cloning repo for thread 7 30500 /305axm board/siemens/smartweb/smartweb.c | 25 ++--- include/configs/smartweb.h| 5 + 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 2d42488..d82f1b7 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -90,7 +90,8 @@ static void smartweb_macb_hw_init(void) pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), &pioa->pudr); at91_phy_reset(); @@ -101,7 +102,8 @@ static void smartweb_macb_hw_init(void) pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), &pioa->puer); /* Initialize EMAC=MACB hardware */ @@ -141,13 +143,6 @@ int board_early_init_f(void) int board_init(void) { - /* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - smartweb_nand_hw_init(); -#ifdef CONFIG_MACB - smartweb_macb_hw_init(); -#endif /* power LED red */ at91_set_gpio_output(AT91_PIN_PC6, 0); at91_set_gpio_output(AT91_PIN_PC7, 1); @@ -163,6 +158,13 @@ int board_init(void) at91_udc_probe(&board_udc_data); #endif + /* Adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + smartweb_nand_hw_init(); +#ifdef CONFIG_MACB + smartweb_macb_hw_init(); +#endif return 0; } @@ -197,6 +199,7 @@ void matrix_init(void) void spl_board_init(void) { + /* power LED orange */ at91_set_gpio_output(AT91_PIN_PC6, 1); at91_set_gpio_output(AT91_PIN_PC7, 1); /* alarm LED orange */ @@ -212,8 +215,8 @@ void spl_board_init(void) /* check if both button are pressed */ if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && - at91_get_gpio_value(AT91_PIN_PA29) == 0) { - debug("Recovery button pressed\n"); + at91_get_gpio_value(AT91_PIN_PA29) == 0) { + smartweb_nand_hw_init(); nand_init(); spl_nand_erase_one(0, 0); } diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d189c3f..fbb66d5 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -117,6 +117,9 @@ * */ #define CONFIG_MACB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_RMII/* use reduced MII inteface */ #define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ #define CONFIG_AT91_WANTS_COMMON_PHY @@ -182,6 +185,8 @@ /* General Boot Parameter */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_BOOT_RETRY_TIME 30 +#define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] FIX: fat: Provide correct return code from disk_{read|write} to upper layers
On 09/23/2015 02:40 AM, Lukasz Majewski wrote: > Hi Stephen, > >> On 09/03/2015 08:18 AM, Lukasz Majewski wrote: >>> Hi Lukasz, >>> Hi Tom, > On Thu, Sep 03, 2015 at 02:21:39PM +0200, Lukasz Majewski wrote: > >> It is very common that FAT code is using following pattern: >> if (disk_{read|write}() < 0) >> return -1; >> >> Up till now the above code was dead, since disk_{read|write) >> could only return value >= 0. >> As a result some errors from medium layer (i.e. eMMC/SD) were not >> caught. >> >> The above behavior was caused by block_{read|write|erase} >> declared at struct block_dev_desc (@part.h). It returns unsigned >> long, where 0 indicates error and > 0 indicates that medium >> operation was correct. >> >> This patch as error regards 0 returned from >> block_{read|write|erase} when nr_blocks is grater than zero. >> Read/Write operation with nr_blocks=0 should return 0 and hence >> is not considered as an error. >> >> Signed-off-by: Lukasz Majewski >> >> Test HW: Odroid XU3 - Exynos 5433 > > Can you pick up Stephen's FAT replacement series and see if it > also fixes this problem? Thanks! > Ok, I will test this fat implementation. >>> >>> I've applied v2 of this patchset >>> on top of SHA1: 79c884d7e449a63fa8f07b7495f8f9873355c48f >>> >>> Unfortunately, DFU tests fail with first attempt to pass the test. >> >> I've found a couple of problems. >> >> First up, file_fat_write() wasn't truncating the file when writing, so >> the file size wasn't changing when over-writing a large file with a >> small file. With this fixed, I can run the DFU tests just fine for all >> the small files (<1M). I've fixed this locally and in the ff branch on >> my github. > > Nice to hear that you have found the error. > >> Second, ff is slow: >> >> Some random old build I had in flash on my system: >>> Tegra124 (Jetson TK1) # load mmc 1:1 $loadaddr dfu1.bin >>> reading dfu1.bin >>> 1048576 bytes read in 95 ms (10.5 MiB/s) >> >> With my ff branch: >>> Tegra124 (Jetson TK1) # load mmc 1:1 $loadaddr dfu1.bin >>> 1048576 bytes read in 5038 ms (203.1 KiB/s) >> >> That's quite the slow-down! I believe this is causing dfu-util to time >> out on the larger files (1M+). Just for functional testing, I'll try >> and find a way to hack dfu-util to have a much larger timeout for the >> final flush operation. I wonder if the old FAT implementation had a >> disk cache (e.g. that 32K buffer in BSS?) and we need the same for >> ff? Extending the timeout (massively) in dfu-util did make dfu_gadget_test.sh work. > I think that our current Fat implementation is optimized for tiny > embedded system (and probably no cache). The ff library claims to be too. I'll try tracing the IO pattern in sandbox and see where the difference lies. >> I'll try and track down why it's so slow. >> >> Perhaps there are other issues as yet unfound. > > We might also check with sandbox FS set of tests. I get the same failures for fs-test.sh with or without this series; TC10 fails and everything else passes, for the non-"sb" FAT tests. (with the file truncation fix I mentioned above applied, although I don't know if it matters for fs-test.sh) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 0/2] arm, imx6, aristainetos2: set gpr register after reset
setting the gpr 1,8 and 12 registers to a fix value. This is needed because after a WDT reset, this registers are not correct resettet, and prevent linux from booting again. with this patches no compileerrors found: $ ./tools/buildman/buildman -b 20150925 mx6 boards.cfg is up to date. Nothing to do. Building 4 commits for 49 boards (8 threads, 1 job per thread) Cloning repo for thread 2 Cloning repo for thread 3 Cloning repo for thread 4 Cloning repo for thread 5 Cloning repo for thread 6 Cloning repo for thread 7 19600 /196mx6qsabreauto $ Heiko Schocher (2): arm, imx: add some gpr register defines arm, imx6, aristainetos2: set gpr register after reset arch/arm/include/asm/arch-mx6/imx-regs.h | 35 board/aristainetos/aristainetos-v2.c | 16 +++ 2 files changed, 51 insertions(+) -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 1/2] arm, imx: add some gpr register defines
add some missing gpr register defines. Signed-off-by: Heiko Schocher --- arch/arm/include/asm/arch-mx6/imx-regs.h | 35 1 file changed, 35 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 74512ac..0e112e9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -413,10 +413,37 @@ struct src { }; /* GPR1 bitfields */ +#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) +#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) +#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) +#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) +#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) +#define IOMUXC_GPR1_DPI_OFFBIT(24) +#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET21 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) +#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUXBIT(20) +#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUXBIT(19) +#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) +#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) +#define IOMUXC_GPR1_PCIE_REF_CLK_ENBIT(16) +#define IOMUXC_GPR1_USB_EXP_MODE BIT(15) +#define IOMUXC_GPR1_PCIE_INT BIT(14) #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK(1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) +#define IOMUXC_GPR1_GINT BIT(12) +#define IOMUXC_GPR1_ADDRS3_MASK(0x3 << 10) +#define IOMUXC_GPR1_ADDRS3_32MB(0x0 << 10) +#define IOMUXC_GPR1_ADDRS3_64MB(0x1 << 10) +#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) +#define IOMUXC_GPR1_ACT_CS3BIT(9) +#define IOMUXC_GPR1_ADDRS2_MASK(0x3 << 7) +#define IOMUXC_GPR1_ACT_CS2BIT(6) +#define IOMUXC_GPR1_ADDRS1_MASK(0x3 << 4) +#define IOMUXC_GPR1_ACT_CS1BIT(3) +#define IOMUXC_GPR1_ADDRS0_OFFSET (1) +#define IOMUXC_GPR1_ADDRS0_MASK(0x3 << 1) +#define IOMUXC_GPR1_ACT_CS0BIT(0) /* GPR3 bitfields */ #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 @@ -465,6 +492,14 @@ struct src { #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET2 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3
[U-Boot] [PATCH v1 2/2] arm, imx6, aristainetos2: set gpr register after reset
setting the gpr 1,8 and 12 registers to a fix value. This is needed because after a WDT reset, this registers are not correct resettet, and prevent linux from booting again. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos-v2.c | 16 1 file changed, 16 insertions(+) diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c index 49dbd2e..fa4b4d2 100644 --- a/board/aristainetos/aristainetos-v2.c +++ b/board/aristainetos/aristainetos-v2.c @@ -580,6 +580,21 @@ static void setup_iomux_gpio(void) imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); } +static void set_gpr_register(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 | + IOMUXC_GPR1_EXC_MON_SLVE | + (2 << IOMUXC_GPR1_ADDRS0_OFFSET) | + IOMUXC_GPR1_ACT_CS0, + &iomuxc_regs->gpr[1]); + writel(0x0, &iomuxc_regs->gpr[8]); + writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN | + IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN, + &iomuxc_regs->gpr[12]); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -588,6 +603,7 @@ int board_early_init_f(void) gpio_direction_output(SOFT_RESET_GPIO, 1); gpio_direction_output(SD2_DRIVER_ENABLE, 1); setup_display(); + set_gpr_register(); return 0; } -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] Fix fdt 'reg' parsing and unbreak Odroid U3
Hello again, On 09/25/2015 10:56 AM, Przemyslaw Marczak wrote: Hello, On 09/24/2015 05:29 PM, Przemyslaw Marczak wrote: Booting of Odroid U3 with SD card, ends with error: MMC: EXYNOS DWMMC: 0 Card did not respond to voltage select! *** Warning - MMC init failed, using default environment Generally this was broken, because of wrong addresses assigned to GPIOs. The source of the problem was in rework of lib/fdtdec.c, after which function fdtdec_get_addr() doesn't work as previous and function dev_get_addr() doesn't works as expected. The code after rework in lib/fdtdec.c assume, that #size-cells property, should be always greater or equal to 1. This was wrong, because it can be 0. In case of debugging the issue I found, that mmc clock was computed wrong, for Exynos4, because of function get_mmc_clk(), which always return -1 for this SoC. Tested on: Odroid U3 and Odroid XU3. Przemyslaw Marczak (3): fix: fdtdec: allow parse 'reg' property with zero value in '#size-cells' fix: s5p_gpio: call: dev_get_addr() instead of fdtdec_get_addr() fix: mach-exynos: clock: restore calling dead exynos4_get_mmc_clk() arch/arm/mach-exynos/clock.c | 10 -- drivers/gpio/s5p_gpio.c | 18 +++--- lib/fdtdec.c | 2 +- 3 files changed, 16 insertions(+), 14 deletions(-) +Tested-on: Odroid X2 Best regards, This patchset also fixes broken boot on Trats2. Probably the same for other Exynos4 boards. +Tested-on: Trats2 Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] Fix fdt 'reg' parsing and unbreak Odroid U3
Hello Jaehoon, On 09/25/2015 04:40 AM, Jaehoon Chung wrote: Hi, Przemyslaw. On 09/25/2015 12:29 AM, Przemyslaw Marczak wrote: Booting of Odroid U3 with SD card, ends with error: MMC: EXYNOS DWMMC: 0 Card did not respond to voltage select! *** Warning - MMC init failed, using default environment Generally this was broken, because of wrong addresses assigned to GPIOs. Great! I will check this patch-set..But it seems to look good to me. :) Best Regards, Jaehoon Chung At present, the patchset was tested on U3/X2 and XU3. The source of the problem was in rework of lib/fdtdec.c, after which function fdtdec_get_addr() doesn't work as previous and function dev_get_addr() doesn't works as expected. The code after rework in lib/fdtdec.c assume, that #size-cells property, should be always greater or equal to 1. This was wrong, because it can be 0. In case of debugging the issue I found, that mmc clock was computed wrong, for Exynos4, because of function get_mmc_clk(), which always return -1 for this SoC. Tested on: Odroid U3 and Odroid XU3. Przemyslaw Marczak (3): fix: fdtdec: allow parse 'reg' property with zero value in '#size-cells' fix: s5p_gpio: call: dev_get_addr() instead of fdtdec_get_addr() fix: mach-exynos: clock: restore calling dead exynos4_get_mmc_clk() arch/arm/mach-exynos/clock.c | 10 -- drivers/gpio/s5p_gpio.c | 18 +++--- lib/fdtdec.c | 2 +- 3 files changed, 16 insertions(+), 14 deletions(-) Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] Fix fdt 'reg' parsing and unbreak Odroid U3
Hello, On 09/24/2015 05:29 PM, Przemyslaw Marczak wrote: Booting of Odroid U3 with SD card, ends with error: MMC: EXYNOS DWMMC: 0 Card did not respond to voltage select! *** Warning - MMC init failed, using default environment Generally this was broken, because of wrong addresses assigned to GPIOs. The source of the problem was in rework of lib/fdtdec.c, after which function fdtdec_get_addr() doesn't work as previous and function dev_get_addr() doesn't works as expected. The code after rework in lib/fdtdec.c assume, that #size-cells property, should be always greater or equal to 1. This was wrong, because it can be 0. In case of debugging the issue I found, that mmc clock was computed wrong, for Exynos4, because of function get_mmc_clk(), which always return -1 for this SoC. Tested on: Odroid U3 and Odroid XU3. Przemyslaw Marczak (3): fix: fdtdec: allow parse 'reg' property with zero value in '#size-cells' fix: s5p_gpio: call: dev_get_addr() instead of fdtdec_get_addr() fix: mach-exynos: clock: restore calling dead exynos4_get_mmc_clk() arch/arm/mach-exynos/clock.c | 10 -- drivers/gpio/s5p_gpio.c | 18 +++--- lib/fdtdec.c | 2 +- 3 files changed, 16 insertions(+), 14 deletions(-) +Tested-on: Odroid X2 Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] fix: s5p_gpio: call: dev_get_addr() instead of fdtdec_get_addr()
Hello Stephen, On 09/24/2015 07:29 PM, Stephen Warren wrote: On 09/24/2015 09:29 AM, Przemyslaw Marczak wrote: After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property, set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Migrating everything to dev_get_addr() is the correct long-term fix, so this patch, Acked-by: Stephen Warren ... although I'd have liked to see a smaller diff that didn't both re-order all the code /and/ call a different function, but I suppose that's not possible given the need to pass the device object to dev_get_addr(). You could have used fdtdec_get_addr_size_auto_parent() directly. Yes, it's not a single line diff, but the driver supports driver-model, so it's natural that it should use driver model API if can, instead of fdtdec API. This approach makes things easier to test and catch mistakes in the future. I think it'd be good to fix fdtdec_get_addr_size() to have the same semantics that it previously did. There might be other code in U-Boot that's affected by the same issue, and fixing fdtdec_get_addr_size() would make sure that all got fixed too. Are you willing to send that patch too? Essentially, fdtdec_get_addr_size() used to assume: #address-cells == sizeof(fdt_addr_t) if sizep == NULL: #size-cells == 0 else: #size-cells == sizeof(fdt_addr_t) However, it now assumes: #address-cells == sizeof(fdt_addr_t) #size-cells == sizeof(fdt_addr_t) Let's just add that condition back by doing something like the following in fdtdec_get_addr_size(): u32 ns; if (sizep) ns = sizeof(fdt_size_t) / sizeof(fdt32_t); else ns = 0; ... and replacing the ns parameter that's passed to fdtdec_get_addr_size_fixed() with that variable, rather than hard-coding it. Sorry, currently I have some other things to do, and I wouldn't prefer fixing this without proper testing. Such core things should be tested in sandbox by couple of unit tests. This seem to be okay, but is still wrong. We should always call fdtdec_get_addr_size_fixed() with arguments, which fits to the dtb, instead of hardcoded values. So, only the implementation of function fdtdec_get_addr_size_auto_parent() seem to be correct. It check the real #address-cells and #size-cells. If this is slow, then maybe we need some cache with nodes, its parents/childs and its size/addr cells to be checked only once? Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] fix: fdtdec: allow parse 'reg' property with zero value in '#size-cells'
Hello Stephen, On 09/24/2015 07:14 PM, Stephen Warren wrote: On 09/24/2015 09:29 AM, Przemyslaw Marczak wrote: After rework of lib/fdtdec.c by commit: commit 02464e386bb5f0a022c121f95ae75cf583759d95 Author: Stephen Warren Date: Thu Aug 6 15:31:02 2015 -0600 That'd usually be abbreviated as: Commit 02464e386bb5 "fdt: add new fdt address parsing functions". Ok, I will update the commit message. Of course, if you want to shame me that's justified too:-) Tracking down regressions sucks:-( Oh no no... maybe a little :) the function fdtdec_get_addr() doesn't work as previous, because the implementation assumes that properties '#address-cells' and '#size-cells' are equal to 1, which can be not true sometimes. "are equal to" should be "is at least"; the purpose of that rework was to support values greater than one. But it describe the fdtdec_get_addr(), which calls fdtdec_get_addr_size_fixed(...) and for this call we have: na = sizeof(fdt_addr_t) / sizeof(fdt32_t) == 1 ns = sizeof(fdt_size_t) / sizeof(fdt32_t) == 1 This is consistent with the description for this function in include/fdtdec.h. The new API introduced fdtdec_get_addr_size_auto_parent() for the 'reg' property parsing, but the implementation assumes, that #size-cells can't be less than 1. This causes that the following children's 'reg' property can't be reached: parent@0x0 { #address-cells = <1>; #size-cells = <0>; children@0x100 { reg = < 0x100 >; }; }; Change the condition value from '1' to '0', which allows parsing property with at least zero #size-cells, fixes the issue. Now, fdtdec_get_addr_size_auto_parent() works properly. Sorry about that. This patch, Don't worry, no one is infallible :) Acked-by: Stephen Warren (but not tested, but since this allows a previously failing case, it's hard to see how this patch could cause any problems.) This just fixes the problem, which I noticed, but it looks, that it shouldn't break other things. Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] tools: moveconfig: Update the URL for nds32 toolchain
Give a full URL for a working nds32 toolchain for U-Boot. Signed-off-by: Bin Meng --- tools/moveconfig.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/moveconfig.py b/tools/moveconfig.py index 496c90a..1b53f95 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -181,7 +181,7 @@ SLEEP_TIME=0.03 # (https://www.kernel.org/pub/tools/crosstool/files/bin/), except the followings: # arc: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases # blackfin: http://sourceforge.net/projects/adi-toolchain/files/ -# nds32: http://osdk.andestech.com/packages/ +# nds32: http://osdk.andestech.com/packages/nds32le-linux-glibc-v1.tgz # nios2: https://sourcery.mentor.com/GNUToolchain/subscription42545 # sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu CROSS_COMPILE = { -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Add generic defconfigs for A33 Q8 tablets with 1024x600 / 800x480 LCD
Hi, On 25-09-15 10:06, Hans de Goede wrote: Hi, On 25-09-15 04:35, Chen-Yu Tsai wrote: On Thu, Sep 24, 2015 at 11:24 PM, Hans de Goede wrote: diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig new file mode 100644 index 000..a9c2b62 --- /dev/null +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=456 +CONFIG_DRAM_ZQ=15291 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH8" +CONFIG_AXP_GPIO=y +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" FYI my q8h-v1.5 uses a slightly different mode line: x:800,y:480,depth:18,pclk_khz:36000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0 Yes, there are multiple modelines floating around for 800x480 panels, I've 2 A13 tablets and the modeline of the fex file from tablet a causes the images to not be properly centered on the screen of tablet b. Luckily the other way around does work, so for the q8_a13_tablet_defconfig I'm using the modeline from the fex file from tablet b. I hope we can do something similar with q8 a23 and a33 800x480 tablets. I've been buying q8 tablets with cracked screens To be clear s/screen/digitizer/ aka touchscreen, it usually is almost always the touchscreen which gets cracked and replacing that costs 4 usd (and half an hour of work). Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sunxi: Add generic defconfigs for A33 Q8 tablets with 1024x600 / 800x480 LCD
Hi, On 25-09-15 04:35, Chen-Yu Tsai wrote: On Thu, Sep 24, 2015 at 11:24 PM, Hans de Goede wrote: diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig new file mode 100644 index 000..a9c2b62 --- /dev/null +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=456 +CONFIG_DRAM_ZQ=15291 +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH8" +CONFIG_AXP_GPIO=y +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" FYI my q8h-v1.5 uses a slightly different mode line: x:800,y:480,depth:18,pclk_khz:36000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0 Yes, there are multiple modelines floating around for 800x480 panels, I've 2 A13 tablets and the modeline of the fex file from tablet a causes the images to not be properly centered on the screen of tablet b. Luckily the other way around does work, so for the q8_a13_tablet_defconfig I'm using the modeline from the fex file from tablet b. I hope we can do something similar with q8 a23 and a33 800x480 tablets. I've been buying q8 tablets with cracked screens (people seem to drop them quite a lot) for cheap from a local 2nd hand website, so now I've 5 ever so slightly different models, I still need to make a generic q8 config for those, and see if I can find a modeline which works on all of them. That modeline should probably be a good one to use for the a33 defconfig too. I'll find some time to give yours a test. Thanks! Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] nios2 : convert altera_pio to driver model
Convert altera_pio to driver model. Signed-off-by: Thomas Chou --- v2 fix ranges of pio in dts fix coding style as Marek suggested. arch/nios2/dts/3c120_devboard.dts | 41 arch/nios2/include/asm/gpio.h | 80 +--- board/altera/nios2-generic/nios2-generic.c | 7 - configs/nios2-generic_defconfig| 2 + drivers/gpio/Kconfig | 7 + drivers/gpio/altera_pio.c | 316 +++-- include/configs/nios2-generic.h| 20 -- 7 files changed, 127 insertions(+), 346 deletions(-) diff --git a/arch/nios2/dts/3c120_devboard.dts b/arch/nios2/dts/3c120_devboard.dts index a35f5fe..06c9422 100644 --- a/arch/nios2/dts/3c120_devboard.dts +++ b/arch/nios2/dts/3c120_devboard.dts @@ -68,6 +68,9 @@ <0x4400 0x08004400 0x0040>, <0x4800 0x08004800 0x0040>, <0x4c80 0x08004c80 0x0020>, + <0x4cc0 0x08004cc0 0x0010>, + <0x4ce0 0x08004ce0 0x0010>, + <0x4d00 0x08004d00 0x0010>, <0x4d50 0x08004d50 0x0008>, <0x8000 0x08008000 0x0020>, <0x0040 0x0840 0x0020>; @@ -132,6 +135,44 @@ clock-frequency = <6250>; u-boot,dm-pre-reloc; }; + + user_led_pio_8out: gpio@0x4cc0 { + compatible = "altr,pio-1.0"; + reg = <0x4cc0 0x0010>; + resetvalue = <255>; + width = <8>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "led"; + }; + + user_dipsw_pio_8in: gpio@0x4ce0 { + compatible = "altr,pio-1.0"; + reg = <0x4ce0 0x0010>; + interrupt-parent = <&cpu>; + interrupts = <8>; + edge_type = <2>; + level_trigger = <0>; + resetvalue = <0>; + width = <8>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "dipsw"; + }; + + user_pb_pio_4in: gpio@0x4d00 { + compatible = "altr,pio-1.0"; + reg = <0x4d00 0x0010>; + interrupt-parent = <&cpu>; + interrupts = <9>; + edge_type = <2>; + level_trigger = <0>; + resetvalue = <0>; + width = <4>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "pb"; + }; }; cfi_flash_64m: flash@0x0 { diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h index 908381f..306ab4c 100644 --- a/arch/nios2/include/asm/gpio.h +++ b/arch/nios2/include/asm/gpio.h @@ -1,79 +1 @@ -/* - * nios2 gpio driver - * - * This gpio core is described in http://nioswiki.com/GPIO - * bit[0] data - * bit[1] output enable - * - * When CONFIG_SYS_GPIO_BASE is not defined, the board may either - * provide its own driver or the altera_pio driver may be used. - * - * Copyright (C) 2010 Thomas Chou - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _ASM_NIOS2_GPIO_H_ -#define _ASM_NIOS2_GPIO_H_ - -#ifdef CONFIG_SYS_GPIO_BASE -#include - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -static inline int gpio_free(unsigned gpio) -{ - return 0; -} - -static inline int gpio_direction_input(unsigned gpio) -{ - writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2)); - return 0; -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2)); - return 0; -} - -static inline int gpio_get_value(unsigned gpio) -{ - return readl(CONFIG_SYS_GPIO_BASE + (gpio << 2)); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2)); -} - -static inline int gpio_is_valid(in
Re: [U-Boot] buildman toolchains
On Fri, Sep 25, 2015 at 3:48 PM, Bin Meng wrote: > Hi Masahiro, > > On Thu, Sep 24, 2015 at 5:51 PM, Masahiro Yamada > wrote: >> Hi Bin, >> >> 2015-09-24 10:53 GMT+09:00 Bin Meng : >>> Thanks Simon. >>> >>> On Tue, Sep 22, 2015 at 10:48 PM, Simon Glass wrote: +Masahiro, Hi, On 22 September 2015 at 08:01, Tom Rini wrote: > On Tue, Sep 22, 2015 at 01:12:56PM +0800, Bin Meng wrote: > >> Hi, >> >> I was using buildman to get toolchains from kernel.org to build U-Boot >> for as many boards as possible. But I still see some boards do not >> build. Are these build failures a known issue? Error log below: >> >> blackfin: + cm-bf561 blackstamp bct-brettl2 cm-bf527 bf506f-ezkit >> ip04 bf527-sdp bf537-minotaur bf609-ezkit bf537-stamp bf527-ezkit-v2 >> cm-bf537e tcm-bf518 cm-bf537u bf527-ezkit cm-bf533 pr1 bf533-ezkit >> ibf-dsp561 bf537-pnav bf537-srv1 cm-bf548 bf538f-ezkit bf548-ezkit >> bf525-ucr2 blackvme tcm-bf537 bf533-stamp bf518f-ezbrd >> bf527-ad7160-eval bf526-ezbrd bf561-ezkit br4 >>aarch64: + xilinx_zynqmp_ep hikey >> avr32: + atngw100mkii grasshopper atstk1002 atngw100 >>powerpc: + ebony taihu ocotea TQM834x taishan katmai >> sh: + sh7753evb rsk7269 rsk7264 shmin ms7720se mpr2 rsk7203 >> sh7785lcr_32bit sh7785lcr >>arm: + openrd_base axm openrd_ultimate zynq_zc70x >> openrd_client taurus > > I don't do sh but: > blackfin: + bf537-stamp bf527-ezkit-v2 bf527-ezkit bf538f-ezkit > bf526-ezbrd >aarch64: + p2371-2180 xilinx_zynqmp_ep hikey > avr32: + atngw100mkii grasshopper atstk1002 atngw100 >powerpc: + ebony taihu ocotea taishan katmai >sandbox: + sandbox >arm: + axm smartweb zynq_zc70x tricorder stm32f429-discovery > x600 tricorder_f > lash taurus > > is my list currently. This does include warnings (sandbox, hikey) and > some failures to link (ebony, etc). Sorry Bin, I didn't get back to your earlier email on this. I can't build everything at present, but these notes from Masahiro in the moveconfig.py script might be helpful: # Here is the list of cross-tools I use. # Most of them are available at kernel.org # (https://www.kernel.org/pub/tools/crosstool/files/bin/), except the followings: # arc: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases # blackfin: http://sourceforge.net/projects/adi-toolchain/files/ >>> >>> So is the kernel.org blackfin unusable for U-Boot build? >> >> IIRC, the kernel.org one could not build some of Bfin boards. >> > > Ah, yes, I just noticed that bf506f-ezkit_defconfig and > bf609-ezkit_defconfig cannot be parsed by moveconfig too. Just to avoid confusion, I wanted to say: with kernel.org blackfin toolchain, moveconfig failed to parse bf506f-ezkit_defconfig and bf609-ezkit_defconfig, due to toolchain limitations. [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] buildman toolchains
Hi Masahiro, On Thu, Sep 24, 2015 at 5:51 PM, Masahiro Yamada wrote: > Hi Bin, > > 2015-09-24 10:53 GMT+09:00 Bin Meng : >> Thanks Simon. >> >> On Tue, Sep 22, 2015 at 10:48 PM, Simon Glass wrote: >>> +Masahiro, >>> >>> Hi, >>> >>> On 22 September 2015 at 08:01, Tom Rini wrote: On Tue, Sep 22, 2015 at 01:12:56PM +0800, Bin Meng wrote: > Hi, > > I was using buildman to get toolchains from kernel.org to build U-Boot > for as many boards as possible. But I still see some boards do not > build. Are these build failures a known issue? Error log below: > > blackfin: + cm-bf561 blackstamp bct-brettl2 cm-bf527 bf506f-ezkit > ip04 bf527-sdp bf537-minotaur bf609-ezkit bf537-stamp bf527-ezkit-v2 > cm-bf537e tcm-bf518 cm-bf537u bf527-ezkit cm-bf533 pr1 bf533-ezkit > ibf-dsp561 bf537-pnav bf537-srv1 cm-bf548 bf538f-ezkit bf548-ezkit > bf525-ucr2 blackvme tcm-bf537 bf533-stamp bf518f-ezbrd > bf527-ad7160-eval bf526-ezbrd bf561-ezkit br4 >aarch64: + xilinx_zynqmp_ep hikey > avr32: + atngw100mkii grasshopper atstk1002 atngw100 >powerpc: + ebony taihu ocotea TQM834x taishan katmai > sh: + sh7753evb rsk7269 rsk7264 shmin ms7720se mpr2 rsk7203 > sh7785lcr_32bit sh7785lcr >arm: + openrd_base axm openrd_ultimate zynq_zc70x openrd_client > taurus I don't do sh but: blackfin: + bf537-stamp bf527-ezkit-v2 bf527-ezkit bf538f-ezkit bf526-ezbrd aarch64: + p2371-2180 xilinx_zynqmp_ep hikey avr32: + atngw100mkii grasshopper atstk1002 atngw100 powerpc: + ebony taihu ocotea taishan katmai sandbox: + sandbox arm: + axm smartweb zynq_zc70x tricorder stm32f429-discovery x600 tricorder_f lash taurus is my list currently. This does include warnings (sandbox, hikey) and some failures to link (ebony, etc). >>> >>> Sorry Bin, I didn't get back to your earlier email on this. I can't >>> build everything at present, but these notes from Masahiro in the >>> moveconfig.py script might be helpful: >>> >>> # Here is the list of cross-tools I use. >>> # Most of them are available at kernel.org >>> # (https://www.kernel.org/pub/tools/crosstool/files/bin/), except the >>> followings: >>> # arc: >>> https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases >>> # blackfin: http://sourceforge.net/projects/adi-toolchain/files/ >> >> So is the kernel.org blackfin unusable for U-Boot build? > > IIRC, the kernel.org one could not build some of Bfin boards. > Ah, yes, I just noticed that bf506f-ezkit_defconfig and bf609-ezkit_defconfig cannot be parsed by moveconfig too. > > >>> # nds32: http://osdk.andestech.com/packages/ >> >> Looks like this link is out of date, as there is no prebuilt toolchain >> available for download. Is there any alternative? > > > Try this: > http://osdk.andestech.com/packages/nds32le-linux-glibc-v1.tgz > > > It worked for me today. > Thank you very much. This works for me too. I can submit a patch to mention this link. > >>> # nios2: https://sourcery.mentor.com/GNUToolchain/subscription42545 >>> # sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu >>> Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot