Re: [U-Boot] [PATCH v2 3/4] mips: ath79: add serial driver for ar933x SOC

[Marek Vasut]

On Tuesday, December 22, 2015 at 08:44:44 AM, Wills Wang wrote:
> Signed-off-by: Wills Wang 
> ---
> 
>  drivers/serial/Makefile|   1 +
>  drivers/serial/serial_ar933x.c | 337
> + 2 files changed, 338
> insertions(+)
>  create mode 100644 drivers/serial/serial_ar933x.c
> 
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index dd87147..9a7ad89 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -17,6 +17,7 @@ endif
> 
>  obj-$(CONFIG_ALTERA_UART) += altera_uart.o
>  obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
> +obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o
>  obj-$(CONFIG_ARM_DCC) += arm_dcc.o
>  obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
>  obj-$(CONFIG_EFI_APP) += serial_efi.o
> diff --git a/drivers/serial/serial_ar933x.c
> b/drivers/serial/serial_ar933x.c new file mode 100644
> index 000..6ea500a
> --- /dev/null
> +++ b/drivers/serial/serial_ar933x.c
> @@ -0,0 +1,337 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define REG_READ(b, o)  readl(KSEG1ADDR(b + o))
> +#define REG_WRITE(b, o, v)  writel(v, KSEG1ADDR((b + o)))
> +#define UART_READ(a)REG_READ(AR933X_UART_BASE, a)
> +#define UART_WRITE(a, v)REG_WRITE(AR933X_UART_BASE, a, v)

Please remove these macros (see below)

> +static void ar933x_serial_get_scale_step(u32 *uart_scale, u32 *uart_step)
> +{
> + u32 val;
> +
> + val = REG_READ(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP);
> + if (val & AR933X_BOOTSTRAP_REF_CLK_40) {
> + switch (gd->baudrate) {
> + case 600:
> + *uart_scale = 255;
> + *uart_step  = 503;
> + break;
> + case 1200:
> + *uart_scale = 249;
> + *uart_step  = 983;

I suppose this cannot be calculated, right ? What about making this into a
table, something like:

struct {
u16 baudrate;
u16 scale;
u16 step;
} uart_something[] {
{ 600, 255, 503 },
{ 1200,  },

};

and then look things up:

for (i = 0; i < ARRAY_SIZE(uart_something); i++)
if (gd->baudrate == uart_something[i].baudrate)
break;

if (i == ARRAY_SIZE(uart_something))
do default handling here
[...]

> + default:
> + *uart_scale = (4000 / (16 * gd->baudrate)) - 1;
> + *uart_step = 8192;
> + }
> + } else {
> + switch (gd->baudrate) {
> + case 600:
> + *uart_scale = 255;
> + *uart_step  = 805;
> + break;

You can wrap this part into the table as well then, quite easily.

[...]

> +static void ar933x_serial_setbrg(void)
> +{
> + /* TODO: better clock calculation, baudrate, etc. */
> + u32 val, scale, step;
> +
> + ar933x_serial_get_scale_step(, );
> + val  = ((scale & AR933X_UART_CLOCK_SCALE_M)
> + << AR933X_UART_CLOCK_SCALE_S);
> + val |= ((step & AR933X_UART_CLOCK_STEP_M)
> + << AR933X_UART_CLOCK_STEP_S);

Drop the extraneous parenthesis around the statement please.

> + UART_WRITE(AR933X_UART_CLOCK_REG, val);

This should be just writel().

> +}
> +
> +int ar933x_serial_init(void)
> +{
> + u32 val;
> +
> + /*
> +  * Set GPIO10 (UART_SO) as output and enable UART,
> +  * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
> +  */
> + val = REG_READ(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
> + val |= BIT(10);
> + REG_WRITE(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);

Use setbits_le32()

> + val = REG_READ(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
> + val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
> + REG_WRITE(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val);

Same here.

> + /*
> +  * UART controller configuration:
> +  * - no DMA
> +  * - no interrupt
> +  * - DCE mode
> +  * - no flow control
> +  * - set RX ready oride
> +  * - set TX ready oride
> +  */
> + val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
> + | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
> + UART_WRITE(AR933X_UART_CS_REG, val);
> + ar933x_serial_setbrg();
> +
> + return 0;
> +}
> +
> +void ar933x_serial_putc(const char c)
> +{
> + u32 data;
> +
> + if (c == '\n')
> + ar933x_serial_putc('\r');
> +
> + do {
> + data = UART_READ(AR933X_UART_DATA_REG);
> + } while (!(data & AR933X_UART_DATA_TX_CSR));
> +
> + data  = (u32)c | AR933X_UART_DATA_TX_CSR;

$c is already u32, no need for the cast.

> + 

Re: [U-Boot] [PATCH v2 0/4] add support for atheros ath79 based SOCs

[Marek Vasut]

On Tuesday, December 22, 2015 at 08:44:41 AM, Wills Wang wrote:
> These series of patch add support for atheros ath79 based SOCs in u-boot,
> at the present moment it's just available for ar933x chip.
> 
> Changes since V1:
> 1. Move all SoC specific header files into arch/mips/include/asm/arch-ath79
> 2. Check SOC type and extract common code into arch/mips/mach-ath79
> 3. Add a compatible spi driver
> 4. Move serial driver code into drivers/serial
> 5. Add a reference board implemention
> 
> 
> Wills Wang (4):
>   mips: add base support for atheros ath79 based SOCs
>   mips: ath79: add spi driver
>   mips: ath79: add serial driver for ar933x SOC
>   mips: ath79: add AP121 reference board

And here I wanted to work on ar9331 over the xmas :) I'm glad someone else is
doing this task, please keep me on CC on the patches :)

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 2/2] arm: imx6: Enable DDR calibration on Novena

[Marek Vasut]

On Tuesday, December 22, 2015 at 09:30:00 AM, Nikolay Dimitrov wrote:
> Hi Marek,
> 
> On 12/22/2015 03:26 AM, Marek Vasut wrote:
> > On Sunday, December 20, 2015 at 08:33:58 PM, Eric Nelson wrote:
> >> Hi Marek,
> >> 
> >> On 12/16/2015 07:40 AM, Marek Vasut wrote:
> >>> Enable the DDR calibration functionality on Novena to deal with the
> >>> memory SoDIMM on this board.
> >> 
> >> Shouldn't this be in two patches?
> > 
> > Not really, the old values work without the enabled calibration. This
> > change needs to be done atomically.
> > 
> > [...]
> > 
> >>>   static void ccgr_init(void)
> >>> 
> >>> @@ -601,6 +601,11 @@ void board_init_f(ulong dummy)
> >>> 
> >>>   mx6dq_dram_iocfg(64, _ddr_ioregs, _grp_ioregs);
> >>>   mx6_dram_cfg(_ddr_info, _mmdc_calib,
> >>>   _4gib_1600);
> >>> 
> >>> + /* Perform DDR DRAM calibration */
> >>> + udelay(100);
> >> 
> >> Shouldn't the return values be tested?
> > 
> > I guess yes, but if the calibration fails, that what ? It's game over ;-)
> 
> Do you think it's possible/practical to reboot the system in this case?

Well, you can call hang() , that's how we've been handling critical failures.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] ARM: uniphier: add const qualifier to constant array

[Masahiro Yamada]

2015-12-16 10:36 GMT+09:00 Masahiro Yamada :
> Signed-off-by: Masahiro Yamada 
> ---

applied to u-boot-uniphier/master.




-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH] ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_*

[Masahiro Yamada]

2015-12-16 10:42 GMT+09:00 Masahiro Yamada :
> The bit 27-24 of the DTCR register is described as RANKEN in the
> DDR PHY databook.  Follow this abbreviation.
>
> Signed-off-by: Masahiro Yamada 

applied to u-boot-uniphier/master.


-- 
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Re: [U-Boot] [PATCH] ARM: uniphier: use BIT() macro for DDR PHY header

[Masahiro Yamada]

2015-12-16 10:44 GMT+09:00 Masahiro Yamada :
> Signed-off-by: Masahiro Yamada 


applied to u-boot-uniphier/master.


-- 
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Re: [U-Boot] [PATCH 1/2] ARM: dts: uniphier: factor out common nodes to uniphier-common32.dtsi

[Masahiro Yamada]

2015-12-16 10:54 GMT+09:00 Masahiro Yamada :
> UniPhier SoCs (except PH1-sLD3) have several nodes in common.
> Factor out them into uniphier-common32.dtsi.  This improves the code
> maintainability.
>
> PH1-sLD3 is so old that it has more or less different register maps
> than the others.  So, it cannot be included in this refactoring.
>
> Signed-off-by: Masahiro Yamada 

applied to u-boot-uniphier/master.

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Re: [U-Boot] [PATCH 2/2] ARM: dts: uniphier: add outer cache nodes

[Masahiro Yamada]

2015-12-16 10:54 GMT+09:00 Masahiro Yamada :
> These nodes are not parsed by U-Boot for now, but syncing device trees
> with Linux is helpful for easier diffing.
>
> Signed-off-by: Masahiro Yamada 

applied to u-boot-uniphier/master.

-- 
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Re: [U-Boot] [PATCH] ARM: uniphier: add static qualifiers to locally used functions

[Masahiro Yamada]

2015-12-11 17:17 GMT+09:00 Masahiro Yamada :
> Signed-off-by: Masahiro Yamada 

applied to u-boot-uniphier/master.


-- 
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Re: [U-Boot] [PATCH] ARM: dts: uniphier: use stdout-path instead of console

[Masahiro Yamada]

2015-12-17 15:05 GMT+09:00 Masahiro Yamada :
> Sync device trees with Linux.
>
> Linux commit: 06ff6b2d63210922a1b1d0f4997e29ce75b5e0c0
>
> Signed-off-by: Masahiro Yamada 

applied to u-boot-uniphier/master.

-- 
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Re: [U-Boot] [PATCH 6/6] arm: socfpga: Add support for Denali NAND controller

[Chin Liang See]

On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> Add common configuration bits for the Denali NAND controller and also
> support for using it as a boot device in SPL.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
>  include/configs/socfpga_common.h | 23 +++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> index 4124d8b..8886ccf 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -162,6 +162,19 @@
>  #endif
>  
>  /*
> + * NAND Support
> + */
> +#ifdef CONFIG_NAND_DENALI
> +#define CONFIG_SYS_MAX_NAND_DEVICE   1
> +#define CONFIG_SYS_NAND_MAX_CHIPS1
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +#define CONFIG_NAND_DENALI_ECC_SIZE  512
> +#define CONFIG_SYS_NAND_REGS_BASE0xffb8
> +#define CONFIG_SYS_NAND_DATA_BASE0xff90

You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS

> +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BA
> SE + 0x10)
> +#endif
> +
> +/*
>   * I2C support
>   */
>  #define CONFIG_SYS_I2C
> @@ -302,6 +315,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #ifdef CONFIG_DM_SPI
>  #define CONFIG_SPL_SPI_SUPPORT
>  #endif
> +#ifdef CONFIG_SPL_NAND_DENALI
> +#define CONFIG_SPL_NAND_SUPPORT
> +#endif
>  
>  /* SPL SDMMC boot support */
>  #ifdef CONFIG_SPL_MMC_SUPPORT
> @@ -324,6 +340,13 @@ unsigned int
> cm_get_qspi_controller_clk_hz(void);
>  #define CONFIG_SYS_SPI_U_BOOT_OFFS   0x4
>  #endif
>  
> +/* SPL NAND boot support */
> +#ifdef CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#define CONFIG_SYS_NAND_BAD_BLOCK_POS0

I believe this is need for U-Boot too, right?

Thanks
Chin Liang

> +#define CONFIG_SYS_NAND_U_BOOT_OFFS  0x4
> +#endif
> +
>  /*
>   * Stack setup
>   */
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Re: [U-Boot] [PATCH 0/7] ARM: uniphier: misc changes for v2016.01-rc3

[Masahiro Yamada]

2015-12-17 17:47 GMT+09:00 Masahiro Yamada :
>
> Masahiro Yamada (7):
>   ARM: uniphier: add functions to get SoC model/revision
>   ARM: uniphier: call uniphier_get_board_param() without FDT blob
>   ARM: uniphier: split ProXstream2 board data and change DDR frequency
>   ARM: uniphier: compile uniphier_get_board_param() for U-Boot proper
>   ARM: uniphier: add macros and revision code for sLD11 and LD10
>   ARM: uniphier: display model number all the time on boot up
>   ARM: uniphier: merge umc/ and ddrphy/ into a single directory


Series, applied to u-boot-uniphier/master.


-- 
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Re: [U-Boot] [PATCH 0/5] ARM: uniphier: consolidate defconfig files

[Masahiro Yamada]

2015-12-17 18:00 GMT+09:00 Masahiro Yamada :
>
>
>
> Masahiro Yamada (5):
>   ARM: uniphier: set DTB file name to fdt_file environment
>   ARM: uniphier: drop fdt_file from CONFIG_EXTRA_ENV_SETTINGS
>   ARM: uniphier: merge ph1_ld4_defconfig and ph1_sld8_defconfig
>   ARM: uniphier: support ProXstream2, PH1-LD6b boards in single
> defconfig
>   ARM: uniphier: rename defconfig files

Series, applied to u-boot-uniphier/master.


-- 
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Re: [U-Boot] [PATCH 5/6] arm: socfpga: Enable DFU MMC support only if DM_MMC is enabled

[Chin Liang See]

On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> It is not possible to compile DFU MMC support if the MMC support is
> not
> compiled into U-Boot. Secure the code with an ifdef to prevent
> compiler
> splat.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
>  include/configs/socfpga_common.h | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Chin Liang See 

Thanks
Chin Liang
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[U-Boot] pull request: u-boot-uniphier/master

[Masahiro Yamada]

Hi Tom,

Here are various cleanups and preparation for new SoCs support.
Please pull!


The following changes since commit f84c2b665b87fc6713a756d0fddf5c45e02255e5:

  Prepare v2016.01-rc3 (2015-12-21 21:07:04 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-uniphier.git master

for you to fetch changes up to 8182b41994f0b1824c31652d64171ffa596517fc:

  ARM: dts: uniphier: add SD/MMC pinmux nodes (2015-12-23 00:09:05 +0900)


Masahiro Yamada (22):
  ARM: uniphier: add static qualifiers to locally used functions
  ARM: uniphier: add const qualifier to constant array
  ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_*
  ARM: uniphier: use BIT() macro for DDR PHY header
  ARM: uniphier: allow DDR function to return more precise error code
  ARM: dts: uniphier: factor out common nodes to uniphier-common32.dtsi
  ARM: dts: uniphier: add outer cache nodes
  ARM: dts: uniphier: use stdout-path instead of console
  ARM: uniphier: add functions to get SoC model/revision
  ARM: uniphier: call uniphier_get_board_param() without FDT blob
  ARM: uniphier: split ProXstream2 board data and change DDR frequency
  ARM: uniphier: compile uniphier_get_board_param() for U-Boot proper
  ARM: uniphier: add macros and revision IDs for sLD11 and LD10
  ARM: uniphier: display model number all the time on boot up
  ARM: uniphier: merge umc/ and ddrphy/ into a single directory
  ARM: uniphier: set DTB file name to fdt_file environment
  ARM: uniphier: drop fdt_file from CONFIG_EXTRA_ENV_SETTINGS
  ARM: uniphier: merge ph1_ld4_defconfig and ph1_sld8_defconfig
  ARM: uniphier: support ProXstream2, PH1-LD6b boards in single defconfig
  ARM: uniphier: rename rest of defconfig files
  ARM: uniphier: allow to run zImage rather than uImage
  ARM: dts: uniphier: add SD/MMC pinmux nodes

 MAINTAINERS  |   2 +-
 arch/arm/dts/uniphier-common32.dtsi  | 105
++
 arch/arm/dts/uniphier-ph1-ld4-ref.dts|   3 +-
 arch/arm/dts/uniphier-ph1-ld4.dtsi   | 269
+-
 arch/arm/dts/uniphier-ph1-ld6b-ref.dts   |   3 +-
 arch/arm/dts/uniphier-ph1-pro4-ref.dts   |   3 +-
 arch/arm/dts/uniphier-ph1-pro4.dtsi  | 327
+-
 arch/arm/dts/uniphier-ph1-pro5-4kbox.dts |   3 +-
 arch/arm/dts/uniphier-ph1-pro5.dtsi  | 294
-
 arch/arm/dts/uniphier-ph1-sld3-ref.dts   |   3 +-
 arch/arm/dts/uniphier-ph1-sld8-ref.dts   |   3 +-
 arch/arm/dts/uniphier-ph1-sld8.dtsi  | 269
+-
 arch/arm/dts/uniphier-pinctrl.dtsi   |  15 ++
 arch/arm/dts/uniphier-proxstream2-gentil.dts |   3 +-
 arch/arm/dts/uniphier-proxstream2-vodka.dts  |   3 +-
 arch/arm/dts/uniphier-proxstream2.dtsi   | 308
---
 arch/arm/mach-uniphier/Makefile  |   4 +-
 arch/arm/mach-uniphier/board_late_init.c |  35 +
 arch/arm/mach-uniphier/boards.c  |  27 +++-
 arch/arm/mach-uniphier/cmd_ddrphy.c  |  12 +-
 arch/arm/mach-uniphier/cpu_info.c|   9 +-
 arch/arm/mach-uniphier/ddrphy/Makefile   |   7 -
 arch/arm/mach-uniphier/dram/Makefile |  10 ++
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-ld4.c |   0
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-pro4.c|   0
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-ph1-sld8.c|   0
 arch/arm/mach-uniphier/{ddrphy => dram}/ddrphy-training.c|  11 +-
 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-ld4.c   |   0
 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-pro4.c  |   0
 arch/arm/mach-uniphier/{umc => dram}/umc-ph1-sld8.c  |   0
 arch/arm/mach-uniphier/include/mach/ddrphy-regs.h|  95 ++--
 arch/arm/mach-uniphier/include/mach/init.h   |   2 +-
 arch/arm/mach-uniphier/include/mach/soc_info.h   |  15 +-
 arch/arm/mach-uniphier/init/init.c   |   4 +-
 arch/arm/mach-uniphier/soc_info.c|  22 +++
 arch/arm/mach-uniphier/umc/Makefile  |   7 -
 configs/ph1_sld8_defconfig   |  30 
 configs/{ph1_ld4_defconfig => uniphier_ld4_sld8_defconfig}   |   1 +
 configs/{ph1_pro4_defconfig => uniphier_pro4_defconfig}  |   0
 configs/{ph1_pro5_defconfig => uniphier_pro5_defconfig}  |   0
 

Re: [U-Boot] [PATCH 3/6] arm: socfpga: Unreset NAND in U-Boot

[Chin Liang See]

On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> Make sure the NAND reset is not asserted in full U-Boot.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
>  arch/arm/mach-socfpga/misc.c | 4 
>  1 file changed, 4 insertions(+)
> 

Acked-by: Chin Liang See 

Thanks
Chin Liang
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Re: [U-Boot] [PATCH 4/6] arm: socfpga: Enable SPL MMC/SPI support only if DM_MMC/SPI is enabled

[Chin Liang See]

On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> It is not possible to compile MMC/SPI SPL if the respective
> DM_MMC/DM_SPI
> bits are not enabled. Secure the code with an ifdef to prevent
> compiler
> splat.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> ---
> 


Acked-by: Chin Liang See 

Thanks
Chin Liang
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Re: [U-Boot] [PATCH 4/9] efi_loader: Add boot time services

[Alexander Graf]

On 22.12.15 15:15, Andreas Färber wrote:
> Am 22.12.2015 um 14:57 schrieb Alexander Graf:
>> diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
>> new file mode 100644
>> index 000..ed95962
>> --- /dev/null
>> +++ b/lib/efi_loader/efi_boottime.c
> [...]
>> +/*
>> + * The "gd" pointer lives in a register on ARM and AArch64 that we declare
>> + * fixed when compiling U-Boot. However, the payload does now know about 
>> that
> 
> "does not"?

Yup, fixed for v2, thanks :).


Alex
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Re: [U-Boot] [PATCH] ARM: uniphier: allow DDR function to return more precise error code

[Masahiro Yamada]

2015-12-16 10:50 GMT+09:00 Masahiro Yamada :
> Return different error code depending on the reason so that the
> caller can know the cause of the failure.
>
> Signed-off-by: Masahiro Yamada 

applied to u-boot-uniphier/master.

-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 1/2] arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL

[Eric Nelson]

Hi Marek,

On 12/21/2015 06:52 PM, Marek Vasut wrote:
> On Sunday, December 20, 2015 at 08:31:46 PM, Eric Nelson wrote:
>> On 12/16/2015 07:40 AM, Marek Vasut wrote:
...
>>> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
>>> index 6b039e4..194411f 100644
>>> --- a/arch/arm/cpu/armv7/mx6/ddr.c
>>> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
>>> @@ -13,6 +13,565 @@
>>>
>>>  #include 
>>>  #include 
>>>
>>> +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) ||
>>> defined(CONFIG_MX6D) +
>>
>> Should this use the common wait_for_bit?
>>  http://lists.denx.de/pipermail/u-boot/2015-December/thread.html#237952
>>
>> I'm not certain that the  handling is appropriate when
>> used here.
> 
> Yes, that's why I called it exactly the same, so once the patches above hit
> mainline, I could just nuke this function and replace it with the common one.
> 

Sounds good.

>>> +static int wait_for_bit(void *reg, const uint32_t mask, bool set)
>>> +{

...

>>
>> See comments below about chip-selects during calibration.
>>
>>> +static void precharge_all(const bool cs0_enable, const bool cs1_enable)
>>> +{
>>> +   struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
>>> +
>>> +   /*
>>> +* Issue the Precharge-All command to the DDR device for both
>>> +* chip selects. Note, CON_REQ bit should also remain set. If
>>> +* only using one chip select, then precharge only the desired
>>> +* chip select.
>>> +*/
>>
>> AN4467 says that a wait for tRP is needed here, though none of the
>> other implementations explicitly do that.
>>
>> The wait for CON_ACK seems like a good idea, though I wonder if
>> the waits shouldn't be performed **before** the commands are issued.
>>
>> I'd also like to see a named constant for MDSCR_CON_ACK
> 
> That'd be great. Do you know of some header where the MMDC register bits
> are defined ?

I don't.

I think this is stuff that's supposed to be done by the boot loader ;).

> I am definitelly not gonna rewrite the the i.MX6 MMDC bits
> from the datasheet by hand.
> 

How about just one constant?

>> , and since
>> waiting for it is done in multiple places, perhaps wait_for_con_ack().
> 
> Implementing a function for the sake of just wrapping another function
> seems wasteful to me.
> 

I was thinking macro, but okay.

>>> +   if (cs0_enable) { /* CS0 */
>>> +   writel(0x04008050, >mdscr);
>>> +   wait_for_bit(>mdscr, 1 << 14, 1);
>>> +   }
>>> +
>>> +   if (cs1_enable) { /* CS1 */
>>> +   writel(0x04008058, >mdscr);
>>> +   wait_for_bit(>mdscr, 1 << 14, 1);
>>> +   }
>>> +}
>>> +
>>> +static void force_delay_measurement(int bus_size)
>>> +{
>>> +   struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
>>> +   struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
>>> +
>>> +   writel(0x800, >mpmur0);
>>> +   if (bus_size == 0x2)
>>> +   writel(0x800, >mpmur0);
>>> +}
>>> +
>>> +static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
>>> +{
>>> +   u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
>>> +
>>> +   /*
>>> +* DQS gating absolute offset should be modified from reflecting
>>> +* (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
>>> +*/
>>> +
>>> +   val_ctrl = readl(reg_ctrl);
>>> +   val_ctrl &= 0xf000;
>>> +
>>
>> Though this matches the app note and other implementations, I think
>> this would be easier to understand by shifting first and anding with
>> 0x7ff.
> 
> I think it is better to stick with the appnote, so it's easy to map the
> code and the appnote between one another.
> 

Okay. My hope is that a future app note will refer to the new code...

>>> +   dg_tmp_val = ((readl(reg_st0) & 0x07ff) >> 16) - 0xc0;
>>
>> Especially since these calculations operate on the shifted values:
>>> +   dg_dl_abs_offset = dg_tmp_val & 0x7f;
>>> +   dg_hc_del = (dg_tmp_val & 0x780) << 1;
>>> +
>>> +   val_ctrl |= dg_dl_abs_offset + dg_hc_del;
>>> +
>>> +   dg_tmp_val = ((readl(reg_st1) & 0x07ff) >> 16) - 0xc0;
>>> +   dg_dl_abs_offset = dg_tmp_val & 0x7f;
>>> +   dg_hc_del = (dg_tmp_val & 0x780) << 1;
>>> +
>>> +   val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
>>> +
>>> +   writel(val_ctrl, reg_ctrl);
>>> +}
>>> +
>>
>> I'd recommend passing parameters of mx6_ddr_sysinfo (input) and
>> mx6_mmdc_calibration (output) to this routine.
> 
> Why exactly ?
> 

I sent a note about this in response to Tim's comment.

>>> +int mmdc_do_write_level_calibration(void)
>>> +{
>>> +   struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
>>> +   struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
>>> +   u32 esdmisc_val, zq_val;
>>> +   u32 errors = 0;
>>> +   u32 ldectrl[4];
>>
>> I believe the 4 here comes from this calculation:
>>
>>  ddr_mr1 = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
>>((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
>>
>>> +   u32 ddr_mr1 = 0x4;
>>> +
>>
>> I'm not sure how 

Re: [U-Boot] Driver model test breakages

[Joe Hershberger]

Hi Simon,

On Mon, Dec 21, 2015 at 9:17 PM, Joe Hershberger
 wrote:
> Hi Bin and Simon,
>
> On Mon, Dec 21, 2015 at 9:08 PM, Joe Hershberger
>  wrote:
>> Hi Bin,
>>
>> On Mon, Dec 21, 2015 at 9:00 PM, Bin Meng  wrote:
>>> Hi Joe,
>>>
>>> On Tue, Dec 22, 2015 at 10:39 AM, Joe Hershberger
>>>  wrote:
 On Mon, Dec 21, 2015 at 8:36 PM, Bin Meng  wrote:
> Hi Joe,
>
> On Tue, Dec 22, 2015 at 10:32 AM, Joe Hershberger
>  wrote:
>> Hi Bin,
>>
>> On Mon, Dec 21, 2015 at 8:12 PM, Bin Meng  wrote:
>>> Hi Joe, Simon,
>>>
>>> On Tue, Dec 22, 2015 at 6:46 AM, Joe Hershberger
>>>  wrote:
 Hi Simon and Bin

 On Thu, Dec 10, 2015 at 8:05 PM, Simon Glass  wrote:
> Hi,
>
> The following three commits causes breakages in the driver model 
> tests:
>
> 4efad20a  sf: Update status reg check in spi_flash_cmd_wait_ready
> 45b47734 net/arp: account for ARP delay, avoid duplicate packets 
> on timeout
> 9961a0b6sandbox: add a sandbox timer and basic test
>
> Can you please take a look? You can run them with ./test/dm/test-dm.sh

 It appears that ac1d313 (net: eth: Check return value in various
 places) breaks the eth_rotate test.

 Looking into it. Bin, do you have any ideas?
>>>
>>> I will look into this.
>>>
>>> BTW: I applied the following two patches [1][2] to the tree based on
>>> dm/master, and got a segmentation fault:
>>>
>>> Test: dm_test_usb_keyb
>>> ./test/dm/test-dm.sh: line 14: 24902 Segmentation fault
>>> ./sandbox/u-boot -d ./sandbox/arch/sandbox/dts/test.dtb -c "ut dm"
>>>
>>> [1] http://patchwork.ozlabs.org/patch/97/
>>> [2] http://patchwork.ozlabs.org/patch/559783/
>>
>> Interesting. I haven't tested on top of dm/master, but I tested it
>> based on origin/master and the issue is resolved.
>>
>
> Which issue is resolved? I just tested on top of origin/master with
> the above two patches, still the same segmentation fault.

 The net_retry dm test hang that Simon reported.

>>>
>>> The segmentation fault happens after "Test: dm_test_usb_keyb". It
>>> seems to be a new issue.
>>
>> I agree it's a new issue that was masked by the net_retry hang.
>
> It appears, not too surprisingly, that d77a7d8 (dm: test: usb:
> sandbox: Add keyboard tests for sandbox) is the source of the seg
> fault.
>
> Simon?

In looking for the seg fault in the usb kbd test, I found that the
udev ptr passed to usb uclass is garbage, so the usb_ops is null, so
we crash. Do you have a quick explanation for how this emulated USB is
supposed to work? I haven't looked at it before. I'll keep digging
until you can provide some insight.

-Joe
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Re: [U-Boot] [RESEND PATCH 0/5] clk: some fixes, device tree support, new features

[Simon Glass]

Hi Masahiro,

On 22 December 2015 at 03:04, Masahiro Yamada
 wrote:
> This series contains the same commits
> as 01-05 of the RFC series.
>
> Since somebody immediately marked it as RFC
> (i.e. dropped from the TODO items in the patchwork),
> nothing has happened to it.
>
> I am resending 01-05 without RFC prefix
> in order to leave this series in the TODO list
> until appropriate action is taken.
>
> As you see, 01 and 02 are apparent fixes
> which can be applied soon.

I noticed this a few days ago and applied it locally. I did manage to
find it in patchwork in the end. I have a few review comments so will
tidy those up and send them through...

>
>
>
> Masahiro Yamada (5):
>   clk: fix comments in include/clk.h
>   clk: add needed include and declaration to include/clk.h
>   clk: add function to get peripheral ID
>   clk: add device tree support for clock framework
>   clk: add enable() callback
>
>  drivers/clk/Makefile |  1 +
>  drivers/clk/clk-fdt.c| 37 
>  drivers/clk/clk-uclass.c | 10 ++
>  include/clk.h| 87 
> ++--
>  4 files changed, 125 insertions(+), 10 deletions(-)
>  create mode 100644 drivers/clk/clk-fdt.c
>
> --
> 1.9.1
>

Regards,
Simon
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Re: [U-Boot] [PATCH 0/9] EFI payload / application support

[Matwey V. Kornilov]

2015-12-22 16:57 GMT+03:00 Alexander Graf :
> This is my Christmas present for my openSUSE friends :).
>

Santa, do you have u-boot rpm packed with the patches to test?

-- 
With best regards,
Matwey V. Kornilov
http://blog.matwey.name
xmpp://0x2...@jabber.ru
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Re: [U-Boot] [PATCH 1/1] common: nvedit: use snprintf instead of sprintf

[Joe Hershberger]

On Tue, Dec 22, 2015 at 3:14 AM, Peng Fan  wrote:
> From: Peng Fan 
>
> Use snprintf to replace sprintf.
>
> Signed-off-by: Peng Fan 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Joe Hershberger 

Seems safer.
Reviewed-by: Joe Hershberger 
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 

Applied, thanks.

I will push your patches to [1] in a few hours, can you try and see if the
CV SOCDK works fine for you? Thanks

[1] http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/master

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Marek Vasut]

On Tuesday, December 22, 2015 at 05:00:42 PM, Chin Liang See wrote:
> On Tue, 2015-12-22 at 16:53 +0100, Marek Vasut wrote:
> > On Tuesday, December 22, 2015 at 04:49:54 PM, Chin Liang See wrote:
> > > On Fri, 2015-12-18 at 14:10 +0100, Marek Vasut wrote:
> > > > On Friday, December 18, 2015 at 10:39:12 AM, Chin Liang See
> > > 
> > > > wrote:
> > > [..]
> > > 
> > > > > > I will send that patch out shortly, but I think there is
> > > > > > something
> > > > > > else
> > > > > > going on. I am starting to suspect something with the L3
> > > > > > interconnect.
> > > > > > Maybe some R/W reordering or something like that in NIC301 .
> > > > > > 
> > > > > > Are you able to replicate my USB issue with mainline on
> > > > > > socfpga ?
> > > > > > What
> > > > > > happens if you run usb reset with a USB stick plugged in?
> > > > > > What
> > > > > > compiler
> > > > > > version do you use ?
> > > > > 
> > > > > I tried that few weeks back and it works for me. FYI, I am
> > > > > using
> > > > > the
> > > > > mentor toolchain "arm-altera-eabi" that come with SOCEDS. Maybe
> > > > > I
> > > > > can
> > > > > try again with your toolchain.
> > > > 
> > > > I am using the unreleased ELDK 5.8 (gcc 4.9.2) and debian gcc
> > > > 5.2.
> > > > Which gcc version is in the mentor toolchain?
> > > 
> > > Mine is Sourcery CodeBench Lite 2015.05-11 (gcc 4.9.2 also)
> > > 
> > > > Can you try it again with u-boot/master ? I'd be interested in
> > > > your
> > > > results.
> > > > Can you share the entire output of the U-Boot and run 'dcache'
> > > > command before
> > > > doing 'usb reset' ? I am seeing this issue with Sandisk Cruzer
> > > > USB
> > > > 2.0 sticks
> > > > now too.
> > > 
> > > I can do that but git clone will take some time
> > 
> > You can use git fetch in your current repo.
> > 
> > I started wondering how you're testing the CV SoCDK, since I
> > discovered just
> > this morning that it doesn't even boot (I already sent patches to fix
> > that).
> 
> I presume you are referring to SPL? FYI, I am still using the SPL from
> SOCEDS while using latest U-Boot from mainstream. That's why I didn't
> the issue noticed by Shengjiang and you.

Well, at least you're honest ... but *sigh*, it'd be nice if you tested
mainline only, really.

> But will make the switch soon once done with few in progress patches
> for U-Boot.

I will collect the remaining patches today and see how socdk fares.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 01/17] arm: socfpga: Enable ubi and ubifs support

[Marek Vasut]

On Tuesday, December 22, 2015 at 08:32:26 AM, Chin Liang See wrote:
> When QSPI and NAND is enabled, the ubi and ubifs support
> will be enabled too.
> 
> Signed-off-by: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 

Applied all, thanks.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 04/17] arm: socfpga: sockit: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS

[Marek Vasut]

On Tuesday, December 22, 2015 at 08:32:29 AM, Chin Liang See wrote:
> Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS for UBI
> and UBIFS support on serial NOR flash
> 
> Signed-off-by: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 
> ---
>  configs/socfpga_sockit_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/socfpga_sockit_defconfig
> b/configs/socfpga_sockit_defconfig index b4f41a9..dc32fe8 100644
> --- a/configs/socfpga_sockit_defconfig
> +++ b/configs/socfpga_sockit_defconfig
> @@ -25,3 +25,4 @@ CONFIG_DESIGNWARE_SPI=y
>  CONFIG_DM_MMC=y
>  CONFIG_USB=y
>  CONFIG_DM_USB=y
> +CONFIG_SPI_FLASH_USE_4K_SECTORS=n

Chin, would it be difficult to build your patchset before you submit it?
This one builds with an obvious warning :'-(

There's buildman for doing such bulk builds, let me know if you need help
setting it up.

I will drop this patch and fix the remaining three during application, since
I want to get this set out of the door, but please do some better testing
next time.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/1] common: nvedit: use snprintf instead of sprintf

[Tom Rini]

On Tue, Dec 22, 2015 at 07:53:12AM -0200, Fabio Estevam wrote:
> Hi Peng,
> 
> On Tue, Dec 22, 2015 at 7:14 AM, Peng Fan  wrote:
> > From: Peng Fan 
> >
> > Use snprintf to replace sprintf.
> 
> You need to improve your commit log by saying why you are doing this change.


Yes, please do so.  And if you're using Coverity internally you can
still do a Reported-by: Coverity.

-- 
Tom


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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Marek Vasut]

On Wednesday, December 23, 2015 at 01:24:00 AM, Chin Liang See wrote:
> On Tue, 2015-12-22 at 21:10 +0100, Marek Vasut wrote:
> > On Tuesday, December 22, 2015 at 05:00:42 PM, Chin Liang See wrote:
> > > On Tue, 2015-12-22 at 16:53 +0100, Marek Vasut wrote:
> > > > On Tuesday, December 22, 2015 at 04:49:54 PM, Chin Liang See
> > > > 
> > > > wrote:
> > > > > On Fri, 2015-12-18 at 14:10 +0100, Marek Vasut wrote:
> > > > > > On Friday, December 18, 2015 at 10:39:12 AM, Chin Liang See
> > > > > 
> > > > > > wrote:
> > > > > [..]
> > > > > 
> > > > > > > > I will send that patch out shortly, but I think there is
> > > > > > > > something
> > > > > > > > else
> > > > > > > > going on. I am starting to suspect something with the L3
> > > > > > > > interconnect.
> > > > > > > > Maybe some R/W reordering or something like that in
> > > > > > > > NIC301 .
> > > > > > > > 
> > > > > > > > Are you able to replicate my USB issue with mainline on
> > > > > > > > socfpga ?
> > > > > > > > What
> > > > > > > > happens if you run usb reset with a USB stick plugged in?
> > > > > > > > What
> > > > > > > > compiler
> > > > > > > > version do you use ?
> > > > > > > 
> > > > > > > I tried that few weeks back and it works for me. FYI, I am
> > > > > > > using
> > > > > > > the
> > > > > > > mentor toolchain "arm-altera-eabi" that come with SOCEDS.
> > > > > > > Maybe
> > > > > > > I
> > > > > > > can
> > > > > > > try again with your toolchain.
> > > > > > 
> > > > > > I am using the unreleased ELDK 5.8 (gcc 4.9.2) and debian gcc
> > > > > > 5.2.
> > > > > > Which gcc version is in the mentor toolchain?
> > > > > 
> > > > > Mine is Sourcery CodeBench Lite 2015.05-11 (gcc 4.9.2 also)
> > > > > 
> > > > > > Can you try it again with u-boot/master ? I'd be interested
> > > > > > in
> > > > > > your
> > > > > > results.
> > > > > > Can you share the entire output of the U-Boot and run
> > > > > > 'dcache'
> > > > > > command before
> > > > > > doing 'usb reset' ? I am seeing this issue with Sandisk
> > > > > > Cruzer
> > > > > > USB
> > > > > > 2.0 sticks
> > > > > > now too.
> > > > > 
> > > > > I can do that but git clone will take some time
> > > > 
> > > > You can use git fetch in your current repo.
> > > > 
> > > > I started wondering how you're testing the CV SoCDK, since I
> > > > discovered just
> > > > this morning that it doesn't even boot (I already sent patches to
> > > > fix
> > > > that).
> > > 
> > > I presume you are referring to SPL? FYI, I am still using the SPL
> > > from
> > > SOCEDS while using latest U-Boot from mainstream. That's why I
> > > didn't
> > > the issue noticed by Shengjiang and you.
> > 
> > Well, at least you're honest ... but *sigh*, it'd be nice if you
> > tested
> > mainline only, really.
> 
> Yah, after all the build error issue, I believe I would need to make
> the switch. Let me take a look so I can check the SPL health. I will
> fetch and try it out.

Please check USB host, I suspect it is broken. I don't have the cable
handy now, so I cannot check.

> > > But will make the switch soon once done with few in progress
> > > patches
> > > for U-Boot.
> > 
> > I will collect the remaining patches today and see how socdk fares.
> 
> Let me know if you notice any failure while I will do the test my side
> later.

Looks like with u-boot-socfpga/master, all is good.
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 02:25:29 AM, 圣江 吴 wrote:
> On Dec 22, 2015, at 05:22 PM, 圣江 吴  wrote:
> 
> 
> 
> On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> 
> On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> 
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> > 
> > Signed-off-by: shengjiangwu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> 
> Applied, thanks.
> 
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
> 
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
> 
> Pushed. Please let me know how SoCDK works for you now and if there are
> still some problems.
> 
> 
> Best regards,
> Marek Vasut
> 
> 
> Hi Marek,
> 
> Thank you for your help, I tested the master branch, emac1 and QSPI
> works. Below is log.
> 
> Best Regards,
> ShengjiangWu
> 
> => reset
> resetting ...
> 
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> 
> 
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
> 
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0@ff704000: 0
> *** Warning - bad CRC, using default environment
> 
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> Error: ethernet@ff702000 address not set.
> No ethernet found.
> Hit any key to stop autoboot: 0
> => env default -a
> ## Resetting to default environment
> => setenv netmask 255.255.254.0
> => setenv gatewayip 128.224.98.1
> => setenv ipaddr 128.224.98.85
> => setenv serverip 128.224.99.137
> => setenv ethaddr 00:04:9f:13:57:b4
> => saveenv
> Saving Environment to MMC...
> Writing to MMC(0)... done
> => reset
> resetting ...
> 
> U-Boot SPL 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> 
> 
> U-Boot 2016.01-rc2-09121-gc339ea5 (Dec 23 2015 - 09:13:52 +0800)
> 
> CPU: Altera SoCFPGA Platform
> FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT: SD/MMC External Transceiver (1.8V)
> Watchdog enabled
> I2C: ready
> DRAM: 1 GiB
> MMC: dwmmc0@ff704000: 0
> In: serial
> Out: serial
> Err: serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net: eth0: ethernet@ff702000
> Hit any key to stop autoboot: 0
> => tftp 0x800 /tftpboot/altera/uVxWorks
> Speed: 100, full duplex
> Using ethernet@ff702000 device
> TFTP from server 128.224.99.137; our IP address is 128.224.98.85
> Filename '/tftpboot/altera/uVxWorks'.
> Load address: 0x800
> Loading: #
> #
> #
> #
> #
> #
> 
> 3.3 MiB/s
> done
> Bytes transferred = 6418496 (61f040 hex)
> => sf probe
> SF: Detected N25Q1024 with page size 256 Bytes, erase size 64 KiB, total
> 128 MiB => sf read 0x700 0 0x6
> device 0 offset 0x0, size 0x6
> SF: 393216 bytes @ 0x0 Read: OK
> => md 0x700
> 0700: ea1a e59ff014 e59ff014 e59ff014 
> 0710: e59ff014 e59ff014 e59ff014 e59ff014 
> 0720: 0020 0024 0028 002c ...$...(...,...
> 0730: 0030 0100 0038 12345678 0...8...xV4.
> 0740: 31305341 2e16 0139 ea07 AS01..9.
> 0750: 0140 b854 b854 b900 @...T...T...
> 0760: b854 0badc0de 0badc0de 0badc0de T...
> 0770: eb40 e10f e3c0001f e38000d3 @...
> 0780: e129f000 ee110f10 e3c00a02 ee010f10 ..).
> 0790: e59f00a8 ee0c0f10 eb08 eb15 
> 07a0: eb000690 ee070f15 ee070f9a ee070f95 
> 07b0: e59f0088 ee0c0f10 e12fff1e e12fff1e ../.../.
> 07c0: e3a0 ee080f17 ee070f15 ee070fd5 
> 07d0: ee070f9a 

Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
> On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> > On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:

[..]

> > > 
> > > Hi Marek,
> > > 
> > > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > > then usb
> > > works,
> > > 
> > > => usb start
> > > starting USB...
> > > USB0: Core Release: 2.93a
> > > scanning bus 0 for devices... 2 USB Device(s) found
> > > => usb tree
> > > USB device tree:
> > > 1 Hub (480 Mb/s, 0mA)
> > > 
> > > > U-Boot Root Hub
> > > 
> > > +-2 Mass Storage (480 Mb/s, 98mA)
> > > Generic USB Storage 0272
> > 
> > Cool, thanks! Patch please ;-)
> 
> Nice, guess Altera email is very slow
> 

Yup, it work for me too with the pinmux change and dcache on.

U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29)
drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
drivers/ddr/altera/sequencer.c: Calibration complete
Trying to boot from MMC
spl: mmc boot mode: raw
 
 
U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
 
CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC External Transceiver (1.8V)
   Watchdog enabled
I2C:   ready
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
*** Warning - bad CRC, using default environment
 
In:serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Error: ethernet@ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot:  0
=> dcache
Data (writethrough) Cache is ON
=> usb reset
resetting USB...
USB0:   Core Release: 2.93a
scanning bus 0 for devices... 2 USB Device(s) found
=> usb info
1: Hub,  USB Revision 1.10
-  U-Boot Root Hub
- Class: Hub
- PacketSize: 8  Configurations: 1
- Vendor: 0x  Product 0x Version 0.0
   Configuration: 1
   - Interfaces: 1 Self Powered 0mA
 Interface: 0
 - Alternate Setting 0, Endpoints: 1
 - Class Hub
 - Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
 
2: Mass Storage,  USB Revision 2.0
-  USB DISK 2.0 0781076602A6
- Class: (from Interface) Mass Storage
- PacketSize: 64  Configurations: 1
- Vendor: 0x13fe  Product 0x1e00 Version 1.16
   Configuration: 1
   - Interfaces: 1 Bus Powered 200mA
 Interface: 0
 - Alternate Setting 0, Endpoints: 2
 - Class Mass Storage, Transp. SCSI, Bulk only
 - Endpoint 1 In Bulk MaxPacket 512
 - Endpoint 2 Out Bulk MaxPacket 512

Thanks
Chin Liang

> Thanks
> Chin Liang
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Re: [U-Boot] [PATCH v3 04/17] arm: socfpga: sockit: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS

[Chin Liang See]

On Wed, 2015-12-23 at 02:47 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 02:36:13 AM, Chin Liang See wrote:
> > On Wed, 2015-12-23 at 01:47 +0100, Marek Vasut wrote:
> > > On Wednesday, December 23, 2015 at 01:21:31 AM, Chin Liang See
> > > wrote:
> > > > On Tue, 2015-12-22 at 21:28 +0100, Marek Vasut wrote:
> > > > > On Tuesday, December 22, 2015 at 08:32:29 AM, Chin Liang See
> > 
> > > > > wrote:
> > 

[..]

> > 
> > > > > I will drop this patch and fix the remaining three during
> > > > > application, since
> > > > > I want to get this set out of the door, but please do some
> > > > > better
> > > > > testing
> > > > > next time.
> > > > 
> > > > Do share you build error so I can simulate the build error.
> > > 
> > > CONFIG_SPI_FLASH_USE_4K_SECTORS was used twice in the config file
> > > sockit
> > > config file (configs/socfpga_sockit) .
> > 
> > Oh I believe its commented out.
> > 
> > bash-3.2$ git grep --color CONFIG_SPI_FLASH_USE_4K_SECTORS
> > configs/socfpga_arria5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> > configs/socfpga_cyclone5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=
> > n
> > configs/socfpga_sockit_defconfig:# CONFIG_SPI_FLASH_USE_4K_SECTORS
> > is
> > not set
> > configs/socfpga_sockit_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> 
> But it's twice in there. Also, =n is not valid construct, to disable
> config option you should comment it out the way it's done above.

Oh unaware the =n is invalid.
Thanks for the fix.

Chin Liang

> 
> > configs/socfpga_sr1500_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> > drivers/mtd/spi/sf_internal.h:#ifdef
> > CONFIG_SPI_FLASH_USE_4K_SECTORS
> > 
> > Thanks
> > Chin Liang
> 
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH v3 04/17] arm: socfpga: sockit: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS

[Chin Liang See]

On Tue, 2015-12-22 at 21:28 +0100, Marek Vasut wrote:
> On Tuesday, December 22, 2015 at 08:32:29 AM, Chin Liang See wrote:
> > Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS for UBI
> > and UBIFS support on serial NOR flash
> > 
> > Signed-off-by: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> > ---
> >  configs/socfpga_sockit_defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/configs/socfpga_sockit_defconfig
> > b/configs/socfpga_sockit_defconfig index b4f41a9..dc32fe8 100644
> > --- a/configs/socfpga_sockit_defconfig
> > +++ b/configs/socfpga_sockit_defconfig
> > @@ -25,3 +25,4 @@ CONFIG_DESIGNWARE_SPI=y
> >  CONFIG_DM_MMC=y
> >  CONFIG_USB=y
> >  CONFIG_DM_USB=y
> > +CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> 
> Chin, would it be difficult to build your patchset before you submit
> it?
> This one builds with an obvious warning :'-(
> 

That really strange as I built cyclone5, arria5, sockit, sr1500 and
even mcvevk in case it break (as mcvevk dun have qspi). Wonder what is
the build error you got?

FYI, here is my build info which indicate success build
bash-3.2$ export CROSS_COMPILE=arm-altera-eabi-; make mrproper; make
socfpga_sockit_defconfig; make
[..]
  CFG spl/u-boot-spl.cfg
  FDTGREP spl/u-boot-spl.dtb
  CAT spl/u-boot-spl-dtb.bin
  MKIMAGE spl/u-boot-spl-dtb.sfp
make[1]: warning:  Clock skew detected.  Your build may be incomplete.
  MKIMAGE u-boot.img
  COPYu-boot.dtb
  CAT u-boot-dtb.bin
  MKIMAGE u-boot-dtb.img
bash-3.2$
bash-3.2$ git log -20 --pretty=oneline
32d38cdf1211544f26cbcf81bdf90c2358fee9e6 arm: socfpga: sr1500: Update
qspiboot to use UBIFS
aa66a23109f2c1f0038dbd495fdbfc7e768935d6 arm: socfpga: sockit: Update
qspiboot to use UBIFS
8d1d779e348f5b81614e4b4b58966bc828b769c3 arm: socfpga: arria5_socdk:
Update qspiboot to use UBIFS
72bd3790884fd95d496ef39106fd6dbcbefbc364 arm: socfpga: cyclone5_socdk:
Update qspiboot to use UBIFS
0695327d3895a8ea018b69002c57a0cbdd92c801 arm: socfpga: sr1500: Enable
qspiload console command
3b8137edb764042c2c66f74f8778fd4ca615ee75 arm: socfpga: sockit: Enable
qspiload console command
d855cecf6441f1c0f8cb54fb824e5192f857cdc2 arm: socfpga: arria5_socdk:
Enable qspiload console command
d32087cc5cdb44b7279d8d4cc2318fcf82b0390e arm: socfpga: cyclone5_socdk:
Enable qspiload console command
b576fdeb24d045a5efc9eefa745dfeae20ef7663 arm: socfpga: sr1500: Enable
ubiload console command
f693537d6fa42f19f537557b0e6f2cea00449958 arm: socfpga: sockit: Enable
ubiload console command
3acc42460689bf92a06d85c9cfa6901ffdf6bc15 arm: socfpga: arria5_socdk:
Enable ubiload console command
b275951fa08e3321767a12ba2c79b841e05e27c9 arm: socfpga: cyclone5_socdk:
Enable ubiload console command
0e9ba6d2aa50555a5d358de4aa129e6899f60bbc arm: socfpga: sr1500: Undefine
CONFIG_SPI_FLASH_USE_4K_SECTORS
577d38e36d694e15d9363e6f351aae7b1de59854 arm: socfpga: sockit: Undefine
CONFIG_SPI_FLASH_USE_4K_SECTORS
fea05b3eae5928b0df20e6ae1a3252dbae9215ab arm: socfpga: arria5: Undefine
CONFIG_SPI_FLASH_USE_4K_SECTORS
bc882c4539925c1cb8294638d2d2e7e28e91941e arm: socfpga: cyclone5:
Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS
9b15c22ac90ffa12bc1d015d7aef703e07c67fc4 arm: socfpga: Enable ubi and
ubifs support
55639073aaf33306df7fe24d4cef22d8eb53e2d8 arm: socfpga: Enabling MTD
default partitions
58398c6bc59ee23a05c83bbff168fa6a7b337e14 arm: socfpga: socrates:
Consolidate SDMMC environment
780fa75bf6aa79cf78a76d17a03c91d8a5928f5e arm: socfpga: sockit:
Consolidate SDMMC environment
bash-3.2$
bash-3.2$ arm-altera-eabi-gcc --version
arm-altera-eabi-gcc (Sourcery CodeBench Lite 2015.11-45) 5.2.0
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is
NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE.

> There's buildman for doing such bulk builds, let me know if you need
> help
> setting it up.
> 

That's sound good to me instead i invoke it manually every time. Let me
take a look. A quick link would be much appreciated.

> I will drop this patch and fix the remaining three during
> application, since
> I want to get this set out of the door, but please do some better
> testing
> next time.

Do share you build error so I can simulate the build error.

Thanks
Chin Liang

> 
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH 6/6] arm: socfpga: Add support for Denali NAND controller

[Chin Liang See]

On Tue, 2015-12-22 at 21:23 +0100, Marek Vasut wrote:
> On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote:
> > On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> > > Add common configuration bits for the Denali NAND controller and
> > > also
> > > support for using it as a boot device in SPL.
> > > 
> > > Signed-off-by: Marek Vasut 
> > > Cc: Dinh Nguyen 
> > > Cc: Chin Liang See 
> > > ---
> > > 
> > >  include/configs/socfpga_common.h | 23 +++
> > >  1 file changed, 23 insertions(+)
> > > 
> > > diff --git a/include/configs/socfpga_common.h
> > > b/include/configs/socfpga_common.h
> > > index 4124d8b..8886ccf 100644
> > > --- a/include/configs/socfpga_common.h
> > > +++ b/include/configs/socfpga_common.h
> > > @@ -162,6 +162,19 @@
> > > 
> > >  #endif
> > >  
> > >  /*
> > > 
> > > + * NAND Support
> > > + */
> > > +#ifdef CONFIG_NAND_DENALI
> > > +#define CONFIG_SYS_MAX_NAND_DEVICE   1
> > > +#define CONFIG_SYS_NAND_MAX_CHIPS1
> > > +#define CONFIG_SYS_NAND_ONFI_DETECTION
> > > +#define CONFIG_NAND_DENALI_ECC_SIZE  512
> > > +#define CONFIG_SYS_NAND_REGS_BASE0xffb8
> > > +#define CONFIG_SYS_NAND_DATA_BASE0xff90
> > 
> > You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS
> 
> Fixed and applied, thanks.

Nice

Thanks
Chin Liang

> 
> I believe we should be getting close to a good stable setup, so it's
> about
> time to start testing once I issue this last heftier PR.
> 
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH v3 04/17] arm: socfpga: sockit: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS

[Marek Vasut]

On Wednesday, December 23, 2015 at 01:21:31 AM, Chin Liang See wrote:
> On Tue, 2015-12-22 at 21:28 +0100, Marek Vasut wrote:
> > On Tuesday, December 22, 2015 at 08:32:29 AM, Chin Liang See wrote:
> > > Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS for UBI
> > > and UBIFS support on serial NOR flash
> > > 
> > > Signed-off-by: Chin Liang See 
> > > Cc: Dinh Nguyen 
> > > Cc: Dinh Nguyen 
> > > Cc: Pavel Machek 
> > > Cc: Marek Vasut 
> > > Cc: Stefan Roese 
> > > ---
> > > 
> > >  configs/socfpga_sockit_defconfig | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/configs/socfpga_sockit_defconfig
> > > b/configs/socfpga_sockit_defconfig index b4f41a9..dc32fe8 100644
> > > --- a/configs/socfpga_sockit_defconfig
> > > +++ b/configs/socfpga_sockit_defconfig
> > > @@ -25,3 +25,4 @@ CONFIG_DESIGNWARE_SPI=y
> > > 
> > >  CONFIG_DM_MMC=y
> > >  CONFIG_USB=y
> > >  CONFIG_DM_USB=y
> > > 
> > > +CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> > 
> > Chin, would it be difficult to build your patchset before you submit
> > it?
> > This one builds with an obvious warning :'-(
> 
> That really strange as I built cyclone5, arria5, sockit, sr1500 and
> even mcvevk in case it break (as mcvevk dun have qspi). Wonder what is
> the build error you got?
> 
> FYI, here is my build info which indicate success build
> bash-3.2$ export CROSS_COMPILE=arm-altera-eabi-; make mrproper; make
> socfpga_sockit_defconfig; make

I fixed it in u-boot-socfpga/master, so it will compile fine, but you
should see a warning with the original patch, see at the end of this mail.

> [..]
>   CFG spl/u-boot-spl.cfg
>   FDTGREP spl/u-boot-spl.dtb
>   CAT spl/u-boot-spl-dtb.bin
>   MKIMAGE spl/u-boot-spl-dtb.sfp
> make[1]: warning:  Clock skew detected.  Your build may be incomplete.

This is a bit weird, isn't it ;-)

>   MKIMAGE u-boot.img
>   COPYu-boot.dtb
>   CAT u-boot-dtb.bin
>   MKIMAGE u-boot-dtb.img

[...]

> > There's buildman for doing such bulk builds, let me know if you need
> > help
> > setting it up.
> 
> That's sound good to me instead i invoke it manually every time. Let me
> take a look. A quick link would be much appreciated.

Thomas did a good concise writeup on setting up buildman:

http://www.mail-archive.com/u-boot@lists.denx.de/msg191914.html

> > I will drop this patch and fix the remaining three during
> > application, since
> > I want to get this set out of the door, but please do some better
> > testing
> > next time.
> 
> Do share you build error so I can simulate the build error.

CONFIG_SPI_FLASH_USE_4K_SECTORS was used twice in the config file sockit
config file (configs/socfpga_sockit) .
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Chin Liang See]

On Wed, 2015-12-23 at 01:48 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 01:24:00 AM, Chin Liang See wrote:
> > On Tue, 2015-12-22 at 21:10 +0100, Marek Vasut wrote:
> > > On Tuesday, December 22, 2015 at 05:00:42 PM, Chin Liang See
> > > wrote:
> > > > On Tue, 2015-12-22 at 16:53 +0100, Marek Vasut wrote:

[..]

> > > > 
> > > > I presume you are referring to SPL? FYI, I am still using the
> > > > SPL
> > > > from
> > > > SOCEDS while using latest U-Boot from mainstream. That's why I
> > > > didn't
> > > > the issue noticed by Shengjiang and you.
> > > 
> > > Well, at least you're honest ... but *sigh*, it'd be nice if you
> > > tested
> > > mainline only, really.
> > 
> > Yah, after all the build error issue, I believe I would need to
> > make
> > the switch. Let me take a look so I can check the SPL health. I
> > will
> > fetch and try it out.
> 
> Please check USB host, I suspect it is broken. I don't have the cable
> handy now, so I cannot check.
> 

Sure, let me try it out now.

> > > > But will make the switch soon once done with few in progress
> > > > patches
> > > > for U-Boot.
> > > 
> > > I will collect the remaining patches today and see how socdk
> > > fares.
> > 
> > Let me know if you notice any failure while I will do the test my
> > side
> > later.
> 
> Looks like with u-boot-socfpga/master, all is good.

Nice

Thanks
Chin Liang
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Re: [U-Boot] [PATCH v3 04/17] arm: socfpga: sockit: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS

[Marek Vasut]

On Wednesday, December 23, 2015 at 02:36:13 AM, Chin Liang See wrote:
> On Wed, 2015-12-23 at 01:47 +0100, Marek Vasut wrote:
> > On Wednesday, December 23, 2015 at 01:21:31 AM, Chin Liang See wrote:
> > > On Tue, 2015-12-22 at 21:28 +0100, Marek Vasut wrote:
> > > > On Tuesday, December 22, 2015 at 08:32:29 AM, Chin Liang See
> 
> > > > wrote:
> [..]
> 
> > >   CFG spl/u-boot-spl.cfg
> > >   FDTGREP spl/u-boot-spl.dtb
> > >   CAT spl/u-boot-spl-dtb.bin
> > >   MKIMAGE spl/u-boot-spl-dtb.sfp
> > > 
> > > make[1]: warning:  Clock skew detected.  Your build may be
> > > incomplete.
> > 
> > This is a bit weird, isn't it ;-)
> 
> Yah, this is something need be hammered
> 
> > >   MKIMAGE u-boot.img
> > >   COPYu-boot.dtb
> > >   CAT u-boot-dtb.bin
> > >   MKIMAGE u-boot-dtb.img
> > 
> > [...]
> > 
> > > > There's buildman for doing such bulk builds, let me know if you
> > > > need
> > > > help
> > > > setting it up.
> > > 
> > > That's sound good to me instead i invoke it manually every time.
> > > Let me
> > > take a look. A quick link would be much appreciated.
> > 
> > Thomas did a good concise writeup on setting up buildman:
> > 
> > http://www.mail-archive.com/u-boot@lists.denx.de/msg191914.html
> 
> Yah, I saw the conversation. Cool, let me set it up.
> 
> > > > I will drop this patch and fix the remaining three during
> > > > application, since
> > > > I want to get this set out of the door, but please do some better
> > > > testing
> > > > next time.
> > > 
> > > Do share you build error so I can simulate the build error.
> > 
> > CONFIG_SPI_FLASH_USE_4K_SECTORS was used twice in the config file
> > sockit
> > config file (configs/socfpga_sockit) .
> 
> Oh I believe its commented out.
> 
> bash-3.2$ git grep --color CONFIG_SPI_FLASH_USE_4K_SECTORS
> configs/socfpga_arria5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> configs/socfpga_cyclone5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> configs/socfpga_sockit_defconfig:# CONFIG_SPI_FLASH_USE_4K_SECTORS is
> not set
> configs/socfpga_sockit_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n

But it's twice in there. Also, =n is not valid construct, to disable
config option you should comment it out the way it's done above.

> configs/socfpga_sr1500_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> drivers/mtd/spi/sf_internal.h:#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
> 
> Thanks
> Chin Liang

Best regards,
Marek Vasut
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Re: [U-Boot] pull request: u-boot-uniphier/master

[Masahiro Yamada]

Hi Tom,

2015-12-23 0:59 GMT+09:00 Tom Rini :
> On Wed, Dec 23, 2015 at 12:22:22AM +0900, Masahiro Yamada wrote:
>
>> Hi Tom,
>>
>> Here are various cleanups and preparation for new SoCs support.
>> Please pull!
>>
>>
>> The following changes since commit f84c2b665b87fc6713a756d0fddf5c45e02255e5:
>>
>>   Prepare v2016.01-rc3 (2015-12-21 21:07:04 -0500)
>>
>> are available in the git repository at:
>>
>>   git://git.denx.de/u-boot-uniphier.git master
>>
>> for you to fetch changes up to 8182b41994f0b1824c31652d64171ffa596517fc:
>>
>>   ARM: dts: uniphier: add SD/MMC pinmux nodes (2015-12-23 00:09:05 +0900)
>
> This looks very self contained.  But it's also not bug fixes.  Are you
> sure you want this in now?  Thanks!


Right, not bug fixes.

I know the community is trying to be more strict to the MW
and now it is -rc3, but my local branch is getting huge
and I wanted to flush it at some point.

So, I want this in now, but I leave this decision to you.
If you are not inclined to do so, I can wait by the next MW.



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH 0/3] This series adds support for fastboot related to USB.

[Marek Vasut]

On Tuesday, December 22, 2015 at 09:25:49 AM, Frank Wang wrote:
>  [PATCH 1/3] Modified the check condition for max packet size of ep_in in
> high speed
> 
>  [PATCH 2/3] Fixed the error that the last packet transmission could not be
> terminated
> 
>  [PATCH 3/3] Add usb phy control to support fastboot for rk3036
> 
>  Tested on RK3036 SDK board, it works Okay.
> 
>  board/evb_rk3036/evb_rk3036/evb_rk3036.c   |   30 +
>  drivers/usb/gadget/Makefile|1 +
>  drivers/usb/gadget/dwc2_udc_otg.c  |4 +--
>  drivers/usb/gadget/dwc2_udc_otg_regs.h |5 +++
>  drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |2 +-
>  drivers/usb/gadget/rk_otg_phy.c|   48
>  include/configs/rk3036_common.h| 
>  20 
>  7 files changed, 107 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/usb/gadget/rk_otg_phy.c

Series looks sensible to me, but I'd like to have Lukasz take a look at it
and review it thoroughly too.

Thanks!

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/6] arm: socfpga: cyclone5-socdk: Enabling mtd partitioning layout

[Chin Liang See]

On Tue, 2015-12-22 at 21:10 +0100, Marek Vasut wrote:
> On Tuesday, December 22, 2015 at 05:00:42 PM, Chin Liang See wrote:
> > On Tue, 2015-12-22 at 16:53 +0100, Marek Vasut wrote:
> > > On Tuesday, December 22, 2015 at 04:49:54 PM, Chin Liang See
> > > wrote:
> > > > On Fri, 2015-12-18 at 14:10 +0100, Marek Vasut wrote:
> > > > > On Friday, December 18, 2015 at 10:39:12 AM, Chin Liang See
> > > > 
> > > > > wrote:
> > > > [..]
> > > > 
> > > > > > > I will send that patch out shortly, but I think there is
> > > > > > > something
> > > > > > > else
> > > > > > > going on. I am starting to suspect something with the L3
> > > > > > > interconnect.
> > > > > > > Maybe some R/W reordering or something like that in
> > > > > > > NIC301 .
> > > > > > > 
> > > > > > > Are you able to replicate my USB issue with mainline on
> > > > > > > socfpga ?
> > > > > > > What
> > > > > > > happens if you run usb reset with a USB stick plugged in?
> > > > > > > What
> > > > > > > compiler
> > > > > > > version do you use ?
> > > > > > 
> > > > > > I tried that few weeks back and it works for me. FYI, I am
> > > > > > using
> > > > > > the
> > > > > > mentor toolchain "arm-altera-eabi" that come with SOCEDS.
> > > > > > Maybe
> > > > > > I
> > > > > > can
> > > > > > try again with your toolchain.
> > > > > 
> > > > > I am using the unreleased ELDK 5.8 (gcc 4.9.2) and debian gcc
> > > > > 5.2.
> > > > > Which gcc version is in the mentor toolchain?
> > > > 
> > > > Mine is Sourcery CodeBench Lite 2015.05-11 (gcc 4.9.2 also)
> > > > 
> > > > > Can you try it again with u-boot/master ? I'd be interested
> > > > > in
> > > > > your
> > > > > results.
> > > > > Can you share the entire output of the U-Boot and run
> > > > > 'dcache'
> > > > > command before
> > > > > doing 'usb reset' ? I am seeing this issue with Sandisk
> > > > > Cruzer
> > > > > USB
> > > > > 2.0 sticks
> > > > > now too.
> > > > 
> > > > I can do that but git clone will take some time
> > > 
> > > You can use git fetch in your current repo.
> > > 
> > > I started wondering how you're testing the CV SoCDK, since I
> > > discovered just
> > > this morning that it doesn't even boot (I already sent patches to
> > > fix
> > > that).
> > 
> > I presume you are referring to SPL? FYI, I am still using the SPL
> > from
> > SOCEDS while using latest U-Boot from mainstream. That's why I
> > didn't
> > the issue noticed by Shengjiang and you.
> 
> Well, at least you're honest ... but *sigh*, it'd be nice if you
> tested
> mainline only, really.

Yah, after all the build error issue, I believe I would need to make
the switch. Let me take a look so I can check the SPL health. I will
fetch and try it out.

> 
> > But will make the switch soon once done with few in progress
> > patches
> > for U-Boot.
> 
> I will collect the remaining patches today and see how socdk fares.

Let me know if you notice any failure while I will do the test my side
later.

Thanks
Chin Liang

> 
> Best regards,
> Marek Vasut
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Re: [U-Boot] [PATCH v2 7/8] mvebu: Support Synology DS414

[Phil Sutter]

Hi,

On Tue, Dec 22, 2015 at 10:05:03AM +0100, Stefan Roese wrote:
> I've consolidated a bit of the Armada XP / 38x defines and
> Kconfig options just very recently. Please take a look at
> these two patches from yesterday:
> 
> http://patchwork.ozlabs.org/patch/559579/
> http://patchwork.ozlabs.org/patch/559580/
> 
> It would be great if you could base your DS414 support on
> top of these as well (sorry, I missed adding you on CC for these
> patches). It should fairly easy and make things clearer (e.g.
> CONFIG_ARMADA_XP only defined on AXP devices).

I see.

> I could also add a new git branch available, with the latest
> versions of all the mvebu related patches applied. Just let
> me know if this would help.

No problem, I just fetched the relevant patches from the list and
applied them locally.

[...]

> > SATA Support
> > 
> >
> > There is a Marvell 88SX7042 controller attached to PCIe which is
> > supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv.
> > I'm not sure if extending the latter to support PCI devices is worth the
> > effort at all.
> 
> Yes, this is probably not worth the effort.

What bothers me is that Synology's patched U-Boot supports it, so I
consider it a regression for users wanting to switch to mainline. And
since there is sata_mv in U-Boot now and Linux's sata_mv simply supports
both the platform device and the various PCI devices, one might think it
should be straightforward to add support to it. But Linux's sata_mv with
it's 4.5k LoC is quite a thing, too.

[...]

> > EHCI Support
> > 
> >
> > This seems functional after issuing 'usb start'. At least it detects USB
> > storage devices, and IIRC reading from them was OK. OTOH Linux fails to
> > register the controller if 'usb start' wasn't given before in U-Boot.
> >
> > According to Synology sources, this board seems to support USB device
> > (gadget?) mode. Though I didn't play around with it.
> 
> This is something that should be fixed. Linux should be able to
> use all devices without any bootloader interference. So it might
> be, that some USB related configuration is missing here. Perhaps
> in the USB PHY (setup setup_usb_phys in cpu.c).
> 
> Does this work in Linux when the original U-Boot is used?

I will check. Also printing the relevant registers in Linux and
comparing the values in working and broken condition might help.

> > PCIe Support
> > 
> >
> > This is fine, but trying to gate the clocks of unused lanes will hang
> > PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI.
> 
> Right. Patches welcome. ;)

I actually started, thought it can't be that hard. So far I'm stuck at a
point where enumeration gets just 0xfbfb for both vendor and product
IDs. Looks like a follow-up project to me. :)

[...]

> > diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h 
> > b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
> > index f00f327..3dca6a1 100644
> > --- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
> > +++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
> > @@ -43,8 +43,9 @@
> >   #define RD_78460_SERVER_REV2_ID   (DB_78X60_PCAC_REV2_ID + 1)
> >   #define DB_784MP_GP_ID(RD_78460_SERVER_REV2_ID + 1)
> >   #define RD_78460_CUSTOMER_ID  (DB_784MP_GP_ID + 1)
> > -#define MV_MAX_BOARD_ID(RD_78460_CUSTOMER_ID + 1)
> > -#define INVALID_BAORD_ID   0x
> > +#define SYNOLOGY_DS414_ID  (RD_78460_CUSTOMER_ID + 1)
> > +#define MV_MAX_BOARD_ID(SYNOLOGY_DS414_ID + 1)
> > +#define INVALID_BOARD_ID   0x
> 
> Do you really need these changes here?

Sadly, yes. See high_speed_env_lib.c for details: There it is needed by
serdes_phy_config() to get the right satr11 value via board_id_get().
Maybe this should be refactored to always use board_sat_r_get() and the
latter return a static value from a macro which board configs may define
instead of reading from i2c.

[...]

> > +/* DDR3 static MC configuration */
> > +
> > +/* 1G_v1 (4x2Gbits) adapted by DS414 */
> > +MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
> > +   {0x1400, 0x73014A28},   /*DDR SDRAM Configuration Register */
> > +   {0x1404, 0x3800},   /*Dunit Control Low Register */
> > +   {0x1408, 0x44148887},   /*DDR SDRAM Timing (Low) Register */
> > +   /* {0x140C, 0x38000C6}, */  /*DDR SDRAM Timing (High) Register */
> > +   {0x140C, 0x3AD83FEA},   /*DDR SDRAM Timing (High) Register */
> 
> Why do you have commented-out values here? Its generally not allowed
> to add "dead code". So please either add it in some comment, so that
> it can be identified as a important comment. Or remove it completely.

Took that over from Synology's sources (mainly for the sake of
completeness). But you're right, without explanation (which I couldn't
find, either) it's pretty much useless.

[...]

> > +   /* gate unused clocks */
> > +   /* 

Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> 
> On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> 
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> > 
> > Signed-off-by: shengjiangwu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> 
> Applied, thanks.
> 
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
> 
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master
> 
> Pushed. Please let me know how SoCDK works for you now and if there are
> still some problems.
> 
> 
> Best regards,
> Marek Vasut
> 
> 
> Hi Marek,
> 
> Thank you for your help, I tested the master branch, emac1 and QSPI
> works. Below is log.

Good! so we're happy ? Can you give USB a spin too? I think it might have
some issues and I don't have the necessary cable here.

[...]

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Wednesday, December 23, 2015 9:25 AM
> > To: 圣江 吴
> > Cc: u-boot@lists.denx.de; cl...@altera.com;
> > dingu...@opensource.altera.com; dinh.li...@gmail.com; pa...@denx.de;
> > s...@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on
> > socdk board
> > 
> > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > > On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> > > 
> > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > > 
> > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > Updated QSPI clock.
> > > > 
> > > > Signed-off-by: shengjiangwu 
> > > > Cc: Chin Liang See 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Pavel Machek 
> > > > Cc: Marek Vasut 
> > > > Cc: Stefan Roese 
> > > 
> > > Applied, thanks.
> > > 
> > > I will push your patches to [1] in a few hours, can you try and see if
> > > the CV SOCDK works fine for you? Thanks
> > > 
> > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > socfpga.git;a=shortlog;h=refs/heads/master
> > > 
> > > Pushed. Please let me know how SoCDK works for you now and if there
> > > are still some problems.
> > > 
> > > 
> > > Best regards,
> > > Marek Vasut
> > > 
> > > 
> > > Hi Marek,
> > > 
> > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > works. Below is log.
> > 
> > Good! so we're happy ? Can you give USB a spin too? I think it might have
> > some issues and I don't have the necessary cable here.
> > 
> > [...]
> > 
> > Best regards,
> > Marek Vasut
> 
> Hi Marek,
> 
> Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> 
> => usb reset
> resetting USB...
> USB0:   Core Release: 2.93a
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> scanning bus 0 for devices... 1 USB Device(s) found
> => usb tree
> USB device tree:
>   1  Hub (480 Mb/s, 0mA)
>   U-Boot Root Hub

Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Wed, 2015-12-23 at 03:07 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:

[..]

> > Hi Marek,
> > 
> > Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> > 
> > => usb reset
> > resetting USB...
> > USB0:   Core Release: 2.93a
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > dwc_otg_core_host_init: Timeout!
> > scanning bus 0 for devices... 1 USB Device(s) found
> > => usb tree
> > USB device tree:
> >   1  Hub (480 Mb/s, 0mA)
> >   U-Boot Root Hub
> 
> Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB
> node
> in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .

I am still setting up the SPL into SD card. In the mean time, I believe
the error come from pinmux. Shengjiang, can you try out below change?

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 06783dc..fb8648b 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -8,20 +8,20 @@
#define __SOCFPGA_PINMUX_CONFIG_H__
 
const u8 sys_mgr_init_table[] = {
-   3, /* EMACIO0 */
-   3, /* EMACIO1 */
-   3, /* EMACIO2 */
-   3, /* EMACIO3 */
-   3, /* EMACIO4 */
-   3, /* EMACIO5 */
-   3, /* EMACIO6 */
-   3, /* EMACIO7 */
-   3, /* EMACIO8 */
-   3, /* EMACIO9 */
-   3, /* EMACIO10 */
-   3, /* EMACIO11 */
-   3, /* EMACIO12 */
-   3, /* EMACIO13 */
+   0, /* EMACIO0 */
+   2, /* EMACIO1 */
+   2, /* EMACIO2 */
+   2, /* EMACIO3 */
+   2, /* EMACIO4 */
+   2, /* EMACIO5 */
+   2, /* EMACIO6 */
+   2, /* EMACIO7 */
+   2, /* EMACIO8 */
+   0, /* EMACIO9 */
+   2, /* EMACIO10 */
+   2, /* EMACIO11 */
+   2, /* EMACIO12 */
+   2, /* EMACIO13 */
0, /* EMACIO14 */
0, /* EMACIO15 */
0, /* EMACIO16 */

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
> > From: Marek Vasut
> > Date: 2015-12-23 10:07
> > To: ShengjiangWu
> > CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
> > Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board
> > 
> > On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu wrote:
> > > > -Original Message-
> > > > From: Marek Vasut [mailto:ma...@denx.de]
> > > > Sent: Wednesday, December 23, 2015 9:25 AM
> > > > To: 圣江 吴
> > > > Cc: u-boot@lists.denx.de; cl...@altera.com;
> > > > dingu...@opensource.altera.com; dinh.li...@gmail.com; pa...@denx.de;
> > > > s...@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work
> > > > on socdk board
> > > > 
> > > > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut  wrote:
> > > > > 
> > > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> > > > > 
> > > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > > > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > > > Updated QSPI clock.
> > > > > > 
> > > > > > Signed-off-by: shengjiangwu 
> > > > > > Cc: Chin Liang See 
> > > > > > Cc: Dinh Nguyen 
> > > > > > Cc: Dinh Nguyen 
> > > > > > Cc: Pavel Machek 
> > > > > > Cc: Marek Vasut 
> > > > > > Cc: Stefan Roese 
> > > > > 
> > > > > Applied, thanks.
> > > > > 
> > > > > I will push your patches to [1] in a few hours, can you try and see
> > > > > if the CV SOCDK works fine for you? Thanks
> > > > > 
> > > > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > > > socfpga.git;a=shortlog;h=refs/heads/master
> > > > > 
> > > > > Pushed. Please let me know how SoCDK works for you now and if there
> > > > > are still some problems.
> > > > > 
> > > > > 
> > > > > Best regards,
> > > > > Marek Vasut
> > > > > 
> > > > > 
> > > > > Hi Marek,
> > > > > 
> > > > > Thank you for your help, I tested the master branch, emac1 and QSPI
> > > > > works. Below is log.
> > > > 
> > > > Good! so we're happy ? Can you give USB a spin too? I think it might
> > > > have some issues and I don't have the necessary cable here.
> > > > 
> > > > [...]
> > > > 
> > > > Best regards,
> > > > Marek Vasut
> > > 
> > > Hi Marek,
> > > 
> > > Yes, emac1 and qspi are working now. I'm afraid USB is not working,
> > > 
> > > => usb reset
> > > resetting USB...
> > > USB0: Core Release: 2.93a
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > dwc_otg_core_host_init: Timeout!
> > > scanning bus 0 for devices... 1 USB Device(s) found
> > > => usb tree
> > > USB device tree:
> > > 1 Hub (480 Mb/s, 0mA)
> > > U-Boot Root Hub
> > 
> > Hm, darn. Can you or Chin check it ? It's either pinmux or wrong USB node
> > in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
> 
> Hi Marek,
> 
> Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2, then usb
> works,
> 
> => usb start
> starting USB...
> USB0: Core Release: 2.93a
> scanning bus 0 for devices... 2 USB Device(s) found
> => usb tree
> USB device tree:
> 1 Hub (480 Mb/s, 0mA)
> 
> | U-Boot Root Hub
> 
> +-2 Mass Storage (480 Mb/s, 98mA)
> Generic USB Storage 0272

Cool, thanks! Patch please ;-)
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:38:25 AM, Chin Liang See wrote:
> On Wed, 2015-12-23 at 10:29 +0800, Chin Liang See wrote:
> > On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> > > On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
> [..]
> 
> > > > Hi Marek,
> > > > 
> > > > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > > > then usb
> > > > works,
> > > > 
> > > > => usb start
> > > > starting USB...
> > > > USB0: Core Release: 2.93a
> > > > scanning bus 0 for devices... 2 USB Device(s) found
> > > > => usb tree
> > > > USB device tree:
> > > > 1 Hub (480 Mb/s, 0mA)
> > > > 
> > > > > U-Boot Root Hub
> > > > 
> > > > +-2 Mass Storage (480 Mb/s, 98mA)
> > > > Generic USB Storage 0272
> > > 
> > > Cool, thanks! Patch please ;-)
> > 
> > Nice, guess Altera email is very slow
> 
> Yup, it work for me too with the pinmux change and dcache on.
> 
> U-Boot SPL 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29)
> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
> drivers/ddr/altera/sequencer.c: CALIBRATION PASSED
> drivers/ddr/altera/sequencer.c: Calibration complete
> Trying to boot from MMC
> spl: mmc boot mode: raw
> 
> 
> U-Boot 2016.01-rc2-09121-gc339ea5-dirty (Dec 23 2015 - 10:21:29 +0800)
> 
> CPU:   Altera SoCFPGA Platform
> FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> BOOT:  SD/MMC External Transceiver (1.8V)
>Watchdog enabled
> I2C:   ready
> DRAM:  1 GiB
> MMC:   dwmmc0@ff704000: 0
> *** Warning - bad CRC, using default environment
> 
> In:serial
> Out:   serial
> Err:   serial
> Model: Altera SOCFPGA Cyclone V SoC Development Kit
> Net:
> Error: ethernet@ff702000 address not set.
> No ethernet found.
> Hit any key to stop autoboot:  0
> => dcache
> Data (writethrough) Cache is ON
> => usb reset
> resetting USB...
> USB0:   Core Release: 2.93a
> scanning bus 0 for devices... 2 USB Device(s) found
> => usb info
> 1: Hub,  USB Revision 1.10
> -  U-Boot Root Hub
> - Class: Hub
> - PacketSize: 8  Configurations: 1
> - Vendor: 0x  Product 0x Version 0.0
>Configuration: 1
>- Interfaces: 1 Self Powered 0mA
>  Interface: 0
>  - Alternate Setting 0, Endpoints: 1
>  - Class Hub
>  - Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
> 
> 2: Mass Storage,  USB Revision 2.0
> -  USB DISK 2.0 0781076602A6
> - Class: (from Interface) Mass Storage
> - PacketSize: 64  Configurations: 1
> - Vendor: 0x13fe  Product 0x1e00 Version 1.16
>Configuration: 1
>- Interfaces: 1 Bus Powered 200mA
>  Interface: 0
>  - Alternate Setting 0, Endpoints: 2
>  - Class Mass Storage, Transp. SCSI, Bulk only
>  - Endpoint 1 In Bulk MaxPacket 512
>  - Endpoint 2 Out Bulk MaxPacket 512

Cool, I will pick the patch shortly.
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Re: [U-Boot] [PATCH] arm: socfpga: Fix USB doesn't work on socdk board

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:40:19 AM, Chin Liang See wrote:
> On Wed, 2015-12-23 at 10:37 +0800, shengjiangwu wrote:
> > Updated pinmux group EMACIO[1-8] and EMACIO[10-13] for USB.
> > 
> > Signed-off-by: shengjiangwu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> > ---
> > 
> >  board/altera/cyclone5-socdk/qts/pinmux_config.h |   24 +++--
> > 
> > --
> > 
> >  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> Tested-by: Chin Liang See 
> Acked-by: Chin Liang See 

Applied, thanks.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 04/17] arm: socfpga: sockit: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS

[Marek Vasut]

On Wednesday, December 23, 2015 at 03:57:21 AM, Chin Liang See wrote:
> On Wed, 2015-12-23 at 02:47 +0100, Marek Vasut wrote:
> > On Wednesday, December 23, 2015 at 02:36:13 AM, Chin Liang See wrote:
> > > On Wed, 2015-12-23 at 01:47 +0100, Marek Vasut wrote:
> > > > On Wednesday, December 23, 2015 at 01:21:31 AM, Chin Liang See
> > > > 
> > > > wrote:
> > > > > On Tue, 2015-12-22 at 21:28 +0100, Marek Vasut wrote:
> > > > > > On Tuesday, December 22, 2015 at 08:32:29 AM, Chin Liang See
> 
> > > > > > wrote:
> [..]
> 
> > > > > > I will drop this patch and fix the remaining three during
> > > > > > application, since
> > > > > > I want to get this set out of the door, but please do some
> > > > > > better
> > > > > > testing
> > > > > > next time.
> > > > > 
> > > > > Do share you build error so I can simulate the build error.
> > > > 
> > > > CONFIG_SPI_FLASH_USE_4K_SECTORS was used twice in the config file
> > > > sockit
> > > > config file (configs/socfpga_sockit) .
> > > 
> > > Oh I believe its commented out.
> > > 
> > > bash-3.2$ git grep --color CONFIG_SPI_FLASH_USE_4K_SECTORS
> > > configs/socfpga_arria5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> > > configs/socfpga_cyclone5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=
> > > n
> > > configs/socfpga_sockit_defconfig:# CONFIG_SPI_FLASH_USE_4K_SECTORS
> > > is
> > > not set
> > > configs/socfpga_sockit_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
> > 
> > But it's twice in there. Also, =n is not valid construct, to disable
> > config option you should comment it out the way it's done above.
> 
> Oh unaware the =n is invalid.
> Thanks for the fix.

NP

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/1] common: nvedit: use snprintf instead of sprintf

[Peng Fan]

Hi All,
On Tue, Dec 22, 2015 at 02:40:58PM -0500, Tom Rini wrote:
>On Tue, Dec 22, 2015 at 07:53:12AM -0200, Fabio Estevam wrote:
>> Hi Peng,
>> 
>> On Tue, Dec 22, 2015 at 7:14 AM, Peng Fan  wrote:
>> > From: Peng Fan 
>> >
>> > Use snprintf to replace sprintf.
>> 
>> You need to improve your commit log by saying why you are doing this change.

will add more commit log.
>
>
>Yes, please do so.  And if you're using Coverity internally you can
>still do a Reported-by: Coverity.
will add this.

Thanks,
Peng.


>
>-- 
>Tom


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Re: [U-Boot] [PATCH 1/1] common: env: initialize scalar variable

[Peng Fan]

Hi Wolfgang
On Tue, Dec 22, 2015 at 10:29:51AM +0100, Wolfgang Denk wrote:
>Dear Peng Fan,
>
>In message <1450775655-2979-2-git-send-email-van.free...@gmail.com> you wrote:
>> From: Peng Fan 
>> 
>> Before calling hsearch_r, initialize callback entry to NULL.
>
>Which exact problem are you fixing here?

This was reported by Coverity.
"
Uninitialized scalar variable (UNINIT)
uninit_use_in_call: Using uninitialized value e. Field e.callback is 
uninitialized when calling hsearch_r.
"
I'll add more commit log in V2.

Regards,
Peng.
>
>Best regards,
>
>Wolfgang Denk
>
>-- 
>DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
>Beware of the Turing Tar-pit in  which  everything  is  possible  but
>nothing of interest is easy.
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[U-Boot] [PULL] u-boot-socfpga/master

[Marek Vasut]

The following changes since commit 3721208fa7fdb2af6ac13300d5d81433742c6ba1:

  x86: Remove Graeme Russ from the git alias file (2015-12-21 09:37:46 -0500)

are available in the git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to f464a631426a30ffcbf2d7f732e678df1b684be8:

  arm: socfpga: Fix USB doesn't work on socdk board (2015-12-23 04:04:46 +0100)


Chin Liang See (24):
  arm: socfpga: Consolidate SDMMC environment
  arm: socfpga: cyclone5_socdk: Consolidate SDMMC environment
  arm: socfpga: arria5_socdk: Consolidate SDMMC environment
  arm: socfpga: de0_nano_soc: Consolidate SDMMC environment
  arm: socfpga: mcvevk: Consolidate SDMMC environment
  arm: socfpga: sockit: Consolidate SDMMC environment
  arm: socfpga: socrates: Consolidate SDMMC environment
  arm: socfpga: Enabling MTD default partitions
  arm: socfpga: Enable ubi and ubifs support
  arm: socfpga: cyclone5: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS
  arm: socfpga: arria5: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS
  arm: socfpga: sr1500: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS
  arm: socfpga: cyclone5_socdk: Enable ubiload console command
  arm: socfpga: arria5_socdk: Enable ubiload console command
  arm: socfpga: sockit: Enable ubiload console command
  arm: socfpga: sr1500: Enable ubiload console command
  arm: socfpga: cyclone5_socdk: Enable qspiload console command
  arm: socfpga: arria5_socdk: Enable qspiload console command
  arm: socfpga: sockit: Enable qspiload console command
  arm: socfpga: sr1500: Enable qspiload console command
  arm: socfpga: cyclone5_socdk: Update qspiboot to use UBIFS
  arm: socfpga: arria5_socdk: Update qspiboot to use UBIFS
  arm: socfpga: sockit: Update qspiboot to use UBIFS
  arm: socfpga: sr1500: Update qspiboot to use UBIFS

  
Marek Vasut (11):   
  
  arm: socfpga: Actually enable L2 cache
  
  net: designware: Zap CONFIG_DW_AUTONEG
  
  net: designware: Zap trailing backslash   
  
  arm: socfpga: Make /soc available in pre-reloc
  
  arm: socfpga: Enable simple bus in SPL on all boards  
  
  arm: socfpga: Define NAND reset bit   
  
  arm: socfpga: Unreset NAND in SPL
  arm: socfpga: Unreset NAND in U-Boot
  arm: socfpga: Enable SPL MMC/SPI support only if DM_MMC/SPI is enabled
  arm: socfpga: Enable DFU MMC support only if DM_MMC is enabled
  arm: socfpga: Add support for Denali NAND controller

Thomas Chou (1):
  net: eth_designware: select PHYLIB in Kconfig

shengjiangwu (3):
  arm: socfpga: Fix emac1 doesn't work on socdk board
  arm: socfpga: Fix QSPI doesn't work on socdk board
  arm: socfpga: Fix USB doesn't work on socdk board

 arch/arm/dts/socfpga_cyclone5_socdk.dts|  4 
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  3 ++-
 arch/arm/mach-socfpga/misc.c   | 17 +++--
 arch/arm/mach-socfpga/spl.c|  1 +
 board/altera/cyclone5-socdk/qts/pinmux_config.h| 64 

 board/altera/cyclone5-socdk/qts/pll_config.h   |  4 ++--
 board/spear/spear600/spear600.c|  3 ---
 configs/socfpga_arria5_defconfig   |  2 ++
 configs/socfpga_cyclone5_defconfig |  2 ++
 configs/socfpga_sr1500_defconfig   |  1 +
 drivers/net/Kconfig|  1 +
 drivers/net/designware.c   | 18 +++---
 include/configs/axs101.h   |  6 --
 include/configs/bf609-ezkit.h  |  1 -
 include/configs/galileo.h  |  1 -
 include/configs/socfpga_arria5_socdk.h | 12 ++--
 include/configs/socfpga_common.h   | 69 
+++--
 include/configs/socfpga_cyclone5_socdk.h   | 12 ++--
 

Re: [U-Boot] [PATCH v3 04/17] arm: socfpga: sockit: Undefine CONFIG_SPI_FLASH_USE_4K_SECTORS

[Chin Liang See]

On Wed, 2015-12-23 at 01:47 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 01:21:31 AM, Chin Liang See wrote:
> > On Tue, 2015-12-22 at 21:28 +0100, Marek Vasut wrote:
> > > On Tuesday, December 22, 2015 at 08:32:29 AM, Chin Liang See
> > > wrote:

[..]

> > > > 
> >   CFG spl/u-boot-spl.cfg
> >   FDTGREP spl/u-boot-spl.dtb
> >   CAT spl/u-boot-spl-dtb.bin
> >   MKIMAGE spl/u-boot-spl-dtb.sfp
> > make[1]: warning:  Clock skew detected.  Your build may be
> > incomplete.
> 
> This is a bit weird, isn't it ;-)

Yah, this is something need be hammered

> 
> >   MKIMAGE u-boot.img
> >   COPYu-boot.dtb
> >   CAT u-boot-dtb.bin
> >   MKIMAGE u-boot-dtb.img
> 
> [...]
> 
> > > There's buildman for doing such bulk builds, let me know if you
> > > need
> > > help
> > > setting it up.
> > 
> > That's sound good to me instead i invoke it manually every time.
> > Let me
> > take a look. A quick link would be much appreciated.
> 
> Thomas did a good concise writeup on setting up buildman:
> 
> http://www.mail-archive.com/u-boot@lists.denx.de/msg191914.html

Yah, I saw the conversation. Cool, let me set it up.

> 
> > > I will drop this patch and fix the remaining three during
> > > application, since
> > > I want to get this set out of the door, but please do some better
> > > testing
> > > next time.
> > 
> > Do share you build error so I can simulate the build error.
> 
> CONFIG_SPI_FLASH_USE_4K_SECTORS was used twice in the config file
> sockit
> config file (configs/socfpga_sockit) .

Oh I believe its commented out.

bash-3.2$ git grep --color CONFIG_SPI_FLASH_USE_4K_SECTORS
configs/socfpga_arria5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
configs/socfpga_cyclone5_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
configs/socfpga_sockit_defconfig:# CONFIG_SPI_FLASH_USE_4K_SECTORS is
not set
configs/socfpga_sockit_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
configs/socfpga_sr1500_defconfig:CONFIG_SPI_FLASH_USE_4K_SECTORS=n
drivers/mtd/spi/sf_internal.h:#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS

Thanks
Chin Liang

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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Wed, 2015-12-23 at 03:27 +0100, Marek Vasut wrote:
> On Wednesday, December 23, 2015 at 03:26:07 AM, 圣江 吴 wrote:
> > > From: Marek Vasut
> > > Date: 2015-12-23 10:07
> > > To: ShengjiangWu
> > > CC: u-boot; clsee; dinguyen; dinh.linux; pavel; sr
> > > Subject: Re: [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk
> > > board
> > > 
> > > On Wednesday, December 23, 2015 at 03:02:10 AM, ShengjiangWu
> > > wrote:
> > > > > -Original Message-
> > > > > From: Marek Vasut [mailto:ma...@denx.de]
> > > > > Sent: Wednesday, December 23, 2015 9:25 AM
> > > > > To: 圣江 吴
> > > > > Cc: u-boot@lists.denx.de; cl...@altera.com;
> > > > > dingu...@opensource.altera.com; dinh.li...@gmail.com; 
> > > > > pa...@denx.de;
> > > > > s...@denx.de Subject: Re: [PATCH] arm: socfpga: Fix QSPI
> > > > > doesn't work
> > > > > on socdk board
> > > > > 
> > > > > On Wednesday, December 23, 2015 at 02:22:49 AM, 圣江 吴 wrote:
> > > > > > On Dec 22, 2015, at 12:33 PM, Marek Vasut 
> > > > > > wrote:
> > > > > > 
> > > > > > On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut
> > > > > > wrote:
> > > > > > 
> > > > > > On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu
> > > > > > wrote:
> > > > > > > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > > > > > > Updated QSPI clock.
> > > > > > > 
> > > > > > > Signed-off-by: shengjiangwu 
> > > > > > > Cc: Chin Liang See 
> > > > > > > Cc: Dinh Nguyen 
> > > > > > > Cc: Dinh Nguyen 
> > > > > > > Cc: Pavel Machek 
> > > > > > > Cc: Marek Vasut 
> > > > > > > Cc: Stefan Roese 
> > > > > > 
> > > > > > Applied, thanks.
> > > > > > 
> > > > > > I will push your patches to [1] in a few hours, can you try
> > > > > > and see
> > > > > > if the CV SOCDK works fine for you? Thanks
> > > > > > 
> > > > > > [1] http://git.denx.de/?p=u-boot/u-boot-
> > > > > > socfpga.git;a=shortlog;h=refs/heads/master
> > > > > > 
> > > > > > Pushed. Please let me know how SoCDK works for you now and
> > > > > > if there
> > > > > > are still some problems.
> > > > > > 
> > > > > > 
> > > > > > Best regards,
> > > > > > Marek Vasut
> > > > > > 
> > > > > > 
> > > > > > Hi Marek,
> > > > > > 
> > > > > > Thank you for your help, I tested the master branch, emac1
> > > > > > and QSPI
> > > > > > works. Below is log.
> > > > > 
> > > > > Good! so we're happy ? Can you give USB a spin too? I think
> > > > > it might
> > > > > have some issues and I don't have the necessary cable here.
> > > > > 
> > > > > [...]
> > > > > 
> > > > > Best regards,
> > > > > Marek Vasut
> > > > 
> > > > Hi Marek,
> > > > 
> > > > Yes, emac1 and qspi are working now. I'm afraid USB is not
> > > > working,
> > > > 
> > > > => usb reset
> > > > resetting USB...
> > > > USB0: Core Release: 2.93a
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > dwc_otg_core_host_init: Timeout!
> > > > scanning bus 0 for devices... 1 USB Device(s) found
> > > > => usb tree
> > > > USB device tree:
> > > > 1 Hub (480 Mb/s, 0mA)
> > > > U-Boot Root Hub
> > > 
> > > Hm, darn. Can you or Chin check it ? It's either pinmux or wrong
> > > USB node
> > > in DT in arch/arm/dts/socfpga_cyclone5_socdk.dts .
> > 
> > Hi Marek,
> > 
> > Pin mux settings has error, set EMACIO[1-8] [10-13] from 3 to 2,
> > then usb
> > works,
> > 
> > => usb start
> > starting USB...
> > USB0: Core Release: 2.93a
> > scanning bus 0 for devices... 2 USB Device(s) found
> > => usb tree
> > USB device tree:
> > 1 Hub (480 Mb/s, 0mA)
> > 
> > > U-Boot Root Hub
> > 
> > +-2 Mass Storage (480 Mb/s, 98mA)
> > Generic USB Storage 0272
> 
> Cool, thanks! Patch please ;-)

Nice, guess Altera email is very slow

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] arm: socfpga: Fix USB doesn't work on socdk board

[Chin Liang See]

On Wed, 2015-12-23 at 10:37 +0800, shengjiangwu wrote:
> Updated pinmux group EMACIO[1-8] and EMACIO[10-13] for USB.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 
> ---
>  board/altera/cyclone5-socdk/qts/pinmux_config.h |   24 +++--
> --
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> 

Tested-by: Chin Liang See  
Acked-by: Chin Liang See 

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] imx: mx6sxsabresd: support emmc

[Peng Fan]

Hi Otavio,
On Tue, Dec 22, 2015 at 09:51:37AM -0200, Otavio Salvador wrote:
>On Tue, Dec 22, 2015 at 7:03 AM, Peng Fan  wrote:
>> From: Peng Fan 
>>
>> For i.MX6SX SABRESD, USDHC4 can be used for SD and EMMC, default
>> it is used for SD.
>>
>> This patch introduces EMMC pinmux settings and a new macro
>> CONFIG_MX6SXSABRESD_EMMC_REWORK. If the board has been reworked
>> to support emmc, need to enable this macro.
>>
>> Signed-off-by: Peng Fan 
>> Cc: Stefano Babic 
>
>Is it worth supporting this 'reworked' board? if someone reworks a
>board it is expected to have to rework the BSP of it, as well.

usdhc4 can be used for SD and emmc. This is the feature of the board,
so I think we need to support it. But there is no way to dynamically check
whether using sd or emmc now, adding the macro for using emmc.

Regards,
Peng.

>
>-- 
>Otavio Salvador O.S. Systems
>http://www.ossystems.com.brhttp://code.ossystems.com.br
>Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750
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Re: [U-Boot] [PATCH 2/2] dm: eth: Stick to 'ethact' when 'ethrotate' is 'no' in eth_init()

[Joe Hershberger]

On Tue, Dec 22, 2015 at 12:43 AM, Bin Meng  wrote:
> When 'ethrotate' variable is set to 'no' and 'ethact' variable
> is already set to an ethernet device, we should stick to 'ethact'.
>
> Signed-off-by: Bin Meng 

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 1/2] dm: eth: Test 'ethrotate' before changing current ethernet device

[Joe Hershberger]

On Tue, Dec 22, 2015 at 12:43 AM, Bin Meng  wrote:
> In eth_current_changed(), the call to eth_get_dev() below has a side
> effect of rotating ethernet device if uc_priv->current == NULL. This
> is not what we want when 'ethrotate' variable is 'no'.
>
> Signed-off-by: Bin Meng 

Acked-by: Joe Hershberger 
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Re: [U-Boot] Driver model test breakages

[Joe Hershberger]

Hi Simon,

On Tue, Dec 22, 2015 at 1:14 PM, Joe Hershberger
 wrote:
> Hi Simon,
>
> On Mon, Dec 21, 2015 at 9:17 PM, Joe Hershberger
>  wrote:
>> Hi Bin and Simon,
>>
>> On Mon, Dec 21, 2015 at 9:08 PM, Joe Hershberger
>>  wrote:
>>> Hi Bin,
>>>
>>> On Mon, Dec 21, 2015 at 9:00 PM, Bin Meng  wrote:
 Hi Joe,

 On Tue, Dec 22, 2015 at 10:39 AM, Joe Hershberger
  wrote:
> On Mon, Dec 21, 2015 at 8:36 PM, Bin Meng  wrote:
>> Hi Joe,
>>
>> On Tue, Dec 22, 2015 at 10:32 AM, Joe Hershberger
>>  wrote:
>>> Hi Bin,
>>>
>>> On Mon, Dec 21, 2015 at 8:12 PM, Bin Meng  wrote:
 Hi Joe, Simon,

 On Tue, Dec 22, 2015 at 6:46 AM, Joe Hershberger
  wrote:
> Hi Simon and Bin
>
> On Thu, Dec 10, 2015 at 8:05 PM, Simon Glass  
> wrote:
>> Hi,
>>
>> The following three commits causes breakages in the driver model 
>> tests:
>>
>> 4efad20a  sf: Update status reg check in spi_flash_cmd_wait_ready
>> 45b47734 net/arp: account for ARP delay, avoid duplicate packets 
>> on timeout
>> 9961a0b6sandbox: add a sandbox timer and basic test
>>
>> Can you please take a look? You can run them with 
>> ./test/dm/test-dm.sh
>
> It appears that ac1d313 (net: eth: Check return value in various
> places) breaks the eth_rotate test.
>
> Looking into it. Bin, do you have any ideas?

 I will look into this.

 BTW: I applied the following two patches [1][2] to the tree based on
 dm/master, and got a segmentation fault:

 Test: dm_test_usb_keyb
 ./test/dm/test-dm.sh: line 14: 24902 Segmentation fault
 ./sandbox/u-boot -d ./sandbox/arch/sandbox/dts/test.dtb -c "ut dm"

 [1] http://patchwork.ozlabs.org/patch/97/
 [2] http://patchwork.ozlabs.org/patch/559783/
>>>
>>> Interesting. I haven't tested on top of dm/master, but I tested it
>>> based on origin/master and the issue is resolved.
>>>
>>
>> Which issue is resolved? I just tested on top of origin/master with
>> the above two patches, still the same segmentation fault.
>
> The net_retry dm test hang that Simon reported.
>

 The segmentation fault happens after "Test: dm_test_usb_keyb". It
 seems to be a new issue.
>>>
>>> I agree it's a new issue that was masked by the net_retry hang.
>>
>> It appears, not too surprisingly, that d77a7d8 (dm: test: usb:
>> sandbox: Add keyboard tests for sandbox) is the source of the seg
>> fault.
>>
>> Simon?
>
> In looking for the seg fault in the usb kbd test, I found that the
> udev ptr passed to usb uclass is garbage, so the usb_ops is null, so
> we crash. Do you have a quick explanation for how this emulated USB is
> supposed to work? I haven't looked at it before. I'll keep digging
> until you can provide some insight.

Actually the controller passed in is OK and the driver ptr is OK, but
the ops ptr is NULL. Seems odd.

-Joe
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Re: [U-Boot] [PATCH 6/6] arm: socfpga: Add support for Denali NAND controller

[Marek Vasut]

On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote:
> On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote:
> > Add common configuration bits for the Denali NAND controller and also
> > support for using it as a boot device in SPL.
> > 
> > Signed-off-by: Marek Vasut 
> > Cc: Dinh Nguyen 
> > Cc: Chin Liang See 
> > ---
> > 
> >  include/configs/socfpga_common.h | 23 +++
> >  1 file changed, 23 insertions(+)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 4124d8b..8886ccf 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -162,6 +162,19 @@
> > 
> >  #endif
> >  
> >  /*
> > 
> > + * NAND Support
> > + */
> > +#ifdef CONFIG_NAND_DENALI
> > +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> > +#define CONFIG_SYS_NAND_MAX_CHIPS  1
> > +#define CONFIG_SYS_NAND_ONFI_DETECTION
> > +#define CONFIG_NAND_DENALI_ECC_SIZE512
> > +#define CONFIG_SYS_NAND_REGS_BASE  0xffb8
> > +#define CONFIG_SYS_NAND_DATA_BASE  0xff90
> 
> You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS

Fixed and applied, thanks.

I believe we should be getting close to a good stable setup, so it's about
time to start testing once I issue this last heftier PR.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Marek Vasut]

On Tuesday, December 22, 2015 at 09:19:16 PM, Marek Vasut wrote:
> On Tuesday, December 22, 2015 at 10:18:09 AM, shengjiangwu wrote:
> > Updated pinmux group MIXED1IO[15-20] for QSPI.
> > Updated QSPI clock.
> > 
> > Signed-off-by: shengjiangwu 
> > Cc: Chin Liang See 
> > Cc: Dinh Nguyen 
> > Cc: Dinh Nguyen 
> > Cc: Pavel Machek 
> > Cc: Marek Vasut 
> > Cc: Stefan Roese 
> 
> Applied, thanks.
> 
> I will push your patches to [1] in a few hours, can you try and see if the
> CV SOCDK works fine for you? Thanks
> 
> [1] http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/master

Pushed. Please let me know how SoCDK works for you now and if there are still
some problems.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board

[Marek Vasut]

On Tuesday, December 22, 2015 at 08:22:02 AM, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[0-13] for RGMII1.
> Updated EMAC1 clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 

Applied, thanks.

Best regards,
Marek Vasut
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Re: [U-Boot] Driver model test breakages

[Joe Hershberger]

Hi Bin,

On Tue, Dec 22, 2015 at 12:43 AM, Bin Meng  wrote:
> Hi Joe,
>
> On Tue, Dec 22, 2015 at 12:50 PM, Bin Meng  wrote:
>> On Tue, Dec 22, 2015 at 12:04 PM, Bin Meng  wrote:
>>> Hi Joe,
>>>
>>> On Tue, Dec 22, 2015 at 11:08 AM, Joe Hershberger
>>>  wrote:
 Hi Bin,

 On Mon, Dec 21, 2015 at 9:00 PM, Bin Meng  wrote:
> Hi Joe,
>
> On Tue, Dec 22, 2015 at 10:39 AM, Joe Hershberger
>  wrote:
>> On Mon, Dec 21, 2015 at 8:36 PM, Bin Meng  wrote:
>>> Hi Joe,
>>>
>>> On Tue, Dec 22, 2015 at 10:32 AM, Joe Hershberger
>>>  wrote:
 Hi Bin,

 On Mon, Dec 21, 2015 at 8:12 PM, Bin Meng  wrote:
> Hi Joe, Simon,
>
> On Tue, Dec 22, 2015 at 6:46 AM, Joe Hershberger
>  wrote:
>> Hi Simon and Bin
>>
>> On Thu, Dec 10, 2015 at 8:05 PM, Simon Glass  
>> wrote:
>>> Hi,
>>>
>>> The following three commits causes breakages in the driver model 
>>> tests:
>>>
>>> 4efad20a  sf: Update status reg check in 
>>> spi_flash_cmd_wait_ready
>>> 45b47734 net/arp: account for ARP delay, avoid duplicate 
>>> packets on timeout
>>> 9961a0b6sandbox: add a sandbox timer and basic test
>>>
>>> Can you please take a look? You can run them with 
>>> ./test/dm/test-dm.sh
>>
>> It appears that ac1d313 (net: eth: Check return value in various
>> places) breaks the eth_rotate test.
>>
>> Looking into it. Bin, do you have any ideas?
>
> I will look into this.
>
> BTW: I applied the following two patches [1][2] to the tree based on
> dm/master, and got a segmentation fault:
>
> Test: dm_test_usb_keyb
> ./test/dm/test-dm.sh: line 14: 24902 Segmentation fault
> ./sandbox/u-boot -d ./sandbox/arch/sandbox/dts/test.dtb -c "ut dm"
>
> [1] http://patchwork.ozlabs.org/patch/97/
> [2] http://patchwork.ozlabs.org/patch/559783/

 Interesting. I haven't tested on top of dm/master, but I tested it
 based on origin/master and the issue is resolved.

>>>
>>> Which issue is resolved? I just tested on top of origin/master with
>>> the above two patches, still the same segmentation fault.
>>
>> The net_retry dm test hang that Simon reported.
>>
>
> The segmentation fault happens after "Test: dm_test_usb_keyb". It
> seems to be a new issue.

 I agree it's a new issue that was masked by the net_retry hang.

> I am looking into _dm_test_eth_rotate1 failure, but I don't understand
> the comments here.
>
> /* If ethrotate is no, then we should fail on a bad MAC */
> setenv("ethact", "eth@10004000");
> setenv("ethrotate", "no");
> ut_asserteq(-EINVAL, net_loop(PING));
> ut_asserteq_str("eth@10004000", getenv("ethact"));
>
> Does 'bad MAC' mean no MAC address? For eth@10004000, it does have a
> MAC address defined in the env variable in sandbox.h.

 I think if you look at dm_test_eth_rotate(), the eth1addr is deleted
 before the test. Later, ethaddr is deleted before the second part of
 the test.

> I also tested manually with the same test sequence from U-Boot shell,
> it can pass. I am still looking into it.

 It's not as though it hangs or something, but it now fails to return
 the error code that it used to before your patch.

 Test: dm_test_eth_rotate
 ../test/dm/eth.c:160, _dm_test_eth_rotate1(): -EINVAL ==
 net_loop(PING): Expected -22, got 0

>>>
>>> During debug I've noticed another strange issue:
>>>
>>> Sometimes the sandbox's setenv() does not successfully set the
>>> environment variable to the expected value. This occurs from time to
>>> time, even with the same u-boot image. Do you have any idea about
>>> this?
>>>
>>
>> I may have been dazed that I looked the wrong message line. The issue
>> is complicated. My commit just exposed an existing issue that have
>> been in the dm eth codes from the beginning, that the eth_set_dev()
>> logic is not controlled by the env variable "ethrotate". If the
>> "ethact" is set to an eth device which cannot be probed (eg: no valid
>> ethaddr) and "ethrotate" is set to "no" (like in this test case), the
>> "ethact" will still point to the first probable eth device, in this
>> sandbox case, eth@10002000.
>>
>> I am still figuring out where to fix. Joe, you might want to have a look?
>>
>
> Please check the following two patches for dm_eth_rorate test.
>
> http://patchwork.ozlabs.org/patch/559882/
> 

Re: [U-Boot] [RFC PATCH 01/11] serial: Add support for Qualcomm serial port

[Simon Glass]

Hi Masahiro,

On 20 December 2015 at 23:50, Masahiro Yamada
 wrote:
> 2015-12-16 3:58 GMT+09:00 Simon Glass :
>
>>> +++ b/drivers/serial/serial_msm.c
>>> @@ -0,0 +1,204 @@
>>> +/*
>>> + * Qualcomm UART driver
>>> + *
>>> + * (C) Copyright 2015 Mateusz Kulikowski 
>>> + *
>>> + * UART will work in Data Mover mode.
>>> + * Based on Linux driver.
>>> + *
>>> + * SPDX-License-Identifier:GPL-2.0+
>>> + */
>>> +
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>
>> Ordering:
>>
>> common.h
>> clk.h
>> dm.h
>> errno.h
>> serial.h
>> watchdog.h
>> asm/
>> linux/
>>
>>
>
> No.
>
> Put  above , at least.
> (the same order in Linux)
>
>
>
> BTW, the "Include file order" in
> http://www.denx.de/wiki/U-Boot/CodingStyle
>
> Is this your opinion? Or community's opinion.
>
> Did anybody review it?

This came from Mike Frysinger some years ago on the mailing list and I
have followed it since. I took it to be a U-Boot standard and added it
to the Wiki at some point. Linux perhaps has linux/ above asm/ for its
own reasons (e.g. because it is Linux and needs its headers first) but
I don't think that is a good idea for U-Boot. It is unnecessary and
makes the sort order more confusing.

Regards,
Simon
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Re: [U-Boot] [PATCH 2/2] arm: socfpga: Enable simple bus in SPL on all boards

[Marek Vasut]

On Tuesday, December 22, 2015 at 04:41:09 AM, Marek Vasut wrote:
> The simple bus support must be enabled in SPL, otherwise the boards
> will not be able to parse the DT and will fail to boot.
> 
> Signed-off-by: Marek Vasut 
> Cc: Dinh Nguyen 

Applied both, thanks.

Best regards,
Marek Vasut
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[U-Boot] Pull request: u-boot-net

[Joe Hershberger]

A few patches that came in during the merge window and appear harmless.

These cause no additional build warnings or errors.

Thanks,
-Joe

The following changes since commit 4832e17787acb29734d895751bc7a594908aecc6:

  Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
(2015-12-18 07:28:24 -0500)

are available in the git repository at:


  git://git.denx.de/u-boot-net.git master

for you to fetch changes up to 140bc33e05382545b762ef51d6fc31dd5b6ec82c:

  net: e1000: Mark _disable_wr() and _write_status() as __maybe_unused
(2015-12-21 20:01:57 -0600)


Bin Meng (5):
  fdt: Deprecate "usbethaddr" usage in fdt_fixup_ethernet()
  fdt: Rewrite the logic in fdt_fixup_ethernet()
  net: e1000: Remove dead codes wrapped by #if 0
  net: e1000: Remove CONFIG_MVBC_1G
  net: e1000: Mark _disable_wr() and _write_status() as __maybe_unused

Fabio Estevam (1):
  include: net: Simplify the usage of __always_inline

 common/fdt_support.c| 64 
 drivers/net/e1000.c | 77 +
 drivers/net/e1000.h | 31 
 drivers/net/e1000_spi.c |  9 +++---
 include/net.h   |  9 +++---
 5 files changed, 42 insertions(+), 148 deletions(-)
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Re: [U-Boot] [PATCH v3 2/2] fdt: Rewrite the logic in fdt_fixup_ethernet()

[Joe Hershberger]

Hi Bin,

On Tue, Nov 3, 2015 at 6:24 AM, Bin Meng  wrote:
> Currently in fdt_fixup_ethernet() the MAC address fix up is
> handled in a loop of which the exit condition is to test the
> "eth%daddr" env is not NULL. However this creates unnecessary
> constrains that those "eth%daddr" env variables must be
> sequential even if "ethernet%d" does not start from 0 in the
> "/aliases" node. For example, with "/aliases" node below:
>
> aliases {
> ethernet3 = 
> ethernet4 = 
> };
>
> "ethaddr", "eth1addr", "eth2addr" must exist in order to fix
> up ethernet3's MAC address successfully.
>
> Now we change the loop logic to iterate the properties in the
> "/aliases" node. For each property, test if it is in a format
> of "ethernet%d", then get its MAC address from corresponding
> "eth%daddr" env and fix it up in the dtb.
>
> Signed-off-by: Bin Meng 
> Acked-by: Joe Hershberger 
> Reviewed-by: Tom Rini 
> On OMAP4 Panda (+v4.3 kernel)
> Tested-by: Tom Rini 

Applied to u-boot-net/master, thanks!
-Joe
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Re: [U-Boot] [PATCH 1/3] net: e1000: Remove dead codes wrapped by #if 0

[Joe Hershberger]

On Mon, Nov 16, 2015 at 3:19 AM, Bin Meng  wrote:
> Remove those dead codes wrapped by #if 0 and #endif.
>
> Signed-off-by: Bin Meng 

Applied to u-boot-net/master, thanks!
-Joe
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Re: [U-Boot] [PATCH v3 1/2] fdt: Deprecate "usbethaddr" usage in fdt_fixup_ethernet()

[Joe Hershberger]

Hi Bin,

On Tue, Nov 3, 2015 at 6:24 AM, Bin Meng  wrote:
> In fdt_fixup_ethernet() only "usbethaddr" is handled to fix up the
> first usb ethernet port MAC address. Other additional usb ethernet
> ports are ignored as there is no logic to handle "usbeth%daddr".
>
> It is suggested we should use "ethaddr" for all ethernet devices.
> Hence deprecate "usbethaddr" usage in fdt_fixup_ethernet().
>
> This actually reverts commit b1f49ab8c7bad60426b30c134ae065ef77d2dfc1
> "ARM: fdt support: Add usbethaddr as an acceptable MAC".
>
> Signed-off-by: Bin Meng 
> Acked-by: Joe Hershberger 
> Reviewed-by: Tom Rini 
> On OMAP4 Panda (+ v4.3 kernel)
> Tested-by: Tom Rini 

Applied to u-boot-net/master, thanks!
-Joe
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Re: [U-Boot] [PATCH 3/3] net: e1000: Mark _disable_wr() and _write_status() as __maybe_unused

[Joe Hershberger]

On Mon, Nov 16, 2015 at 3:19 AM, Bin Meng  wrote:
> Per the comments, e1000_spi_eeprom_disable_wr() and
> e1000_spi_eeprom_write_status() have been tested.
> Remove the #if 0, #endif and mark them as __maybe_unused.
>
> Signed-off-by: Bin Meng 

Applied to u-boot-net/master, thanks!
-Joe
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Re: [U-Boot] [PATCH 2/3] net: e1000: Remove CONFIG_MVBC_1G

[Joe Hershberger]

On Mon, Nov 16, 2015 at 3:19 AM, Bin Meng  wrote:
> CONFIG_MVBC_1G is not referenced anywhere, hence remove it.
>
> Signed-off-by: Bin Meng 

Applied to u-boot-net/master, thanks!
-Joe
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Re: [U-Boot] [PATCH] include: net: Simplify the usage of __always_inline

[Joe Hershberger]

On Sun, Nov 8, 2015 at 6:25 PM, Fabio Estevam  wrote:
> From: Fabio Estevam 
>
> Since commit de4d2e9e7ce0f9 (" bitops: Add fls_long and __ffs64")
>  is included in include/linux/bitops.h,
> which allows us to marking a function as 'always_inline' in a simpler
> format.
>
> Signed-off-by: Fabio Estevam 

Applied to u-boot-net/master, thanks!
-Joe
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[U-Boot] [PATCH v2] cmd_boot: Add a poweroff command

[Hans de Goede]

From: Michael van Slingerland 

Add a 'poweroff' command to boot commands, this only gets enabled if the
board Kconfig does a "select CMD_POWEROFF".

Signed-off-by: Michael van Slingerland 
[hdego...@redhat.com: Make the cmd conditional on a CMD_POWEROFF Kconfig]
Signed-off-by: Hans de Goede 
---
Changes in v2:
-Improve poweroff help text
-Remove unnecessary #ifdef from command.h
---
 common/Kconfig| 3 +++
 common/cmd_boot.c | 8 
 include/command.h | 1 +
 3 files changed, 12 insertions(+)

diff --git a/common/Kconfig b/common/Kconfig
index ccf5475..9d446bf 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -184,6 +184,9 @@ config CMD_XIMG
help
  Extract a part of a multi-image.
 
+config CMD_POWEROFF
+   bool
+
 endmenu
 
 menu "Environment commands"
diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 8f2e070..72f2cf3 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -61,3 +61,11 @@ U_BOOT_CMD(
"Perform RESET of the CPU",
""
 );
+
+#ifdef CONFIG_CMD_POWEROFF
+U_BOOT_CMD(
+   poweroff, 1, 0, do_poweroff,
+   "Perform POWEROFF of the device",
+   ""
+);
+#endif
diff --git a/include/command.h b/include/command.h
index 2ae9b6c..0524c0b 100644
--- a/include/command.h
+++ b/include/command.h
@@ -110,6 +110,7 @@ extern int common_diskboot(cmd_tbl_t *cmdtp, const char 
*intf, int argc,
   char *const argv[]);
 
 extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[]);
 
 /*
  * Error codes that commands return to cmd_process(). We use the standard 0
-- 
2.5.0

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Re: [U-Boot] [RFC PATCH 01/11] serial: Add support for Qualcomm serial port

[Masahiro Yamada]

Hi Simon,



>> BTW, the "Include file order" in
>> http://www.denx.de/wiki/U-Boot/CodingStyle
>>
>> Is this your opinion? Or community's opinion.
>>
>> Did anybody review it?
>
> This came from Mike Frysinger some years ago on the mailing list and I
> have followed it since. I took it to be a U-Boot standard and added it
> to the Wiki at some point. Linux perhaps has linux/ above asm/ for its
> own reasons (e.g. because it is Linux and needs its headers first) but
> I don't think that is a good idea for U-Boot. It is unnecessary and
> makes the sort order more confusing.
>

OK, but I want to know the reason.
Do you remember why Mike Frysinger suggested so?

I guess Linux sorts headers from global to local.

#include global in the project
#include   arch-specific
#include "foo.h"local in the directory


Likewise, the following makes sense for U-Boot

#include 
#include <*.h>  global in the project (U-boot orignal)
#include global in the project (come from Linux)
#include   arch-specific
#include  SoC-specific
#include "foo.h"local in the directory

if I am not missing something...


-- 
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Masahiro Yamada
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[U-Boot] [PATCH V2] common: nvedit: use snprintf instead of sprintf

[Peng Fan]

From: Peng Fan 

Use snprintf to replace sprintf.

Coverity log:
"
Unbounded source buffer (STRING_SIZE)
string_size: Passing string init_val of unknown size to sprintf.
"

Reported-by: Coverity
Signed-off-by: Peng Fan 
Cc: Tom Rini 
Cc: Simon Glass 
Reviewed-by: Joe Hershberger 
---
 common/cmd_nvedit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index f4c2523..3d295d1 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -594,7 +594,7 @@ static int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc,
/* Set read buffer to initial value or empty sting */
init_val = getenv(argv[1]);
if (init_val)
-   sprintf(buffer, "%s", init_val);
+   snprintf(buffer, CONFIG_SYS_CBSIZE, "%s", init_val);
else
buffer[0] = '\0';
 
-- 
2.6.2

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[U-Boot] [PATCH V2] common: env: initialize scalar variable

[Peng Fan]

From: Peng Fan 

Before calling hsearch_r, initialize callback entry to NULL.

Coverity log:
"
Uninitialized scalar variable (UNINIT)
uninit_use_in_call: Using uninitialized value e.
Field e.callback is uninitialized when calling hsearch_r.
"

Reported-by: Coverity
Signed-off-by: Peng Fan 
Cc: Tom Rini 
Cc: Simon Glass 
---
 common/env_callback.c | 1 +
 common/env_flags.c| 1 +
 2 files changed, 2 insertions(+)

diff --git a/common/env_callback.c b/common/env_callback.c
index f4d3dbd..1957cc1 100644
--- a/common/env_callback.c
+++ b/common/env_callback.c
@@ -97,6 +97,7 @@ static int set_callback(const char *name, const char *value, 
void *priv)
 
e.key   = name;
e.data  = NULL;
+   e.callback = NULL;
hsearch_r(e, FIND, , _htab, 0);
 
/* does the env variable actually exist? */
diff --git a/common/env_flags.c b/common/env_flags.c
index e682d85..7719355 100644
--- a/common/env_flags.c
+++ b/common/env_flags.c
@@ -455,6 +455,7 @@ static int set_flags(const char *name, const char *value, 
void *priv)
 
e.key   = name;
e.data  = NULL;
+   e.callback = NULL;
hsearch_r(e, FIND, , _htab, 0);
 
/* does the env variable actually exist? */
-- 
2.6.2

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Re: [U-Boot] [PATCH 0/9] EFI payload / application support

[Alexander Graf]

On 22.12.15 19:28, Matwey V. Kornilov wrote:
> 2015-12-22 16:57 GMT+03:00 Alexander Graf :
>> This is my Christmas present for my openSUSE friends :).
>>
> 
> Santa, do you have u-boot rpm packed with the patches to test?

Once OBS has finished compiling, they should be available here:

  https://build.opensuse.org/project/show/home:algraf:branches:Base:System

If you also want a 32bit ARM grub2 binary, check out

  https://build.opensuse.org/project/show/devel:ARM:Factory:Contrib:HIP04D01


Merry Christmas ;)

Alex
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Re: [U-Boot] [PATCH] net: lpc32xx: Fix MDIO busy wait

[MESSIER, ALEXANDRE]

Hello Vladimir,

> Hi Alexandre,
>
> On 16.12.2015 20:37, amessier.t...@gmail.com wrote:
> > From: Alexandre Messier 
> >
> > The MDIO read function waits on the busy flag after issuing the read
> > command,
>
> that's correct, after issuing the read command and before register read.
>
> > while the MDIO write function waits on the busy flag before
> > issuing the write command.
>
> and that is not correct, I believe.
>
> From the spec (MII Mgmt Indicators Register):
>
>   For PHY Write if scan is not used:
>   1. Write 0 to MCMD
>   2. Write PHY address and register address to MADR
>   3. Write data to MWTD
> -->   4. Wait for busy bit to be cleared in MIND
>
>   For PHY Read if scan is not used:
>   1. Write 1 to MCMD
>   2. Write PHY address and register address to MADR
> -->   3. Wait for busy bit to be cleared in MIND
>   4. Write 0 to MCMD
>   5. Read data from MRDD
>
> Could you please test/review an alternative fix? I believe it adds proper
> serialization of all command sequences (read/read, read/write, write/read
> and write/write). Thank you in advance.

Yes, this approach is fine too. I tested it and it fixes the issue.

If you want to submit it as a new patch:
Tested-by: Alexandre Messier 

>
> diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
> index e76e9bc..3ba5b4b 100644
> --- a/drivers/net/lpc32xx_eth.c
> +++ b/drivers/net/lpc32xx_eth.c
> @@ -304,6 +304,13 @@ static int mii_reg_write(const char *devname, u8
> phy_adr, u8 reg_ofs, u16 data)
>   return -EFAULT;
>   }
>
> + /* write the phy and reg addressse into the MII address reg */
> + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs <<
> MADR_REG_OFFSET),
> +>madr);
> +
> + /* write data to the MII write register */
> + writel(data, >mwtd);
> +
>   /* wait till the MII is not busy */
>   timeout = MII_TIMEOUT;
>   do {
> @@ -319,13 +326,6 @@ static int mii_reg_write(const char *devname, u8
> phy_adr, u8 reg_ofs, u16 data)
>   return -EFAULT;
>   }
>
> - /* write the phy and reg addressse into the MII address reg */
> - writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs <<
> MADR_REG_OFFSET),
> ->madr);
> -
> - /* write data to the MII write register */
> - writel(data, >mwtd);
> -
>   /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
>   reg_ofs, data);*/
>
>
> > This causes an issue when writing then immediately reading. As the MDIO
> > module is still busy, the read command is not processed. The wait on
> > busy flag in the read command passes because the previous write
> command
> > finishes. In the end, the value returned by the read function is
> > whatever was present in the MDIO data register.
> >
> > Fix the issue by making sure the busy flag is cleared before issuing a
> > read command. This way, it is still possible to issue a write command
> > and continue executing u-boot code while the command is processed by
> > the hardware. Any following MDIO read/write commands after a write
> > command will wait for a cleared busy flag.
>
> --
> With best wishes,
> Vladimir
>
>




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[U-Boot] [RESEND PATCH 0/5] clk: some fixes, device tree support, new features

[Masahiro Yamada]

This series contains the same commits
as 01-05 of the RFC series.

Since somebody immediately marked it as RFC
(i.e. dropped from the TODO items in the patchwork),
nothing has happened to it.

I am resending 01-05 without RFC prefix
in order to leave this series in the TODO list
until appropriate action is taken.

As you see, 01 and 02 are apparent fixes
which can be applied soon.



Masahiro Yamada (5):
  clk: fix comments in include/clk.h
  clk: add needed include and declaration to include/clk.h
  clk: add function to get peripheral ID
  clk: add device tree support for clock framework
  clk: add enable() callback

 drivers/clk/Makefile |  1 +
 drivers/clk/clk-fdt.c| 37 
 drivers/clk/clk-uclass.c | 10 ++
 include/clk.h| 87 ++--
 4 files changed, 125 insertions(+), 10 deletions(-)
 create mode 100644 drivers/clk/clk-fdt.c

-- 
1.9.1

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[U-Boot] [RESEND PATCH 3/5] clk: add function to get peripheral ID

[Masahiro Yamada]

Currently, this framework does not provide the systematic way
to get the peripheral ID (clock index).

I assume that the functions added by this commit are mainly used to
get the ID from "clocks" properties in device trees although they are
not limited to that use.

Signed-off-by: Masahiro Yamada 
---

 drivers/clk/clk-uclass.c | 10 ++
 include/clk.h| 34 ++
 2 files changed, 44 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 73dfd7d..8078b0f 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -52,6 +52,16 @@ ulong clk_set_periph_rate(struct udevice *dev, int periph, 
ulong rate)
return ops->set_periph_rate(dev, periph, rate);
 }
 
+int clk_get_id(struct udevice *dev, int args_count, uint32_t *args)
+{
+   struct clk_ops *ops = clk_get_ops(dev);
+
+   if (!ops->get_id)
+   return -ENOSYS;
+
+   return ops->get_id(dev, args_count, args);
+}
+
 UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name   = "clk",
diff --git a/include/clk.h b/include/clk.h
index 371784a..1efbaf2 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -49,6 +49,16 @@ struct clk_ops {
 * @return new clock rate in Hz, or -ve error code
 */
ulong (*set_periph_rate)(struct udevice *dev, int periph, ulong rate);
+
+   /**
+* get_id() - Get peripheral ID
+*
+* @dev:clock provider
+* @args_count: number of arguments
+* @args:   arguments.  The meaning is driver specific.
+* @return peripheral ID, or -ve error code
+*/
+   int (*get_id)(struct udevice *dev, int args_count, uint32_t *args);
 };
 
 #define clk_get_ops(dev)   ((struct clk_ops *)(dev)->driver->ops)
@@ -87,4 +97,28 @@ ulong clk_get_periph_rate(struct udevice *dev, int periph);
  */
 ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate);
 
+/**
+ * clk_get_id() - Get peripheral ID
+ *
+ * @dev:   clock provider
+ * @args_count:number of arguments
+ * @args:  arguments.  The meaning is driver specific.
+ * @return peripheral ID, or -ve error code
+ */
+int clk_get_id(struct udevice *dev, int args_count, uint32_t *args);
+
+/**
+ * clk_get_id_simple() - Simple implementation of get_id() callback
+ *
+ * @dev:   clock provider
+ * @args_count:number of arguments
+ * @args:  arguments.
+ * @return peripheral ID, or -ve error code
+ */
+static inline int clk_get_id_simple(struct udevice *dev, int args_count,
+   uint32_t *args)
+{
+   return args_count > 0 ? args[0] : 0;
+}
+
 #endif /* _CLK_H_ */
-- 
1.9.1

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[U-Boot] [RESEND PATCH 1/5] clk: fix comments in include/clk.h

[Masahiro Yamada]

The comment about get_periph_rate() is the same as that of
set_periph_rate().

I am fixing typos here and there while I am in this file.

Signed-off-by: Masahiro Yamada 
---

 include/clk.h | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/include/clk.h b/include/clk.h
index 254ad2b..f244301 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -29,19 +29,19 @@ struct clk_ops {
ulong (*set_rate)(struct udevice *dev, ulong rate);
 
/**
-   * clk_set_periph_rate() - Set clock rate for a peripheral
-   *
-   * @dev: Device to adjust (UCLASS_CLK)
-   * @rate:New clock rate in Hz
-   * @return new clock rate in Hz, or -ve error code
-   */
+* get_periph_rate() - Get clock rate for a peripheral
+*
+* @dev:Device to check (UCLASS_CLK)
+* @periph: Peripheral ID to check
+* @return clock rate in Hz, or -ve error code
+*/
ulong (*get_periph_rate)(struct udevice *dev, int periph);
 
/**
-* clk_set_periph_rate() - Set current clock rate for a peripheral
+* set_periph_rate() - Set current clock rate for a peripheral
 *
 * @dev:Device to update (UCLASS_CLK)
-* @periph: Peripheral ID to cupdate
+* @periph: Peripheral ID to update
 * @return new clock rate in Hz, or -ve error code
 */
ulong (*set_periph_rate)(struct udevice *dev, int periph, ulong rate);
@@ -58,7 +58,7 @@ struct clk_ops {
 ulong clk_get_rate(struct udevice *dev);
 
 /**
- * set_rate() - Set current clock rate
+ * clk_set_rate() - Set current clock rate
  *
  * @dev:   Device to adjust
  * @rate:  New clock rate in Hz
@@ -78,7 +78,7 @@ ulong clk_get_periph_rate(struct udevice *dev, int periph);
  * clk_set_periph_rate() - Set current clock rate for a peripheral
  *
  * @dev:   Device to update (UCLASS_CLK)
- * @periph:Peripheral ID to cupdate
+ * @periph:Peripheral ID to update
  * @return new clock rate in Hz, or -ve error code
  */
 ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate);
-- 
1.9.1

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[U-Boot] [RESEND PATCH 5/5] clk: add enable() callback

[Masahiro Yamada]

The most basic thing for clock is to enable it, but it is missing
in this uclass.

Signed-off-by: Masahiro Yamada 
---

 include/clk.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/include/clk.h b/include/clk.h
index 518cb47..ce2db41 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -33,6 +33,15 @@ struct clk_ops {
ulong (*set_rate)(struct udevice *dev, ulong rate);
 
/**
+* enable() - Enable the clock for a peripheral
+*
+* @dev:clock provider
+* @periph: Peripheral ID to enable
+* @return zero on success, or -ve error code
+*/
+   int (*enable)(struct udevice *dev, int periph);
+
+   /**
 * get_periph_rate() - Get clock rate for a peripheral
 *
 * @dev:Device to check (UCLASS_CLK)
-- 
1.9.1

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[U-Boot] is it worth enhancing cmd_immap.c to handle 83xx?

[Robert P. J. Day]

  as i'm currently messing with MPC8360e-based board, is there any
value in submitting a patch so that cmd_immap.c can handle 83xx? it
seems pretty straightforward. i'm also working on the politics of
being allowed to submit a patch to deal with an MPC8360e-based system
currently being ported to linux so that that cmd_immap.c enhancement
would have actual value.

rday

-- 


Robert P. J. Day Ottawa, Ontario, CANADA
http://crashcourse.ca

Twitter:   http://twitter.com/rpjday
LinkedIn:   http://ca.linkedin.com/in/rpjday


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Re: [U-Boot] [PATCH v2 2/4] mips: ath79: add spi driver

[Jagan Teki]

On 22 December 2015 at 13:14, Wills Wang  wrote:
> Signed-off-by: Wills Wang 
> ---
>
>  drivers/spi/Makefile|   1 +
>  drivers/spi/ath79_spi.c | 142 
> 

Please write it on driver-model, we're accepting new drivers will be
in driver-model format.

>  2 files changed, 143 insertions(+)
>  create mode 100644 drivers/spi/ath79_spi.c
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 3eca745..7fb2926 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -17,6 +17,7 @@ endif
>
>  obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
>  obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
> +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
>  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
>  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
>  obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
> diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
> new file mode 100644
> index 000..e9a9dd2
> --- /dev/null
> +++ b/drivers/spi/ath79_spi.c
> @@ -0,0 +1,142 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, 
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define REG_READ(b, o) readl(KSEG1ADDR(b + o))
> +#define REG_WRITE(b, o, v) writel((v), KSEG1ADDR(b + o))
> +#define SPI_READ(a)REG_READ(AR71XX_SPI_BASE, a)
> +#define SPI_WRITE(a, v)REG_WRITE(AR71XX_SPI_BASE, a, v)
> +
> +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
> +#define SPI_CLK_DIV(x) ((x >> 1) - 1)
> +
> +struct ar71xx_spi_slave {
> +   struct spi_slave slave;
> +   unsigned int mode;
> +};
> +
> +static inline struct ar71xx_spi_slave *to_ar71xx_spi(struct spi_slave *slave)
> +{
> +   return container_of(slave, struct ar71xx_spi_slave, slave);
> +}
> +
> +void spi_init(void)
> +{
> +   /* Init SPI Hardware, disable remap, set clock */
> +   SPI_WRITE(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
> +   SPI_WRITE(AR71XX_SPI_REG_CTRL, AR71XX_SPI_CTRL_RD | SPI_CLK_DIV(8));
> +   SPI_WRITE(AR71XX_SPI_REG_FS, 0);
> +}
> +
> +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
> +   unsigned int max_hz, unsigned int mode)
> +{
> +   struct ar71xx_spi_slave *ss;
> +
> +   if (bus || (cs > 2))
> +   return NULL;
> +
> +   ss = malloc(sizeof(struct ar71xx_spi_slave));
> +   if (!ss)
> +   return NULL;
> +   memset(ss, 0, sizeof(struct ar71xx_spi_slave));
> +
> +   ss->slave.bus = bus;
> +   ss->slave.cs = cs;
> +   ss->slave.memory_map = (void *)KSEG0ADDR(AR71XX_SPI_BASE);
> +   ss->mode = mode;
> +
> +   return >slave;
> +}
> +
> +void spi_free_slave(struct spi_slave *slave)
> +{
> +   struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave);
> +
> +   free(ss);
> +}
> +
> +int spi_claim_bus(struct spi_slave *slave)
> +{
> +   return 0;
> +}
> +
> +void spi_release_bus(struct spi_slave *slave)
> +{
> +}
> +
> +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
> +   void *din, unsigned long flags)
> +{
> +   uint8_t *rx = din;
> +   const uint8_t *tx = dout;
> +   uint8_t curbyte, curbitlen, restbits;
> +   uint32_t bytes = bitlen / 8;
> +   uint32_t out;
> +   uint32_t in;
> +
> +   if (flags & SPI_XFER_BEGIN) {
> +   SPI_WRITE(AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
> +   SPI_WRITE(AR71XX_SPI_REG_IOC, AR71XX_SPI_IOC_CS_ALL);
> +   }
> +
> +   restbits = (bitlen % 8);
> +   if (restbits)
> +   bytes++;
> +
> +   /* enable chip select */
> +   out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
> +   while (bytes--) {
> +   curbyte = 0;
> +   if (tx)
> +   curbyte = *tx++;
> +
> +   if (restbits) {
> +   curbitlen = restbits;
> +   curbyte <<= 8 - restbits;
> +   } else {
> +   curbitlen = 8;
> +   }
> +
> +   /* clock starts at inactive polarity */
> +   for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
> +   if (curbyte & 0x80)
> +   out |= AR71XX_SPI_IOC_DO;
> +   else
> +   out &= ~(AR71XX_SPI_IOC_DO);
> +
> +   /* setup MSB (to slave) on trailing edge */
> +   SPI_WRITE(AR71XX_SPI_REG_IOC, out);
> +   SPI_WRITE(AR71XX_SPI_REG_IOC, out | 
> AR71XX_SPI_IOC_CLK);
> +
> +   curbyte <<= 1;
> +   }
> +
> +   in = SPI_READ(AR71XX_SPI_REG_RDS);
> +   if (rx) {
> +   if (restbits)
> +   *rx++ = (in << (8 - restbits));
> + 

Re: [U-Boot] [PATCH v2 2/8] mvebu: Fix for non-DM ehci-marvell support

[Stefan Roese]

Hi Phil,

On 22.12.2015 00:25, Phil Sutter wrote:

This mimics the relevant code in mach-kirkwood headers. The
*_winctrl_calcsize functions are identical, as well as the MVCPU_WIN_*
macros. Implementing shared headers/code between mvebu and kirkwood is
left for someone with a better knowledge of how u-boot is organized
internally.


Why do you need this functionality on your Armada XP board? It
should be able to use the DM enabled ehci-marvell driver.

Thanks,
Stefan

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Re: [U-Boot] [PATCH 1/1] common: nvedit: use snprintf instead of sprintf

[Fabio Estevam]

Hi Peng,

On Tue, Dec 22, 2015 at 7:14 AM, Peng Fan  wrote:
> From: Peng Fan 
>
> Use snprintf to replace sprintf.

You need to improve your commit log by saying why you are doing this change.
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Re: [U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[Chin Liang See]

On Tue, 2015-12-22 at 17:18 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
> 
> Signed-off-by: shengjiangwu 
> Cc: Chin Liang See 
> Cc: Dinh Nguyen 
> Cc: Dinh Nguyen 
> Cc: Pavel Machek 
> Cc: Marek Vasut 
> Cc: Stefan Roese 
> ---
>  board/altera/cyclone5-socdk/qts/pinmux_config.h |   12 ++--
>  board/altera/cyclone5-socdk/qts/pll_config.h|2 +-
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 


Acked-by: Chin Liang See 

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] mmc: update MMC_ERASE argument to match Linux kernel.

[Fabio Estevam]

Hi Tom and Pantelis,

On Wed, Dec 9, 2015 at 8:55 AM, Hector Palacios
 wrote:
> Hi Eric and Fabio,
>
> On 12/07/2015 03:50 PM, Eric Nelson wrote:
>> Table 41 of the JEDEC standard for eMMC says that bit 31 of
>> the command argument is obsolete when issuing the ERASE
>> command (CMD38) on page 115 of this document:
>>   http://www.jedec.org/sites/default/files/docs/jesd84-B45.pdf
>>
>> The SD Card Association Physical Layer Simplified Specification also
>> makes no mention of the use of bit 31.
>>   https://www.sdcard.org/downloads/pls/part1_410.pdf
>>
>> The Linux kernel distinguishes between secure (bit 31 set) and
>> non-secure erase, and this patch copies the macro names from
>> include/linux/mmc/core.h.
>>
>> Tested-by: Fabio Estevam 
>> Signed-off-by: Eric Nelson 
>> ---
>>  drivers/mmc/mmc_write.c | 2 +-
>>  include/mmc.h   | 7 ++-
>>  2 files changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
>> index 7aea7e9..221bf30 100644
>> --- a/drivers/mmc/mmc_write.c
>> +++ b/drivers/mmc/mmc_write.c
>> @@ -51,7 +51,7 @@ static ulong mmc_erase_t(struct mmc *mmc, ulong start, 
>> lbaint_t blkcnt)
>>   goto err_out;
>>
>>   cmd.cmdidx = MMC_CMD_ERASE;
>> - cmd.cmdarg = SECURE_ERASE;
>> + cmd.cmdarg = MMC_ERASE_ARG;
>>   cmd.resp_type = MMC_RSP_R1b;
>>
>>   err = mmc_send_cmd(mmc, , NULL);
>> diff --git a/include/mmc.h b/include/mmc.h
>> index cda9a19..b89962a 100644
>> --- a/include/mmc.h
>> +++ b/include/mmc.h
>> @@ -121,7 +121,12 @@
>>  #define OCR_VOLTAGE_MASK 0x007FFF80
>>  #define OCR_ACCESS_MODE  0x6000
>>
>> -#define SECURE_ERASE 0x8000
>> +#define MMC_ERASE_ARG0x
>> +#define MMC_SECURE_ERASE_ARG 0x8000
>> +#define MMC_TRIM_ARG 0x0001
>> +#define MMC_DISCARD_ARG  0x0003
>> +#define MMC_SECURE_TRIM1_ARG 0x8001
>> +#define MMC_SECURE_TRIM2_ARG 0x80008000
>>
>>  #define MMC_STATUS_MASK  (~0x0206BF7F)
>>  #define MMC_STATUS_SWITCH_ERROR  (1 << 7)
>>
>
> This fixes the issue on eMMC. Very good job! Thank you.
>
> Tested-by: Hector Palacios 

Could this one be applied to 2016.01?

Thanks
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[U-Boot] [RESEND PATCH 4/5] clk: add device tree support for clock framework

[Masahiro Yamada]

Add device tree binding support for the clock uclass.  This allows
clock consumers to get the peripheral ID based on the "clocks"
property in the device tree.

Usage:
Assume the following device tree:

  clk: myclock {
  compatible = "myclocktype";
  #clock-cells = <1>;
  };

  uart {
  compatible = "myuart";
  clocks = < 3>;
  };

  i2c {
  compatible = "myi2c";
  clocks = < 5>;
  };

The UART, I2C driver can get the peripheral ID 3, 5, respectively
by calling fdt_clk_get().  The clock provider should set its get_id
callback to clk_get_id_simple.  This should be enough for most cases
although more complicated DT-PeripheralID translation would be
possible by a specific get_id callback.

Signed-off-by: Masahiro Yamada 
---

 drivers/clk/Makefile  |  1 +
 drivers/clk/clk-fdt.c | 37 +
 include/clk.h | 20 
 3 files changed, 58 insertions(+)
 create mode 100644 drivers/clk/clk-fdt.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4a6a4a8..5fcdf39 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -6,6 +6,7 @@
 #
 
 obj-$(CONFIG_CLK) += clk-uclass.o
+obj-$(CONFIG_$(SPL_)OF_CONTROL) += clk-fdt.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
diff --git a/drivers/clk/clk-fdt.c b/drivers/clk/clk-fdt.c
new file mode 100644
index 000..fc53157
--- /dev/null
+++ b/drivers/clk/clk-fdt.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada 
+ *
+ * Device Tree support for clk uclass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+int fdt_clk_get(const void *fdt, int nodeoffset, int index,
+   struct udevice **dev)
+{
+   struct fdtdec_phandle_args clkspec;
+   struct udevice *clkdev;
+   int rc;
+
+   rc = fdtdec_parse_phandle_with_args(fdt, nodeoffset, "clocks",
+   "#clock-cells", 0, index, );
+   if (rc)
+   return rc;
+
+   rc = uclass_get_device_by_of_offset(UCLASS_CLK, clkspec.node, );
+   if (rc)
+   return rc;
+
+   rc = clk_get_id(clkdev, clkspec.args_count, clkspec.args);
+   if (rc < 0)
+   return rc;
+
+   if (dev)
+   *dev = clkdev;
+
+   return rc;
+}
diff --git a/include/clk.h b/include/clk.h
index 1efbaf2..518cb47 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -121,4 +121,24 @@ static inline int clk_get_id_simple(struct udevice *dev, 
int args_count,
return args_count > 0 ? args[0] : 0;
 }
 
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/**
+ * fdt_clk_get() - Get peripheral ID from device tree
+ *
+ * @fdt:   FDT blob
+ * @periph:Offset of clock consumer node
+ * @index: index of a phandle to parse out in "clocks" property
+ * @dev:   if not NULL, filled with pointer of clock provider
+ * @return peripheral ID, or -ve error code
+ */
+int fdt_clk_get(const void *fdt, int nodeoffset, int index,
+   struct udevice **dev);
+#else
+static inline int fdt_clk_get(const void *fdt, int nodeoffset, int index,
+ struct udevice **dev);
+{
+   return -ENOSYS;
+}
+#endif
+
 #endif /* _CLK_H_ */
-- 
1.9.1

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[U-Boot] [RESEND PATCH 2/5] clk: add needed include and declaration to include/clk.h

[Masahiro Yamada]

This header uses ulong, so it needs to include .
Likewise, "struct udevice" must be declared before it is used.

Signed-off-by: Masahiro Yamada 
---

 include/clk.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/clk.h b/include/clk.h
index f244301..371784a 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -8,6 +8,10 @@
 #ifndef _CLK_H_
 #define _CLK_H_
 
+#include 
+
+struct udevice;
+
 int soc_clk_dump(void);
 
 struct clk_ops {
-- 
1.9.1

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Re: [U-Boot] [PATCH v2 3/8] README: Review the u-boot porting guide list

[Stefan Roese]

On 22.12.2015 00:25, Phil Sutter wrote:

* There is no boards.cfg anymore, so drop (1).
* Creating flash.c and u-boot.lds seems not mandatory as well.
* Adjusting the enumerators for the above implicitly fixed for
   double items numbered (3).

Signed-off-by: Phil Sutter 
---
  README | 11 ---
  1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/README b/README
index 4fee706..dcc9478 100644
--- a/README
+++ b/README
@@ -5153,14 +5153,11 @@ If the system board that you have is not listed, then 
you will need
  to port U-Boot to your hardware platform. To do this, follow these
  steps:

-1.  Add a new configuration option for your board to the toplevel
-"boards.cfg" file, using the existing entries as examples.
-Follow the instructions there to keep the boards in order.
-2.  Create a new directory to hold your board specific code. Add any
+1.  Create a new directory to hold your board specific code. Add any
  files you need. In your board directory, you will need at least
-the "Makefile", a ".c", "flash.c" and "u-boot.lds".
-3.  Create a new configuration file "include/configs/.h" for
-your board
+the "Makefile" and a ".c".
+2.  Create a new configuration file "include/configs/.h" for
+your board.
  3.  If you're porting U-Boot to a new CPU, then also create a new
  directory to hold your CPU specific code. Add any files you need.
  4.  Run "make _defconfig" with your new name.



Seems this documentation is really outdated and needs some further
adjustments. But still, this is definitely the right direction, so:

Reviewed-by: Stefan Roese 

Thanks,
Stefan

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Re: [U-Boot] [PATCH v2 4/8] axp: Fix debugging support in DDR3 write leveling

[Stefan Roese]

On 22.12.2015 00:25, Phil Sutter wrote:

If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing.
In addition to that, get rid of debug output printing non-existent
counter variable.

Signed-off-by: Phil Sutter 
---
  drivers/ddr/marvell/axp/ddr3_write_leveling.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/ddr/marvell/axp/ddr3_write_leveling.c 
b/drivers/ddr/marvell/axp/ddr3_write_leveling.c
index df3a3df..da384f3 100644
--- a/drivers/ddr/marvell/axp/ddr3_write_leveling.c
+++ b/drivers/ddr/marvell/axp/ddr3_write_leveling.c
@@ -22,6 +22,8 @@
DEBUG_WL_FULL_S(s); DEBUG_WL_FULL_D(d, l); DEBUG_WL_FULL_S("\n")

  #ifdef MV_DEBUG_WL
+#define DEBUG_WL_S(s)  puts(s)
+#define DEBUG_WL_D(d, l)   printf("%x", d)
  #define DEBUG_RL_S(s) \
debug_cond(ddr3_get_log_level() >= MV_LOG_LEVEL_2, "%s", s)
  #define DEBUG_RL_D(d, l) \
@@ -1229,8 +1231,6 @@ static int ddr3_write_leveling_single_cs(u32 cs, u32 
freq, int ratio_2to1,
DEBUG_WL_FULL_D((u32) phase, 1);
DEBUG_WL_FULL_S(", Delay = ");
DEBUG_WL_FULL_D((u32) delay, 1);
-   DEBUG_WL_FULL_S(", Counter = ");
-   DEBUG_WL_FULL_D((u32) i, 1);
DEBUG_WL_FULL_S("\n");

/* Drive DQS high for one cycle - All data PUPs */



Reviewed-by: Stefan Roese 

Thanks,
Stefan

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Re: [U-Boot] [PATCH 2/2] arm: imx6: Enable DDR calibration on Novena

[Nikolay Dimitrov]

Hi Marek,

On 12/22/2015 03:26 AM, Marek Vasut wrote:

On Sunday, December 20, 2015 at 08:33:58 PM, Eric Nelson wrote:

Hi Marek,

On 12/16/2015 07:40 AM, Marek Vasut wrote:

Enable the DDR calibration functionality on Novena to deal with the
memory SoDIMM on this board.


Shouldn't this be in two patches?


Not really, the old values work without the enabled calibration. This
change needs to be done atomically.

[...]


  static void ccgr_init(void)

@@ -601,6 +601,11 @@ void board_init_f(ulong dummy)

mx6dq_dram_iocfg(64, _ddr_ioregs, _grp_ioregs);
mx6_dram_cfg(_ddr_info, _mmdc_calib, _4gib_1600);

+   /* Perform DDR DRAM calibration */
+   udelay(100);


Shouldn't the return values be tested?


I guess yes, but if the calibration fails, that what ? It's game over ;-)


Do you think it's possible/practical to reboot the system in this case?



I will just change those functions to void type and do hang() if we get errors.
I believe that's the most sane way to handle it and it prevents development of
boilerplate code.


+   mmdc_do_write_level_calibration();
+   mmdc_do_dqs_calibration();
+

/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);


Best regards,
Marek Vasut
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Regards,
Nikolay
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Re: [U-Boot] [PATCH v2 8/8] common: Implement Synology specific command set

[Stefan Roese]

On 22.12.2015 00:25, Phil Sutter wrote:

Synology keeps per item configuration in a dedicated 'partition' in SPI
flash, namely the one named 'vendor' in DTS file. It contains the two
NICs MAC addresses as well as the item's serial number. I didn't find a
way to have this information extracted automatically, therefore
implemented 'syno populate_env' command which extracts the three values
and puts them into environment. To make things permanent though, one has
to 'saveenv'.

Another command is 'syno clk_gate', which allows to change the clock
gating which is done in DS414 board file.

Signed-off-by: Phil Sutter 


All this is very board specific. So I suggest to move it into
the board directory instead.

Thanks,
Stefan

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Re: [U-Boot] [PATCH v2 1/8] drivers/pci: Fix for debug builds without CONFIG_PCI_ENUM_ONLY

[Stefan Roese]

(adding Simon and Bin to Cc)

On 22.12.2015 00:25, Phil Sutter wrote:

The debug printing references bar_res, which exists only if
CONFIG_PCI_ENUM_ONLY is not defined. Therefore move it into the ifdef'd
area.

Signed-off-by: Phil Sutter 
---
  drivers/pci/pci_auto_old.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
index 932eab8..8f17779 100644
--- a/drivers/pci/pci_auto_old.c
+++ b/drivers/pci/pci_auto_old.c
@@ -98,11 +98,11 @@ void pciauto_setup_device(struct pci_controller *hose,
bar_res = prefetch;
else
bar_res = mem;
-#endif

debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  (unsigned long long)bar_size);
+#endif
}

  #ifndef CONFIG_PCI_ENUM_ONLY



Reviewed-by: Stefan Roese 

Thanks,
Stefan

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Re: [U-Boot] [PATCH v2 7/8] mvebu: Support Synology DS414

[Stefan Roese]

Hi Phil,

I've consolidated a bit of the Armada XP / 38x defines and
Kconfig options just very recently. Please take a look at
these two patches from yesterday:

http://patchwork.ozlabs.org/patch/559579/
http://patchwork.ozlabs.org/patch/559580/

It would be great if you could base your DS414 support on
top of these as well (sorry, I missed adding you on CC for these
patches). It should fairly easy and make things clearer (e.g.
CONFIG_ARMADA_XP only defined on AXP devices).

I could also add a new git branch available, with the latest
versions of all the mvebu related patches applied. Just let
me know if this would help.

A few comments below...

On 22.12.2015 00:25, Phil Sutter wrote:

This adds support for the MV78230 based DS414 NAS by Synology. The
relevant bits have been extracted from the 'synogpl-5004-armadaxp'
package Synology kindly published, garnished with a fair amount of
trial-and-error.

Sadly, support is far from perfect. The major parts I have failed in
are SATA and XHCI support. Details about these and some other things
follow:

Device Tree
---

The device tree file armada-xp-synology-ds414.dts has been copied from
Linux and enhanced by recent U-Boot specific changes to
armada-xp-gp.dts.

SATA Support


There is a Marvell 88SX7042 controller attached to PCIe which is
supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv.
I'm not sure if extending the latter to support PCI devices is worth the
effort at all.


Yes, this is probably not worth the effort.


Porting sata_mv from Linux exceeded my brain's
capacities. :(


Heh. ;)


XHCI Support


There is an EtronTech EJ168A XHCI controller attached to PCIe which
drives the two rear USB3 ports. After a bit of playing around I managed
to get it recognized by xhci-pci, but never was able to access any
devices attached to it. Enabling it in ds414 board config shows that it
does not respond to commands for whatever reason. The (somewhat) bright
side to it is that it is not even supported in Synology's customized
U-Boot, but that also means nowhere to steal the relevant bits from.

EHCI Support


This seems functional after issuing 'usb start'. At least it detects USB
storage devices, and IIRC reading from them was OK. OTOH Linux fails to
register the controller if 'usb start' wasn't given before in U-Boot.

According to Synology sources, this board seems to support USB device
(gadget?) mode. Though I didn't play around with it.


This is something that should be fixed. Linux should be able to
use all devices without any bootloader interference. So it might
be, that some USB related configuration is missing here. Perhaps
in the USB PHY (setup setup_usb_phys in cpu.c).

Does this work in Linux when the original U-Boot is used?


PCIe Support


This is fine, but trying to gate the clocks of unused lanes will hang
PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI.


Right. Patches welcome. ;)


DDR3 Training
-

Marvell/Synology uses eight PUPs instead of four. Does not look like
this is meant to be customized in mainline U-Boot at all. OTOH I have
no idea what a "PUP" actually is.

PEX Init


Synology uses different values than mainline U-Boot with this patch:
pex_max_unit_get returns 2, pex_max_if_get returns 7 and
max_serdes_lines is set to 7. Not changing this seems to not have an
impact, although I'm not entirely sure it does not cause issues I am not
aware of.

Static Environment
--

This allows to boot stock Synology firmware at least. In order to be a
little more flexible when it comes to booting custom kernels, do not
only load zImage partition, but also rd.gz into memory. This way it is
possible to use about 7MB for kernel with piggyback initramfs.

Signed-off-by: Phil Sutter 
---
  arch/arm/Kconfig   |   1 +
  arch/arm/dts/Makefile  |   2 +
  arch/arm/dts/armada-xp-synology-ds414.dts  | 337 +
  arch/arm/mach-mvebu/Kconfig|   3 +
  arch/arm/mach-mvebu/serdes/axp/board_env_spec.h|   5 +-
  .../arm/mach-mvebu/serdes/axp/high_speed_env_lib.c |   3 +
  board/Synology/ds414/Kconfig   |  12 +
  board/Synology/ds414/Makefile  |   1 +
  board/Synology/ds414/ds414.c   | 173 +++
  board/Synology/ds414/kwbimage.cfg  |  12 +
  configs/ds414_defconfig|  18 ++
  include/configs/ds414.h| 164 ++
  12 files changed, 729 insertions(+), 2 deletions(-)
  create mode 100644 arch/arm/dts/armada-xp-synology-ds414.dts
  create mode 100644 board/Synology/ds414/Kconfig
  create mode 100644 board/Synology/ds414/Makefile
  create mode 100644 board/Synology/ds414/ds414.c
  create mode 100644 board/Synology/ds414/kwbimage.cfg
  create mode 100644 configs/ds414_defconfig
  

Re: [U-Boot] [PATCH v2 5/8] drivers/pci/pci_mvebu: Fix for boards with X4 lanes

[Stefan Roese]

On 22.12.2015 00:25, Phil Sutter wrote:
> Armada XP has support for X4 lanes, boards specify this in their
> serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration
> is stored in GEN_PURP_RES_2_REG.
> 
> When enumerating PEX, subsequent interfaces of an X4 lane must be
> skipped. Otherwise the enumeration hangs up the board.
> 
> The way this is implemented here is not exactly beautiful, but it mimics
> how Marvell's BSP does it. Alternatively we could get the information
> using board_serdes_cfg_get(), but that won't lead to clean code, either.
> Especially since the ugly includes will have to be done anyway.
> 
> Signed-off-by: Phil Sutter 
> ---
>   drivers/pci/pci_mvebu.c | 21 +
>   1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> index fd2744d..aab53f4 100644
> --- a/drivers/pci/pci_mvebu.c
> +++ b/drivers/pci/pci_mvebu.c
> @@ -18,6 +18,11 @@
>   #include 
>   #include 
>   
> +#if defined(CONFIG_ARMADA_XP)
> +#include "../ddr/marvell/axp/ddr3_init.h"
> +#include "../../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
> +#endif

Yes, this is ugly. And AFAICT, you only need it to include the 
GEN_PURP_RES_2_REG define from these headers.

I would prefer to add this macro either here (again), or in soc.h.
And use the name from the Marvell manual, so something like

#define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8))

> +
>   DECLARE_GLOBAL_DATA_PTR;
>   
>   /* PCIe unit register offsets */
> @@ -155,6 +160,16 @@ static void mvebu_get_port_lane(struct mvebu_pcie *pcie, 
> int pex_idx,
>   }
>   #endif
>   
> +#if defined(CONFIG_ARMADA_XP)
> +static int mvebu_pex_unit_is_x4(int pex_idx)
> +{
> + int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3;
> + u32 mask = (0x0f << (pex_unit * 8));
> +
> + return (reg_read(GEN_PURP_RES_2_REG) & mask) == mask;

readl() with the new define please.

> +}
> +#endif

Please drop the #ifdef here. This can go in unconditionally.

> +
>   static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
>   {
>   u32 val;
> @@ -419,5 +434,11 @@ void pci_init_board(void)
>   writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
>   
>   bus = hose->last_busno + 1;
> +
> +#if defined(CONFIG_ARMADA_XP)
> + /* need to skip more for X4 links, otherwise scan will hang */
> + if (mvebu_pex_unit_is_x4(i))
> + i += 3;
> +#endif

And please use this version here:

/* need to skip more for X4 links, otherwise scan will hang */
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
if (mvebu_pex_unit_is_x4(i))
i += 3;
}

Thanks,
Stefan

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[U-Boot] [PATCH 2/3] imx: nand: update GPMI NAND driver to support MX7

[Peng Fan]

From: Peng Fan 

Update GPMI NAND driver and BCH head file to support i.MX7

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 arch/arm/include/asm/imx-common/regs-bch.h | 4 ++--
 drivers/mtd/nand/mxs_nand.c| 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/imx-common/regs-bch.h 
b/arch/arm/include/asm/imx-common/regs-bch.h
index 5c47783..adfbace 100644
--- a/arch/arm/include/asm/imx-common/regs-bch.h
+++ b/arch/arm/include/asm/imx-common/regs-bch.h
@@ -123,7 +123,7 @@ struct mxs_bch_regs {
 #defineBCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
 #defineBCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
 #defineBCH_FLASHLAYOUT0_META_SIZE_OFFSET   16
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
 #defineBCH_FLASHLAYOUT0_ECC0_MASK  (0x1f << 11)
 #defineBCH_FLASHLAYOUT0_ECC0_OFFSET11
 #else
@@ -154,7 +154,7 @@ struct mxs_bch_regs {
 
 #defineBCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0x << 16)
 #defineBCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET   16
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
 #defineBCH_FLASHLAYOUT1_ECCN_MASK  (0x1f << 11)
 #defineBCH_FLASHLAYOUT1_ECCN_OFFSET11
 #else
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index f15cf36..ba019a0 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -30,7 +30,7 @@
 #defineMXS_NAND_DMA_DESCRIPTOR_COUNT   4
 
 #defineMXS_NAND_CHUNK_DATA_CHUNK_SIZE  512
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
 #defineMXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT2
 #else
 #defineMXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT0
@@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t 
page_data_size,
int max_ecc_strength_supported;
 
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
-   if (is_cpu_type(MXC_CPU_MX6SX))
+   if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
-- 
2.6.2

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[U-Boot] [PATCH] imx: mx6sxsabresd: support emmc

[Peng Fan]

From: Peng Fan 

For i.MX6SX SABRESD, USDHC4 can be used for SD and EMMC, default
it is used for SD.

This patch introduces EMMC pinmux settings and a new macro
CONFIG_MX6SXSABRESD_EMMC_REWORK. If the board has been reworked
to support emmc, need to enable this macro.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 32 +
 1 file changed, 32 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 78f0151..6168b26 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -109,6 +109,20 @@ static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const usdhc4_emmc_pads[] = {
+   MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+   MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -302,7 +316,11 @@ int board_early_init_f(void)
 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR},
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+   {USDHC4_BASE_ADDR, 0, 8},
+#else
{USDHC4_BASE_ADDR},
+#endif
 };
 
 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
@@ -327,7 +345,11 @@ int board_mmc_getcd(struct mmc *mmc)
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+   ret = 1;
+#else
ret = !gpio_get_value(USDHC4_CD_GPIO);
+#endif
break;
}
 
@@ -361,9 +383,14 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads));
+#else
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
+#endif
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
@@ -410,9 +437,14 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
break;
case 3:
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads));
+#else
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
+#endif
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
break;
-- 
2.6.2

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[U-Boot] [PATCH 3/3] imx: mx7dsabresd: support nand

[Peng Fan]

From: Peng Fan 

Add pinmux settings.
Add related macro definitions.
Nand pin conflicts with emmc, so if want to enable nand, need to do
hardware rework. After hardware rework, define CONFIG_NAND_MXS in
board header file.

Signed-off-by: Peng Fan 
Cc: Stefano Babic 
---
 board/freescale/mx7dsabresd/mx7dsabresd.c | 39 +++
 include/configs/mx7dsabresd.h | 25 
 2 files changed, 64 insertions(+)

diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c 
b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 12327c2..3d520d6 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -47,6 +47,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_PAD_CTRL  \
(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
 
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -196,6 +199,38 @@ static void iox74lv_init(void)
gpio_direction_output(IOX_STCP, 1);
 };
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const gpmi_pads[] = {
+   MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_CLK__NAND_CLE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_CMD__NAND_ALE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SAI1_MCLK__NAND_WP_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
+   MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | 
MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+   imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+   /* NAND_USDHC_BUS_CLK is set in rom */
+   set_clk_nand();
+}
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
@@ -493,6 +528,10 @@ int board_init(void)
setup_fec();
 #endif
 
+#ifdef CONFIG_NAND_MXS
+   setup_gpmi_nand();
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
setup_lcd();
 #endif
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 22e515c..d23e4f3 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -179,8 +179,33 @@
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_SIZESZ_8K
 #define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * If want to use nand, define CONFIG_NAND_MXS and rework board
+ * to support nand, since emmc has pin conflicts with nand
+ */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE   0x4000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
 #define CONFIG_ENV_OFFSET  (8 * SZ_64K)
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM   1
+#else
 #define CONFIG_SYS_FSL_USDHC_NUM   2
+#endif
 
 #define CONFIG_SYS_MMC_ENV_DEV 0   /* USDHC1 */
 #define CONFIG_SYS_MMC_ENV_PART0   /* user area */
-- 
2.6.2

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