Re: [U-Boot] [PATCH 0/9] EFI payload / application support

[Tom Rini]

On Tue, Dec 22, 2015 at 02:57:47PM +0100, Alexander Graf wrote:

> This is my Christmas present for my openSUSE friends :).
> 
> U-Boot is a great project for embedded devices. However, convincing
> everyone involved that only for "a few oddball ARM devices" we need to
> support different configuration formats from grub2 when all other platforms
> (PPC, System Z, x86) are standardized on a single format is a nightmare.
> 
> So we started to explore alternatives. At first, people tried to get
> grub2 running using the u-boot api interface. However, FWIW that one
> doesn't support relocations, so you need to know where to link grub2 to
> at compile time. It also seems to be broken more often than not. And on
> top of it all, it's a one-off interface, so yet another thing to maintain.
> 
> That led to a nifty idea. What if we can just implement the EFI application
> protocol on top of U-Boot? Then we could compile a single grub2 binary for
> uEFI based systems and U-Boot based systems and as soon as that one's loaded,
> everything looks and feels (almost) the same.
> 
> This patch set is the result of pursuing this endeavor.

So, I owe the whole codebase a real review.  My very quick question
however is, aside from what you had to borrow from wine, can you license
everything else as GPL v2 or later rather than LGPL?

-- 
Tom


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Re: [U-Boot] [PATCH v3 2/4] mips: ath79: add serial driver for ar933x SOC

[Thomas Chou]

On 2015年12月25日 14:05, Wills Wang wrote:



On 12/25/2015 10:39 AM, Thomas Chou wrote:

Hi Wills,

Is there any reason that you need to support pre-DM serial driver? It
should be safe to support DM only. You may add debug_uart support
which might be helpful during debug. The ops for DM serial is
different to pre-DM though the name look similar. Please see the
comments below.


I will remove the code about pre-DM serial driver.

I worked on mips before I moved to nios very long ago (20 yr). And
nios2 mostly followed mips.

I understand there is not device tree control for u-boot on mips yet.
But I added it to nios2 recently. It might be worthy if you could add
it to mips. You may find the dts binding on Linux kernel. And please
add dts binding to doc/ and you might copy them from Linux kernel.


I has taken a long time to add base device tree for this patch, but i
can't get the driver serial number if don't specify explicitly "aliases"
section in dts file. but It seems to not need for ARM device.

+


You will need to add "stdout-path=..." property with your serial path to 
the chosen

node, like this,
chosen {
stdout-path = 
};



+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 


Please sort the sequence of header files inclusion.


+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+u32 baudrate;
+u32 scale;
+u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+{600,   255,503},
+{1200,  249,983},
+{2400,  167,1321},
+{4800,  87, 1384},
+{9600,  45, 1447},
+{14400, 53, 2548},
+{19200, 22, 1447},
+{28800, 26, 2548},
+{38400, 28, 3649},
+{56000, 7,  1468},
+{57600, 34, 6606},
+{115200,28, 10947},
+{128000,6,  2936},
+{153600,18, 9563},
+{230400,16, 12834},
+{25,4,  4096},
+{256000,6,  5872},
+{460800,7,  12079},
+{576000,4,  9437},
+{921600,3,  12079},
+{100,   2,  9830},
+{1152000,   2,  11324},
+{150,   0,  4915},
+{200,   0,  6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+{600,   255,805},
+{1200,  209,1321},
+{2400,  104,1321},
+{4800,  54, 1384},
+{9600,  78, 3976},
+{14400, 98, 7474},
+{19200, 55, 5637},
+{28800, 77, 11777},
+{38400, 36, 7449},
+{56000, 4,  1468},
+{57600, 35, 10871},
+{115200,20, 12683},
+{128000,11, 8053},
+{153600,9,  8053},
+{230400,9,  12079},
+{25,6,  9175},
+{256000,5,  8053},
+{460800,4,  12079},
+{576000,3,  12079},
+{921600,1,  9663},
+{100,   1,  10485},
+{1152000,   1,  12079},
+{150,   0,  7864},
+{200,   0,  10485},
+};


The requirement of u-boot is much simpler than Linux kernel. For the
uart header, you should include only the macros that the driver really
used. Or you can add it to the driver directly without the additional
header file. The same rule applies to the baudrate tables. You need
only some practical rates, not every possible one.


+
+static inline u32 ar933x_read(u32 base, u32 offset)
+{
+return readl(KSEG1ADDR(base + offset));
+}
+
+static inline void ar933x_write(u32 base, u32 offset, u32 val)
+{
+writel(val, KSEG1ADDR(base + offset));
+}
+


For the KSEG1ADDR mapping, which Marek also mentioned, I would suggest
rework map_physmem() in asm/io.h on mips to map K1 kernel space, which
is very similar to ioremap() on Linux kernel. So that you don't need
to map it for every IO.

plat->regs = map_physmem(dev_get_addr(dev),
sizeof(...),
MAP_NOCACHE);


In MIPS,  function "map_physmem" is empty.


Yes. But you may improve it to do the real work. For example, not tested,

#define MAP_NOCACHE 1
#define MAP_WRCOMBINE   0
#define MAP_WRBACK  0
#define MAP_WRTHROUGH   0

static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
if (flags)
return (void *)KSEG1ADDR(paddr);
else
return (void *)KSEG0ADDR(paddr);
}



+static int ar933x_serial_init(void)
+{
+u32 val;
+
+/*
+ * Set GPIO10 (UART_SO) as output and enable UART,
+ * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+ */
+val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
+val |= BIT(10);
+ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);
+
+val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
+val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+

Re: [U-Boot] [PATCH v2 02/19] dm: timer: uclass: add timer init to add timer device

[Bin Meng]

Hi Mugunthan,

On Thu, Dec 24, 2015 at 6:38 PM, Mugunthan V N  wrote:
> Adding timer_init function to create and initialize the timer
> device on platforms where u-boot,dm-pre-reloc is not used. Since
> there will be multiple timer devices in the system, adding a
> tick-timer node in chosen node to know which timer device to be
> used as tick timer in u-boot.
>
> Signed-off-by: Mugunthan V N 
> ---
>  doc/device-tree-bindings/chosen.txt | 43 
> +
>  drivers/timer/timer-uclass.c| 42 
>  lib/time.c  | 13 ++-
>  3 files changed, 87 insertions(+), 11 deletions(-)
>  create mode 100644 doc/device-tree-bindings/chosen.txt
>
> diff --git a/doc/device-tree-bindings/chosen.txt 
> b/doc/device-tree-bindings/chosen.txt
> new file mode 100644
> index 000..bf9a30a
> --- /dev/null
> +++ b/doc/device-tree-bindings/chosen.txt
> @@ -0,0 +1,43 @@
> +The chosen node
> +---
> +The chosen node does not represent a real device, but serves as a place
> +for passing data like which serial device to used to print the logs etc
> +
> +
> +stdout-path property
> +
> +Device trees may specify the device to be used for boot console output
> +with a stdout-path property under /chosen.
> +
> +Example
> +---
> +/ {
> +   chosen {
> +   stdout-path = "/serial@f00:115200";
> +   };
> +
> +   serial@f00 {
> +   compatible = "vendor,some-uart";
> +   reg = <0xf00 0x10>;
> +   };
> +};
> +
> +tick-timer property
> +---
> +In a system there are multiple timers, specify which timer to be used
> +as the tick-timer. Earlier it was hardcoded in the timer driver now
> +since device tree has all the timer nodes. Specify which timer to be
> +used as tick timer.
> +
> +Example
> +---
> +/ {
> +   chosen {
> +   tick-timer = "/timer2@f00";
> +   };
> +
> +   timer2@f00 {
> +   compatible = "vendor,some-timer";
> +   reg = <0xf00 0x10>;
> +   };
> +};
> diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
> index aca421b..db43611 100644
> --- a/drivers/timer/timer-uclass.c
> +++ b/drivers/timer/timer-uclass.c
> @@ -6,6 +6,8 @@
>
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
>  #include 
>
> @@ -56,6 +58,46 @@ u64 timer_conv_64(u32 count)
> return ((u64)gd->timebase_h << 32) | gd->timebase_l;
>  }
>
> +int timer_init(void)
> +{
> +   const void *blob = gd->fdt_blob;
> +   struct udevice *dev;
> +   int node;
> +   int ret;
> +
> +   /* Check for a chosen timer to be used for tick */
> +   node = fdtdec_get_chosen_node(blob, "tick-timer");
> +   if (node < 0)
> +   return -ENODEV;

This changes now require every device tree provide a "tick-timer"
under /chosen, which break all the existing dm timer enabled boards,
and is not necessary.

We should do:

if (node < 0) {
ret = uclass_first_device(UCLASS_TIMER, );
if (ret)
return ret;
if (!dev)
return -ENODEV;
gd->timer = dev;
} else {

}

> +
> +   if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, )) {
> +   /*
> +* If the timer is not marked to be bound before
> +* relocation, bind it anyway.
> +*/
> +   if (node > 0 &&
> +   !lists_bind_fdt(gd->dm_root, blob, node, )) {
> +   int ret = device_probe(dev);
> +   if (ret)
> +   return ret;
> +   }
> +   }
> +
> +   if (dev) {
> +   gd->timer = dev;
> +   return 0;
> +   }
> +
> +   ret = uclass_first_device(UCLASS_TIMER, );
> +   if (ret)
> +   return ret;
> +   if (!dev)
> +   return -ENODEV;
> +
> +   gd->timer = dev;
> +   return 0;
> +}
> +
>  UCLASS_DRIVER(timer) = {
> .id = UCLASS_TIMER,
> .name   = "timer",
> diff --git a/lib/time.c b/lib/time.c
> index f37a662..d4060f1 100644
> --- a/lib/time.c
> +++ b/lib/time.c
> @@ -43,17 +43,8 @@ extern unsigned long __weak timer_read_counter(void);
>  #ifdef CONFIG_TIMER
>  static int notrace dm_timer_init(void)
>  {
> -   struct udevice *dev;
> -   int ret;
> -
> -   if (!gd->timer) {
> -   ret = uclass_first_device(UCLASS_TIMER, );
> -   if (ret)
> -   return ret;
> -   if (!dev)
> -   return -ENODEV;
> -   gd->timer = dev;
> -   }
> +   if (!gd->timer)
> +   return timer_init();

Looks timer_init() is only called in timer-uclass.c, should we declare
it as static? Otherwise timer_init() will be called in either
board_f.c or board_r.c 

Re: [U-Boot] [PATCH 4/5] altera_qspi: show erase progress

[Marek Vasut]

On Friday, December 25, 2015 at 01:12:28 AM, Thomas Chou wrote:
> Hi Marek,
> 
> On 2015年12月24日 13:37, Marek Vasut wrote:
> > On Thursday, December 24, 2015 at 06:24:45 AM, Thomas Chou wrote:
> >> Hi Marek,
> >> 
> >> On 2015年12月24日 11:42, Marek Vasut wrote:
> >>> On Thursday, December 24, 2015 at 04:26:57 AM, Thomas Chou wrote:
>  Hi Marek,
> >>> 
> >>> Hi Thomas,
> >>> 
>  On 2015年12月24日 11:02, Marek Vasut wrote:
> > On Thursday, December 24, 2015 at 03:50:57 AM, Thomas Chou wrote:
> >> Hi Marek,
> >> 
> >> On 2015年12月24日 09:29, Marek Vasut wrote:
> >>> On Thursday, December 24, 2015 at 01:51:23 AM, Thomas Chou wrote:
>  Show sector erase progress with dot and comma.
>  
>  Signed-off-by: Thomas Chou 
>  ---
> >>> 
> >>> Shouldn't this go into common code ?
> >> 
> >> The code to print a dot is minimal. It will cost more if this go
> >> into common code.
> > 
> > But then this driver behaves in a non-standard manner AND noone
> > benefits from this functionality but this driver.
>  
>  The sector erase might take very long when there are a lot of sectors
>  to erase, say 12 min to 50 min for 1024 sectors on the 10m50 board.
>  Without the display of progress, it will look like the board hangs.
> >>> 
> >>> Yeah, that I do understand and I agree this is a good idea :)
> >>> 
>  The dotting code comes from the old cfi_flash.c. Some other parallel
>  flash have this, but not spi-flash. It is trivial to add though.
> >>> 
> >>> Urm, altera_qspi is CFI, right ? So can we stuff this into common code
> >>> or not? Sorry if I am confused and off the mark.
> >> 
> >> No worries. I think the dotting is best done per driver.
> > 
> > Well why do you think so ?
> 
> Well, it is only a putc() which is plain and simple.

Sure, but then I still don't understand why this cannot be in the common code.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 4/5] altera_qspi: show erase progress

[Thomas Chou]

Hi Marek,

On 2015年12月24日 13:37, Marek Vasut wrote:

On Thursday, December 24, 2015 at 06:24:45 AM, Thomas Chou wrote:

Hi Marek,

On 2015年12月24日 11:42, Marek Vasut wrote:

On Thursday, December 24, 2015 at 04:26:57 AM, Thomas Chou wrote:

Hi Marek,


Hi Thomas,


On 2015年12月24日 11:02, Marek Vasut wrote:

On Thursday, December 24, 2015 at 03:50:57 AM, Thomas Chou wrote:

Hi Marek,

On 2015年12月24日 09:29, Marek Vasut wrote:

On Thursday, December 24, 2015 at 01:51:23 AM, Thomas Chou wrote:

Show sector erase progress with dot and comma.

Signed-off-by: Thomas Chou 
---


Shouldn't this go into common code ?


The code to print a dot is minimal. It will cost more if this go into
common code.


But then this driver behaves in a non-standard manner AND noone
benefits from this functionality but this driver.


The sector erase might take very long when there are a lot of sectors to
erase, say 12 min to 50 min for 1024 sectors on the 10m50 board. Without
the display of progress, it will look like the board hangs.


Yeah, that I do understand and I agree this is a good idea :)


The dotting code comes from the old cfi_flash.c. Some other parallel
flash have this, but not spi-flash. It is trivial to add though.


Urm, altera_qspi is CFI, right ? So can we stuff this into common code or
not? Sorry if I am confused and off the mark.


No worries. I think the dotting is best done per driver.


Well why do you think so ?


Well, it is only a putc() which is plain and simple.

Best regards,
Thomas
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Re: [U-Boot] [PATCH v3 2/4] mips: ath79: add serial driver for ar933x SOC

[Thomas Chou]

Hi Wills,

Is there any reason that you need to support pre-DM serial driver? It 
should be safe to support DM only. You may add debug_uart support which 
might be helpful during debug. The ops for DM serial is different to 
pre-DM though the name look similar. Please see the comments below.


I worked on mips before I moved to nios very long ago (20 yr). And nios2 
mostly followed mips.


I understand there is not device tree control for u-boot on mips yet. 
But I added it to nios2 recently. It might be worthy if you could add it 
to mips. You may find the dts binding on Linux kernel. And please add 
dts binding to doc/ and you might copy them from Linux kernel.



+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 


Please sort the sequence of header files inclusion.


+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+   u32 baudrate;
+   u32 scale;
+   u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+   {600,   255,503},
+   {1200,  249,983},
+   {2400,  167,1321},
+   {4800,  87, 1384},
+   {9600,  45, 1447},
+   {14400, 53, 2548},
+   {19200, 22, 1447},
+   {28800, 26, 2548},
+   {38400, 28, 3649},
+   {56000, 7,  1468},
+   {57600, 34, 6606},
+   {115200,28, 10947},
+   {128000,6,  2936},
+   {153600,18, 9563},
+   {230400,16, 12834},
+   {25,4,  4096},
+   {256000,6,  5872},
+   {460800,7,  12079},
+   {576000,4,  9437},
+   {921600,3,  12079},
+   {100,   2,  9830},
+   {1152000,   2,  11324},
+   {150,   0,  4915},
+   {200,   0,  6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+   {600,   255,805},
+   {1200,  209,1321},
+   {2400,  104,1321},
+   {4800,  54, 1384},
+   {9600,  78, 3976},
+   {14400, 98, 7474},
+   {19200, 55, 5637},
+   {28800, 77, 11777},
+   {38400, 36, 7449},
+   {56000, 4,  1468},
+   {57600, 35, 10871},
+   {115200,20, 12683},
+   {128000,11, 8053},
+   {153600,9,  8053},
+   {230400,9,  12079},
+   {25,6,  9175},
+   {256000,5,  8053},
+   {460800,4,  12079},
+   {576000,3,  12079},
+   {921600,1,  9663},
+   {100,   1,  10485},
+   {1152000,   1,  12079},
+   {150,   0,  7864},
+   {200,   0,  10485},
+};


The requirement of u-boot is much simpler than Linux kernel. For the 
uart header, you should include only the macros that the driver really 
used. Or you can add it to the driver directly without the additional 
header file. The same rule applies to the baudrate tables. You need only 
some practical rates, not every possible one.



+
+static inline u32 ar933x_read(u32 base, u32 offset)
+{
+   return readl(KSEG1ADDR(base + offset));
+}
+
+static inline void ar933x_write(u32 base, u32 offset, u32 val)
+{
+   writel(val, KSEG1ADDR(base + offset));
+}
+


For the KSEG1ADDR mapping, which Marek also mentioned, I would suggest 
rework map_physmem() in asm/io.h on mips to map K1 kernel space, which 
is very similar to ioremap() on Linux kernel. So that you don't need to 
map it for every IO.


plat->regs = map_physmem(dev_get_addr(dev),
sizeof(...),
MAP_NOCACHE);


+static int ar933x_serial_init(void)
+{
+   u32 val;
+
+   /*
+* Set GPIO10 (UART_SO) as output and enable UART,
+* BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+*/
+   val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
+   val |= BIT(10);
+   ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);
+
+   val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
+   val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+   ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val);


These might go to the pinctrl driver or board initialization.


+
+   /*
+* UART controller configuration:
+* - no DMA
+* - no interrupt
+* - DCE mode
+* - no flow control
+* - set RX ready oride
+* - set TX ready oride
+*/
+   val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
+   | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
+   ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val);
+   return 0;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+#else
+static void ar933x_serial_setbrg(void)
+{
+   int baudrate = 

Re: [U-Boot] [PATCH v3 2/4] mips: ath79: add serial driver for ar933x SOC

[Wills Wang]

On 12/25/2015 10:39 AM, Thomas Chou wrote:

Hi Wills,

Is there any reason that you need to support pre-DM serial driver? It 
should be safe to support DM only. You may add debug_uart support 
which might be helpful during debug. The ops for DM serial is 
different to pre-DM though the name look similar. Please see the 
comments below.



I will remove the code about pre-DM serial driver.
I worked on mips before I moved to nios very long ago (20 yr). And 
nios2 mostly followed mips.


I understand there is not device tree control for u-boot on mips yet. 
But I added it to nios2 recently. It might be worthy if you could add 
it to mips. You may find the dts binding on Linux kernel. And please 
add dts binding to doc/ and you might copy them from Linux kernel.


I has taken a long time to add base device tree for this patch, but i 
can't get the driver serial number if don't specify explicitly "aliases" 
section in dts file. but It seems to not need for ARM device.

+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 


Please sort the sequence of header files inclusion.


+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+u32 baudrate;
+u32 scale;
+u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+{600,   255,503},
+{1200,  249,983},
+{2400,  167,1321},
+{4800,  87, 1384},
+{9600,  45, 1447},
+{14400, 53, 2548},
+{19200, 22, 1447},
+{28800, 26, 2548},
+{38400, 28, 3649},
+{56000, 7,  1468},
+{57600, 34, 6606},
+{115200,28, 10947},
+{128000,6,  2936},
+{153600,18, 9563},
+{230400,16, 12834},
+{25,4,  4096},
+{256000,6,  5872},
+{460800,7,  12079},
+{576000,4,  9437},
+{921600,3,  12079},
+{100,   2,  9830},
+{1152000,   2,  11324},
+{150,   0,  4915},
+{200,   0,  6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+{600,   255,805},
+{1200,  209,1321},
+{2400,  104,1321},
+{4800,  54, 1384},
+{9600,  78, 3976},
+{14400, 98, 7474},
+{19200, 55, 5637},
+{28800, 77, 11777},
+{38400, 36, 7449},
+{56000, 4,  1468},
+{57600, 35, 10871},
+{115200,20, 12683},
+{128000,11, 8053},
+{153600,9,  8053},
+{230400,9,  12079},
+{25,6,  9175},
+{256000,5,  8053},
+{460800,4,  12079},
+{576000,3,  12079},
+{921600,1,  9663},
+{100,   1,  10485},
+{1152000,   1,  12079},
+{150,   0,  7864},
+{200,   0,  10485},
+};


The requirement of u-boot is much simpler than Linux kernel. For the 
uart header, you should include only the macros that the driver really 
used. Or you can add it to the driver directly without the additional 
header file. The same rule applies to the baudrate tables. You need 
only some practical rates, not every possible one.



+
+static inline u32 ar933x_read(u32 base, u32 offset)
+{
+return readl(KSEG1ADDR(base + offset));
+}
+
+static inline void ar933x_write(u32 base, u32 offset, u32 val)
+{
+writel(val, KSEG1ADDR(base + offset));
+}
+


For the KSEG1ADDR mapping, which Marek also mentioned, I would suggest 
rework map_physmem() in asm/io.h on mips to map K1 kernel space, which 
is very similar to ioremap() on Linux kernel. So that you don't need 
to map it for every IO.


plat->regs = map_physmem(dev_get_addr(dev),
sizeof(...),
MAP_NOCACHE);


In MIPS,  function "map_physmem" is empty.

+static int ar933x_serial_init(void)
+{
+u32 val;
+
+/*
+ * Set GPIO10 (UART_SO) as output and enable UART,
+ * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+ */
+val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
+val |= BIT(10);
+ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);
+
+val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
+val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val);


These might go to the pinctrl driver or board initialization.


+
+/*
+ * UART controller configuration:
+ * - no DMA
+ * - no interrupt
+ * - DCE mode
+ * - no flow control
+ * - set RX ready oride
+ * - set TX ready oride
+ */
+val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
+| (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
+ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val);
+return 0;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int 

Re: [U-Boot] [PATCH v2 02/19] dm: timer: uclass: add timer init to add timer device

[Mugunthan V N]

On Friday 25 December 2015 07:40 AM, Bin Meng wrote:
>> +   /* Check for a chosen timer to be used for tick */
>> > +   node = fdtdec_get_chosen_node(blob, "tick-timer");
>> > +   if (node < 0)
>> > +   return -ENODEV;
> This changes now require every device tree provide a "tick-timer"
> under /chosen, which break all the existing dm timer enabled boards,
> and is not necessary.
> 
> We should do:
> 
> if (node < 0) {
> ret = uclass_first_device(UCLASS_TIMER, );
> if (ret)
> return ret;
> if (!dev)
> return -ENODEV;
> gd->timer = dev;
> } else {
> 
> }
> 

Oops!, will fix it in next version.

Regards
Mugunthan V N
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[U-Boot] [Patch V2 2/3] armv8/ls1043aqds: add QSPI support in SD boot

[Gong Qianyu]

From: Gong Qianyu 

QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot. If
QSPI is enabled, IFC should be disabled in kernel as well.

Signed-off-by: Gong Qianyu 
---
V2:
 - Modified rcw file to change core frequency to 1600MHz for SD_BOOT_QSPI.

 arch/arm/cpu/armv8/fsl-layerscape/fdt.c|  5 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c|  3 +++
 arch/arm/dts/fsl-ls1043a-qds.dts   | 14 +
 arch/arm/dts/fsl-ls1043a.dtsi  | 11 +++
 board/freescale/ls1043aqds/MAINTAINERS |  1 +
 .../ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg  |  8 
 configs/ls1043aqds_sdcard_qspi_defconfig   | 10 ++
 include/configs/ls1043a_common.h   | 13 
 include/configs/ls1043aqds.h   | 23 ++
 9 files changed, 88 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index eafdd71..a247510 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -201,4 +201,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_LSCH3
fdt_fixup_smmu(blob);
 #endif
+
+#ifdef CONFIG_FSL_QSPI
+   do_fixup_by_compat(blob, "fsl,ifc",
+  "status", "disabled", 8 + 1, 1);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..4b1f792 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -219,6 +219,9 @@ void fsl_lsch2_early_init_f(void)
init_early_memctl_regs();   /* tighten IFC timing */
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+   out_be32(>qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
/* Make SEC reads and writes snoopable */
setbits_be32(>snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
 SCFG_SNPCNFGCR_SECWRSNP);
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts
index 93d73a6..9916f1b 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ b/arch/arm/dts/fsl-ls1043a-qds.dts
@@ -16,6 +16,7 @@
 / {
model = "LS1043A QDS Board";
aliases {
+   spi0 = 
spi1 = 
};
 };
@@ -49,6 +50,19 @@
};
 };
 
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   qflash0: s25fl128s@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <2000>;
+   reg = <0>;
+   };
+};
+
  {
status = "okay";
pca9547@77 {
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 85ea81e..f83cc3e 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -182,5 +182,16 @@
interrupts = <0 55 0x4>;
clocks = < 4 0>;
};
+
+   qspi: quadspi@155 {
+   compatible = "fsl,vf610-qspi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x155 0x1>,
+   <0x4000 0x400>;
+   num-cs = <2>;
+   big-endian;
+   status = "disabled";
+   };
};
 };
diff --git a/board/freescale/ls1043aqds/MAINTAINERS 
b/board/freescale/ls1043aqds/MAINTAINERS
index 0c7f648..868bb72 100644
--- a/board/freescale/ls1043aqds/MAINTAINERS
+++ b/board/freescale/ls1043aqds/MAINTAINERS
@@ -7,3 +7,4 @@ F:  configs/ls1043aqds_defconfig
 F: configs/ls1043aqds_nor_ddr3_defconfig
 F: configs/ls1043aqds_nand_defconfig
 F: configs/ls1043aqds_sdcard_ifc_defconfig
+F: configs/ls1043aqds_sdcard_qspi_defconfig
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 
b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
new file mode 100644
index 000..7783521
--- /dev/null
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable QSPI; disable IFC
+08100010 0a00  
+14550002 80004012 6004 c1002000
+   00038800
+20124000 1100 0096 0001
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig 
b/configs/ls1043aqds_sdcard_qspi_defconfig
new file mode 100644
index 000..37e8b3c
--- /dev/null
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_SYS_NS16550=y
+CONFIG_OF_CONTROL=y

[U-Boot] [Patch V2 0/3] LS1043AQDS related patches

[Gong Qianyu]

Hi all,

The version 2 patchset has:

 - Fixed some format issues according to the comments.
 - Changed the core frequency to 1600M for SD boot with QSPI support.

Also note that to apply the patchset and work well on LS1043AQDS board, it
depends on the QSPI driver bug fixing and QIXIS patchsets that I have 
already
sent out and are still under review.


[Patch V2 1/3] armv8/ls1043aqds: add DSPI support
[Patch V2 2/3] armv8/ls1043aqds: add QSPI support in SD boot
[Patch V2 3/3] armv8/ls1043aqds: add QSPI boot support




Regards,
Qianyu
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[U-Boot] [Patch V2 1/3] armv8/ls1043aqds: add DSPI support

[Gong Qianyu]

From: Gong Qianyu 

Enable three DSPI flash memories on board.

Commands:
=> sf probe 1:0
SF: Detected N25Q128A with page size 256 Bytes,
erase size 64 KiB, total 16 MiB
=> sf probe 1:1
SF: Detected SST25WF040B with page size 256 Bytes,
erase size 4 KiB, total 512 KiB
=> sf probe 1:2
SF: Detected EN25S64 with page size 256 Bytes,
erase size 64 KiB, total 8 MiB

Signed-off-by: Gong Qianyu 
---
V2:
 - Remove blank line and add necessary blank lines.

 arch/arm/dts/fsl-ls1043a-qds.dts| 32 
 configs/ls1043aqds_defconfig|  3 +++
 configs/ls1043aqds_nand_defconfig   |  5 +
 configs/ls1043aqds_sdcard_ifc_defconfig |  5 +
 include/configs/ls1043a_common.h| 12 
 include/configs/ls1043ardb.h| 10 --
 6 files changed, 57 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-qds.dts
index 7435222..93d73a6 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dts
+++ b/arch/arm/dts/fsl-ls1043a-qds.dts
@@ -15,6 +15,38 @@
 
 / {
model = "LS1043A QDS Board";
+   aliases {
+   spi1 = 
+   };
+};
+
+ {
+   bus-num = <0>;
+   status = "okay";
+
+   dflash0: n25q128a {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   reg = <0>;
+   spi-max-frequency = <100>; /* input clock */
+   };
+
+   dflash1: sst25wf040b {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <350>;
+   reg = <1>;
+   };
+
+   dflash2: en25s64 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   spi-max-frequency = <350>;
+   reg = <2>;
+   };
 };
 
  {
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 60fb0ad..5b12632 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -4,3 +4,6 @@ CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_NS16550=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
 CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
diff --git a/configs/ls1043aqds_nand_defconfig 
b/configs/ls1043aqds_nand_defconfig
index e9d5afd..d4f758c 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -3,3 +3,8 @@ 
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig 
b/configs/ls1043aqds_sdcard_ifc_defconfig
index 6765d3d..25ae9cc 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -3,3 +3,8 @@ 
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
 CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 677d281..38e5b9b 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -197,6 +197,18 @@
 #define CONFIG_DOS_PARTITION
 #endif
 
+/*  DSPI  */
+#define CONFIG_FSL_DSPI
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO   /* cs0 */
+#define CONFIG_SPI_FLASH_SST   /* cs1 */
+#define CONFIG_SPI_FLASH_EON   /* cs2 */
+#define CONFIG_SF_DEFAULT_BUS  1
+#define CONFIG_SF_DEFAULT_CS   0
+#endif
+
 /* FMan ucode */
 #define CONFIG_SYS_DPAA_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 585114f..f768348 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -222,16 +222,6 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
 
-/* DSPI */
-#define CONFIG_FSL_DSPI
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
-#define CONFIG_DM_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_BUS  1
-#define CONFIG_SF_DEFAULT_CS   0
-#endif
-
 /*
  * Environment
  */
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH 1/3] armv8/ls1043aqds: add DSPI support

[Shaohui Xie]

> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Thursday, December 24, 2015 4:40 PM
> To: u-boot@lists.denx.de
> Cc: Mingkai Hu; r58...@freescale.com; b48...@freescale.com;
> shaohui@freescale.com; wenbin.s...@freescale.com;
> b07...@freescale.com; Gong Qianyu; Qianyu Gong
> Subject: [PATCH 1/3] armv8/ls1043aqds: add DSPI support
> 
> From: Gong Qianyu 
> 
> Enable three DSPI flash memories on board.
> 
> Commands:
> => sf probe 1:0
> SF: Detected N25Q128A with page size 256 Bytes,
>   erase size 64 KiB, total 16 MiB
> => sf probe 1:1
> SF: Detected SST25WF040B with page size 256 Bytes,
>   erase size 4 KiB, total 512 KiB
> => sf probe 1:2
> SF: Detected EN25S64 with page size 256 Bytes,
>   erase size 64 KiB, total 8 MiB
> 
> Signed-off-by: Gong Qianyu 
> Signed-off-by: Gong Qianyu 
[S.H] keep one email address.

> ---
>  arch/arm/dts/fsl-ls1043a-qds.dts| 30
> ++
>  configs/ls1043aqds_defconfig|  3 +++
>  configs/ls1043aqds_nand_defconfig   |  5 +
>  configs/ls1043aqds_sdcard_ifc_defconfig |  5 +
>  include/configs/ls1043a_common.h| 13 +
>  include/configs/ls1043ardb.h| 10 --
>  6 files changed, 56 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/dts/fsl-ls1043a-qds.dts b/arch/arm/dts/fsl-ls1043a-
> qds.dts
> index 7435222..0fe9c54 100644
> --- a/arch/arm/dts/fsl-ls1043a-qds.dts
> +++ b/arch/arm/dts/fsl-ls1043a-qds.dts
> @@ -15,6 +15,36 @@
> 
>  / {
>   model = "LS1043A QDS Board";
> + aliases {
> + spi1 = 
> + };
> +};
> +
> + {
> + bus-num = <0>;
> + status = "okay";
> +
> + dflash0: n25q128a {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + reg = <0>;
> + spi-max-frequency = <100>; /* input clock */
> + };
[S.H] empty line.

> + dflash1: sst25wf040b {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + spi-max-frequency = <350>;
> + reg = <1>;
> + };
[S.H] ditto.

> + dflash2: en25s64 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash";
> + spi-max-frequency = <350>;
> + reg = <2>;
> + };
>  };
> 
>   {
> diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
> index 60fb0ad..5b12632 100644
> --- a/configs/ls1043aqds_defconfig
> +++ b/configs/ls1043aqds_defconfig
> @@ -4,3 +4,6 @@ CONFIG_TARGET_LS1043AQDS=y  CONFIG_SYS_NS16550=y
> CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
>  CONFIG_OF_CONTROL=y
> +CONFIG_DM=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_SPI=y
> diff --git a/configs/ls1043aqds_nand_defconfig
> b/configs/ls1043aqds_nand_defconfig
> index e9d5afd..d4f758c 100644
> --- a/configs/ls1043aqds_nand_defconfig
> +++ b/configs/ls1043aqds_nand_defconfig
> @@ -3,3 +3,8 @@
> CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
>  CONFIG_ARM=y
>  CONFIG_TARGET_LS1043AQDS=y
>  CONFIG_SYS_NS16550=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
> +CONFIG_OF_CONTROL=y
> +CONFIG_DM=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_SPI=y
> diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig
> b/configs/ls1043aqds_sdcard_ifc_defconfig
> index 6765d3d..25ae9cc 100644
> --- a/configs/ls1043aqds_sdcard_ifc_defconfig
> +++ b/configs/ls1043aqds_sdcard_ifc_defconfig
> @@ -3,3 +3,8 @@
> CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
>  CONFIG_ARM=y
>  CONFIG_TARGET_LS1043AQDS=y
>  CONFIG_SYS_NS16550=y
> +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
> +CONFIG_OF_CONTROL=y
> +CONFIG_DM=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_SPI=y
> diff --git a/include/configs/ls1043a_common.h
> b/include/configs/ls1043a_common.h
> index 677d281..139d1d4 100644
> --- a/include/configs/ls1043a_common.h
> +++ b/include/configs/ls1043a_common.h
> @@ -197,6 +197,19 @@
>  #define CONFIG_DOS_PARTITION
>  #endif
> 
> +/*  DSPI  */
> +#define CONFIG_FSL_DSPI
> +#ifdef CONFIG_FSL_DSPI
> +#define CONFIG_CMD_SF
> +#define CONFIG_DM_SPI_FLASH
> +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
> +#define CONFIG_SPI_FLASH_SST /* cs1 */
> +#define CONFIG_SPI_FLASH_EON /* cs2 */
> +#define CONFIG_SF_DEFAULT_BUS1
> +#define CONFIG_SF_DEFAULT_CS 0
> +#endif
> +
> +
[S.H] remove one empty line.

>  /* FMan ucode */
>  #define CONFIG_SYS_DPAA_FMAN
>  #ifdef CONFIG_SYS_DPAA_FMAN
> diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
> index 585114f..f768348 100644
> --- a/include/configs/ls1043ardb.h
> +++ b/include/configs/ls1043ardb.h
> @@ -222,16 +222,6 @@
>  #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS3
>  

[U-Boot] [Patch V2 3/3] armv8/ls1043aqds: add QSPI boot support

[Gong Qianyu]

From: Gong Qianyu 

Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver.

Signed-off-by: Gong Qianyu 
---
V2:
 - No change.

 arch/arm/include/asm/arch-fsl-layerscape/cpu.h |  2 ++
 board/freescale/ls1043aqds/MAINTAINERS |  1 +
 board/freescale/ls1043aqds/README  |  1 +
 board/freescale/ls1043aqds/ls1043aqds.c|  7 +++
 configs/ls1043aqds_qspi_defconfig  |  9 +
 include/configs/ls1043a_common.h   |  6 +++---
 include/configs/ls1043aqds.h   | 15 ---
 7 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index e030430..f2f1206 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -150,6 +150,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
  PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+   { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
diff --git a/board/freescale/ls1043aqds/MAINTAINERS 
b/board/freescale/ls1043aqds/MAINTAINERS
index 868bb72..65a0af1 100644
--- a/board/freescale/ls1043aqds/MAINTAINERS
+++ b/board/freescale/ls1043aqds/MAINTAINERS
@@ -8,3 +8,4 @@ F:  configs/ls1043aqds_nor_ddr3_defconfig
 F: configs/ls1043aqds_nand_defconfig
 F: configs/ls1043aqds_sdcard_ifc_defconfig
 F: configs/ls1043aqds_sdcard_qspi_defconfig
+F: configs/ls1043aqds_qspi_defconfig
diff --git a/board/freescale/ls1043aqds/README 
b/board/freescale/ls1043aqds/README
index 6261a77..a6fd7a3 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -94,3 +94,4 @@ a) Promjet Boot
 b) NOR boot
 c) NAND boot
 d) SD boot
+e) QSPI boot
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c 
b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca..770b79f 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -43,15 +43,19 @@ enum {
 
 int checkboard(void)
 {
+#ifndef CONFIG_QSPI_BOOT
char buf[64];
 #ifndef CONFIG_SD_BOOT
u8 sw;
 #endif
+#endif
 
puts("Board: LS1043AQDS, boot from ");
 
 #ifdef CONFIG_SD_BOOT
puts("SD\n");
+#elif defined(CONFIG_QSPI_BOOT)
+   puts("QSPI\n");
 #else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -68,12 +72,15 @@ int checkboard(void)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 #endif
 
+#ifndef CONFIG_QSPI_BOOT
+   /* For QSPI boot, here I2C is not ready yet. */
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
   QIXIS_READ(id), QIXIS_READ(arch));
 
printf("FPGA:  v%d (%s), build %d\n",
   (int)QIXIS_READ(scver), qixis_read_tag(buf),
   (int)qixis_read_minor());
+#endif
 
return 0;
 }
diff --git a/configs/ls1043aqds_qspi_defconfig 
b/configs/ls1043aqds_qspi_defconfig
new file mode 100644
index 000..fcbaf31
--- /dev/null
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_SYS_NS16550=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 707405c..afddedc 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -121,7 +121,7 @@
 #endif
 
 /* IFC */
-#ifndef CONFIG_SD_BOOT_QSPI
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_FSL_IFC
 /*
  * CONFIG_SYS_FLASH_BASE has the final address (core view)
@@ -207,7 +207,7 @@
 #define CONFIG_SPI_FLASH_STMICRO   /* cs0 */
 #define CONFIG_SPI_FLASH_SST   /* cs1 */
 #define CONFIG_SPI_FLASH_EON   /* cs2 */
-#ifndef CONFIG_SD_BOOT_QSPI
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SF_DEFAULT_BUS  1
 #define CONFIG_SF_DEFAULT_CS   0
 #endif
@@ -218,7 +218,7 @@
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_FM_MURAM_SIZE   0x6
 
-#ifdef CONFIG_SD_BOOT_QSPI
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR0x400d
 #define CONFIG_ENV_SPI_BUS 0
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index cb519e1..e01f06d 100644
--- 

Re: [U-Boot] [PATCH v3 2/4] mips: ath79: add serial driver for ar933x SOC

[Thomas Chou]

Hi Wills,

There is code to set baud rate in Linux kernel,

drivers/tty/serial/ar933x_uart.c

Best regards,
Thomas
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Re: [U-Boot] [PATCH] sunxi: Remove Orangepi PC RAM speed to 624 MHz

[Peter Korsgaard]

> "Hans" == Hans de Goede  writes:

 > There are some reports of stability issues at 672 MHz, see:
 > http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit

 > So reduce the DRAM speed to 624MHz which seems to be reliable everywhere.

With the subject s/Remove/Reduce/

Acked-by: Peter Korsgaard 

 > Signed-off-by: Hans de Goede 
 > ---
 >  configs/orangepi_pc_defconfig | 2 +-
 >  1 file changed, 1 insertion(+), 1 deletion(-)

 > diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
 > index 75afca9..358caa5 100644
 > --- a/configs/orangepi_pc_defconfig
 > +++ b/configs/orangepi_pc_defconfig
 > @@ -1,7 +1,7 @@
 >  CONFIG_ARM=y
 >  CONFIG_ARCH_SUNXI=y
 >  CONFIG_MACH_SUN8I_H3=y
 > -CONFIG_DRAM_CLK=672
 > +CONFIG_DRAM_CLK=624
 >  CONFIG_DRAM_ZQ=3881979
 >  CONFIG_DRAM_ODT_EN=y
 >  # CONFIG_VIDEO is not set
 > -- 
 > 2.5.0

 > ___
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-- 
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Re: [U-Boot] [PATCH] sunxi: Remove Orangepi PC RAM speed to 624 MHz

[Ian Campbell]

On Wed, 2015-12-23 at 11:50 +0100, Hans de Goede wrote:
> There are some reports of stability issues at 672 MHz, see:
> http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit

Looks like only one (in that table at least)? And do we expect this
data to remain in the wiki, I suppose so.

In any case, this...
> So reduce the DRAM speed to 624MHz which seems to be reliable
> everywhere.

...seems reasonable to me.

> Signed-off-by: Hans de Goede 

Acked-by: Ian Campbell 

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[U-Boot] [PATCH 6/7] driver: net: ldpaa: Add debug info of printing DPMAC stats

[Prabhakar Kushwaha]

Add debug information prints to provide DPMAC statistics
 - Number of bytes received
 - Number of received and discard frames
 - Number of bytes transferred
 - Number of frames transferred
 etc.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/net/ldpaa_eth/ldpaa_eth.c | 78 +++
 1 file changed, 78 insertions(+)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index a2e455f..e09553a 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -100,6 +100,83 @@ static void ldpaa_eth_get_dpni_counter(void)
}
printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value);
 }
+
+static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev)
+{
+   struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
+   int err = 0;
+   u64 value;
+
+   err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+DPMAC_CNT_ING_BYTE,
+);
+   if (err < 0) {
+   printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n");
+   return;
+   }
+   printf("DPMAC_CNT_ING_BYTE=%lld\n", value);
+
+   err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+DPMAC_CNT_ING_FRAME_DISCARD,
+);
+   if (err < 0) {
+   printf("dpmac_get_counter: DPMAC_CNT_ING_FRAME_DISCARD 
failed\n");
+   return;
+   }
+   printf("DPMAC_CNT_ING_FRAME_DISCARD=%lld\n", value);
+
+   err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+DPMAC_CNT_ING_ALIGN_ERR,
+);
+   if (err < 0) {
+   printf("dpmac_get_counter: DPMAC_CNT_ING_ALIGN_ERR failed\n");
+   return;
+   }
+   printf("DPMAC_CNT_ING_ALIGN_ERR =%lld\n", value);
+
+   err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+DPMAC_CNT_ING_BYTE,
+);
+   if (err < 0) {
+   printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n");
+   return;
+   }
+   printf("DPMAC_CNT_ING_BYTE=%lld\n", value);
+
+   err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+DPMAC_CNT_ING_ERR_FRAME,
+);
+   if (err < 0) {
+   printf("dpmac_get_counter: DPMAC_CNT_ING_ERR_FRAME failed\n");
+   return;
+   }
+   printf("DPMAC_CNT_ING_ERR_FRAME=%lld\n", value);
+
+   err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+DPMAC_CNT_EGR_BYTE ,
+);
+   if (err < 0) {
+   printf("dpmac_get_counter: DPMAC_CNT_EGR_BYTE failed\n");
+   return;
+   }
+   printf("DPMAC_CNT_EGR_BYTE =%lld\n", value);
+
+   err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+DPMAC_CNT_EGR_ERR_FRAME ,
+);
+   if (err < 0) {
+   printf("dpmac_get_counter: DPMAC_CNT_EGR_ERR_FRAME failed\n");
+   return;
+   }
+   printf("DPMAC_CNT_EGR_ERR_FRAME =%lld\n", value);
+}
 #endif
 
 static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
@@ -436,6 +513,7 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
 
 #ifdef DEBUG
ldpaa_eth_get_dpni_counter();
+   ldpaa_eth_get_dpmac_counter(net_dev);
 #endif
 
err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
-- 
1.9.1


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[U-Boot] [PATCH 4/7] driver: net: ldpaa: Report back only error frames for tx

[Prabhakar Kushwaha]

Management Complex FW 9.0 puts a new requirement to provide Tx confirmation
and error queue configuration by calling dpni_set_tx_conf API.

Configure report of only error frames for a tx frame.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/net/ldpaa_eth/ldpaa_eth.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 85eb2c4..a2e455f 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -783,6 +783,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
 {
struct dpni_pools_cfg pools_params;
struct dpni_tx_flow_cfg dflt_tx_flow;
+   struct dpni_tx_conf_cfg tx_conf_cfg;
int err = 0;
 
pools_params.num_dpbp = 1;
@@ -807,6 +808,17 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
return err;
}
 
+   memset(_conf_cfg, 0, sizeof(struct dpni_tx_conf_cfg));
+   tx_conf_cfg.errors_only = true;
+   /*Set tx-conf and error configuration*/
+   err = dpni_set_tx_conf(dflt_mc_io, MC_CMD_NO_FLAGS,
+  dflt_dpni->dpni_handle,
+  priv->tx_flow_id, _conf_cfg);
+   if (err) {
+   printf("dpni_set_tx_conf() failed\n");
+   return err;
+   }
+
return 0;
 }
 
-- 
1.9.1


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[U-Boot] [PATCH v2 11/19] arm: dts: am335x-boneblack: add tick-timer to chosen node

[Mugunthan V N]

Specify which timer to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N 
---
 arch/arm/dts/am335x-boneblack.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/am335x-boneblack.dts 
b/arch/arm/dts/am335x-boneblack.dts
index 679248a..27ebe4a 100644
--- a/arch/arm/dts/am335x-boneblack.dts
+++ b/arch/arm/dts/am335x-boneblack.dts
@@ -15,6 +15,7 @@
compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
chosen {
stdout-path = 
+   tick-timer = 
};
 };
 
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 14/19] defconfig: am335x_gp_evm: enable timer driver model

[Mugunthan V N]

Enable timer driver model for am335x_gp_evm as omap-timer supports
driver model.

Signed-off-by: Mugunthan V N 
---
 configs/am335x_gp_evm_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
index 74d9ffb..49461e2 100644
--- a/configs/am335x_gp_evm_defconfig
+++ b/configs/am335x_gp_evm_defconfig
@@ -16,3 +16,5 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
 CONFIG_RSA=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 13/19] arm: dts: am335x-evm: add tick-timer to chosen node

[Mugunthan V N]

Specify timer2 to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N 
---
 arch/arm/dts/am335x-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index e1c5d4f..c0bc2af 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -16,6 +16,7 @@
 
chosen {
stdout-path = 
+   tick-timer = 
};
 
cpus {
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 15/19] ti_omap5_common: timer: do not define CONFIG_TIMER for spl

[Mugunthan V N]

Since OMAP's spl doesn't support DM currently, do not define
CONFIG_TIMER for spl build.

Signed-off-by: Mugunthan V N 
---
 include/configs/ti_omap5_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ti_omap5_common.h 
b/include/configs/ti_omap5_common.h
index 2d492f8..d164e6a 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -164,6 +164,7 @@
  */
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
 #endif
 
 #endif /* __CONFIG_TI_OMAP5_COMMON_H */
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 10/19] am335x_evm: timer: do not define CONFIG_TIMER for spl

[Mugunthan V N]

Since OMAP's spl doesn't support DM currently, do not define
CONFIG_TIMER for spl build.

Signed-off-by: Mugunthan V N 
---
 include/configs/am335x_evm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index c51db8c..d93fdf1 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -361,6 +361,7 @@
  */
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
 #endif
 
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 12/19] defconfig: am335x_boneblack_vboot: enable timer driver model

[Mugunthan V N]

Enable timer driver model for am335x_boneblack_vboot as
omap-timer supports driver model.

Signed-off-by: Mugunthan V N 
---
 configs/am335x_boneblack_vboot_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/am335x_boneblack_vboot_defconfig 
b/configs/am335x_boneblack_vboot_defconfig
index ad40b07..888d5b1 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -18,3 +18,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 09/19] defconfig: am437x_gp_evm: enable timer driver model

[Mugunthan V N]

Enable timer driver model for am437x_gp_evm as omap-timer supports
driver model.

Signed-off-by: Mugunthan V N 
---
 configs/am437x_gp_evm_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
index 7155c98..1d79ba19 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_gp_evm_defconfig
@@ -18,3 +18,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH 0/7] driver: net: fsl-mc: Update existing driver for MC FW 9.0.0

[Prabhakar Kushwaha]

Freescale's Management complex firmware version 9.0.0 provide support
of new APIs, update in existing APIs, change in Major and minor version
DPAA2 objects, provide new requirements etc.

This patch set provide support of new Management Complex firmware 9.0.0.

This patch set depends upon "http://patchwork.ozlabs.org/patch/559982/;

Prabhakar Kushwaha (7):
  driver: net: fsl-mc: Add version check for MC objects
  driver: net: fsl-mc: flib changes for MC FW 9.0.0
  driver: net: fsl-mc: Prepare extended cfg for DPNI create
  driver: net: ldpaa: Report back only error frames for tx
  driver: net: ldpaa: Increase num of buffers for a pool
  driver: net: ldpaa: Add debug info of printing DPMAC stats
  driver: net: fsl-mc: Remove portal id hard-coding

 drivers/net/fsl-mc/dpni.c |  81 ++
 drivers/net/fsl-mc/mc.c   |  67 -
 drivers/net/ldpaa_eth/ldpaa_eth.c | 122 -
 drivers/net/ldpaa_eth/ldpaa_eth.h |   2 +-
 include/fsl-mc/fsl_dpbp.h |   2 +-
 include/fsl-mc/fsl_dpio.h |   5 +-
 include/fsl-mc/fsl_dpmac.h|   2 +-
 include/fsl-mc/fsl_dpmng.h|   2 +-
 include/fsl-mc/fsl_dpni.h | 539 +++---
 include/fsl-mc/fsl_dprc.h |  94 ++-
 include/fsl-mc/fsl_mc_cmd.h   |   5 +-
 11 files changed, 748 insertions(+), 173 deletions(-)

-- 
1.9.1


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[U-Boot] [PATCH 2/7] driver: net: fsl-mc: flib changes for MC FW 9.0.0

[Prabhakar Kushwaha]

MC firmware version 9.0.0 contains
 - Support of new APIs
 - Update in existing APIs
 - Change in Major and minor version of DPAA2 objects

This patch contains modifications in FLIB files to support new MC firmware
version.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/net/fsl-mc/dpni.c |  81 ++
 drivers/net/ldpaa_eth/ldpaa_eth.c |   4 +-
 include/fsl-mc/fsl_dpbp.h |   2 +-
 include/fsl-mc/fsl_dpio.h |   5 +-
 include/fsl-mc/fsl_dpmac.h|   2 +-
 include/fsl-mc/fsl_dpmng.h|   2 +-
 include/fsl-mc/fsl_dpni.h | 539 +++---
 include/fsl-mc/fsl_dprc.h |  94 ++-
 include/fsl-mc/fsl_mc_cmd.h   |   5 +-
 9 files changed, 565 insertions(+), 169 deletions(-)

diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c
index eacb3c8..41bf56a 100644
--- a/drivers/net/fsl-mc/dpni.c
+++ b/drivers/net/fsl-mc/dpni.c
@@ -8,6 +8,26 @@
 #include 
 #include 
 
+int dpni_prepare_extended_cfg(const struct dpni_extended_cfg   *cfg,
+ uint8_t   *ext_cfg_buf)
+{
+   uint64_t *ext_params = (uint64_t *)ext_cfg_buf;
+
+   DPNI_PREP_EXTENDED_CFG(ext_params, cfg);
+
+   return 0;
+}
+
+int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg,
+ const uint8_t *ext_cfg_buf)
+{
+   uint64_t *ext_params = (uint64_t *)ext_cfg_buf;
+
+   DPNI_EXT_EXTENDED_CFG(ext_params, cfg);
+
+   return 0;
+}
+
 int dpni_open(struct fsl_mc_io *mc_io,
  uint32_t cmd_flags,
  int dpni_id,
@@ -162,6 +182,7 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io,
cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
  cmd_flags,
  token);
+   DPNI_CMD_GET_ATTR(cmd, attr);
 
/* send command to mc*/
err = mc_send_command(mc_io, );
@@ -174,6 +195,23 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io,
return 0;
 }
 
+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
+uint32_t cmd_flags,
+uint16_t token,
+ struct dpni_error_cfg *cfg)
+{
+   struct mc_command cmd = { 0 };
+
+   /* prepare command */
+   cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR,
+ cmd_flags,
+ token);
+   DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg);
+
+   /* send command to mc*/
+   return mc_send_command(mc_io, );
+}
+
 int dpni_get_rx_buffer_layout(struct fsl_mc_io *mc_io,
  uint32_t cmd_flags,
  uint16_t token,
@@ -602,3 +640,46 @@ int dpni_get_rx_flow(struct fsl_mc_io *mc_io,
 
return 0;
 }
+
+int dpni_set_tx_conf(struct fsl_mc_io  *mc_io,
+uint32_t   cmd_flags,
+uint16_t   token,
+uint16_t   flow_id,
+const struct dpni_tx_conf_cfg  *cfg)
+{
+   struct mc_command cmd = { 0 };
+
+   /* prepare command */
+   cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONF,
+ cmd_flags,
+ token);
+   DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg);
+
+   /* send command to mc*/
+   return mc_send_command(mc_io, );
+}
+
+int dpni_get_tx_conf(struct fsl_mc_io  *mc_io,
+uint32_t   cmd_flags,
+uint16_t   token,
+uint16_t   flow_id,
+struct dpni_tx_conf_attr   *attr)
+{
+   struct mc_command cmd = { 0 };
+   int err;
+
+   /* prepare command */
+   cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_CONF,
+ cmd_flags,
+ token);
+   DPNI_CMD_GET_TX_CONF(cmd, flow_id);
+
+   /* send command to mc*/
+   err = mc_send_command(mc_io, );
+   if (err)
+   return err;
+
+   DPNI_RSP_GET_TX_CONF(cmd, attr);
+
+   return 0;
+}
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 47a3a23..85eb2c4 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -798,9 +798,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
priv->tx_flow_id = DPNI_NEW_FLOW_ID;
memset(_tx_flow, 0, sizeof(dflt_tx_flow));
 
-   dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR;
-   dflt_tx_flow.conf_err_cfg.use_default_queue = 0;
-   dflt_tx_flow.conf_err_cfg.errors_only = 1;
+   dflt_tx_flow.use_common_tx_conf_queue = 0;
err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
   

[U-Boot] [PATCH 7/7] driver: net: fsl-mc: Remove portal id hard-coding

[Prabhakar Kushwaha]

Management Complex firmware 9.0 has fixed the issue of dprc_destroy_container
i.e. the used portal is not return to the free pool. Which was resulting in
error ethernet driver want to use this portal via either DPL or dynamically
in Linux.

So, Remove hard-coding of portal id.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/net/fsl-mc/mc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index a45a30d..9e042f6 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -821,7 +821,7 @@ static int dprc_init(void)
  DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
  DPRC_CFG_OPT_ALLOC_ALLOWED;
cfg.icid = DPRC_GET_ICID_FROM_POOL;
-   cfg.portal_id = 250;
+   cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL;
err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
root_dprc_handle,
,
-- 
1.9.1


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[U-Boot] [PATCH v2 00/19] driver model bring-up of omap timer on dra72, dra74, am335x and am437x-sk evm

[Mugunthan V N]

This patch series enables omap timer to adopt driver model. This
has been tested on the following evms (logs [1]) by invoking
'sleep 10' command with minicom timestamps.
* dra72 evm
* dra74 evm
* am335x evm
* am335x bbb
* am437x-sk evm
* am437x-gp evm

Also pushed a branch for testing [2]

[1] - http://pastebin.ubuntu.com/14190309/
[2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-timer-v2

Changes from initial->v2:
* Moved get timer either from choosen/first available timer from
  dm_timer_init to timer_init.
* Fixed typo errors in doc and comments
* Changed omap_timer_get_count dedfinition as per latest code base.

Mugunthan V N (19):
  arm: omap-common: do not build timer when CONFIG_TIMER defined
  dm: timer: uclass: add timer init to add timer device
  dm: timer: uclass: Add flag to control sequence numbering
  drivers: timer: omap_timer: add timer driver for omap devices based on
dm
  am43xx_evm: timer: do not define CONFIG_TIMER for spl
  arm: dts: am437x-sk-evm: add tick-timer to chosen node
  defconfig: am437x_sk_evm: enable timer driver model
  arm: dts: am437x-gp-evm: add tick-timer to chosen node
  defconfig: am437x_gp_evm: enable timer driver model
  am335x_evm: timer: do not define CONFIG_TIMER for spl
  arm: dts: am335x-boneblack: add tick-timer to chosen node
  defconfig: am335x_boneblack_vboot: enable timer driver model
  arm: dts: am335x-evm: add tick-timer to chosen node
  defconfig: am335x_gp_evm: enable timer driver model
  ti_omap5_common: timer: do not define CONFIG_TIMER for spl
  arm: dts: dra72-evm: add tick-timer to chosen node
  defconfig: dra72_evm: enable timer driver model
  arm: dts: dra7-evm: add tick-timer to chosen node
  defconfig: dra74_evm: enable timer driver model

 arch/arm/cpu/armv7/omap-common/Makefile  |   6 ++
 arch/arm/dts/am335x-boneblack.dts|   1 +
 arch/arm/dts/am335x-evm.dts  |   1 +
 arch/arm/dts/am437x-gp-evm.dts   |   1 +
 arch/arm/dts/am437x-sk-evm.dts   |   1 +
 arch/arm/dts/dra7-evm.dts|   1 +
 arch/arm/dts/dra72-evm.dts   |   1 +
 configs/am335x_boneblack_vboot_defconfig |   2 +
 configs/am335x_gp_evm_defconfig  |   2 +
 configs/am437x_gp_evm_defconfig  |   2 +
 configs/am437x_sk_evm_defconfig  |   2 +
 configs/dra72_evm_defconfig  |   2 +
 configs/dra74_evm_defconfig  |   2 +
 doc/device-tree-bindings/chosen.txt  |  43 
 drivers/timer/Kconfig|   6 ++
 drivers/timer/Makefile   |   1 +
 drivers/timer/omap-timer.c   | 108 +++
 drivers/timer/timer-uclass.c |  43 
 include/configs/am335x_evm.h |   1 +
 include/configs/am43xx_evm.h |   1 +
 include/configs/ti_omap5_common.h|   1 +
 lib/time.c   |  13 +---
 22 files changed, 230 insertions(+), 11 deletions(-)
 create mode 100644 doc/device-tree-bindings/chosen.txt
 create mode 100644 drivers/timer/omap-timer.c

-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 01/19] arm: omap-common: do not build timer when CONFIG_TIMER defined

[Mugunthan V N]

To prepare timer driver to DM/DT conversion do not build the
exiting timer driver when CONFIG_TIMER is defined. But since
omap's SPL doesn't support DM yet so built timer driver only for
SPL build when CONFIG_TIMER is defined.

Signed-off-by: Mugunthan V N 
---
 arch/arm/cpu/armv7/omap-common/Makefile | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile 
b/arch/arm/cpu/armv7/omap-common/Makefile
index 464a5d1..87a7ac0 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -6,7 +6,13 @@
 #
 
 obj-y  := reset.o
+ifeq ($(CONFIG_TIMER),)
 obj-y  += timer.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y  += timer.o
+endif
+endif
 obj-y  += utils.o
 
 ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 02/19] dm: timer: uclass: add timer init to add timer device

[Mugunthan V N]

Adding timer_init function to create and initialize the timer
device on platforms where u-boot,dm-pre-reloc is not used. Since
there will be multiple timer devices in the system, adding a
tick-timer node in chosen node to know which timer device to be
used as tick timer in u-boot.

Signed-off-by: Mugunthan V N 
---
 doc/device-tree-bindings/chosen.txt | 43 +
 drivers/timer/timer-uclass.c| 42 
 lib/time.c  | 13 ++-
 3 files changed, 87 insertions(+), 11 deletions(-)
 create mode 100644 doc/device-tree-bindings/chosen.txt

diff --git a/doc/device-tree-bindings/chosen.txt 
b/doc/device-tree-bindings/chosen.txt
new file mode 100644
index 000..bf9a30a
--- /dev/null
+++ b/doc/device-tree-bindings/chosen.txt
@@ -0,0 +1,43 @@
+The chosen node
+---
+The chosen node does not represent a real device, but serves as a place
+for passing data like which serial device to used to print the logs etc
+
+
+stdout-path property
+
+Device trees may specify the device to be used for boot console output
+with a stdout-path property under /chosen.
+
+Example
+---
+/ {
+   chosen {
+   stdout-path = "/serial@f00:115200";
+   };
+
+   serial@f00 {
+   compatible = "vendor,some-uart";
+   reg = <0xf00 0x10>;
+   };
+};
+
+tick-timer property
+---
+In a system there are multiple timers, specify which timer to be used
+as the tick-timer. Earlier it was hardcoded in the timer driver now
+since device tree has all the timer nodes. Specify which timer to be
+used as tick timer.
+
+Example
+---
+/ {
+   chosen {
+   tick-timer = "/timer2@f00";
+   };
+
+   timer2@f00 {
+   compatible = "vendor,some-timer";
+   reg = <0xf00 0x10>;
+   };
+};
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index aca421b..db43611 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -6,6 +6,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 
@@ -56,6 +58,46 @@ u64 timer_conv_64(u32 count)
return ((u64)gd->timebase_h << 32) | gd->timebase_l;
 }
 
+int timer_init(void)
+{
+   const void *blob = gd->fdt_blob;
+   struct udevice *dev;
+   int node;
+   int ret;
+
+   /* Check for a chosen timer to be used for tick */
+   node = fdtdec_get_chosen_node(blob, "tick-timer");
+   if (node < 0)
+   return -ENODEV;
+
+   if (uclass_get_device_by_of_offset(UCLASS_TIMER, node, )) {
+   /*
+* If the timer is not marked to be bound before
+* relocation, bind it anyway.
+*/
+   if (node > 0 &&
+   !lists_bind_fdt(gd->dm_root, blob, node, )) {
+   int ret = device_probe(dev);
+   if (ret)
+   return ret;
+   }
+   }
+
+   if (dev) {
+   gd->timer = dev;
+   return 0;
+   }
+
+   ret = uclass_first_device(UCLASS_TIMER, );
+   if (ret)
+   return ret;
+   if (!dev)
+   return -ENODEV;
+
+   gd->timer = dev;
+   return 0;
+}
+
 UCLASS_DRIVER(timer) = {
.id = UCLASS_TIMER,
.name   = "timer",
diff --git a/lib/time.c b/lib/time.c
index f37a662..d4060f1 100644
--- a/lib/time.c
+++ b/lib/time.c
@@ -43,17 +43,8 @@ extern unsigned long __weak timer_read_counter(void);
 #ifdef CONFIG_TIMER
 static int notrace dm_timer_init(void)
 {
-   struct udevice *dev;
-   int ret;
-
-   if (!gd->timer) {
-   ret = uclass_first_device(UCLASS_TIMER, );
-   if (ret)
-   return ret;
-   if (!dev)
-   return -ENODEV;
-   gd->timer = dev;
-   }
+   if (!gd->timer)
+   return timer_init();
 
return 0;
 }
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 03/19] dm: timer: uclass: Add flag to control sequence numbering

[Mugunthan V N]

Like SPI and I2C, timer devices also have multiple chip
instances. This patch adds the flag 'DM_UC_FLAG_SEQ_ALIAS' in
timer_uclass driver to control device sequence numbering.

Signed-off-by: Mugunthan V N 
Reviewed-by: Simon Glass 
Reviewed-by: Bin Meng 
---
 drivers/timer/timer-uclass.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index db43611..abeb060 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -102,5 +102,6 @@ UCLASS_DRIVER(timer) = {
.id = UCLASS_TIMER,
.name   = "timer",
.pre_probe  = timer_pre_probe,
+   .flags  = DM_UC_FLAG_SEQ_ALIAS,
.per_device_auto_alloc_size = sizeof(struct timer_dev_priv),
 };
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 05/19] am43xx_evm: timer: do not define CONFIG_TIMER for spl

[Mugunthan V N]

Since OMAP's spl doesn't support DM currently, do not define
CONFIG_TIMER for spl build.

Signed-off-by: Mugunthan V N 
---
 include/configs/am43xx_evm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index aac550a..9980203 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -142,6 +142,7 @@
  */
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
 #endif
 
 #ifndef CONFIG_SPL_BUILD
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 08/19] arm: dts: am437x-gp-evm: add tick-timer to chosen node

[Mugunthan V N]

Specify which timer to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N 
---
 arch/arm/dts/am437x-gp-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
index b5f0b4e..8e23b96 100644
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -26,6 +26,7 @@
 
chosen {
stdout-path = 
+   tick-timer = 
};
 
vmmcsd_fixed: fixedregulator-sd {
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 07/19] defconfig: am437x_sk_evm: enable timer driver model

[Mugunthan V N]

Enable timer driver model for am437x_sk_evm as omap-timer supports
driver model.

Signed-off-by: Mugunthan V N 
---
 configs/am437x_sk_evm_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index a9b6f52..56a7b11 100644
--- a/configs/am437x_sk_evm_defconfig
+++ b/configs/am437x_sk_evm_defconfig
@@ -18,3 +18,5 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 06/19] arm: dts: am437x-sk-evm: add tick-timer to chosen node

[Mugunthan V N]

Specify which timer to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N 
---
 arch/arm/dts/am437x-sk-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/am437x-sk-evm.dts b/arch/arm/dts/am437x-sk-evm.dts
index 3f9d808..85d3381 100644
--- a/arch/arm/dts/am437x-sk-evm.dts
+++ b/arch/arm/dts/am437x-sk-evm.dts
@@ -26,6 +26,7 @@
 
chosen {
stdout-path = 
+   tick-timer = 
};
 
backlight {
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 04/19] drivers: timer: omap_timer: add timer driver for omap devices based on dm

[Mugunthan V N]

Adding a timer driver for omap devices based on driver model
and device tree.

Signed-off-by: Mugunthan V N 
---
 drivers/timer/Kconfig  |   6 +++
 drivers/timer/Makefile |   1 +
 drivers/timer/omap-timer.c | 108 +
 3 files changed, 115 insertions(+)
 create mode 100644 drivers/timer/omap-timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 2b10d2b..ff65a73 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -30,4 +30,10 @@ config X86_TSC_TIMER
help
  Select this to enable Time-Stamp Counter (TSC) timer for x86.
 
+config OMAP_TIMER
+   bool "Omap timer support"
+   depends on TIMER
+   help
+ Select this to enable an timer for Omap devices.
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index fe954ec..f351fbb 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_TIMER) += timer-uclass.o
 obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
 obj-$(CONFIG_SANDBOX_TIMER)+= sandbox_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_OMAP_TIMER)   += omap-timer.o
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
new file mode 100644
index 000..3bb38c5
--- /dev/null
+++ b/drivers/timer/omap-timer.c
@@ -0,0 +1,108 @@
+/*
+ * TI OMAP timer driver
+ *
+ * Copyright (C) 2015, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timer register bits */
+#define TCLR_START BIT(0)  /* Start=1 */
+#define TCLR_AUTO_RELOAD   BIT(1)  /* Auto reload */
+#define TCLR_PRE_ENBIT(5)  /* Pre-scaler enable */
+#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
+
+#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
+
+struct omap_gptimer_regs {
+   unsigned int tidr;  /* offset 0x00 */
+   unsigned char res1[12];
+   unsigned int tiocp_cfg; /* offset 0x10 */
+   unsigned char res2[12];
+   unsigned int tier;  /* offset 0x20 */
+   unsigned int tistatr;   /* offset 0x24 */
+   unsigned int tistat;/* offset 0x28 */
+   unsigned int tisr;  /* offset 0x2c */
+   unsigned int tcicr; /* offset 0x30 */
+   unsigned int twer;  /* offset 0x34 */
+   unsigned int tclr;  /* offset 0x38 */
+   unsigned int tcrr;  /* offset 0x3c */
+   unsigned int tldr;  /* offset 0x40 */
+   unsigned int ttgr;  /* offset 0x44 */
+   unsigned int twpc;  /* offset 0x48 */
+   unsigned int tmar;  /* offset 0x4c */
+   unsigned int tcar1; /* offset 0x50 */
+   unsigned int tscir; /* offset 0x54 */
+   unsigned int tcar2; /* offset 0x58 */
+};
+
+/* Omap Timer Priv */
+struct omap_timer_priv {
+   struct omap_gptimer_regs *regs;
+};
+
+static int omap_timer_get_count(struct udevice *dev, u64 *count)
+{
+   struct omap_timer_priv *priv = dev_get_priv(dev);
+
+   *count = readl(>regs->tcrr);
+
+   return 0;
+}
+
+static int omap_timer_probe(struct udevice *dev)
+{
+   struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+   struct omap_timer_priv *priv = dev_get_priv(dev);
+
+   uc_priv->clock_rate = TIMER_CLOCK;
+
+   /* start the counter ticking up, reload value on overflow */
+   writel(0, >regs->tldr);
+   /* enable timer */
+   writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
+  TCLR_START, >regs->tclr);
+
+   return 0;
+}
+
+static int omap_timer_ofdata_to_platdata(struct udevice *dev)
+{
+   struct omap_timer_priv *priv = dev_get_priv(dev);
+
+   priv->regs = (struct omap_gptimer_regs *)dev_get_addr(dev);
+
+   return 0;
+}
+
+
+static const struct timer_ops omap_timer_ops = {
+   .get_count = omap_timer_get_count,
+};
+
+static const struct udevice_id omap_timer_ids[] = {
+   { .compatible = "ti,am335x-timer" },
+   { .compatible = "ti,am4372-timer" },
+   { .compatible = "ti,omap5430-timer" },
+   {}
+};
+
+U_BOOT_DRIVER(omap_timer) = {
+   .name   = "omap_timer",
+   .id = UCLASS_TIMER,
+   .of_match = omap_timer_ids,
+   .ofdata_to_platdata = omap_timer_ofdata_to_platdata,
+   .priv_auto_alloc_size = sizeof(struct omap_timer_priv),
+   .probe = omap_timer_probe,
+   .ops= _timer_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH] armv8: fsl-lsch3: fixup SYSCLK frequency in device tree

[Prabhakar Kushwaha]

SYSCLK frequency is dependent on on-board switch settings. It may
vary as per requirement. boot-loader is aware of board switch
configurations.

So Fixup Linux device tree from boot-loader.

Signed-off-by: Prabhakar Kushwaha 
CC: Mingkai Hu 
---
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c 
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index eafdd71..4e4861d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -190,6 +190,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
   "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
+   do_fixup_by_compat_u32(blob, "fixed-clock",
+  "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+
 #ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
 #endif
-- 
1.9.1


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Re: [U-Boot] [PATCH 8/9] efi_loader: Add "bootefi" command

[Matwey V. Kornilov]

Why just not to implement standard EFI behaviour when EFI looks for
boot-efi partition and proceed?

If ARM board developers will enable EFI support in the future, we can
have single one JeOS having all possible dtb in KIWI image.
BeagleBone Black has its own u-boot on eMMC, and the user need to push
S2 button to force hardware to use our openSUSE u-boot from SD card.
Maybe something like that is for other boards. If the single one
required u-boot feature is to run EFI grub, then we can even don't
touch preinstalled bootloader, that is not possible now, because we
need our openSUSE boot scripts.

2015-12-22 16:57 GMT+03:00 Alexander Graf :
> In order to execute an EFI application, we need to bridge the gap between
> U-Boot's notion of executing images and EFI's notion of doing the same.
>
> The best path forward IMHO here is to stick completely to the way U-Boot
> deals with payloads. You manually load them using whatever method to RAM
> and then have a simple boot command to execute them. So in our case, you
> would do
>
>   # load mmc 0:1 $loadaddr grub.efi
>   # bootefi $loadaddr
>
> which then gets you into a grub shell. Fdt information known to U-boot
> via the fdt addr command is also passed to the EFI payload.
>
> Signed-off-by: Alexander Graf 
> ---
>  common/Makefile  |   1 +
>  common/cmd_bootefi.c | 168 
> +++
>  2 files changed, 169 insertions(+)
>  create mode 100644 common/cmd_bootefi.c
>
> diff --git a/common/Makefile b/common/Makefile
> index 2a1d9f8..a7a728a 100644
> --- a/common/Makefile
> +++ b/common/Makefile
> @@ -67,6 +67,7 @@ obj-$(CONFIG_CMD_SOURCE) += cmd_source.o
>  obj-$(CONFIG_CMD_BDI) += cmd_bdinfo.o
>  obj-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
>  obj-$(CONFIG_CMD_BMP) += cmd_bmp.o
> +obj-$(CONFIG_EFI_LOADER) += cmd_bootefi.o
>  obj-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o
>  obj-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
>  obj-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
> diff --git a/common/cmd_bootefi.c b/common/cmd_bootefi.c
> new file mode 100644
> index 000..8d872d0
> --- /dev/null
> +++ b/common/cmd_bootefi.c
> @@ -0,0 +1,168 @@
> +/*
> + *  EFI application loader
> + *
> + *  Copyright (c) 2015 Alexander Graf
> + *
> + *  This library is free software; you can redistribute it and/or
> + *  modify it under the terms of the GNU Lesser General Public
> + *  License as published by the Free Software Foundation; either
> + *  version 2.1 of the License, or (at your option) any later version.
> + *
> + *  This library is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + *  Lesser General Public License for more details.
> + *
> + *  You should have received a copy of the GNU Lesser General Public
> + *  License along with this library; if not, write to the Free Software
> + *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
> + *
> + *  SPDX-License-Identifier: LGPL-2.1+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* This list contains all the EFI objects our payload has access to */
> +LIST_HEAD(efi_obj_list);
> +
> +/*
> + * When booting using the "bootefi" command, we don't know which
> + * physical device the file came from. So we create a pseudo-device
> + * called "bootefi" with the device path /bootefi.
> + *
> + * In addition to the originating device we also declare the file path
> + * of "bootefi" based loads to be /bootefi.
> + */
> +static struct efi_device_path_file_path bootefi_dummy_path[] = {
> +   {
> +   .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
> +   .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
> +   .dp.length = sizeof(bootefi_dummy_path[0]),
> +   .str = { 'b','o','o','t','e','f','i' },
> +   }, {
> +   .dp.type = DEVICE_PATH_TYPE_END,
> +   .dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
> +   .dp.length = sizeof(bootefi_dummy_path[0]),
> +   }
> +};
> +
> +static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
> +   void **protocol_interface, void *agent_handle,
> +   void *controller_handle, uint32_t attributes)
> +{
> +   *protocol_interface = bootefi_dummy_path;
> +   return EFI_SUCCESS;
> +}
> +
> +/* The EFI loaded_image interface for the image executed via "bootefi" */
> +static struct efi_loaded_image loaded_image_info = {
> +   .device_handle = bootefi_dummy_path,
> +   .file_path = bootefi_dummy_path,
> +};
> +
> +/* The EFI object struct for the image executed via "bootefi" */
> +static struct efi_object loaded_image_info_obj = {
> +   .handle = _image_info,
> +   .protocols = {
> +   {
> +   /* When asking for the loaded_image interface, just
> +   

Re: [U-Boot] [PATCH] axs103: add support of generic OHCI USB 1.1 controller

[Marek Vasut]

On Wednesday, December 23, 2015 at 12:59:28 PM, Alexey Brodkin wrote:
> Hi Marek,

Hi!
[...]
> > > > 
> > > > Am I reading it correctly that the root hub (the one built into the
> > > > controller) is misbehaving here ?
> > > > 
> > > > > Note in case of ARC770 the log is very similar except the fact that
> > > > > it goes further to successful device detection.
> > > 
> > > Applied to u-boot-arc, thanks!
> > 
> > Uh, sorry I didn't get back to you about this. I am wrestling my own
> > issues with the DWC2 USB core :-/ Looks like it doesn't work with
> > USB3340 LPM-capable PHY (it only starts in FS mode), but works with
> > non-LPM-capable USB3300 PHY and starts in HS mode.
> > 
> > Did you figure your issue out by any chance ?
> 
> No unfortunately I wasn't able to figure out what's wrong there.
> For now I parked this activity waiting for response from our hardware guys.
> I spent way too much time on that and basically need to switch to other
> high-priority things.

Please let me know what was it, I'd be interested in what went wrong for
future reference.

> If I ever get that problem resolved I'll let you know.
> 
> And thanks for your time anyway, that's much appreciated!

Thanks!

btw can you put me in touch with some guys who work on the DWC2 OTG core?
I have a few questions of my own, in particular with regard to the USB3340
PHY, which seems to have issues with the DWC2.

Best regards,
Marek Vasut
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[U-Boot] [PATCH 5/7] driver: net: ldpaa: Increase num of buffers for a pool

[Prabhakar Kushwaha]

Management Complex FW 9.0 set the hardware depletion to be 20 buffers
in order to support multiple pools in DPNI. This requires driver to fill
the pool with at least 21 to be able to receive frames.

So, Increase number of buffers for a pool.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/net/ldpaa_eth/ldpaa_eth.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h 
b/drivers/net/ldpaa_eth/ldpaa_eth.h
index af41b27..3b16150 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.h
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.h
@@ -24,7 +24,7 @@ enum ldpaa_eth_type {
 };
 
 /* Arbitrary values for now, but we'll need to tune */
-#define LDPAA_ETH_NUM_BUFS (2 * 7)
+#define LDPAA_ETH_NUM_BUFS (7 * 7)
 #define LDPAA_ETH_REFILL_THRESH(LDPAA_ETH_NUM_BUFS/2)
 #define LDPAA_ETH_RX_BUFFER_SIZE   2048
 
-- 
1.9.1


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[U-Boot] [PATCH 1/7] driver: net: fsl-mc: Add version check for MC objects

[Prabhakar Kushwaha]

Check and compare version of management  complex's object with the version
supported by Freescale ldpaa2 ethernet driver.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/net/fsl-mc/mc.c   | 51 ++-
 drivers/net/ldpaa_eth/ldpaa_eth.c | 28 +
 2 files changed, 78 insertions(+), 1 deletion(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index bac4610..b773e35 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -655,6 +655,26 @@ int fsl_mc_ldpaa_init(bd_t *bis)
return 0;
 }
 
+static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle)
+{
+   struct dprc_attributes attr;
+   int error;
+
+   memset(, 0, sizeof(struct dprc_attributes));
+   error = dprc_get_attributes(mc_io, MC_CMD_NO_FLAGS, handle, );
+   if (error == 0) {
+   if ((attr.version.major != DPRC_VER_MAJOR) ||
+   (attr.version.minor != DPRC_VER_MINOR)) {
+   printf("DPRC version mismatch found %u.%u,",
+  attr.version.major,
+  attr.version.minor);
+   printf("supported version is %u.%u\n",
+  DPRC_VER_MAJOR, DPRC_VER_MINOR);
+   }
+   }
+   return error;
+}
+
 static int dpio_init(void)
 {
struct qbman_swp_desc p_des;
@@ -688,11 +708,18 @@ static int dpio_init(void)
goto err_get_attr;
}
 
+   if ((attr.version.major != DPIO_VER_MAJOR) ||
+   (attr.version.minor != DPIO_VER_MINOR)) {
+   printf("DPIO version mismatch found %u.%u,",
+  attr.version.major, attr.version.minor);
+   printf("supported version is %u.%u\n",
+  DPIO_VER_MAJOR, DPIO_VER_MINOR);
+   }
+
dflt_dpio->dpio_id = attr.id;
 #ifdef DEBUG
printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
 #endif
-
err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
if (err < 0) {
printf("dpio_enable() failed %d\n", err);
@@ -784,6 +811,12 @@ static int dprc_init(void)
goto err_root_open;
}
 
+   err = dprc_version_check(root_mc_io, root_dprc_handle);
+   if (err < 0) {
+   printf("dprc_version_check() failed: %d\n", err);
+   goto err_root_open;
+   }
+
cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
  DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
  DPRC_CFG_OPT_ALLOC_ALLOWED;
@@ -906,6 +939,14 @@ static int dpbp_init(void)
goto err_get_attr;
}
 
+   if ((dpbp_attr.version.major != DPBP_VER_MAJOR) ||
+   (dpbp_attr.version.minor != DPBP_VER_MINOR)) {
+   printf("DPBP version mismatch found %u.%u,",
+  dpbp_attr.version.major, dpbp_attr.version.minor);
+   printf("supported version is %u.%u\n",
+  DPBP_VER_MAJOR, DPBP_VER_MINOR);
+   }
+
dflt_dpbp->dpbp_attr.id = dpbp_attr.id;
 #ifdef DEBUG
printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
@@ -994,6 +1035,14 @@ static int dpni_init(void)
goto err_get_attr;
}
 
+   if ((dpni_attr.version.major != DPNI_VER_MAJOR) ||
+   (dpni_attr.version.minor != DPNI_VER_MINOR)) {
+   printf("DPNI version mismatch found %u.%u,",
+  dpni_attr.version.major, dpni_attr.version.minor);
+   printf("supported version is %u.%u\n",
+  DPNI_VER_MAJOR, DPNI_VER_MINOR);
+   }
+
dflt_dpni->dpni_id = dpni_attr.id;
 #ifdef DEBUG
printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c 
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 69530b1..47a3a23 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -599,6 +599,29 @@ static void ldpaa_dpbp_free(void)
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
 }
 
+static int ldpaa_dpmac_version_check(struct fsl_mc_io *mc_io,
+struct ldpaa_eth_priv *priv)
+{
+   struct dpmac_attr attr;
+   int error;
+
+   memset(, 0, sizeof(struct dpmac_attr));
+   error = dpmac_get_attributes(mc_io, MC_CMD_NO_FLAGS,
+priv->dpmac_handle,
+);
+   if (error == 0) {
+   if ((attr.version.major != DPMAC_VER_MAJOR) ||
+   (attr.version.minor != DPMAC_VER_MINOR)) {
+   printf("DPMAC version mismatch found %u.%u,",
+  attr.version.major, attr.version.minor);
+   printf("supported version is %u.%u\n",
+  DPMAC_VER_MAJOR, DPMAC_VER_MINOR);
+   }
+   }
+

[U-Boot] [PATCH 3/7] driver: net: fsl-mc: Prepare extended cfg for DPNI create

[Prabhakar Kushwaha]

Management Complex FW 9.0 puts a new requirement to prepare extended
parameters which should be provided as input in dpni_create. extended
parameters includes traffic class and IP reassembly configurations.

So prepare extended parameters with default "0" as input for dpni_create.

Signed-off-by: Prabhakar Kushwaha 
---
 drivers/net/fsl-mc/mc.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index b773e35..a45a30d 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1004,6 +1004,8 @@ static int dpni_init(void)
 {
int err;
struct dpni_attr dpni_attr;
+   uint8_t ext_cfg_buf[256] = {0};
+   struct dpni_extended_cfg dpni_extended_cfg;
struct dpni_cfg dpni_cfg;
 
dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
@@ -1013,10 +1015,19 @@ static int dpni_init(void)
goto err_malloc;
}
 
+   memset(_extended_cfg, 0, sizeof(dpni_extended_cfg));
+   err = dpni_prepare_extended_cfg(_extended_cfg, _cfg_buf[0]);
+   if (err < 0) {
+   err = -ENODEV;
+   printf("dpni_prepare_extended_cfg() failed: %d\n", err);
+   goto err_prepare_extended_cfg;
+   }
+
memset(_cfg, 0, sizeof(dpni_cfg));
dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER |
   DPNI_OPT_MULTICAST_FILTER;
 
+   dpni_cfg.adv.ext_cfg_iova = (uint64_t)_cfg_buf[0];
err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, _cfg,
  _dpni->dpni_handle);
 
@@ -1057,11 +1068,12 @@ static int dpni_init(void)
return 0;
 
 err_close:
-   free(dflt_dpni);
 err_get_attr:
dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
 err_create:
+err_prepare_extended_cfg:
+   free(dflt_dpni);
 err_malloc:
return err;
 }
-- 
1.9.1


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[U-Boot] [PATCH v2 19/19] defconfig: dra74_evm: enable timer driver model

[Mugunthan V N]

Enable timer driver model for dra74_evm_defconfig as omap-timer
supports driver model.

Signed-off-by: Mugunthan V N 
---
 configs/dra74_evm_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig
index 394edbe..a68870e 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra74_evm_defconfig
@@ -19,3 +19,5 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 18/19] arm: dts: dra7-evm: add tick-timer to chosen node

[Mugunthan V N]

Specify timer2 to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N 
---
 arch/arm/dts/dra7-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index e4daa99..2568aad 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -16,6 +16,7 @@
 
chosen {
stdout-path = 
+   tick-timer = 
};
 
memory {
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 16/19] arm: dts: dra72-evm: add tick-timer to chosen node

[Mugunthan V N]

Specify timer2 to be used as tick-timer in chosen node.

Signed-off-by: Mugunthan V N 
---
 arch/arm/dts/dra72-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
index efb544c..6e3bbfd 100644
--- a/arch/arm/dts/dra72-evm.dts
+++ b/arch/arm/dts/dra72-evm.dts
@@ -16,6 +16,7 @@
 
chosen {
stdout-path = 
+   tick-timer = 
};
 
memory {
-- 
2.7.0.rc1.5.gf3adf45

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[U-Boot] [PATCH v2 17/19] defconfig: dra72_evm: enable timer driver model

[Mugunthan V N]

Enable timer driver model for dra72_evm_defconfig as omap-timer
supports driver model.

Signed-off-by: Mugunthan V N 
---
 configs/dra72_evm_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
index 3205bd5..530a25e 100644
--- a/configs/dra72_evm_defconfig
+++ b/configs/dra72_evm_defconfig
@@ -20,3 +20,5 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
-- 
2.7.0.rc1.5.gf3adf45

___
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[U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs

[Wills Wang]

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by: Wills Wang 
---

Changes in v3: None
Changes in v2: None

 arch/mips/Makefile  |1 +
 arch/mips/config.mk |1 +
 arch/mips/mach-ath79/Makefile   |9 +
 arch/mips/mach-ath79/ar933x/Makefile|6 +
 arch/mips/mach-ath79/ar933x/ddr_tap.S   |  268 ++
 arch/mips/mach-ath79/ar933x/lowlevel_init.S |  460 +
 arch/mips/mach-ath79/cpu.c  |  269 ++
 arch/mips/mach-ath79/dram.c |   27 +
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1144 +++
 arch/mips/mach-ath79/include/mach/ar933x_uart.h |   66 ++
 arch/mips/mach-ath79/include/mach/ath79.h   |  143 +++
 arch/mips/mach-ath79/include/mach/ddr.h |   13 +
 arch/mips/mach-ath79/reset.c|   55 ++
 13 files changed, 2462 insertions(+)
 create mode 100644 arch/mips/mach-ath79/Makefile
 create mode 100644 arch/mips/mach-ath79/ar933x/Makefile
 create mode 100644 arch/mips/mach-ath79/ar933x/ddr_tap.S
 create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S
 create mode 100644 arch/mips/mach-ath79/cpu.c
 create mode 100644 arch/mips/mach-ath79/dram.c
 create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ar933x_uart.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h
 create mode 100644 arch/mips/mach-ath79/reset.c

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 6a9f798..da5fa72 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_ARCH_ATH79) += ath79
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
 libs-y += $(machdirs)
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 3ebc202..fd50909 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
 cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc
 PLATFORM_CPPFLAGS += $(cpuflags-y)
 
 PLATFORM_CPPFLAGS += -D__MIPS__
diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile
new file mode 100644
index 000..bc0a41f
--- /dev/null
+++ b/arch/mips/mach-ath79/Makefile
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o
+
+obj-$(CONFIG_SOC_AR933X)   += ar933x/
diff --git a/arch/mips/mach-ath79/ar933x/Makefile 
b/arch/mips/mach-ath79/ar933x/Makefile
new file mode 100644
index 000..0da8fd4
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += lowlevel_init.o
+obj-y += ddr_tap.o
diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S 
b/arch/mips/mach-ath79/ar933x/ddr_tap.S
new file mode 100644
index 000..18c57de
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRAM_K0(x)  KSEG0ADDR(x)
+#define DRAM_K1(x)  KSEG1ADDR(x)
+
+   .text
+   .set noreorder
+
+LEAF(ddr_tap_init)
+   /* Tap settings for the DDR */
+   li  t0, 0x
+   li  t1, DRAM_K0(0x50)
+   sw  t0, 0x0(t1)
+   sw  t0, 0x4(t1)
+   sw  t0, 0x8(t1)
+   sw  t0, 0xc(t1)
+   nop
+   nop
+
+   li  t8, DRAM_K1(0x2000)
+   li  t0, 0x00
+   li  t1, 0x100
+0:
+   andit2, t0, 0x03
+   li  t3, 0x00
+   bne t2, t3,1f
+nop
+   li  t9, 0x
+   sw  t9, 0x0(t8)
+   b   2f
+nop
+1:
+   li  t3, 0x01
+   bne t2, t3,1f
+nop
+   li  t9, 0x
+   sw  t9, 0x0(t8)
+   b   2f
+nop
+1:
+   li  t3, 0x02
+   bne t2, t3,1f
+nop
+   li  t9, 0x
+   sw  t9, 0x0(t8)
+   b   2f
+nop
+1:
+   li  t3, 0x03
+   bne t2, t3,2f
+nop
+   li  t9, 0x
+   sw  t9, 0x0(t8)
+2:
+   andit2, t0, 0x0c
+   li  t3, 0x00
+   bne t2, t3,1f
+nop
+   li  t9, 0x
+   sw  t9, 0x4(t8)
+   b   2f
+nop
+1:
+   li  t3, 0x04
+   bne t2, t3,1f
+nop
+   li  t9, 0x
+   sw  t9, 0x4(t8)
+   b   2f
+nop

[U-Boot] [PATCH v3 2/4] mips: ath79: add serial driver for ar933x SOC

[Wills Wang]

Signed-off-by: Wills Wang 
---

Changes in v3: None
Changes in v2: None

 drivers/serial/Makefile|   1 +
 drivers/serial/serial_ar933x.c | 274 +
 2 files changed, 275 insertions(+)
 create mode 100644 drivers/serial/serial_ar933x.c

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dd87147..9a7ad89 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
new file mode 100644
index 000..6c0d726
--- /dev/null
+++ b/drivers/serial/serial_ar933x.c
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+   u32 baudrate;
+   u32 scale;
+   u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+   {600,   255,503},
+   {1200,  249,983},
+   {2400,  167,1321},
+   {4800,  87, 1384},
+   {9600,  45, 1447},
+   {14400, 53, 2548},
+   {19200, 22, 1447},
+   {28800, 26, 2548},
+   {38400, 28, 3649},
+   {56000, 7,  1468},
+   {57600, 34, 6606},
+   {115200,28, 10947},
+   {128000,6,  2936},
+   {153600,18, 9563},
+   {230400,16, 12834},
+   {25,4,  4096},
+   {256000,6,  5872},
+   {460800,7,  12079},
+   {576000,4,  9437},
+   {921600,3,  12079},
+   {100,   2,  9830},
+   {1152000,   2,  11324},
+   {150,   0,  4915},
+   {200,   0,  6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+   {600,   255,805},
+   {1200,  209,1321},
+   {2400,  104,1321},
+   {4800,  54, 1384},
+   {9600,  78, 3976},
+   {14400, 98, 7474},
+   {19200, 55, 5637},
+   {28800, 77, 11777},
+   {38400, 36, 7449},
+   {56000, 4,  1468},
+   {57600, 35, 10871},
+   {115200,20, 12683},
+   {128000,11, 8053},
+   {153600,9,  8053},
+   {230400,9,  12079},
+   {25,6,  9175},
+   {256000,5,  8053},
+   {460800,4,  12079},
+   {576000,3,  12079},
+   {921600,1,  9663},
+   {100,   1,  10485},
+   {1152000,   1,  12079},
+   {150,   0,  7864},
+   {200,   0,  10485},
+};
+
+static inline u32 ar933x_read(u32 base, u32 offset)
+{
+   return readl(KSEG1ADDR(base + offset));
+}
+
+static inline void ar933x_write(u32 base, u32 offset, u32 val)
+{
+   writel(val, KSEG1ADDR(base + offset));
+}
+
+static int ar933x_serial_init(void)
+{
+   u32 val;
+
+   /*
+* Set GPIO10 (UART_SO) as output and enable UART,
+* BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+*/
+   val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
+   val |= BIT(10);
+   ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);
+
+   val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
+   val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+   ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val);
+
+   /*
+* UART controller configuration:
+* - no DMA
+* - no interrupt
+* - DCE mode
+* - no flow control
+* - set RX ready oride
+* - set TX ready oride
+*/
+   val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
+   | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
+   ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val);
+   return 0;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+#else
+static void ar933x_serial_setbrg(void)
+{
+   int baudrate = gd->baudrate;
+#endif
+   u32 val, scale, step;
+   const struct ar933x_serial_baudrate *baudrate_table;
+   int i, baudrate_table_size;
+
+   val = ar933x_read(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP);
+   if (val & AR933X_BOOTSTRAP_REF_CLK_40) {
+   baudrate_table = baudrate_table_40mhz;
+   baudrate_table_size = ARRAY_SIZE(baudrate_table_40mhz);
+

[U-Boot] [PATCH v3 4/4] mips: ath79: add AP121 reference board

[Wills Wang]

Signed-off-by: Wills Wang 
---

Changes in v3:
- Convert serial driver to driver model
- Convert spi driver to driver model
- Add support for device tree
- Move SoC specific header files into arch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertion

Changes in v2:
- Move all SoC specific header files into arch/mips/include/asm/arch-ath79
- Check SOC type and extract common code into arch/mips/mach-ath79
- Add a compatible spi driver
- Move serial driver code into drivers/serial
- Add a reference board implemention

 arch/mips/Kconfig |  8 +
 arch/mips/dts/Makefile|  2 +-
 arch/mips/dts/ap121.dts   | 37 
 arch/mips/dts/ar933x.dtsi | 64 +++
 board/ath79/ap121/Kconfig | 15 
 board/ath79/ap121/MAINTAINERS |  6 
 board/ath79/ap121/Makefile|  8 +
 board/ath79/ap121/README  | 18 ++
 board/ath79/ap121/ap121.c | 18 ++
 board/ath79/ap121/config.mk   | 16 +
 configs/ap121_defconfig   | 42 +++
 include/configs/ap121.h   | 79 +++
 12 files changed, 312 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/ap121.dts
 create mode 100644 arch/mips/dts/ar933x.dtsi
 create mode 100644 board/ath79/ap121/Kconfig
 create mode 100644 board/ath79/ap121/MAINTAINERS
 create mode 100644 board/ath79/ap121/Makefile
 create mode 100644 board/ath79/ap121/README
 create mode 100644 board/ath79/ap121/ap121.c
 create mode 100644 board/ath79/ap121/config.mk
 create mode 100644 configs/ap121_defconfig
 create mode 100644 include/configs/ap121.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7f7e258..09b8709 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -51,6 +51,13 @@ config TARGET_PB1X00
select SUPPORTS_CPU_MIPS32_R2
select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config TARGET_AP121
+   bool "Support ap121"
+   select SUPPORTS_BIG_ENDIAN
+   select SUPPORTS_CPU_MIPS32_R1
+   select SUPPORTS_CPU_MIPS32_R2
+   select SYS_MIPS_CACHE_INIT_RAM_LOAD
+
 
 endchoice
 
@@ -59,6 +66,7 @@ source "board/imgtec/malta/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
+source "board/ath79/ap121/Kconfig"
 
 if MIPS
 
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 47b6eb5..6f8b413 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-dtb-y +=
+dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
new file mode 100644
index 000..769458a
--- /dev/null
+++ b/arch/mips/dts/ap121.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+#include "ar933x.dtsi"
+
+/ {
+   model = "AP121 Reference Board";
+   compatible = "ath79,ap121", "ath79,ar933x";
+
+   aliases {
+   spi0 = 
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   clock-frequency = <2500>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   spi-max-frequency = <2500>;
+   status = "okay";
+   spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "spi-flash";
+   memory-map = <0x9f00 0x0080>;
+   spi-max-frequency = <2500>;
+   reg = <0>;
+   };
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
new file mode 100644
index 000..64b30f7
--- /dev/null
+++ b/arch/mips/dts/ar933x.dtsi
@@ -0,0 +1,64 @@
+#include "skeleton.dtsi"
+
+/ {
+   compatible = "ath79,ar933x";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "mips,mips24Kc";
+   reg = <0>;
+   };
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   xtal: xtal {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-output-names = "xtal";
+   };
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   ranges;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   apb {
+   compatible = "simple-bus";
+   ranges;
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   uart0: uart@1802 {
+   compatible = "ath79,ar933x-uart";
+   reg = 

[U-Boot] [PATCH v3 3/4] mips: ath79: add spi driver

[Wills Wang]

Signed-off-by: Wills Wang 
---

Changes in v3: None
Changes in v2: None

 drivers/spi/Kconfig |   6 ++
 drivers/spi/Makefile|   1 +
 drivers/spi/ath79_spi.c | 211 
 3 files changed, 218 insertions(+)
 create mode 100644 drivers/spi/ath79_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2cdb110..04a24ab 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -23,6 +23,12 @@ config ALTERA_SPI
  IP core. Please find details on the "Embedded Peripherals IP
  User Guide" of Altera.
 
+config ATH79_SPI
+   bool "Atheros SPI driver"
+   help
+ Enable the Atheros SPI driver, used to access SPI NOR flash and
+ other SPI peripherals on Atheros ar7xxx/ar9xxx SoCs.
+
 config CADENCE_QSPI
bool "Cadence QSPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3eca745..7fb2926 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
new file mode 100644
index 000..ddfc807
--- /dev/null
+++ b/drivers/spi/ath79_spi.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define SPI_CLK_DIV(x) ((x >> 1) - 1)
+
+struct ath79_spi_platdata {
+   void __iomem *regs;
+};
+
+struct ath79_spi_priv {
+   void __iomem *regs;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{
+   struct ath79_spi_priv *priv = dev_get_priv(bus);
+   const void __iomem *base = (void __iomem *)KSEG1ADDR(priv->regs);
+   return readl(base + offset);
+}
+
+static inline void ath79_spi_write(struct udevice *bus, u32 val,
+   u32 
offset)
+{
+   struct ath79_spi_priv *priv = dev_get_priv(bus);
+   const void __iomem *base = (void __iomem *)KSEG1ADDR(priv->regs);
+   writel(val, base + offset);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+   return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+   return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+   const void *dout, void *din, unsigned 
long flags)
+{
+   struct udevice *bus = dev->parent;
+   struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
+   uint8_t *rx = din;
+   const uint8_t *tx = dout;
+   uint8_t curbyte, curbitlen, restbits;
+   uint32_t bytes = bitlen / 8;
+   uint32_t out;
+   uint32_t in;
+
+   if (flags & SPI_XFER_BEGIN) {
+   ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+   ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC);
+   }
+
+   restbits = (bitlen % 8);
+   if (restbits)
+   bytes++;
+
+   /* enable chip select */
+   out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs));
+   while (bytes--) {
+   curbyte = 0;
+   if (tx)
+   curbyte = *tx++;
+
+   if (restbits) {
+   curbitlen = restbits;
+   curbyte <<= 8 - restbits;
+   } else {
+   curbitlen = 8;
+   }
+
+   /* clock starts at inactive polarity */
+   for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+   if (curbyte & 0x80)
+   out |= AR71XX_SPI_IOC_DO;
+   else
+   out &= ~(AR71XX_SPI_IOC_DO);
+
+   /* setup MSB (to slave) on trailing edge */
+   ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC);
+   ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK,
+   AR71XX_SPI_REG_IOC);
+   curbyte <<= 1;
+   }
+
+   in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
+   if (rx) {
+   if (restbits)
+   *rx++ = (in << (8 - restbits));
+   else
+   *rx++ = in;
+   }
+   }
+
+   if (flags & SPI_XFER_END) {
+   ath79_spi_write(bus, AR71XX_SPI_IOC_CS(slave->cs),
+   AR71XX_SPI_REG_IOC);
+   

[U-Boot] [PATCH v3 0/4] add support for atheros ath79 based SOCs

[Wills Wang]

These series of patch add support for atheros ath79 based SOCs in u-boot,
at the present moment it's just available for ar933x chip.

Changes in v3:
- Convert serial driver to driver model
- Convert spi driver to driver model
- Add support for device tree
- Move SoC specific header files into arch/mips/mach-ath79/include/mach
- Optimize assembly code
- Same code style convertion

Changes in v2:
- Move all SoC specific header files into arch/mips/include/asm/arch-ath79
- Check SOC type and extract common code into arch/mips/mach-ath79
- Add a compatible spi driver
- Move serial driver code into drivers/serial
- Add a reference board implemention

Wills Wang (4):
  mips: add base support for atheros ath79 based SOCs
  mips: ath79: add serial driver for ar933x SOC
  mips: ath79: add spi driver
  mips: ath79: add AP121 reference board

 arch/mips/Kconfig   |8 +
 arch/mips/Makefile  |1 +
 arch/mips/config.mk |1 +
 arch/mips/dts/Makefile  |2 +-
 arch/mips/dts/ap121.dts |   37 +
 arch/mips/dts/ar933x.dtsi   |   64 ++
 arch/mips/mach-ath79/Makefile   |9 +
 arch/mips/mach-ath79/ar933x/Makefile|6 +
 arch/mips/mach-ath79/ar933x/ddr_tap.S   |  268 ++
 arch/mips/mach-ath79/ar933x/lowlevel_init.S |  460 +
 arch/mips/mach-ath79/cpu.c  |  269 ++
 arch/mips/mach-ath79/dram.c |   27 +
 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1144 +++
 arch/mips/mach-ath79/include/mach/ar933x_uart.h |   66 ++
 arch/mips/mach-ath79/include/mach/ath79.h   |  143 +++
 arch/mips/mach-ath79/include/mach/ddr.h |   13 +
 arch/mips/mach-ath79/reset.c|   55 ++
 board/ath79/ap121/Kconfig   |   15 +
 board/ath79/ap121/MAINTAINERS   |6 +
 board/ath79/ap121/Makefile  |8 +
 board/ath79/ap121/README|   18 +
 board/ath79/ap121/ap121.c   |   18 +
 board/ath79/ap121/config.mk |   16 +
 configs/ap121_defconfig |   42 +
 drivers/serial/Makefile |1 +
 drivers/serial/serial_ar933x.c  |  274 ++
 drivers/spi/Kconfig |6 +
 drivers/spi/Makefile|1 +
 drivers/spi/ath79_spi.c |  211 +
 include/configs/ap121.h |   79 ++
 30 files changed, 3267 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/dts/ap121.dts
 create mode 100644 arch/mips/dts/ar933x.dtsi
 create mode 100644 arch/mips/mach-ath79/Makefile
 create mode 100644 arch/mips/mach-ath79/ar933x/Makefile
 create mode 100644 arch/mips/mach-ath79/ar933x/ddr_tap.S
 create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S
 create mode 100644 arch/mips/mach-ath79/cpu.c
 create mode 100644 arch/mips/mach-ath79/dram.c
 create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ar933x_uart.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h
 create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h
 create mode 100644 arch/mips/mach-ath79/reset.c
 create mode 100644 board/ath79/ap121/Kconfig
 create mode 100644 board/ath79/ap121/MAINTAINERS
 create mode 100644 board/ath79/ap121/Makefile
 create mode 100644 board/ath79/ap121/README
 create mode 100644 board/ath79/ap121/ap121.c
 create mode 100644 board/ath79/ap121/config.mk
 create mode 100644 configs/ap121_defconfig
 create mode 100644 drivers/serial/serial_ar933x.c
 create mode 100644 drivers/spi/ath79_spi.c
 create mode 100644 include/configs/ap121.h

-- 
1.9.1

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Re: [U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs

[Marek Vasut]

On Thursday, December 24, 2015 at 12:22:00 PM, Wills Wang wrote:
> This patch enable work for ar933x SOC, tested on ar9331 board.
> 
> Signed-off-by: Wills Wang 

[...]

> diff --git a/arch/mips/config.mk b/arch/mips/config.mk
> index 3ebc202..fd50909 100644
> --- a/arch/mips/config.mk
> +++ b/arch/mips/config.mk
> @@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32
> -Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2
> -Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64
> -Wa,-mips64
>  cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
> +cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc

You can just tune it for MIPS32_R2 , it will be compatible with older toolchains
too. I don't think there is much benefit in being so explicit and using mips24kc
tuning.

>  PLATFORM_CPPFLAGS += $(cpuflags-y)
> 
>  PLATFORM_CPPFLAGS += -D__MIPS__

[...]

> diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S
> b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644
> index 000..18c57de
> --- /dev/null
> +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S
> @@ -0,0 +1,268 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, 
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define DRAM_K0(x)  KSEG0ADDR(x)
> +#define DRAM_K1(x)  KSEG1ADDR(x)
> +
> + .text
> + .set noreorder
> +
> +LEAF(ddr_tap_init)
> + /* Tap settings for the DDR */
> + li  t0, 0x
> + li  t1, DRAM_K0(0x50)
> + sw  t0, 0x0(t1)
> + sw  t0, 0x4(t1)
> + sw  t0, 0x8(t1)
> + sw  t0, 0xc(t1)
> + nop
> + nop
> +
> + li  t8, DRAM_K1(0x2000)
> + li  t0, 0x00
> + li  t1, 0x100
> +0:
> + andit2, t0, 0x03
> + li  t3, 0x00
> + bne t2, t3,1f
> +  nop
> + li  t9, 0x
> + sw  t9, 0x0(t8)
> + b   2f
> +  nop

Please rewrite this into C, I believe it should be pretty easy.

[...]

> diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S
> b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644
> index 000..72509ca
> --- /dev/null
> +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
> @@ -0,0 +1,460 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define SET_BIT(val, bit)   ((val) | (1 << (bit)))
> +#define SET_PLL_PD(val) SET_BIT(val, 30)
> +#define AHB_DIV_TO_4(val)   SET_BIT(SET_BIT(val, 15), 16)
> +#define PLL_BYPASS(val) SET_BIT(val, 2)
> +
> +#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
> + (((0x3F & divint) << 10) | \
> + ((0x1F & refdiv) << 16) | \
> + ((0x1 & range)   << 21) | \
> + ((0x7 & outdiv)  << 23) )
> +
> +#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
> +(((0x3 & (cpudiv - 1)) << 5)  | \
> +((0x3 & (ddrdiv - 1)) << 10) | \
> +((0x3 & (ahbdiv - 1)) << 15) )
> +
> +/*
> + * PLL_CPU_CONFIG_VAL
> + *
> + * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
> + * After PLL configuration we need to clear this bit
> + *
> + * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
> + *
> + * bits 10..15  (6bit)  DIV_INT (Integer part of the DIV to CPU PLL)
> + *  =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
> + * bits 16..20  (5bit)  REFDIV  (Reference clock divider)
> + *  =>  1   (0x1)   [Must start at values 1]
> + * bits 21  (1bit)  RANGE   (VCO frequency range of the CPU PLL)
> + *  =>  0   (0x0)   [Doesn't impact clock values]
> + * bits 23..25  (3bit)  OUTDIV  (Ratio between VCO and PLL output)
> + *  =>  1   (0x1)   [0 is illegal!]
> + *  PLLOUT = VCOOUT * (1/2^OUTDIV)
> + */
> +/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
> +#define PLL_CPU_CONFIG_VAL_40M  MK_PLL_CONF(20, 1, 0, 1)
> +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
> +#define PLL_CPU_CONFIG_VAL_25M  MK_PLL_CONF(32, 1, 0, 1)
> +
> +/*
> + * PLL_CLK_CONTROL_VAL
> + *
> + * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
> + * After PLL configuration we need to clear this bit
> + *
> + * Values written into CPU Clock Control Register CLOCK_CONTROL
> + *
> + * bits 2   (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test.
> + *  Software must enable the CPU PLL for normal and
> + *  then set this bit to 0)
> + * bits 5..6(2bit)  CPU_POST_DIV=>  0   (DEFAULT, Ratio = 1)
> + *  CPU_CLK = PLLOUT / CPU_POST_DIV
> + * bits 10..11  (2bit)  DDR_POST_DIV=>  0   (DEFAULT, Ratio = 1)
> + *  DDR_CLK = PLLOUT / DDR_POST_DIV
> + * bits 15..16  (2bit)  

Re: [U-Boot] [PATCH v3 3/4] mips: ath79: add spi driver

[Marek Vasut]

On Thursday, December 24, 2015 at 12:22:02 PM, Wills Wang wrote:
> Signed-off-by: Wills Wang 
> ---
[...]

> diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
> new file mode 100644
> index 000..ddfc807
> --- /dev/null
> +++ b/drivers/spi/ath79_spi.c
> @@ -0,0 +1,211 @@
> +/*
> + * (C) Copyright 2015
> + * Wills Wang, 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
> +#define SPI_CLK_DIV(x) ((x >> 1) - 1)

The x needs parenthesis ... (((x) >> 1) - 1)

> +
> +struct ath79_spi_platdata {
> + void __iomem *regs;
> +};
> +
> +struct ath79_spi_priv {
> + void __iomem *regs;
> +};
> +
> +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + const void __iomem *base = (void __iomem *)KSEG1ADDR(priv->regs);
> + return readl(base + offset);

Just make this readl(KSEG1ADDR(...)) ?

> +}
> +
> +static inline void ath79_spi_write(struct udevice *bus, u32 val,
> + u32 
offset)
> +{
> + struct ath79_spi_priv *priv = dev_get_priv(bus);
> + const void __iomem *base = (void __iomem *)KSEG1ADDR(priv->regs);
> + writel(val, base + offset);

DTTO here.

[...]
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Re: [U-Boot] [PATCH v3 0/4] add support for atheros ath79 based SOCs

[Marek Vasut]

On Thursday, December 24, 2015 at 12:21:59 PM, Wills Wang wrote:
> These series of patch add support for atheros ath79 based SOCs in u-boot,
> at the present moment it's just available for ar933x chip.
> 
> Changes in v3:
> - Convert serial driver to driver model
> - Convert spi driver to driver model
> - Add support for device tree
> - Move SoC specific header files into arch/mips/mach-ath79/include/mach
> - Optimize assembly code
> - Same code style convertion

Cool, thanks! Just some minor nitpicks, but nothing really heavy.
I am looking forward to running this on my AR933x arduino yun, which I bought
exactly and only for this purpose :)

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs

[Wills Wang]

On 12/24/2015 07:52 PM, Marek Vasut wrote:

On Thursday, December 24, 2015 at 12:22:00 PM, Wills Wang wrote:

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by: Wills Wang 

[...]


diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 3ebc202..fd50909 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32
-Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2
-Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64
-Wa,-mips64
  cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc

You can just tune it for MIPS32_R2 , it will be compatible with older toolchains
too. I don't think there is much benefit in being so explicit and using mips24kc
tuning.


  PLATFORM_CPPFLAGS += $(cpuflags-y)

  PLATFORM_CPPFLAGS += -D__MIPS__

[...]


diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S
b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644
index 000..18c57de
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRAM_K0(x)  KSEG0ADDR(x)
+#define DRAM_K1(x)  KSEG1ADDR(x)
+
+   .text
+   .set noreorder
+
+LEAF(ddr_tap_init)
+   /* Tap settings for the DDR */
+   li  t0, 0x
+   li  t1, DRAM_K0(0x50)
+   sw  t0, 0x0(t1)
+   sw  t0, 0x4(t1)
+   sw  t0, 0x8(t1)
+   sw  t0, 0xc(t1)
+   nop
+   nop
+
+   li  t8, DRAM_K1(0x2000)
+   li  t0, 0x00
+   li  t1, 0x100
+0:
+   andit2, t0, 0x03
+   li  t3, 0x00
+   bne t2, t3,1f
+nop
+   li  t9, 0x
+   sw  t9, 0x0(t8)
+   b   2f
+nop

Please rewrite this into C, I believe it should be pretty easy.

[...]


diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S
b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644
index 000..72509ca
--- /dev/null
+++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SET_BIT(val, bit)   ((val) | (1 << (bit)))
+#define SET_PLL_PD(val) SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val)   SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val) SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+ (((0x3F & divint) << 10) | \
+ ((0x1F & refdiv) << 16) | \
+ ((0x1 & range)   << 21) | \
+ ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+(((0x3 & (cpudiv - 1)) << 5)  | \
+((0x3 & (ddrdiv - 1)) << 10) | \
+((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15  (6bit)  DIV_INT (Integer part of the DIV to CPU PLL)
+ *  =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
+ * bits 16..20  (5bit)  REFDIV  (Reference clock divider)
+ *  =>  1   (0x1)   [Must start at values 1]
+ * bits 21  (1bit)  RANGE   (VCO frequency range of the CPU PLL)
+ *  =>  0   (0x0)   [Doesn't impact clock values]
+ * bits 23..25  (3bit)  OUTDIV  (Ratio between VCO and PLL output)
+ *  =>  1   (0x1)   [0 is illegal!]
+ *  PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M  MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M  MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2   (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test.
+ *  Software must enable the CPU PLL for normal and
+ *  then set this bit to 0)
+ * bits 5..6(2bit)  CPU_POST_DIV=>  0   (DEFAULT, Ratio = 1)
+ *  CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11  (2bit)  DDR_POST_DIV=>  0   (DEFAULT, Ratio = 1)
+ *  DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16  (2bit)  AHB_POST_DIV=>  1   (DEFAULT, Ratio = 2)
+ *  AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+.text
+.set 

Re: [U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs

[Marek Vasut]

On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote:

[...]

> >> +LEAF(lowlevel_init)
> >> +   /* These three WLAN_RESET will avoid original issue */
> >> +li  t3, 0x03
> >> +1:
> >> +li  t0, KSEG1ADDR(AR71XX_RESET_BASE)
> >> +lw  t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> +ori t1, t1, 0x0800
> >> +sw  t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> +nop
> >> +lw  t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> +li  t2, 0xf7ff
> >> +and t1, t1, t2
> >> +sw  t1, AR933X_RESET_REG_RESET_MODULE(t0)
> >> +nop
> >> +addit3, t3, -1
> >> +bnezt3, 1b
> >> + nop
> > 
> > This should be also easy to rewrite into C , right ?
> 
> C runtime environment is not available.
> C stack is not ready before DDR has initialized.

Just point the stack into a locked cacheline or some onchip RAM and there
you have a C runtime. That should be pretty easy :)

[...]

> >> +phys_size_t initdram(int board_type)
> >> +{
> >> +  uint8_t *addr, *p;
> >> +  int i;
> >> +
> >> +  ddr_tap_init();
> >> +  addr = (uint8_t *)KSEG1;
> >> +  *addr = 0x77;
> >> +  for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
> >> +  p += 0x100;
> >> +  *p = i;
> >> +  if (*addr != 0x77)
> >> +  break;
> >> +  }
> > 
> > What is this and how does it work ?
> 
> Physical memory was mapped circularly for this chip.

Can you please expand on that ? I am not as deep in this chip as you are,
so please explain it to me in a bit more detail.

> >> +  return (phys_size_t)(p - addr);
> >> +}
> > 

[...]

> >> +  if (reg) {
> >> +  val = RST_READ(reg);
> >> +  val |= AR71XX_RESET_FULL_CHIP;
> >> +  RST_WRITE(reg, val);
> > 
> > setbits_le32() please.
> 
> Macro setbits_le32() is not available for MIPS architecture.

You can always add them :)

> Other, I don't think there is better in being so explicit and using
> little-endian.

I believe your register accesses should have correct endianness exactly
beause mips can be both endian.
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