Re: [U-Boot] [PATCH 16/17] arm: ls1021atwr: Disable CONFIG_E1000 temporarily
Hi York, On Wed, Jan 13, 2016 at 1:52 AM, York Sun wrote: > > > On 01/11/2016 10:38 PM, Bin Meng wrote: >> Before we switch to use driver model ethernet support, disable >> CONFIG_E1000 temporarily as with driver model ethernet, E1000 >> driver depends on driver model PCI which is not ready on this >> board yet. >> > > Any idea when PCI/E1000 can be enabled? > Next on my todo list is to convert layerscape pcie to driver model. But I suspect we should consolidate that driver with imx pcie driver first. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/8] serial: lpuart: Add driver model serial support
Hi Bhuvan, On Wed, Jan 13, 2016 at 1:49 PM, Bhuvanchandra DV wrote: > Hi Bin, > > With reference to the discussion here[1]. > > Unfortunately the lpuart driver is now broken for legacy code and also > the driver doesn't > work with serial driver model enabled on Toradex Colibri VF50/VF61, > Freescale VF610twr > and Phytec pcm052 boards. Did some one tested this patchset on these boards ? I will fix the legacy code build in v2. About serial driver model not working on these boards, is that the caused by no device tree of these boards? > > [1] http://lists.denx.de/pipermail/u-boot/2016-January/240781.html > > Best regards, > Bhuvan > Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/6] rockchip: kylin: Check fastboot request
Hi Simon,
Just know our guys are upstreaming our reboot mode support with our
legacy reboot mode definitions(in our legacy loader & kernel):
https://lkml.org/lkml/2015/12/21/161
and that serial seems close to get accepted, so i think maybe i should
use that definitions too...
On 2016-1-8 18:33, Jeffy Chen wrote:
We will save boot mode flag in grf's os_reg[0], if fastboot
requested or fastboot key pressed, try to enter fastboot mode
at preboot stage.
Signed-off-by: Jeffy Chen
Acked-by: Simon Glass
---
Changes in v2: None
board/kylin/kylin_rk3036/kylin_rk3036.c | 32
include/configs/kylin_rk3036.h | 3 +++
2 files changed, 35 insertions(+)
diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c
b/board/kylin/kylin_rk3036/kylin_rk3036.c
index 40d6b52..df2c123 100644
--- a/board/kylin/kylin_rk3036/kylin_rk3036.c
+++ b/board/kylin/kylin_rk3036/kylin_rk3036.c
@@ -8,10 +8,15 @@
#include
#include
#include
+#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+#define GRF_BASE 0x20008000
+static struct rk3036_grf * const grf = (void *)GRF_BASE;
+
void get_ddr_config(struct rk3036_ddr_config *config)
{
/* K4B4G1646Q config */
@@ -28,6 +33,33 @@ void get_ddr_config(struct rk3036_ddr_config *config)
config->bw = 1;
}
+#define FASTBOOT_KEY_GPIO 93
+#define ROCKCHIP_BOOT_MODE_NORMAL 0
+#define ROCKCHIP_BOOT_MODE_FASTBOOT1
+
+int fastboot_key_pressed(void)
+{
+ gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
+ gpio_direction_input(FASTBOOT_KEY_GPIO);
+ return !gpio_get_value(FASTBOOT_KEY_GPIO);
+}
+
+int board_late_init(void)
+{
+ int boot_mode = readl(&grf->os_reg[0]);
+
+ /* Clear boot mode */
+ writel(ROCKCHIP_BOOT_MODE_NORMAL, &grf->os_reg[0]);
+
+ if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT ||
+ fastboot_key_pressed()) {
+ printf("enter fastboot!\n");
+ setenv("preboot", "setenv preboot; fastboot usb0");
+ }
+
+ return 0;
+}
+
int board_init(void)
{
return 0;
diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
index 49997ec..424e81b 100644
--- a/include/configs/kylin_rk3036.h
+++ b/include/configs/kylin_rk3036.h
@@ -39,6 +39,9 @@
"mmcpart=5\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_PREBOOT
+
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_SYS_HUSH_PARSER
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Re: [U-Boot] axm SPL image too big
Hello Albert, Am 12.01.2016 um 15:25 schrieb Albert ARIBAUD: Hello Heiko, On Tue, 12 Jan 2016 11:48:17 +0100, Heiko Schocher wrote: Hello Albert, Am 12.01.2016 um 11:26 schrieb Albert ARIBAUD: (cc:ing Heiko as the maintainer for axm/taurus) Hello, AXM is currently the only board failing 'buildman arm aarch64': +arm-unknown-linux-gnueabi-ld.bfd: SPL image too big +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +make: *** [sub-make] Error 2 Apparently SPL is already being built in Thumb instruction set, so no way to gain anything that way. I know, it was tricky to get SPL into 4k ... What else can we do to get SPL size back under limit? Hmm.. what is your exact toolchain? I tested with the buildman-fetched gcc, -v gives 'gcc version 4.9.0 (GCC)'. I've deleted the toolchain and re-fetched it again through buildman in case there was an issue with the install, and am getting the same result. I've also tested with the latest ARM gcc package available with Ubuntu, that is, 'gcc version 5.2.1 20151010 (Ubuntu 5.2.1-22ubuntu1)', again with the same result. I see for the axm board: With eldk-5.4 pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot textdata bss dec hex filename 212583 23792 23552 259927 3f757 u-boot pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl textdata bss dec hex filename 1456812121140 169204218 spl/u-boot-spl pollux:u-boot-smartweb hs [master] $ Confirmed right now that with eldk 5.4's gcc 4.7.2 axm builds fine. With eldk-5.5 pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot textdata bss dec hex filename 210690 23672 23556 257918 3ef7e u-boot pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl textdata bss dec hex filename 1447212121140 1682441b8 spl/u-boot-spl pollux:u-boot-smartweb hs [master] $ Confirmed right now that with eldk 5.5's (or 5.5.3's) gcc 4.8.1 axm builds fine. The issue appears with gcc 4.9 and 5.2.1 (and I suspect any version between 4.9 and 5.2.1 and beyond 5.2.1) Yes :-( Tested with linaro 5.2 using: hs@localhost:u-boot [master] $ arm-unknown-linux-gnueabi-gcc --version arm-unknown-linux-gnueabi-gcc (crosstool-NG 1.21.0) 5.2.1 20151005 Copyright (C) 2015 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. hs@localhost:u-boot [master] $ and size is: hs@localhost:u-boot [master] $ arm-unknown-linux-gnueabi-size spl/u-boot-spl textdata bss dec hex filename 1473412121140 1708642be spl/u-boot-spl hs@localhost:u-boot [master] $ aprox 0x100 bigger than with eldk-5.5 ... :-( But I have only 16k sram on at91sam9g20 ... Ok, there are 2 such areas, but between them is a hole :-( damn... Adding Andreas to cc, may he has an idea? Do gcc 4.9 need other settings for optimizing code? bye, Heiko -- -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv3 4/4] igep00x0: UBIize
Hello Ladislav,
Am 12.01.2016 um 23:17 schrieb Ladislav Michl:
Hi Heiko,
On Tue, Jan 12, 2016 at 10:08:21AM +0100, Heiko Schocher wrote:
Am 11.01.2016 um 13:58 schrieb Ladislav Michl:
On Mon, Jan 11, 2016 at 07:20:06AM +0100, Heiko Schocher wrote:
Beside of that, this patch does not apply ...
Ah, igep00x0 part is based on top of this:
http://lists.denx.de/pipermail/u-boot/2016-January/240013.html
I silently hoped to be applied for 2016.01 release, but never mind :)
;-)
Ah, I added them to my automated build, and now it works again :-D
BTW: patch "[U-Boot,PATCHv2,2/5] igep00x0: Cleanup ethernet support"
has a checkpatch warning, search in
http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/43/steps/shell/logs/tbotlog
for "2016-01-12 07:47:08,369"
Hmm, I do not agree with warning as I consider code pretty readable :)
Its a warning only ...
Yes, I am also unhappy to adding blanks in such cases ... maybe this
should be discussed in a seperate thread?
Anyway, there is similar "unaligned case" few lines bellow. Perhaps send
additional patch to fix them both?
If you fix it, then please in a v4 patch, thanks!
Now assumption is that once board switches to UBI, loading u-boot or kernel
>from bare flash does not make a sense anymore, so with CONFIG_SPL_UBI
all that code in spl_nor.c (reevaluate?!), spl_nand.c and spl_onenand.c
is not used in favour of spl_ubi.c. As ubispl can load volumes by volume id
I thought about this change too, and I think your assumption is OK
here. Let us bring in this change, and if someone has other needs,
we have to look again at this place .. but I think, if switching to
use UBI, than it makes no sense to read in raw mode ...
Other opinions?
and not by name, it is bringing some inconsistencies with for example ubi
environment code, which is using volume names. Is it worth fixing?
It would be nice to have ... yes, if it is easy to do? Also we must
have a look at the codesize.
It seems Thomas had a good reason to use volume ids, see ubi_scan_vid_hdr
called from ipl_scan.
Yes indeed ... so let it as it is.
All that ubispl_info structure is board specific and there is not much left
besides initializing it. Also volumes can differ per board basis, so
providing common function is somewhat questionable. However here it is,
just to show how does it look like. Suggestions are very welcome as silence
around this part of patch is a bit suspicious ;-)
Questions are coming if there are users ;-)
I vote for bringing this in, and we will see, where we have to make
things more configurable ... some nitpicks below ...
Okay, I need to be able to load also bare zImage. This change is independent
and possibly controversial, so I'll put it here for disscusion :)
Please post it as a RFC patch seperate, with for example Marek in Cc,
so he can speak up here too.
commit c092b3c0627dd8d4b3f3d756c58b53fcf205587f
Author: Ladislav Michl
Date: Tue Jan 12 16:37:04 2016 +0100
spl: zImage support in Falcon mode
Other payload than uImage is currently considered to be raw U-Boot
image. Check also for zImage in Falcon mode.
Signed-off-by: Ladislav Michl
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f3db7b5..07a9019 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -26,11 +26,13 @@ endif
obj-$(CONFIG_CPU_V7M) += cmd_boot.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += zimage.o
obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
else
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
endif
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index a477cae..fbfc0ad 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -348,38 +348,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
return 0;
}
-#ifdef CONFIG_CMD_BOOTZ
-
-struct zimage_header {
- uint32_tcode[9];
- uint32_tzi_magic;
- uint32_tzi_start;
- uint32_tzi_end;
-};
-
-#defineLINUX_ARM_ZIMAGE_MAGIC 0x016f2818
-
-int bootz_setup(ulong image, ulong *start, ulong *end)
-{
- struct zimage_header *zi;
-
- zi = (struct zimage_header *)map_sysmem(image, 0);
- if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
- puts("Bad Linux ARM zImage magic!\n");
- return 1;
- }
-
- *start = zi->zi_start;
- *end = zi->zi_end;
-
- printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start,
- *end);
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_BOOTZ */
-
#if defined(CONFIG_BOOTM_VXWORKS)
void boot_prep_vxworks(bootm_headers_t *images)
{
diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c
new file mode 100644
index 000..f870d72
--- /dev/null
+++ b/arc
[U-Boot] [PATCH] usb: add clock support for generic EHCI
This driver is designed so generic that clock should also be handled
in a generic way.
Like the one in Linux (drivers/usb/host/ehci-platform.c), get and
enable clock(s) via Device Tree if present.
Signed-off-by: Masahiro Yamada
---
This patch depends on new features that are still under review:
http://patchwork.ozlabs.org/patch/566809/
http://patchwork.ozlabs.org/patch/566812/
Please hold this one until they go in.
drivers/usb/host/ehci-generic.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 1292caa..44bf70b 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -5,9 +5,12 @@
*/
#include
+#include
#include
#include "ehci.h"
+#define EHCI_MAX_CLKS 3
+
/*
* Even though here we don't explicitly use "struct ehci_ctrl"
* ehci_register() expects it to be the first thing that resides in
@@ -15,12 +18,24 @@
*/
struct generic_ehci {
struct ehci_ctrl ctrl;
+ struct udevice *clk_devs[EHCI_MAX_CLKS];
+ int clk_ids[EHCI_MAX_CLKS];
};
static int ehci_usb_probe(struct udevice *dev)
{
+ struct generic_ehci *priv = dev_get_priv(dev);
struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
struct ehci_hcor *hcor;
+ int i;
+
+ for (i = 0; i < EHCI_MAX_CLKS; i++) {
+ priv->clk_ids[i] = fdt_clk_get(dev, i, &priv->clk_devs[i]);
+ if (priv->clk_ids[i] < 0)
+ break;
+ if (clk_enable(priv->clk_devs[i], priv->clk_ids[i]))
+ printf("failed to enable clock %d\n", priv->clk_ids[i]);
+ }
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
--
1.9.1
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[U-Boot] [PATCH v2 0/6] clk: some fixes, device tree support, new features
Masahiro Yamada (6): clk: fix comments in include/clk.h clk: add needed include and declaration to include/clk.h clk: add static qualifier to local functions clk: change the type of return value to long clk: add API to enable clock clk: add device tree support for clock framework drivers/clk/clk-uclass.c | 51 --- drivers/clk/clk_rk3036.c | 6 ++-- drivers/clk/clk_rk3288.c | 6 ++-- drivers/clk/clk_sandbox.c | 8 ++--- include/clk.h | 87 +-- 5 files changed, 126 insertions(+), 32 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/6] clk: change the type of return value to long
The comments in include/clk.h state "or -ve error code" for these
functions, and actually the functions return negative error code
here and there. Returning unsigned value is not suitable.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
drivers/clk/clk-uclass.c | 8
drivers/clk/clk_rk3036.c | 6 +++---
drivers/clk/clk_rk3288.c | 6 +++---
drivers/clk/clk_sandbox.c | 9 -
include/clk.h | 16
5 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 73dfd7d..a5bef59 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -12,7 +12,7 @@
#include
#include
-ulong clk_get_rate(struct udevice *dev)
+long clk_get_rate(struct udevice *dev)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -22,7 +22,7 @@ ulong clk_get_rate(struct udevice *dev)
return ops->get_rate(dev);
}
-ulong clk_set_rate(struct udevice *dev, ulong rate)
+long clk_set_rate(struct udevice *dev, ulong rate)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -32,7 +32,7 @@ ulong clk_set_rate(struct udevice *dev, ulong rate)
return ops->set_rate(dev, rate);
}
-ulong clk_get_periph_rate(struct udevice *dev, int periph)
+long clk_get_periph_rate(struct udevice *dev, int periph)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -42,7 +42,7 @@ ulong clk_get_periph_rate(struct udevice *dev, int periph)
return ops->get_periph_rate(dev, periph);
}
-ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+long clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
{
struct clk_ops *ops = clk_get_ops(dev);
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index f650810..8613123 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -298,7 +298,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru,
uint clk_general_rate,
return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
}
-static ulong rk3036_clk_get_rate(struct udevice *dev)
+static long rk3036_clk_get_rate(struct udevice *dev)
{
struct rk3036_clk_plat *plat = dev_get_platdata(dev);
struct rk3036_clk_priv *priv = dev_get_priv(dev);
@@ -307,14 +307,14 @@ static ulong rk3036_clk_get_rate(struct udevice *dev)
return rkclk_pll_get_rate(priv->cru, plat->clk_id);
}
-static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate)
+static long rk3036_clk_set_rate(struct udevice *dev, ulong rate)
{
debug("%s\n", dev->name);
return 0;
}
-static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
+static long rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 0172ad1..8ed0bff 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -337,7 +337,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
}
}
-static ulong rk3288_clk_get_rate(struct udevice *dev)
+static long rk3288_clk_get_rate(struct udevice *dev)
{
struct rk3288_clk_plat *plat = dev_get_platdata(dev);
struct rk3288_clk_priv *priv = dev_get_priv(dev);
@@ -346,7 +346,7 @@ static ulong rk3288_clk_get_rate(struct udevice *dev)
return rkclk_pll_get_rate(priv->cru, plat->clk_id);
}
-static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
+static long rk3288_clk_set_rate(struct udevice *dev, ulong rate)
{
struct rk3288_clk_plat *plat = dev_get_platdata(dev);
struct rk3288_clk_priv *priv = dev_get_priv(dev);
@@ -508,7 +508,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru,
uint clk_general_rate,
return rockchip_spi_get_clk(cru, clk_general_rate, periph);
}
-static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
+static long rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
{
struct rk3288_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 367130f..0ff4605 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -15,14 +15,14 @@ struct sandbox_clk_priv {
ulong periph_rate[PERIPH_ID_COUNT];
};
-static ulong sandbox_clk_get_rate(struct udevice *dev)
+static long sandbox_clk_get_rate(struct udevice *dev)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
return priv->rate;
}
-static ulong sandbox_clk_set_rate(struct udevice *dev, ulong rate)
+static long sandbox_clk_set_rate(struct udevice *dev, ulong rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
@@ -32,7 +32,7 @@ static ulong sandbox_clk_set_rate(struct udevice *dev, ulong
rate)
return 0;
}
-static ulong sandbox_get_periph_rate(struct udevice *dev,
[U-Boot] [PATCH v2 2/6] clk: add needed include and declaration to include/clk.h
This header uses ulong, so it needs to include .
Likewise, "struct udevice" must be declared before it is used.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
---
Changes in v2: None
include/clk.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/clk.h b/include/clk.h
index f244301..371784a 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -8,6 +8,10 @@
#ifndef _CLK_H_
#define _CLK_H_
+#include
+
+struct udevice;
+
int soc_clk_dump(void);
struct clk_ops {
--
1.9.1
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[U-Boot] [PATCH v2 1/6] clk: fix comments in include/clk.h
The comment about get_periph_rate() is the same as that of
set_periph_rate().
I am fixing typos here and there while I am in this file.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
---
Changes in v2: None
include/clk.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/clk.h b/include/clk.h
index 254ad2b..f244301 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -29,19 +29,19 @@ struct clk_ops {
ulong (*set_rate)(struct udevice *dev, ulong rate);
/**
- * clk_set_periph_rate() - Set clock rate for a peripheral
- *
- * @dev: Device to adjust (UCLASS_CLK)
- * @rate:New clock rate in Hz
- * @return new clock rate in Hz, or -ve error code
- */
+* get_periph_rate() - Get clock rate for a peripheral
+*
+* @dev:Device to check (UCLASS_CLK)
+* @periph: Peripheral ID to check
+* @return clock rate in Hz, or -ve error code
+*/
ulong (*get_periph_rate)(struct udevice *dev, int periph);
/**
-* clk_set_periph_rate() - Set current clock rate for a peripheral
+* set_periph_rate() - Set current clock rate for a peripheral
*
* @dev:Device to update (UCLASS_CLK)
-* @periph: Peripheral ID to cupdate
+* @periph: Peripheral ID to update
* @return new clock rate in Hz, or -ve error code
*/
ulong (*set_periph_rate)(struct udevice *dev, int periph, ulong rate);
@@ -58,7 +58,7 @@ struct clk_ops {
ulong clk_get_rate(struct udevice *dev);
/**
- * set_rate() - Set current clock rate
+ * clk_set_rate() - Set current clock rate
*
* @dev: Device to adjust
* @rate: New clock rate in Hz
@@ -78,7 +78,7 @@ ulong clk_get_periph_rate(struct udevice *dev, int periph);
* clk_set_periph_rate() - Set current clock rate for a peripheral
*
* @dev: Device to update (UCLASS_CLK)
- * @periph:Peripheral ID to cupdate
+ * @periph:Peripheral ID to update
* @return new clock rate in Hz, or -ve error code
*/
ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate);
--
1.9.1
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[U-Boot] [PATCH v2 6/6] clk: add device tree support for clock framework
Add device tree binding support for the clock uclass. This allows
clock consumers to get the peripheral ID based on the "clocks"
property in the device tree.
Usage:
Assume the following device tree:
clk: myclock {
compatible = "myclocktype";
#clock-cells = <1>;
};
uart {
compatible = "myuart";
clocks = <&clk 3>;
};
i2c {
compatible = "myi2c";
clocks = <&clk 5>;
};
In this example, the UART, I2C driver can get the peripheral ID 3, 5,
respectively by calling fdt_clk_get().
By default, fdt_clk_get() returns the value of the first cell, or
zero if #clock-cells == <0>. This should work for most of the cases,
but you can still override this behavior by implementing .fdt_xlate
callback in your driver.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Change the arguments of fdt_clk_get() as Simon mentioned
- rename .get_id() to .fdt_xlate(), which seems a more suitable name
drivers/clk/clk-uclass.c | 33 +
include/clk.h| 29 +
2 files changed, 62 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ac3909d..81ef526 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -62,6 +62,39 @@ long clk_set_periph_rate(struct udevice *dev, int periph,
ulong rate)
return ops->set_periph_rate(dev, periph, rate);
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+int fdt_clk_get(struct udevice *dev, int index, struct udevice **clkdevp)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ struct fdtdec_phandle_args clkspec;
+ struct clk_ops *ops;
+ struct udevice *clkdev;
+ int rc;
+
+ rc = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ "clocks", "#clock-cells", 0, index,
+ &clkspec);
+ if (rc)
+ return rc;
+
+ rc = uclass_get_device_by_of_offset(UCLASS_CLK, clkspec.node, &clkdev);
+ if (rc)
+ return rc;
+
+ ops = clk_get_ops(clkdev);
+
+ if (ops->fdt_xlate)
+ rc = ops->fdt_xlate(clkdev, &clkspec);
+ else
+ rc = clkspec.args_count > 0 ? clkspec.args[0] : 0;
+
+ if (clkdevp)
+ *clkdevp = clkdev;
+
+ return rc;
+}
+#endif
+
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",
diff --git a/include/clk.h b/include/clk.h
index de15999..3f95395 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -10,6 +10,7 @@
#include
+struct fdtdec_phandle_args;
struct udevice;
int soc_clk_dump(void);
@@ -58,6 +59,16 @@ struct clk_ops {
* @return new clock rate in Hz, or -ve error code
*/
long (*set_periph_rate)(struct udevice *dev, int periph, ulong rate);
+
+ /**
+* fdt_xlate() - translate DT arguments into peripheral ID
+*
+* @dev:clock provider
+* @clkspec:arguments taken from the device tree
+* @return peripheral ID, or -ve error code
+*/
+ int (*fdt_xlate)(struct udevice *dev,
+struct fdtdec_phandle_args *clkspec);
};
#define clk_get_ops(dev) ((struct clk_ops *)(dev)->driver->ops)
@@ -105,4 +116,22 @@ long clk_get_periph_rate(struct udevice *dev, int periph);
*/
long clk_set_periph_rate(struct udevice *dev, int periph, ulong rate);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/**
+ * fdt_clk_get() - Get peripheral ID from device tree
+ *
+ * @dev: Peripheral device
+ * @index: index of a phandle to parse out in "clocks" property
+ * @clkdevp: if not NULL, filled with pointer of clock provider
+ * @return peripheral ID, or -ve error code
+ */
+int fdt_clk_get(struct udevice *dev, int index, struct udevice **clkdevp);
+#else
+static inline int fdt_clk_get(struct udevice *dev, int index,
+ struct udevice **clkdevp);
+{
+ return -ENOSYS;
+}
+#endif
+
#endif /* _CLK_H_ */
--
1.9.1
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[U-Boot] [PATCH v2 3/6] clk: add static qualifier to local functions
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
drivers/clk/clk_rk3036.c | 2 +-
drivers/clk/clk_rk3288.c | 2 +-
drivers/clk/clk_sandbox.c | 5 +++--
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index 6c802b6..f650810 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -314,7 +314,7 @@ static ulong rk3036_clk_set_rate(struct udevice *dev, ulong
rate)
return 0;
}
-ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 54d4930..0172ad1 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -508,7 +508,7 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru,
uint clk_general_rate,
return rockchip_spi_get_clk(cru, clk_general_rate, periph);
}
-ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong
rate)
{
struct rk3288_clk_priv *priv = dev_get_priv(dev);
ulong new_rate;
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 058225a..367130f 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -32,7 +32,7 @@ static ulong sandbox_clk_set_rate(struct udevice *dev, ulong
rate)
return 0;
}
-ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
+static ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
@@ -41,7 +41,8 @@ ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
return priv->periph_rate[periph];
}
-ulong sandbox_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong sandbox_set_periph_rate(struct udevice *dev, int periph,
+ulong rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(dev);
ulong old_rate;
--
1.9.1
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[U-Boot] [PATCH v2 5/6] clk: add API to enable clock
The most basic thing for clock is to enable it, but it is missing
in this uclass.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
---
Changes in v2:
- Add clk_enable() function
drivers/clk/clk-uclass.c | 10 ++
include/clk.h| 18 ++
2 files changed, 28 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index a5bef59..ac3909d 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -32,6 +32,16 @@ long clk_set_rate(struct udevice *dev, ulong rate)
return ops->set_rate(dev, rate);
}
+int clk_enable(struct udevice *dev, int periph)
+{
+ struct clk_ops *ops = clk_get_ops(dev);
+
+ if (!ops->enable)
+ return -ENOSYS;
+
+ return ops->enable(dev, periph);
+}
+
long clk_get_periph_rate(struct udevice *dev, int periph)
{
struct clk_ops *ops = clk_get_ops(dev);
diff --git a/include/clk.h b/include/clk.h
index 61bb468..de15999 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -33,6 +33,15 @@ struct clk_ops {
long (*set_rate)(struct udevice *dev, ulong rate);
/**
+* enable() - Enable the clock for a peripheral
+*
+* @dev:clock provider
+* @periph: Peripheral ID to enable
+* @return zero on success, or -ve error code
+*/
+ int (*enable)(struct udevice *dev, int periph);
+
+ /**
* get_periph_rate() - Get clock rate for a peripheral
*
* @dev:Device to check (UCLASS_CLK)
@@ -71,6 +80,15 @@ long clk_get_rate(struct udevice *dev);
long clk_set_rate(struct udevice *dev, ulong rate);
/**
+ * clk_enable() - Enable the clock for a peripheral
+ *
+ * @dev: clock provider
+ * @periph:Peripheral ID to enable
+ * @return zero on success, or -ve error code
+ */
+int clk_enable(struct udevice *dev, int periph);
+
+/**
* clk_get_periph_rate() - Get current clock rate for a peripheral
*
* @dev: Device to check (UCLASS_CLK)
--
1.9.1
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Re: [U-Boot] [PATCH] usb: dwc2: Enhance interrupt handling for CONTROL transaction
On Tuesday, January 05, 2016 at 05:16:05 PM, Marek Vasut wrote: > On Tuesday, January 05, 2016 at 04:51:47 PM, Chin Liang See wrote: > > On Tue, 2016-01-05 at 15:36 +0100, Marek Vasut wrote: > > > On Tuesday, January 05, 2016 at 06:00:04 AM, Chin Liang See wrote: > > > > Per DesignWare USB OTG databook, driver should retry up to > > > > 3 times when transaction error (hcint.xacterr) happen. But > > > > the 3 times doesn't count when the response is nack > > > > (hcint.nak) or frame overrun (hcint.frmoverun) > > > > > > > > This patch solved the enumeration error as spotted at socfpga > > > > cyclone5_socdk when plugging in certain pendrive. > > > > > > > > Signed-off-by: Chin Liang See > > > > Cc: Marek Vasut > > > > Cc: Dinh Nguyen > > > > Cc: Dinh Nguyen > > > > Cc: Pavel Machek > > > > Cc: Oleksandr Tymoshenko > > > > Cc: Stephen Warren > > > > Cc: Alexander Stein > > > > Cc: Peter Griffin > > > > > > I applied this change on top of u-boot-socfpga/master and tested it > > > on > > > SoCFPGA CycloneV SoCDK with "Sandisk cruzer force" stick. The board > > > gets > > > completely stuck if I have dcache ENABLED and perform 'usb reset'. > > > This > > > > > patch is: > > Thanks Marek for testing. I managed to find a SanDisk Cruzer Blade and > > notice the same fail behaviours as yours. FYI, note that this patch > > works well with other 3 pendrive that I have. > > > > With SanDisk, the dwc2 driver was timed out as hcint.xfercomp and > > chhltd never get set even after 1s. It keep retrying endlessly due to > > miss handling for the ETIMEDOUT within this patch. > > > > In short, the retry doesn't work for SanDisk but the dcache disable > > works. Need to figure out more what cause the failure. > > Excellent, I have one of those too (I bought the entire lineup of these > sandisk sticks at one point ;-) ) Hi, any news on the SoCFPGA USB/QSPI problem investigation? Thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Wednesday, January 13, 2016 at 03:45:46 AM, Chin Liang See wrote: > On Wed, 2016-01-13 at 03:34 +0100, Marek Vasut wrote: > > On Wednesday, January 13, 2016 at 03:23:38 AM, Chin Liang See wrote: > > > On Wed, 2016-01-13 at 03:07 +0100, Marek Vasut wrote: > > > > On Wednesday, January 13, 2016 at 03:05:40 AM, Chin Liang See > > > > > > > > wrote: > > > > > On Tue, 2016-01-12 at 03:48 +0100, Marek Vasut wrote: > > > > > > On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See > > > > > > > > > > > > wrote: > > > > > > > On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > > > > > > > > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang > > > > > > > > See > > > > > > > > > > > > > > > > wrote: > > > > > > > > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen > > > > > > > > > > > > > > > > wrote: > > > > > > > [...] > > > > > > > > > > > > > > > btw. Completely off-topic, but is there any chance altera > > > > > > > > will > > > > > > > > release the > > > > > > > > algorithm to compute these magic values which are in the > > > > > > > > header > > > > > > > > files > > > > > > > > from > > > > > > > > the base values inserted into the HPS component in QSys ? > > > > > > > > > > > > > > I would not suggesting that as Qsys and Quartus are doing > > > > > > > heavylifting > > > > > > > tasks there. The value would depends on the options being > > > > > > > choosed, > > > > > > > device type, device revision (if any). They also being > > > > > > > patched > > > > > > > from > > > > > > > time to time too. > > > > > > > > > > > > Is it all really _that_ complicated ? That's why I'd like to > > > > > > see > > > > > > the > > > > > > code > > > > > > that's doing all that computation. > > > > > > > > > > Actually more challenges is that the code is proprietary. We > > > > > might > > > > > get > > > > > stopped by legal team before making this happen too. > > > > > > > > What's proprietary about it ? Isn't that SDRAM controller made in > > > > -house > > > > by Altera ? > > > > > > Oh seems we might discussing slightly different things. I am > > > referring > > > to IOCSR which is the bitstream for setting up the IO buffers. I > > > presume you are referring to SDRAM configuration, right? > > > > Yeah, I'm talking about the SDRAM controller configuration values. > > Cool, let me take a look on the SDRAM handoff we have today. I'm looking forward to your findings :) > > I know the IOCSR is a problem. I am reverse engineering the Cyclone > > IV > > bitstream format in my free time now and then, but I didn't have time > > to look at C V and I don't plan to do it any soon. I think even my > > C/IV > > activity might trigger someone in Altera once I get around to > > releasing > > it ;-) > > haha :) There are various knob in Quartus that might change the IOCSR > itself. Shall let the tools to handle it for better user experience. Is it really that hard ? I'd kinda expect that it's only those bits which you can select in the pin planner and that's very close to what any other SoC can do with the pins. But I'm not really planning to dive into this any soon. > > > > > > Even if it's done at compile-time, it'd > > > > > > still be better than the horrible headers which we have to > > > > > > use > > > > > > now. > > > > > > > > > > I believe DTS would be better format than header file. > > > > > > > > Coming up with sensible bindings would be hard though. > > > > > > Yah, that why this is get rid when we switch to Arria 10 SoC :) > > > > Well you'll still need to configure the HardIP which does the DDR > > calib > > with some DDR config values, so you cannot get rid of it entirely. > > Unless > > you pull these values from SPD, which I doubt would be the case, > > since > > the A10 would be mostly embedded chip. > > Nope, its part of bitstream. Bitstream will contain the information on > the DDR devices on the board. This is similar to what being implemented > in traditional FPGA devices. H, I see. That's also why you need to program the FPGA in SPL, right ? Oh, btw, about that, look at CONFIG_CMD_FPGA_LOADMK and CONFIG_CMD_FPGA_LOADBP, I think that functionality is something you might find useful when doing the SPL for A10. So far, it's xilinx specific (tsk, spit :-)~~* ) but it should be easy to adapt. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Wed, 2016-01-13 at 03:34 +0100, Marek Vasut wrote: > On Wednesday, January 13, 2016 at 03:23:38 AM, Chin Liang See wrote: > > On Wed, 2016-01-13 at 03:07 +0100, Marek Vasut wrote: > > > On Wednesday, January 13, 2016 at 03:05:40 AM, Chin Liang See > > > wrote: > > > > On Tue, 2016-01-12 at 03:48 +0100, Marek Vasut wrote: > > > > > On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See > > > > > > > > > > wrote: > > > > > > On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > > > > > > > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang > > > > > > > See > > > > > > > > > > > > > > wrote: > > > > > > > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen > > > > > > > > wrote: > > > > > > [...] > > > > > > > > > > > > > btw. Completely off-topic, but is there any chance altera > > > > > > > will > > > > > > > release the > > > > > > > algorithm to compute these magic values which are in the > > > > > > > header > > > > > > > files > > > > > > > from > > > > > > > the base values inserted into the HPS component in QSys ? > > > > > > > > > > > > I would not suggesting that as Qsys and Quartus are doing > > > > > > heavylifting > > > > > > tasks there. The value would depends on the options being > > > > > > choosed, > > > > > > device type, device revision (if any). They also being > > > > > > patched > > > > > > from > > > > > > time to time too. > > > > > > > > > > Is it all really _that_ complicated ? That's why I'd like to > > > > > see > > > > > the > > > > > code > > > > > that's doing all that computation. > > > > > > > > Actually more challenges is that the code is proprietary. We > > > > might > > > > get > > > > stopped by legal team before making this happen too. > > > > > > What's proprietary about it ? Isn't that SDRAM controller made in > > > -house > > > by Altera ? > > > > Oh seems we might discussing slightly different things. I am > > referring > > to IOCSR which is the bitstream for setting up the IO buffers. I > > presume you are referring to SDRAM configuration, right? > > Yeah, I'm talking about the SDRAM controller configuration values. Cool, let me take a look on the SDRAM handoff we have today. > > I know the IOCSR is a problem. I am reverse engineering the Cyclone > IV > bitstream format in my free time now and then, but I didn't have time > to look at C V and I don't plan to do it any soon. I think even my > C/IV > activity might trigger someone in Altera once I get around to > releasing > it ;-) haha :) There are various knob in Quartus that might change the IOCSR itself. Shall let the tools to handle it for better user experience. > > > > > > Even if it's done at compile-time, it'd > > > > > still be better than the horrible headers which we have to > > > > > use > > > > > now. > > > > > > > > I believe DTS would be better format than header file. > > > > > > Coming up with sensible bindings would be hard though. > > > > Yah, that why this is get rid when we switch to Arria 10 SoC :) > > Well you'll still need to configure the HardIP which does the DDR > calib > with some DDR config values, so you cannot get rid of it entirely. > Unless > you pull these values from SPD, which I doubt would be the case, > since > the A10 would be mostly embedded chip. Nope, its part of bitstream. Bitstream will contain the information on the DDR devices on the board. This is similar to what being implemented in traditional FPGA devices. Thanks Chin Liang > > Best regards, > Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv3 2/4] nand_spl_simple: Add a simple NAND read function
On Mon, Jan 11, 2016 at 12:16:44AM +0100, Ladislav Michl wrote: > From: Thomas Gleixner > > To support UBI in SPL we need a simple NAND read function. Add one to > nand_spl_simple and keep it as simple as it goes. > > Signed-off-by: Thomas Gleixner > Signed-off-by: Ladislav Michl > Acked-by: Scott Wood Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv3 3/4] spl: Lightweight UBI and UBI fastmap support
On Mon, Jan 11, 2016 at 12:17:28AM +0100, Ladislav Michl wrote: > From: Thomas Gleixner > > Booting a payload out of NAND FLASH from the SPL is a crux today, as > it requires hard partioned FLASH. Not a brilliant idea with the > reliability of todays NAND FLASH chips. > > The upstream UBI + UBI fastmap implementation which is about to > brought to u-boot is too heavy weight for SPLs as it provides way more > functionality than needed for a SPL and does not even fit into the > restricted SPL areas which are loaded from the SoC boot ROM. > > So this provides a fast and lightweight implementation of UBI scanning > and UBI fastmap attach. The scan and logical to physical block mapping > code is developed from scratch, while the fastmap implementation is > lifted from the linux kernel source and stripped down to fit the SPL > needs. > > The text foot print on the board which I used for development is: > > 6854 0 0 68541abd > drivers/mtd/ubispl/built-in.o > > Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are > reserved for the SPL) takes: > > In full scan mode: 1172ms > In fastmap mode: 95ms > > The code requires quite some storage. The largest and unknown part of > it is the number of fastmap blocks to read. Therefor the data > structure is not put into the BSS. The code requires a pointer to free > memory handed in which is initialized by the UBI attach code itself. > > See doc/README.ubispl for further information on how to use it. > > This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi > There is no way to share the fastmap code, as UBISPL only utilizes the > slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap() > from the original kernel ubi fastmap implementation. > > Signed-off-by: Thomas Gleixner > Signed-off-by: Ladislav Michl Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv3 1/4] mtd: Sort subsystem directories aplhabeticaly in Makefile
On Mon, Jan 11, 2016 at 12:15:42AM +0100, Ladislav Michl wrote: > Signed-off-by: Ladislav Michl Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Wednesday, January 13, 2016 at 03:23:38 AM, Chin Liang See wrote: > On Wed, 2016-01-13 at 03:07 +0100, Marek Vasut wrote: > > On Wednesday, January 13, 2016 at 03:05:40 AM, Chin Liang See wrote: > > > On Tue, 2016-01-12 at 03:48 +0100, Marek Vasut wrote: > > > > On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See > > > > > > > > wrote: > > > > > On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > > > > > > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang See > > > > > > > > > > > > wrote: > > > > > > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote: > > > > > [...] > > > > > > > > > > > btw. Completely off-topic, but is there any chance altera > > > > > > will > > > > > > release the > > > > > > algorithm to compute these magic values which are in the > > > > > > header > > > > > > files > > > > > > from > > > > > > the base values inserted into the HPS component in QSys ? > > > > > > > > > > I would not suggesting that as Qsys and Quartus are doing > > > > > heavylifting > > > > > tasks there. The value would depends on the options being > > > > > choosed, > > > > > device type, device revision (if any). They also being patched > > > > > from > > > > > time to time too. > > > > > > > > Is it all really _that_ complicated ? That's why I'd like to see > > > > the > > > > code > > > > that's doing all that computation. > > > > > > Actually more challenges is that the code is proprietary. We might > > > get > > > stopped by legal team before making this happen too. > > > > What's proprietary about it ? Isn't that SDRAM controller made in > > -house > > by Altera ? > > Oh seems we might discussing slightly different things. I am referring > to IOCSR which is the bitstream for setting up the IO buffers. I > presume you are referring to SDRAM configuration, right? Yeah, I'm talking about the SDRAM controller configuration values. I know the IOCSR is a problem. I am reverse engineering the Cyclone IV bitstream format in my free time now and then, but I didn't have time to look at C V and I don't plan to do it any soon. I think even my C/IV activity might trigger someone in Altera once I get around to releasing it ;-) > > > > Even if it's done at compile-time, it'd > > > > still be better than the horrible headers which we have to use > > > > now. > > > > > > I believe DTS would be better format than header file. > > > > Coming up with sensible bindings would be hard though. > > Yah, that why this is get rid when we switch to Arria 10 SoC :) Well you'll still need to configure the HardIP which does the DDR calib with some DDR config values, so you cannot get rid of it entirely. Unless you pull these values from SPD, which I doubt would be the case, since the A10 would be mostly embedded chip. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-dm
On Tue, Jan 12, 2016 at 04:05:42PM -0700, Simon Glass wrote: > Hi Tom, > > This mainly includes various PCI improvements. I have not been keeping up > with applying things to dm/next, so will have to start pulling in patches > quickly. > > > The following changes since commit fa85e826c16b9ce1ad302a57e9c4b24db0d8b930: > > Prepare v2016.01 (2016-01-12 09:06:54 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-dm.git > > for you to fetch changes up to ab971e192adcf0a501c8998542ab116512c0c260: > > sandbox: eth-raw-os.c: Ensure that our interface name is not too long > (2016-01-12 10:19:09 -0700) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Wed, 2016-01-13 at 03:07 +0100, Marek Vasut wrote: > On Wednesday, January 13, 2016 at 03:05:40 AM, Chin Liang See wrote: > > On Tue, 2016-01-12 at 03:48 +0100, Marek Vasut wrote: > > > On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See > > > wrote: > > > > On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > > > > > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang See > > > > > > > > > > wrote: > > > > > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote: > > > > [...] > > > > > > > > > btw. Completely off-topic, but is there any chance altera > > > > > will > > > > > release the > > > > > algorithm to compute these magic values which are in the > > > > > header > > > > > files > > > > > from > > > > > the base values inserted into the HPS component in QSys ? > > > > > > > > I would not suggesting that as Qsys and Quartus are doing > > > > heavylifting > > > > tasks there. The value would depends on the options being > > > > choosed, > > > > device type, device revision (if any). They also being patched > > > > from > > > > time to time too. > > > > > > Is it all really _that_ complicated ? That's why I'd like to see > > > the > > > code > > > that's doing all that computation. > > > > Actually more challenges is that the code is proprietary. We might > > get > > stopped by legal team before making this happen too. > > What's proprietary about it ? Isn't that SDRAM controller made in > -house > by Altera ? Oh seems we might discussing slightly different things. I am referring to IOCSR which is the bitstream for setting up the IO buffers. I presume you are referring to SDRAM configuration, right? > > > Even if it's done at compile-time, it'd > > > still be better than the horrible headers which we have to use > > > now. > > > > I believe DTS would be better format than header file. > > Coming up with sensible bindings would be hard though. > Yah, that why this is get rid when we switch to Arria 10 SoC :) Thanks Chin Liang > Best regards, > Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/6] rockchip: rk3036: Bind GPIO banks
Call dm_scan_fdt_node() in rk3036 pinctrl uclass binding.
Signed-off-by: Jeffy Chen
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3036.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 581b096..1f78bf8 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -252,6 +253,12 @@ static struct pinctrl_ops rk3036_pinctrl_ops = {
.get_periph_id = rk3036_pinctrl_get_periph_id,
};
+static int rk3036_pinctrl_bind(struct udevice *dev)
+{
+ /* scan child GPIO banks */
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
static int rk3036_pinctrl_probe(struct udevice *dev)
{
struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
@@ -272,5 +279,6 @@ U_BOOT_DRIVER(pinctrl_rk3036) = {
.of_match = rk3036_pinctrl_ids,
.priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
.ops= &rk3036_pinctrl_ops,
+ .bind = rk3036_pinctrl_bind,
.probe = rk3036_pinctrl_probe,
};
--
2.1.4
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[U-Boot] [PATCH v3 6/6] rockchip: kylin: Check fastboot request
We will save boot mode flag in grf's os_reg[0], if fastboot
requested or fastboot key pressed, try to enter fastboot mode
at preboot stage.
Signed-off-by: Jeffy Chen
---
Changes in v3:
Use rockchip's legacy reboot mode definitions.
Changes in v2: None
board/kylin/kylin_rk3036/kylin_rk3036.c | 46 +
include/configs/kylin_rk3036.h | 3 +++
2 files changed, 49 insertions(+)
diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c
b/board/kylin/kylin_rk3036/kylin_rk3036.c
index 40d6b52..4fc31b1 100644
--- a/board/kylin/kylin_rk3036/kylin_rk3036.c
+++ b/board/kylin/kylin_rk3036/kylin_rk3036.c
@@ -8,10 +8,15 @@
#include
#include
#include
+#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+#define GRF_BASE 0x20008000
+static struct rk3036_grf * const grf = (void *)GRF_BASE;
+
void get_ddr_config(struct rk3036_ddr_config *config)
{
/* K4B4G1646Q config */
@@ -28,6 +33,47 @@ void get_ddr_config(struct rk3036_ddr_config *config)
config->bw = 1;
}
+#define FASTBOOT_KEY_GPIO 93
+
+int fastboot_key_pressed(void)
+{
+ gpio_request(FASTBOOT_KEY_GPIO, "fastboot_key");
+ gpio_direction_input(FASTBOOT_KEY_GPIO);
+ return !gpio_get_value(FASTBOOT_KEY_GPIO);
+}
+
+enum rockchip_boot_mode {
+ ROCKCHIP_BOOT_MODE_NORMAL = 0x5242C300,
+ ROCKCHIP_BOOT_MODE_LOADER,
+ ROCKCHIP_BOOT_MODE_MASKROM,
+ ROCKCHIP_BOOT_MODE_RECOVER,
+ ROCKCHIP_BOOT_MODE_NORECOVER,
+ ROCKCHIP_BOOT_MODE_SECONDOS,
+ ROCKCHIP_BOOT_MODE_WIPEDATA,
+ ROCKCHIP_BOOT_MODE_WIPEALL,
+ ROCKCHIP_BOOT_MODE_CHECKIMG,
+ ROCKCHIP_BOOT_MODE_FASTBOOT,
+ ROCKCHIP_BOOT_MODE_SECUREBOOT_DISABLE,
+ ROCKCHIP_BOOT_MODE_CHARGING,
+ ROCKCHIP_BOOT_MODE_MAX,
+};
+
+int board_late_init(void)
+{
+ int boot_mode = readl(&grf->os_reg[4]);
+
+ /* Clear boot mode */
+ writel(0, &grf->os_reg[4]);
+
+ if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT ||
+ fastboot_key_pressed()) {
+ printf("enter fastboot!\n");
+ setenv("preboot", "setenv preboot; fastboot usb0");
+ }
+
+ return 0;
+}
+
int board_init(void)
{
return 0;
diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
index 49997ec..424e81b 100644
--- a/include/configs/kylin_rk3036.h
+++ b/include/configs/kylin_rk3036.h
@@ -39,6 +39,9 @@
"mmcpart=5\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_PREBOOT
+
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_SYS_HUSH_PARSER
--
2.1.4
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[U-Boot] [PATCH v3 0/6] rockchip: kylin: Boot with android boot image
We are porting android to kylin board now. This series could let it boot up with android's boot image. Changes in v3: Use rockchip's legacy reboot mode definitions. Changes in v2: Add comments. Jeffy Chen (6): common/image-fdt.c: Make boot_get_fdt() perform a check for Android images ARM: bootm: Try to use relocated ramdisk rockchip: rk3036: Bind GPIO banks rockchip: kylin: Add default gpt partition table rockchip: kylin: Enable boot with android boot image rockchip: kylin: Check fastboot request arch/arm/lib/bootm.c | 12 ++- board/kylin/kylin_rk3036/kylin_rk3036.c | 46 ++ common/image-fdt.c| 4 +++ drivers/pinctrl/rockchip/pinctrl_rk3036.c | 8 + include/configs/kylin_rk3036.h| 55 +++ 5 files changed, 124 insertions(+), 1 deletion(-) -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 5/6] rockchip: kylin: Enable boot with android boot image
The android kernel is using appended dtb by default, and store
ramdisk right after kernel & dtb.
So we needs to relocate ramdisk, and use atags to pass params.
Signed-off-by: Jeffy Chen
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/configs/kylin_rk3036.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
index b750b26..49997ec 100644
--- a/include/configs/kylin_rk3036.h
+++ b/include/configs/kylin_rk3036.h
@@ -35,6 +35,29 @@
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"partitions=" PARTS_DEFAULT \
+ "mmcdev=0\0" \
+ "mmcpart=5\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define CONFIG_SYS_HUSH_PARSER
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "part start mmc ${mmcdev} ${mmcpart} boot_start;" \
+ "part size mmc ${mmcdev} ${mmcpart} boot_size;" \
+ "mmc read ${loadaddr} ${boot_start} ${boot_size};" \
+ "bootm start ${loadaddr}; bootm ramdisk;" \
+ "bootm prep; bootm go;" \
+ "fi;" \
+
+/* Enable atags */
+#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
#endif
--
2.1.4
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[U-Boot] [PATCH v3 4/6] rockchip: kylin: Add default gpt partition table
Add default android gpt partition table for kylin board.
Use "gpt write mmc 0 $partitions" to apply.
Signed-off-by: Jeffy Chen
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/configs/kylin_rk3036.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
index aa07889..b750b26 100644
--- a/include/configs/kylin_rk3036.h
+++ b/include/configs/kylin_rk3036.h
@@ -9,4 +9,33 @@
#include
+#ifndef CONFIG_SPL_BUILD
+
+/* Enable gpt partition table */
+#define CONFIG_CMD_GPT
+#define CONFIG_RANDOM_UUID
+#define CONFIG_EFI_PARTITION
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=loader,start=32K,size=4000K,uuid=${uuid_gpt_loader};" \
+ "name=reserved,size=64K,uuid=${uuid_gpt_reserved};" \
+ "name=misc,size=4M,uuid=${uuid_gpt_misc};" \
+ "name=recovery,size=32M,uuid=${uuid_gpt_recovery};" \
+ "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \
+ "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \
+ "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \
+ "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \
+ "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \
+ "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \
+ "name=cache,size=100M,uuid=${uuid_gpt_cache};" \
+ "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
+ "name=persist,size=4M,uuid=${uuid_gpt_persist};" \
+ "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "partitions=" PARTS_DEFAULT \
+
+#endif
+
#endif
--
2.1.4
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[U-Boot] [PATCH v3 1/6] common/image-fdt.c: Make boot_get_fdt() perform a check for Android images
Android images don't have a fdt.
Signed-off-by: Jeffy Chen
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/image-fdt.c | 4
1 file changed, 4 insertions(+)
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 5e4e5bd..41aaa0d 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -379,6 +379,10 @@ int boot_get_fdt(int flag, int argc, char * const argv[],
uint8_t arch,
(long)fdt_addr);
}
break;
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID:
+ goto no_fdt;
+#endif
default:
puts("ERROR: Did not find a cmdline Flattened Device
Tree\n");
goto no_fdt;
--
2.1.4
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[U-Boot] [PATCH v3 2/6] ARM: bootm: Try to use relocated ramdisk
After boot_ramdisk_high(), ramdisk would be relocated to
initrd_start & initrd_end, so use them instead of rd_start & rd_end.
Signed-off-by: Jeffy Chen
Acked-by: Simon Glass
---
Changes in v3: None
Changes in v2:
Add comments.
arch/arm/lib/bootm.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index a477cae..0838d89 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -225,7 +225,17 @@ static void boot_prep_linux(bootm_headers_t *images)
if (BOOTM_ENABLE_MEMORY_TAGS)
setup_memory_tags(gd->bd);
if (BOOTM_ENABLE_INITRD_TAG) {
- if (images->rd_start && images->rd_end) {
+ /*
+* In boot_ramdisk_high(), it may relocate ramdisk to
+* a specified location. And set images->initrd_start &
+* images->initrd_end to relocated ramdisk's start/end
+* addresses. So use them instead of images->rd_start &
+* images->rd_end when possible.
+*/
+ if (images->initrd_start && images->initrd_end) {
+ setup_initrd_tag(gd->bd, images->initrd_start,
+images->initrd_end);
+ } else if (images->rd_start && images->rd_end) {
setup_initrd_tag(gd->bd, images->rd_start,
images->rd_end);
}
--
2.1.4
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Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Wednesday, January 13, 2016 at 03:05:40 AM, Chin Liang See wrote: > On Tue, 2016-01-12 at 03:48 +0100, Marek Vasut wrote: > > On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See wrote: > > > On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > > > > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang See > > > > > > > > wrote: > > > > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote: > > > [...] > > > > > > > btw. Completely off-topic, but is there any chance altera will > > > > release the > > > > algorithm to compute these magic values which are in the header > > > > files > > > > from > > > > the base values inserted into the HPS component in QSys ? > > > > > > I would not suggesting that as Qsys and Quartus are doing > > > heavylifting > > > tasks there. The value would depends on the options being choosed, > > > device type, device revision (if any). They also being patched from > > > time to time too. > > > > Is it all really _that_ complicated ? That's why I'd like to see the > > code > > that's doing all that computation. > > Actually more challenges is that the code is proprietary. We might get > stopped by legal team before making this happen too. What's proprietary about it ? Isn't that SDRAM controller made in-house by Altera ? > > Even if it's done at compile-time, it'd > > still be better than the horrible headers which we have to use now. > > I believe DTS would be better format than header file. Coming up with sensible bindings would be hard though. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Tue, 2016-01-12 at 03:48 +0100, Marek Vasut wrote: > On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See wrote: > > On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > > > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang See > > > wrote: > > > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote: > > [...] > > > > > btw. Completely off-topic, but is there any chance altera will > > > release the > > > algorithm to compute these magic values which are in the header > > > files > > > from > > > the base values inserted into the HPS component in QSys ? > > > > I would not suggesting that as Qsys and Quartus are doing > > heavylifting > > tasks there. The value would depends on the options being choosed, > > device type, device revision (if any). They also being patched from > > time to time too. > > Is it all really _that_ complicated ? That's why I'd like to see the > code > that's doing all that computation. Actually more challenges is that the code is proprietary. We might get stopped by legal team before making this happen too. > Even if it's done at compile-time, it'd > still be better than the horrible headers which we have to use now. > I believe DTS would be better format than header file. Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10
On Wednesday, January 13, 2016 at 02:58:42 AM, Chin Liang See wrote: > On Tue, 2016-01-12 at 23:16 +0100, Marek Vasut wrote: > > On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote: > > > On 01/12/2016 04:02 PM, Marek Vasut wrote: > > > > On Tuesday, January 12, 2016 at 09:56:42 PM, > > > > dingu...@opensource.altera.com > > > > > > > > wrote: > > > > > From: Dinh Nguyen > > > > > > > > > > Add the Arria10 reset manager defines that is used in Linux. > > > > > Change the > > > > > license to SPDX. > > > > > > > > > > [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux > > > > > kernel] > > > > > > > > > > Signed-off-by: Dinh Nguyen > > > > > > > > Applied all three to u-boot-socfpga/02-arria10 , thanks! > > > > > > > > btw what's the status of A10 ? What will I be able to compile it > > > > (and > > > > thus merge the stuff into mainline and ev. use it on actual A10) > > > > ? A > > > > board would be nice too ;-) > > > > > > Here is my list of to-do that is left for A10: > > > > > > - submit SDRAM controller > > > - rework FPGA manager for A10 > > > - port an SPL for A10 > > > > > > I think the most work will be the SDRAM controller as it needs > > > quite a > > > bit of cleanup. I'm about ~25% through with that. > > > > Didn't you mention that you use nios2 that magically does that init > > for you? > > Shall I expect thousands of LoC SDRAM controller driver again or is > > there > > something "lighter" coming up ? ;-) > > Yah it should be lighter as all SDRAM configuration now part of > bitstream. Driver just need to derive the value from bitstream register > and setup the DDR controller. No more DDR handoff. Whew :) > > > As for HW, I'll see what I can do. > > > > Don't worry about it too much. I also poked Chin about it some time > > ago, but > > I dunno where he got with this. > > I am still working on this. We have limited boards as we will be > getting production board in a month time. Dinh, you have any boards to > spare? Most of boards here already went into test farms. I'll wait for the production ones , no need to hurry :) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10
On Tue, 2016-01-12 at 23:16 +0100, Marek Vasut wrote: > On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote: > > On 01/12/2016 04:02 PM, Marek Vasut wrote: > > > On Tuesday, January 12, 2016 at 09:56:42 PM, > > > dingu...@opensource.altera.com > > > > > > wrote: > > > > From: Dinh Nguyen > > > > > > > > Add the Arria10 reset manager defines that is used in Linux. > > > > Change the > > > > license to SPDX. > > > > > > > > [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux > > > > kernel] > > > > > > > > Signed-off-by: Dinh Nguyen > > > > > > Applied all three to u-boot-socfpga/02-arria10 , thanks! > > > > > > btw what's the status of A10 ? What will I be able to compile it > > > (and > > > thus merge the stuff into mainline and ev. use it on actual A10) > > > ? A > > > board would be nice too ;-) > > > > Here is my list of to-do that is left for A10: > > > > - submit SDRAM controller > > - rework FPGA manager for A10 > > - port an SPL for A10 > > > > I think the most work will be the SDRAM controller as it needs > > quite a > > bit of cleanup. I'm about ~25% through with that. > > Didn't you mention that you use nios2 that magically does that init > for you? > Shall I expect thousands of LoC SDRAM controller driver again or is > there > something "lighter" coming up ? ;-) Yah it should be lighter as all SDRAM configuration now part of bitstream. Driver just need to derive the value from bitstream register and setup the DDR controller. No more DDR handoff. > > > As for HW, I'll see what I can do. > > Don't worry about it too much. I also poked Chin about it some time > ago, but > I dunno where he got with this. I am still working on this. We have limited boards as we will be getting production board in a month time. Dinh, you have any boards to spare? Most of boards here already went into test farms. Thanks Chin Liang > > Thanks! > > Best regards, > Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot Rockchip dwc_hcd question for low-speed devices
On Montag, 11. Januar 2016 09:59:09 CET Simon Glass wrote: > Hi Josh, > > On 8 January 2016 at 06:27, Josh Sanford wrote: > > Thanks Simon, > > > > I've been looking through the code you referenced. So these patches are > > just standalone snippets and not yet part of any branch? (I'm just not > > familiar with U-Boot's development process.) > > Please put your reply at the bottom or the threads will get very confusing! > > There is some information here that might help: > > http://www.denx.de/wiki/U-Boot/Patches > > In short, yes these are patches, and will be applied at some point, at > which point they become part of 'mainline' and end up in the next > release. If you test them you can reply with your Tested-by tag which > helps the process. Just a small followup, I have reworked the patches. I have followed Simons? suggestion and split the "core" transfer from the chunk_msg loop into a seperate function. The SPLIT changes are now much more self contained. The patches need some cleanup, especially the INTERRUPT transfer support (yay, that did not work before), so I will post it soon, but maybe not earlier than during the weekend. Kind regards, Stefan -- Stefan Brüns / Bergstraße 21 / 52062 Aachen home: +49 241 53809034 mobile: +49 151 50412019 work: +49 2405 49936-424 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv3 4/4] igep00x0: UBIize
Hi Heiko,
just one more thing I forgot to mention...
On Tue, Jan 12, 2016 at 10:08:21AM +0100, Heiko Schocher wrote:
> Am 11.01.2016 um 13:58 schrieb Ladislav Michl:
[...]
> >All that ubispl_info structure is board specific and there is not much left
> >besides initializing it. Also volumes can differ per board basis, so
> >providing common function is somewhat questionable. However here it is,
> >just to show how does it look like. Suggestions are very welcome as silence
> >around this part of patch is a bit suspicious ;-)
>
> Questions are coming if there are users ;-)
>
> I vote for bringing this in, and we will see, where we have to make
> things more configurable ... some nitpicks below ...
I wouldn't make payload loading function completely board specific as we
would face danger of copying similar pattern over and over for every board
wanting to support ubispl without anyone even considering consolidation.
History of U-Boot proves that happens :) So lets's make payload loading
function decently generic which will force users to improve it and
eventuelly provide their own as a last option. Also let's not pretend
code works on anything but NAND, so patch would boil down to something
like this:
commit 9fd0671cb68e14d3238867173a8ecdaf0f4695af
Author: Ladislav Michl
Date: Mon Jan 11 13:08:10 2016 +0100
spl: support loading from UBI volumes
Add support for loading from UBI volumes on the top of NAND.
Signed-off-by: Ladislav Michl
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 10a4589..36e5338 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -12,8 +12,11 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+ifndef CONFIG_SPL_UBI
obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+endif
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
+obj-$(CONFIG_SPL_UBI) += spl_ubi.o
obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 6e6dee7..7665105 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -288,8 +288,12 @@ static int spl_load_image(u32 boot_device)
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
+#ifdef CONFIG_SPL_UBI
+ return spl_ubi_load_image(boot_device);
+#else
return spl_nand_load_image();
#endif
+#endif
#ifdef CONFIG_SPL_ONENAND_SUPPORT
case BOOT_DEVICE_ONENAND:
return spl_onenand_load_image();
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
new file mode 100644
index 000..7b6eb31
--- /dev/null
+++ b/common/spl/spl_ubi.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016
+ * Ladislav Michl
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+int spl_ubi_load_image(u32 boot_device)
+{
+ int ret;
+ struct image_header *header;
+ struct ubispl_info info;
+ struct ubispl_load volumes[2];
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ if (boot_device == BOOT_DEVICE_NAND)
+ nand_init();
+#endif
+ info.ubi = (struct ubi_scan_info *) CONFIG_SPL_UBI_INFO_ADDR;
+ info.fastmap = 1;
+ info.read = nand_spl_read_block;
+
+ info.peb_offset = CONFIG_SPL_UBI_PEB_OFFSET;
+ info.peb_size = CONFIG_SYS_NAND_BLOCK_SIZE;
+ info.vid_offset = CONFIG_SPL_UBI_VID_OFFSET;
+ info.leb_start = CONFIG_SPL_UBI_LEB_START;
+ info.peb_count = CONFIG_SPL_UBI_MAX_PEBS - info.peb_offset;
+
+#ifdef CONFIG_SPL_OS_BOOT
+ if (!spl_start_uboot()) {
+ volumes[0].name = "kernel";
+ volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_KERNEL_ID;
+ volumes[0].load_addr = (void *)CONFIG_SYS_LOAD_ADDR;
+ volumes[1].name = "args";
+ volumes[1].vol_id = CONFIG_SPL_UBI_LOAD_ARGS_ID;
+ volumes[1].load_addr = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
+
+ ret = ubispl_load_volumes(&info, volumes, 2);
+ if (!ret) {
+ header = (struct image_header *) volumes[0].load_addr;
+ spl_parse_image_header(header);
+ puts("Linux loaded.\n");
+ goto out;
+ }
+ puts("Loading Linux failed, falling back to U-Boot.\n");
+ }
+#endif
+ header = (struct image_header *)
+ (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
+ volumes[0].name = "monitor";
+ volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_MONITOR_ID;
+ volumes[0].load_addr = (void *)header;
+
+ ret = ubispl_load_volumes(&info, volumes, 1);
+ if (!ret)
+ spl_parse_image_header(header);
+#ifdef CONFIG_SPL_OS_BOOT
+out:
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ if (boot_device == BOOT_DEVICE_NAND)
+ nand_des
[U-Boot] Please pull u-boot-dm
Hi Tom, This mainly includes various PCI improvements. I have not been keeping up with applying things to dm/next, so will have to start pulling in patches quickly. The following changes since commit fa85e826c16b9ce1ad302a57e9c4b24db0d8b930: Prepare v2016.01 (2016-01-12 09:06:54 -0500) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to ab971e192adcf0a501c8998542ab116512c0c260: sandbox: eth-raw-os.c: Ensure that our interface name is not too long (2016-01-12 10:19:09 -0700) Simon Glass (29): dm: pci: Mark legacy files as such dm: pci: Add a dm_ prefix to pci_get_bdf() dm: pci: Add a dm_ prefix to pci_bus_find_bdf() dm: pci: Use driver model PCI API in auto-config dm: pci: Add a driver-model version of pci_find_device() dm: pci: scsi: Use driver-model PCI API dm: pci: Add a driver-model version of pci_find_class() dm: pci: Add a function to read a PCI BAR dm: serial: Convert ns16550 driver to use driver model PCI API dm: x86: ivybridge: Convert graphics init to use DM PCI API dm: Convert bios_interrupts to use DM PCI API dm: pci: video: Convert video and pci_rom to use DM PCI API dm: x86: pci: Adjust bios_run_on_x86() to use the DM PCI API dm: pci: Drop the old version of pci_find_device/s() dm: pci: Drop the old version of pci_find_class() dm: tegra: net: Convert tegra boards to driver model for Ethernet dm: test: Convert PCI tests to use the DM PCI API dm: pci: Add driver model API functions for address mapping dm: net: Convert rtl8169 to use DM PCI API dm: pci: Switch to DM API for PCI address mapping dm: ahci: Convert to use new DM PCI API dm: usb: Convert echi-pci to use new DM PCI API dm: Convert PCI MMC over to use DM PCI API pci: Tidy up comments in pci_bind_bus_devices() dm: net: usb: Refactor mcs7830 driver ready for DM conversion dm: net: usb: Convert mcs7830 driver to support driver model dm: serial: Allow the UART driver to be dropped from the image dm: ns16550: Allow the driver to be omitted if requested rockchip: Use the debug UART on rk3036 Stefan Roese (1): dm: core: Add option to configure an offset for the address translation Tom Rini (1): sandbox: eth-raw-os.c: Ensure that our interface name is not too long arch/arm/mach-rockchip/Makefile | 1 - arch/arm/mach-rockchip/rk3036-board-spl.c | 9 +- arch/arm/mach-rockchip/rk_early_print.c | 63 --- arch/arm/mach-tegra/Kconfig | 1 + arch/sandbox/cpu/eth-raw-os.c | 4 + arch/x86/cpu/baytrail/valleyview.c| 4 +- arch/x86/cpu/ivybridge/bd82x6x.c | 6 +- arch/x86/cpu/ivybridge/gma.c | 15 ++- arch/x86/cpu/quark/quark.c| 4 +- arch/x86/cpu/queensbay/topcliff.c | 4 +- arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 3 +- arch/x86/lib/bios.c | 3 +- arch/x86/lib/bios_interrupts.c| 36 --- board/compulab/trimslice/trimslice.c | 8 -- board/nvidia/cardhu/cardhu.c | 6 -- board/nvidia/jetson-tk1/jetson-tk1.c | 6 -- board/nvidia/p2371-2180/p2371-2180.c | 6 -- board/toradex/apalis_t30/apalis_t30.c | 6 -- common/cmd_pci.c | 2 +- common/cmd_scsi.c | 14 ++- configs/evb-rk3036_defconfig | 6 ++ drivers/block/ahci.c | 70 ++-- drivers/core/device.c | 31 -- drivers/core/root.c | 21 drivers/mmc/pci_mmc.c | 15 ++- drivers/net/designware.c | 2 +- drivers/net/e1000.c | 4 +- drivers/net/pch_gbe.c | 2 +- drivers/net/rtl8169.c | 84 +++ drivers/pci/Makefile | 7 +- drivers/pci/pci-uclass.c | 240 ++ drivers/pci/pci.c | 5 +- drivers/pci/pci_auto.c| 386 +++ drivers/pci/pci_auto_old.c| 54 ++ drivers/pci/pci_common.c | 86 +++ drivers/pci/pci_compat.c | 2 +- drivers/pci/pci_internal.h| 50 + drivers/pci/pci_rom.c | 47 - drivers/serial/Kconfig| 20 drivers/serial/ns16550.c | 7 +- drivers/serial/serial-uclass.c| 4 +- drivers/usb/eth/mcs7830.c
Re: [U-Boot] [PATCHv3 4/4] igep00x0: UBIize
Hi Heiko,
On Tue, Jan 12, 2016 at 10:08:21AM +0100, Heiko Schocher wrote:
> Am 11.01.2016 um 13:58 schrieb Ladislav Michl:
> >On Mon, Jan 11, 2016 at 07:20:06AM +0100, Heiko Schocher wrote:
> >>Beside of that, this patch does not apply ...
> >
> >Ah, igep00x0 part is based on top of this:
> >http://lists.denx.de/pipermail/u-boot/2016-January/240013.html
> >I silently hoped to be applied for 2016.01 release, but never mind :)
>
> ;-)
>
> Ah, I added them to my automated build, and now it works again :-D
>
> BTW: patch "[U-Boot,PATCHv2,2/5] igep00x0: Cleanup ethernet support"
> has a checkpatch warning, search in
>
> http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/43/steps/shell/logs/tbotlog
>
> for "2016-01-12 07:47:08,369"
Hmm, I do not agree with warning as I consider code pretty readable :)
Anyway, there is similar "unaligned case" few lines bellow. Perhaps send
additional patch to fix them both?
> >Now assumption is that once board switches to UBI, loading u-boot or kernel
> >from bare flash does not make a sense anymore, so with CONFIG_SPL_UBI
> >all that code in spl_nor.c (reevaluate?!), spl_nand.c and spl_onenand.c
> >is not used in favour of spl_ubi.c. As ubispl can load volumes by volume id
>
> I thought about this change too, and I think your assumption is OK
> here. Let us bring in this change, and if someone has other needs,
> we have to look again at this place .. but I think, if switching to
> use UBI, than it makes no sense to read in raw mode ...
>
> Other opinions?
>
> >and not by name, it is bringing some inconsistencies with for example ubi
> >environment code, which is using volume names. Is it worth fixing?
>
> It would be nice to have ... yes, if it is easy to do? Also we must
> have a look at the codesize.
It seems Thomas had a good reason to use volume ids, see ubi_scan_vid_hdr
called from ipl_scan.
> >All that ubispl_info structure is board specific and there is not much left
> >besides initializing it. Also volumes can differ per board basis, so
> >providing common function is somewhat questionable. However here it is,
> >just to show how does it look like. Suggestions are very welcome as silence
> >around this part of patch is a bit suspicious ;-)
>
> Questions are coming if there are users ;-)
>
> I vote for bringing this in, and we will see, where we have to make
> things more configurable ... some nitpicks below ...
Okay, I need to be able to load also bare zImage. This change is independent
and possibly controversial, so I'll put it here for disscusion :)
commit c092b3c0627dd8d4b3f3d756c58b53fcf205587f
Author: Ladislav Michl
Date: Tue Jan 12 16:37:04 2016 +0100
spl: zImage support in Falcon mode
Other payload than uImage is currently considered to be raw U-Boot
image. Check also for zImage in Falcon mode.
Signed-off-by: Ladislav Michl
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f3db7b5..07a9019 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -26,11 +26,13 @@ endif
obj-$(CONFIG_CPU_V7M) += cmd_boot.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_BOOTM) += zimage.o
obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
else
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
endif
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index a477cae..fbfc0ad 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -348,38 +348,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
return 0;
}
-#ifdef CONFIG_CMD_BOOTZ
-
-struct zimage_header {
- uint32_tcode[9];
- uint32_tzi_magic;
- uint32_tzi_start;
- uint32_tzi_end;
-};
-
-#defineLINUX_ARM_ZIMAGE_MAGIC 0x016f2818
-
-int bootz_setup(ulong image, ulong *start, ulong *end)
-{
- struct zimage_header *zi;
-
- zi = (struct zimage_header *)map_sysmem(image, 0);
- if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) {
- puts("Bad Linux ARM zImage magic!\n");
- return 1;
- }
-
- *start = zi->zi_start;
- *end = zi->zi_end;
-
- printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start,
- *end);
-
- return 0;
-}
-
-#endif /* CONFIG_CMD_BOOTZ */
-
#if defined(CONFIG_BOOTM_VXWORKS)
void boot_prep_vxworks(bootm_headers_t *images)
{
diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c
new file mode 100644
index 000..f870d72
--- /dev/null
+++ b/arch/arm/lib/zimage.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016
+ * Ladislav Michl
+ *
+ * bootz code:
+ * Copyright (C) 2012 Marek Vasut
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+
+#defineLINUX_ARM_ZIMAGE_MAGIC 0x016f2818
+
+struct arm_z_header {
+ uint32_tcode[9];
+
Re: [U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10
On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote: > On 01/12/2016 04:02 PM, Marek Vasut wrote: > > On Tuesday, January 12, 2016 at 09:56:42 PM, > > dingu...@opensource.altera.com > > > > wrote: > >> From: Dinh Nguyen > >> > >> Add the Arria10 reset manager defines that is used in Linux. Change the > >> license to SPDX. > >> > >> [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] > >> > >> Signed-off-by: Dinh Nguyen > > > > Applied all three to u-boot-socfpga/02-arria10 , thanks! > > > > btw what's the status of A10 ? What will I be able to compile it (and > > thus merge the stuff into mainline and ev. use it on actual A10) ? A > > board would be nice too ;-) > > Here is my list of to-do that is left for A10: > > - submit SDRAM controller > - rework FPGA manager for A10 > - port an SPL for A10 > > I think the most work will be the SDRAM controller as it needs quite a > bit of cleanup. I'm about ~25% through with that. Didn't you mention that you use nios2 that magically does that init for you? Shall I expect thousands of LoC SDRAM controller driver again or is there something "lighter" coming up ? ;-) > As for HW, I'll see what I can do. Don't worry about it too much. I also poked Chin about it some time ago, but I dunno where he got with this. Thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10
On 01/12/2016 04:02 PM, Marek Vasut wrote: > On Tuesday, January 12, 2016 at 09:56:42 PM, dingu...@opensource.altera.com > wrote: >> From: Dinh Nguyen >> >> Add the Arria10 reset manager defines that is used in Linux. Change the >> license to SPDX. >> >> [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] >> >> Signed-off-by: Dinh Nguyen > > Applied all three to u-boot-socfpga/02-arria10 , thanks! > > btw what's the status of A10 ? What will I be able to compile it (and thus > merge the stuff into mainline and ev. use it on actual A10) ? A board would > be nice too ;-) Here is my list of to-do that is left for A10: - submit SDRAM controller - rework FPGA manager for A10 - port an SPL for A10 I think the most work will be the SDRAM controller as it needs quite a bit of cleanup. I'm about ~25% through with that. As for HW, I'll see what I can do. Dinh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10
On Tuesday, January 12, 2016 at 09:56:42 PM, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen > > Add the Arria10 reset manager defines that is used in Linux. Change the > license to SPDX. > > [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] > > Signed-off-by: Dinh Nguyen Applied all three to u-boot-socfpga/02-arria10 , thanks! btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCHv2 3/3] arm: socfpga: arria10: update dwmac reset function to support Arria10
From: Dinh Nguyen
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.
Signed-off-by: Dinh Nguyen
---
v2: simplify the implementation a bit
---
arch/arm/mach-socfpga/include/mach/system_manager.h | 4 +---
arch/arm/mach-socfpga/misc.c| 14 ++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h
b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32 usb0_l3master;
u32 usb1_l3master;
u32 emac_global;
- u32 emac0;
- u32 emac1;
- u32 emac2;
+ u32 emac[3];
u32 _pad_0x50_0x5f[4];
u32 fpgaintf_en_global;
u32 fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index e8bd3cf..5ae1d7d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -22,7 +22,11 @@
#include
#include
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include
+#else
+#include
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int
of_reset_id)
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+ } else if (of_reset_id == EMAC2_RESET) {
+ reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+#else
+ clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
+ SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+ SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII);
+#endif
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
--
2.6.2
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[U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10
From: Dinh Nguyen Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX. [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel] Signed-off-by: Dinh Nguyen --- v2: Add commit hash-id for original commit from Linux kernel --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++ 1 file changed, 103 insertions(+) create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h new file mode 100644 index 000..7619ca2 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET32 +#define EMAC1_RESET33 +#define EMAC2_RESET34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define QSPI_RESET 38 +#define SDMMC_RESET39 +#define EMAC0_OCP_RESET40 +#define EMAC1_OCP_RESET41 +#define EMAC2_OCP_RESET42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +#define QSPI_OCP_RESET 46 +#define SDMMC_OCP_RESET47 +#define DMA_RESET 48 +#define SPIM0_RESET49 +#define SPIM1_RESET50 +#define SPIS0_RESET51 +#define SPIS1_RESET52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define L4WD0_RESET64 +#define L4WD1_RESET65 +#define L4SYSTIMER0_RESET 66 +#define L4SYSTIMER1_RESET 67 +#define SPTIMER0_RESET 68 +#define SPTIMER1_RESET 69 +/* 70-71 is reserved */ +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is reserved */ +#define UART0_RESET80 +#define UART1_RESET81 +/* 82-87 is reserved */ +#define GPIO0_RESET88 +#define GPIO1_RESET89 +#define GPIO2_RESET90 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 +#define F2SSDRAM0_RESET99 +#define F2SSDRAM1_RESET100 +#define F2SSDRAM2_RESET101 +#define DDRSCH_RESET 102 + +/* SYSMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET129 +/* 130 is reserved */ +#define FPGAMGR_RESET 131 +#define S2F_RESET 132 +#define SYSDBG_RESET 133 +#define OCRAM_OCP_RESET134 + +/* COLDMODRST */ +#define CLKMGRCOLD_RESET 160 +/* 161-162 is reserved */ +#define S2FCOLD_RESET 163 +#define TIMESTAMPCOLD_RESET164 +#define TAPCOLD_RESET 165 +#define HMCCOLD_RESET 166 +#define IOMGRCOLD_RESET167 + +/* NRSTMODRST */ +#define NRSTPINOE_RESET192 + +/* DBGMODRST */ +#define DBG_RESET 224 +#endif -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm: socfpga: combine clrbits/setbits into a single clrsetbits
From: Dinh Nguyen There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 517f629..e8bd3cf 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) return; } - /* Clearing emac0 PHY interface select to 0 */ - clrbits_le32(&sysmgr_regs->emacgrp_ctrl, -SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); - /* configure to PHY interface select choosed */ - setbits_le32(&sysmgr_regs->emacgrp_ctrl, -SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 5/6] MIPS: implement bit manipulating I/O accessors
Add support for functions clrbits_X(), setbits_X() and clrsetbits_X()
on MIPS.
Signed-off-by: Daniel Schwierzeck
---
Changes in v3: None
Changes in v2: None
arch/mips/include/asm/io.h | 54 ++
1 file changed, 54 insertions(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index eb06afa..43b4326 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -541,4 +541,58 @@ static inline void unmap_physmem(void *vaddr, unsigned
long flags)
{
}
+#define __BUILD_CLRBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val);\
+ __val &= ~clr; \
+ __val = cpu_to_##end(__val);\
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_SETBITS(bwlq, sfx, end, type) \
+ \
+static inline void setbits_##sfx(volatile void __iomem *mem, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val);\
+ __val |= set; \
+ __val = cpu_to_##end(__val);\
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type) \
+ \
+static inline void clrsetbits_##sfx(volatile void __iomem *mem,
\
+ type clr, type set) \
+{ \
+ type __val = __raw_read##bwlq(mem); \
+ __val = end##_to_cpu(__val);\
+ __val &= ~clr; \
+ __val |= set; \
+ __val = cpu_to_##end(__val);\
+ __raw_write##bwlq(__val, mem); \
+}
+
+#define BUILD_CLRSETBITS(bwlq, sfx, type) \
+ \
+__BUILD_CLRBITS(bwlq, sfx, sfx, type) \
+__BUILD_SETBITS(bwlq, sfx, sfx, type) \
+__BUILD_CLRSETBITS(bwlq, sfx, sfx, type)
+
+#define __to_cpu(v)(v)
+#define cpu_to__(v)(v)
+
+__BUILD_CLRBITS(b, 8, _, u8)
+__BUILD_SETBITS(b, 8, _, u8)
+__BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, u16)
+BUILD_CLRSETBITS(w, be16, u16)
+BUILD_CLRSETBITS(l, le32, u32)
+BUILD_CLRSETBITS(l, be32, u32)
+BUILD_CLRSETBITS(q, le64, u64)
+BUILD_CLRSETBITS(q, be64, u64)
+
#endif /* _ASM_IO_H */
--
2.5.0
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[U-Boot] [PATCH v3 4/6] MIPS: fix SPDX license identifier in remaining arch header files
Add a SPDX license identifier to MIPS header files where it is still missing. Signed-off-by: Daniel Schwierzeck --- Changes in v3: None Changes in v2: None arch/mips/include/asm/addrspace.h | 6 ++ arch/mips/include/asm/bitops.h | 6 ++ arch/mips/include/asm/byteorder.h | 6 ++ arch/mips/include/asm/cachectl.h| 6 ++ arch/mips/include/asm/cacheops.h| 6 ++ arch/mips/include/asm/const.h | 6 +- arch/mips/include/asm/posix_types.h | 9 +++-- arch/mips/include/asm/reboot.h | 6 ++ arch/mips/include/asm/reg.h | 6 ++ arch/mips/include/asm/sgidefs.h | 6 ++ arch/mips/include/asm/string.h | 6 ++ arch/mips/include/asm/system.h | 6 ++ arch/mips/include/asm/types.h | 6 ++ arch/mips/include/asm/unaligned.h | 6 ++ 14 files changed, 32 insertions(+), 55 deletions(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index e7fe6ed..0994e96 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -1,11 +1,9 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 99 Ralf Baechle * Copyright (C) 2000, 2002 Maciej W. Rozycki * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + * + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _ASM_ADDRSPACE_H #define _ASM_ADDRSPACE_H diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index c31ff6e..cce6995 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -1,10 +1,8 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (r...@gnu.org) * Copyright (c) 2000 Silicon Graphics, Inc. + * + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _ASM_BITOPS_H #define _ASM_BITOPS_H diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index b5e685f..67fdf71 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1996, 99, 2003 by Ralf Baechle + * + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _ASM_BYTEORDER_H #define _ASM_BYTEORDER_H diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h index f3ce721..5e77dfa 100644 --- a/arch/mips/include/asm/cachectl.h +++ b/arch/mips/include/asm/cachectl.h @@ -1,9 +1,7 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * SPDX-License-Identifier:GPL-2.0 */ #ifndef_ASM_CACHECTL #define_ASM_CACHECTL diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index af2adc7..a3b07c6 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -1,12 +1,10 @@ /* * Cache operations for the cache instruction. * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle * (C) Copyright 1999 Silicon Graphics, Inc. + * + * SPDX-License-Identifier:GPL-2.0 */ #ifndef__ASM_CACHEOPS_H #define__ASM_CACHEOPS_H diff --git a/arch/mips/include/asm/const.h b/arch/mips/include/asm/const.h index c872bfd..f600e7a 100644 --- a/arch/mips/include/asm/const.h +++ b/arch/mips/include/asm/const.h @@ -1,4 +1,8 @@ -/* const.h: Macros for dealing with constants. */ +/* + * const.h: Macros for dealing with constants. + * + * SPDX-License-Identifier:GPL-2.0 + */ #ifndef _LINUX_CONST_H #define _LINUX_CONST_H diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 4deac52..90c0aff 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -1,10 +1,7 @@ -/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * +/* * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle + * + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _ASM_POSIX_TYPES_H #define _ASM_POSIX_TYPES_H diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h index 978d206..2a6b724
[U-Boot] [PATCH v3 6/6] MIPS: DO NOT MERGE: test I/O accessors
Test patch for compile testing and disassembly analysis of
the updated and new I/O accessors.
Signed-off-by: Daniel Schwierzeck
---
Changes in v3:
- rebased to u-boot-mips/next
Changes in v2: None
arch/mips/lib/io.c | 183 +
1 file changed, 183 insertions(+)
diff --git a/arch/mips/lib/io.c b/arch/mips/lib/io.c
index b2d4a09..e80990e 100644
--- a/arch/mips/lib/io.c
+++ b/arch/mips/lib/io.c
@@ -5,8 +5,191 @@
* SPDX-License-Identifier:GPL-2.0+
*/
+#include
+#include
+
/*
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
const unsigned long mips_io_port_base = -1;
+
+static const void __iomem *addr1 = (const void __iomem
*)CKSEG1ADDR(0x8000);
+static void __iomem *addr2 = (void __iomem *)CKSEG1ADDR(0x80001000);
+
+void test_readb(void)
+{
+ u8 val = readb(addr1);
+ writeb(val, addr2);
+}
+
+void test_readw(void)
+{
+ u16 val = readw(addr1);
+ writew(val, addr2);
+}
+
+void test_readl(void)
+{
+ u32 val = readl(addr1);
+ writel(val, addr2);
+}
+
+void test_readq(void)
+{
+ u32 val = readq(addr1);
+ writeq(val, addr2);
+}
+
+void test_readb_be(void)
+{
+ u8 val = readb_be(addr1);
+ writeb_be(val, addr2);
+}
+
+void test_readw_be(void)
+{
+ u16 val = readw_be(addr1);
+ writew_be(val, addr2);
+}
+
+void test_readl_be(void)
+{
+ u32 val = readl_be(addr1);
+ writel_be(val, addr2);
+}
+
+void test_readq_be(void)
+{
+ u32 val = readq_be(addr1);
+ writeq_be(val, addr2);
+}
+
+void test_raw_readb(void)
+{
+ u8 val = __raw_readb(addr1);
+ __raw_writeb(val, addr2);
+}
+
+void test_raw_readw(void)
+{
+ u16 val = __raw_readw(addr1);
+ __raw_writew(val, addr2);
+}
+
+void test_raw_readl(void)
+{
+ u32 val = __raw_readl(addr1);
+ __raw_writel(val, addr2);
+}
+
+void test_raw_readq(void)
+{
+ u32 val = __raw_readq(addr1);
+ __raw_writeq(val, addr2);
+}
+
+void test_clrbits_8(void)
+{
+ clrbits_8(addr2, BIT(2));
+}
+
+void test_setbits_8(void)
+{
+ setbits_8(addr2, BIT(3));
+}
+
+void test_clrsetbits_8(void)
+{
+ clrsetbits_8(addr2, BIT(2), BIT(3));
+}
+
+void test_clrbits_le16(void)
+{
+ clrbits_le16(addr2, BIT(9));
+}
+
+void test_setbits_le16(void)
+{
+ setbits_le16(addr2, BIT(10));
+}
+
+void test_clrsetbits_le16(void)
+{
+ clrsetbits_le16(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be16(void)
+{
+ clrbits_be16(addr2, BIT(9));
+}
+
+void test_setbits_be16(void)
+{
+ setbits_be16(addr2, BIT(10));
+}
+
+void test_clrsetbits_be16(void)
+{
+ clrsetbits_be16(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_le32(void)
+{
+ clrbits_le32(addr2, BIT(9));
+}
+
+void test_setbits_le32(void)
+{
+ setbits_le32(addr2, BIT(10));
+}
+
+void test_clrsetbits_le32(void)
+{
+ clrsetbits_le32(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be32(void)
+{
+ clrbits_be32(addr2, BIT(9));
+}
+
+void test_setbits_be32(void)
+{
+ setbits_be32(addr2, BIT(10));
+}
+
+void test_clrsetbits_be32(void)
+{
+ clrsetbits_be32(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_le64(void)
+{
+ clrbits_le64(addr2, BIT(9));
+}
+
+void test_setbits_le64(void)
+{
+ setbits_le64(addr2, BIT(10));
+}
+
+void test_clrsetbits_le64(void)
+{
+ clrsetbits_le64(addr2, BIT(9), BIT(10));
+}
+
+void test_clrbits_be64(void)
+{
+ clrbits_be64(addr2, BIT(9));
+}
+
+void test_setbits_be64(void)
+{
+ setbits_be64(addr2, BIT(10));
+}
+
+void test_clrsetbits_be64(void)
+{
+ clrsetbits_be64(addr2, BIT(9), BIT(10));
+}
--
2.5.0
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[U-Boot] [PATCH v3 2/6] MIPS: sync I/O related header files with linux-4.4
Mainly sync asm/io.h to get a working ioremap() implementation as well as the full set of I/O accessors. Pull in additional header files to make this work. Furthermore port over the directory 'arch/mips/include/asm/mach-generic/' with contains default definitions for I/O and memory spaces and default implementations for mapping those spaces. All files in that directory can be overwritten by a SoC/machine. Signed-off-by: Daniel Schwierzeck --- Changes in v3: None Changes in v2: - fix __ioremap_node() implementation for 64 Bit arch/mips/Makefile | 5 +- arch/mips/include/asm/addrspace.h | 4 +- arch/mips/include/asm/const.h | 27 + arch/mips/include/asm/cpu-features.h | 30 + arch/mips/include/asm/io.h | 761 +++-- .../asm/mach-generic/cpu-feature-overrides.h | 11 + arch/mips/include/asm/mach-generic/ioremap.h | 32 + arch/mips/include/asm/mach-generic/mangle-port.h | 50 ++ arch/mips/include/asm/mach-generic/spaces.h| 102 +++ arch/mips/include/asm/pgtable-bits.h | 283 10 files changed, 941 insertions(+), 364 deletions(-) create mode 100644 arch/mips/include/asm/const.h create mode 100644 arch/mips/include/asm/cpu-features.h create mode 100644 arch/mips/include/asm/mach-generic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-generic/ioremap.h create mode 100644 arch/mips/include/asm/mach-generic/mangle-port.h create mode 100644 arch/mips/include/asm/mach-generic/spaces.h create mode 100644 arch/mips/include/asm/pgtable-bits.h diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 90cd590..2133e7e 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -25,4 +25,7 @@ tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc -PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) +# Include default header files +cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic + +PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) $(cflags-y) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index b768bb5..e7fe6ed 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -10,6 +10,8 @@ #ifndef _ASM_ADDRSPACE_H #define _ASM_ADDRSPACE_H +#include + /* * Configure language */ @@ -50,7 +52,7 @@ */ #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fff) #define XPHYSADDR(a) ((_ACAST64_(a)) & \ -_CONST64_(0x00ff)) +_CONST64_(0x)) #ifdef CONFIG_64BIT diff --git a/arch/mips/include/asm/const.h b/arch/mips/include/asm/const.h new file mode 100644 index 000..c872bfd --- /dev/null +++ b/arch/mips/include/asm/const.h @@ -0,0 +1,27 @@ +/* const.h: Macros for dealing with constants. */ + +#ifndef _LINUX_CONST_H +#define _LINUX_CONST_H + +/* Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +#ifdef __ASSEMBLY__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* !(_LINUX_CONST_H) */ diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h new file mode 100644 index 000..a6e9d94 --- /dev/null +++ b/arch/mips/include/asm/cpu-features.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * SPDX-License-Identifier:GPL-2.0 + */ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include + +#ifdef CONFIG_32BIT +# ifndef cpu_has_64bits +# define cpu_has_64bits0 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 0 +# endif +#endif + +#ifdef CONFIG_64BIT +# ifndef cpu_has_64bits +# define cpu_has_64bits1 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 1 +# endif +#endif + +#endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index a7ab087..eb06afa 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -1,21 +1,28 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1994, 1995 Waldorf GmbH - * Copyright (C) 1994 - 2000 Ralf Baechle
[U-Boot] [PATCH v3 1/6] net: pcnet: refactor mapping of virtual addresses to physical ones
pci_virt_to_mem() uses virt_to_phys() to get the physical address.
But pci_virt_to_mem() is also called with uncached addresses which
is wrong according to the documentation of virt_to_phys().
Refactor the PCI_TO_MEM() macro to optionally map an uncached address
back to a cached one before calling pci_virt_to_mem().
Currently pcnet works because virt_to_phys() is incorrectly implemented
on MIPS. With the upcoming asm header file update for MIPS, the
virt_to_phys() implementation will be fixed. Thus this patch is needed
to keep pcnet working on MIPS Malta board.
Signed-off-by: Daniel Schwierzeck
---
@Joe, MIPS Malta board is the only user of pcnet and the patch is required
for my patch series which updates the MIPS asm header files. Thus I'd like
to merge this via the MIPS tree.
Changes in v3:
- newly added due to a regression on MIPS Malta board
Changes in v2: None
drivers/net/pcnet.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index cfcb1b4..16a7512 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -134,8 +134,17 @@ static int pcnet_recv (struct eth_device *dev);
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
-#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
-#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
+static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
+ void *addr, bool uncached)
+{
+ pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+ void *virt_addr = addr;
+
+ if (uncached)
+ virt_addr = (void *)CKSEG0ADDR(addr);
+
+ return pci_virt_to_mem(devbusfn, virt_addr);
+}
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
@@ -352,7 +361,8 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
- uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]);
+ addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+ uc->rx_ring[i].base = cpu_to_le32(addr);
uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
uc->rx_ring[i].status = cpu_to_le16(0x8000);
PCNET_DEBUG1
@@ -383,8 +393,10 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
- uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
- uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);
+ addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+ uc->init_block.rx_ring = cpu_to_le32(addr);
+ addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+ uc->init_block.tx_ring = cpu_to_le32(addr);
PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
uc->init_block.tlen_rlen,
@@ -394,7 +406,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
* Tell the controller where the Init Block is located.
*/
barrier();
- addr = PCI_TO_MEM(dev, &lp->uc->init_block);
+ addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true);
pcnet_write_csr(dev, 1, addr & 0x);
pcnet_write_csr(dev, 2, (addr >> 16) & 0x);
@@ -424,6 +436,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
{
int i, status;
+ u32 addr;
struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
@@ -451,9 +464,10 @@ static int pcnet_send(struct eth_device *dev, void
*packet, int pkt_len)
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
+ addr = pcnet_virt_to_mem(dev, packet, false);
writew(-pkt_len, &entry->length);
writel(0, &entry->misc);
- writel(PCI_TO_MEM(dev, packet), &entry->base);
+ writel(addr, &entry->base);
writew(0x8300, &entry->status);
/* Trigger an immediate send poll. */
--
2.5.0
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[U-Boot] [PATCH v3 3/6] MIPS: sync processor and register definitions with linux-4.4
Update definitions for processor, registers as well as assemby macros. Signed-off-by: Daniel Schwierzeck --- Changes in v3: None Changes in v2: None arch/mips/include/asm/asm.h | 126 ++-- arch/mips/include/asm/isadep.h|6 +- arch/mips/include/asm/mipsregs.h | 1495 ++--- arch/mips/include/asm/processor.h |6 +- arch/mips/include/asm/ptrace.h| 99 ++- arch/mips/include/asm/regdef.h| 12 +- arch/mips/lib/cache.c |4 +- arch/mips/lib/cache_init.S| 16 +- 8 files changed, 1211 insertions(+), 553 deletions(-) diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 8c9c4e2..44694a3 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -1,8 +1,4 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle * Copyright (C) 1999 by Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. @@ -13,6 +9,8 @@ * Some of the routines below contain useless nops that will be optimized * away by gas in -O mode. These nops are however required to fill delay * slots in noreorder mode. + * + * SPDX-License-Identifier:GPL-2.0 */ #ifndef __ASM_ASM_H #define __ASM_ASM_H @@ -33,58 +31,58 @@ * Not used for the kernel but here seems to be the right place. */ #ifdef __PIC__ -#define CPRESTORE(register) \ +#define CPRESTORE(register)\ .cprestore register -#define CPADD(register) \ +#define CPADD(register)\ .cpadd register -#define CPLOAD(register)\ - .cpload register +#define CPLOAD(register) \ + .cpload register #else #define CPRESTORE(register) #define CPADD(register) #define CPLOAD(register) #endif -#define ENTRY(symbol) \ - .globl symbol; \ - .type symbol, @function; \ - .entsymbol, 0; \ +#define ENTRY(symbol) \ + .globl symbol; \ + .type symbol, @function; \ + .entsymbol, 0; \ symbol: /* * LEAF - declare leaf routine */ -#defineLEAF(symbol)\ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .entsymbol, 0; \ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .entsymbol, 0; \ .section .text.symbol, "x"; \ symbol:.frame sp, 0, ra /* * NESTED - declare nested routine entry point */ -#defineNESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .entsymbol, 0; \ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .entsymbol, 0; \ .section .text.symbol, "x"; \ symbol:.frame sp, framesize, rpc /* * END - mark end of function */ -#defineEND(function) \ - .endfunction; \ +#define END(function) \ + .endfunction; \ .size function, .-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* @@ -98,16 +96,16 @@ symbol: /* * ABS - export absolute symbol */ -#defineABS(symbol,value) \ - .globl symbol; \ +#define ABS(symbol,value) \ + .globl symbol; \ symbol = value -#define
[U-Boot] [PATCH v3 0/6] MIPS: sync asm header files with linux-4.4
This patch series updates all MIPS asm header files containing I/O code as well as processor, register and assembly definitions. The source of the update are the MIPS asm header files of linux-4.4. The main goal is to get a complete set of I/O accessors on MIPS and to support platform-specific address spaces and mappings. Also a working ioremap() implementation will be added, which supports platform-specific callbacks. Furthermore support for bit manipulating I/O accessors (clrbits_X, setbits_X, clrsetbits_X) will be added. The patch series is also available on git://git.denx.de/u-boot-mips.git in branch mips_io_v2 and based on next branch. Changes in v3: - newly added due to a regression on MIPS Malta board - rebased to u-boot-mips/next Changes in v2: - fix __ioremap_node() implementation for 64 Bit Daniel Schwierzeck (6): net: pcnet: refactor mapping of virtual addresses to physical ones MIPS: sync I/O related header files with linux-4.4 MIPS: sync processor and register definitions with linux-4.4 MIPS: fix SPDX license identifier in remaining arch header files MIPS: implement bit manipulating I/O accessors MIPS: DO NOT MERGE: test I/O accessors arch/mips/Makefile |5 +- arch/mips/include/asm/addrspace.h | 10 +- arch/mips/include/asm/asm.h| 126 +- arch/mips/include/asm/bitops.h |6 +- arch/mips/include/asm/byteorder.h |6 +- arch/mips/include/asm/cachectl.h |6 +- arch/mips/include/asm/cacheops.h |6 +- arch/mips/include/asm/const.h | 31 + arch/mips/include/asm/cpu-features.h | 30 + arch/mips/include/asm/io.h | 813 ++- arch/mips/include/asm/isadep.h |6 +- .../asm/mach-generic/cpu-feature-overrides.h | 11 + arch/mips/include/asm/mach-generic/ioremap.h | 32 + arch/mips/include/asm/mach-generic/mangle-port.h | 50 + arch/mips/include/asm/mach-generic/spaces.h| 102 ++ arch/mips/include/asm/mipsregs.h | 1495 ++-- arch/mips/include/asm/pgtable-bits.h | 283 arch/mips/include/asm/posix_types.h|9 +- arch/mips/include/asm/processor.h |6 +- arch/mips/include/asm/ptrace.h | 99 +- arch/mips/include/asm/reboot.h |6 +- arch/mips/include/asm/reg.h|6 +- arch/mips/include/asm/regdef.h | 12 +- arch/mips/include/asm/sgidefs.h|6 +- arch/mips/include/asm/string.h |6 +- arch/mips/include/asm/system.h |6 +- arch/mips/include/asm/types.h |6 +- arch/mips/include/asm/unaligned.h |6 +- arch/mips/lib/cache.c |4 +- arch/mips/lib/cache_init.S | 16 +- arch/mips/lib/io.c | 183 +++ drivers/net/pcnet.c| 28 +- 32 files changed, 2440 insertions(+), 977 deletions(-) create mode 100644 arch/mips/include/asm/const.h create mode 100644 arch/mips/include/asm/cpu-features.h create mode 100644 arch/mips/include/asm/mach-generic/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-generic/ioremap.h create mode 100644 arch/mips/include/asm/mach-generic/mangle-port.h create mode 100644 arch/mips/include/asm/mach-generic/spaces.h create mode 100644 arch/mips/include/asm/pgtable-bits.h -- 2.5.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] pull request: u-boot-uniphier/master
On Wed, Jan 13, 2016 at 02:05:28AM +0900, Masahiro Yamada wrote: > Hi Tom, > > U-Boot 2016.01 is out and it means the MW is open. > Excuse my haste, but here is the first pull-req for the 2016.04. > Please pull! Happy to get one so early :) > > > The following changes since commit fa85e826c16b9ce1ad302a57e9c4b24db0d8b930: > > Prepare v2016.01 (2016-01-12 09:06:54 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-uniphier.git master > > for you to fetch changes up to e69514cc7087255d0e9754a9bf04129309d81ed5: > > ARM: uniphier: fix recommended board setting in document (2016-01-13 > 01:55:02 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4] MIPS: add initial infrastructure for device-tree files
Prepare sub-folder for device-tree files. Make support for
device-tree on MIPS available in Kbuild/Kconfig.
Signed-off-by: Daniel Schwierzeck
Signed-off-by: Purna Chandra Mandal
---
Changes in v4:
- add directory arch/mips/dts/include/
- add symlink arch/mips/dts/include/dt-bindings/
Changes in v3:
- keep section .dtb.init.rodata during link in case of CONFIG_OF_EMBED, .dtb
only
does not work
Changes in v2:
- add arch/mips/dts to clean list in dts/Makefile
- keep section .dtb during link in case of CONFIG_OF_EMBED
arch/Kconfig | 1 +
arch/mips/config.mk | 1 +
arch/mips/dts/.gitignore | 1 +
arch/mips/dts/Makefile| 16
arch/mips/dts/include/dt-bindings | 1 +
arch/mips/dts/skeleton.dtsi | 23 +++
dts/Makefile | 2 +-
7 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/.gitignore
create mode 100644 arch/mips/dts/Makefile
create mode 12 arch/mips/dts/include/dt-bindings
create mode 100644 arch/mips/dts/skeleton.dtsi
diff --git a/arch/Kconfig b/arch/Kconfig
index 1709d40..ec12013 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -55,6 +55,7 @@ config MIPS
select HAVE_PRIVATE_LIBGCC
select HAVE_GENERIC_BOARD
select SYS_GENERIC_BOARD
+ select SUPPORT_OF_CONTROL
config NDS32
bool "NDS32 architecture"
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 415ec8a..b78d495 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -72,6 +72,7 @@ PF_ABICALLS := -mabicalls
PF_PIC := -fpic
PF_PIE := -pie
PF_OBJCOPY := -j .got -j .u_boot_list -j .rel.dyn -j
.padding
+PF_OBJCOPY += -j .dtb.init.rodata
endif
PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC)
diff --git a/arch/mips/dts/.gitignore b/arch/mips/dts/.gitignore
new file mode 100644
index 000..b60ed20
--- /dev/null
+++ b/arch/mips/dts/.gitignore
@@ -0,0 +1 @@
+*.dtb
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
new file mode 100644
index 000..47b6eb5
--- /dev/null
+++ b/arch/mips/dts/Makefile
@@ -0,0 +1,16 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+dtb-y +=
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
diff --git a/arch/mips/dts/include/dt-bindings
b/arch/mips/dts/include/dt-bindings
new file mode 12
index 000..0cecb3d
--- /dev/null
+++ b/arch/mips/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/mips/dts/skeleton.dtsi b/arch/mips/dts/skeleton.dtsi
new file mode 100644
index 000..24ee6c3
--- /dev/null
+++ b/arch/mips/dts/skeleton.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value. The bootloader will typically populate the memory
+ * node.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ };
+
+ aliases {
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>;
+ };
+};
diff --git a/dts/Makefile b/dts/Makefile
index d3122aa..c4ac153 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -45,4 +45,4 @@ dtbs: $(obj)/dt.dtb
clean-files := dt.dtb.S
# Let clean descend into dts directories
-subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts
../arch/x86/dts
+subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts
../arch/sandbox/dts ../arch/x86/dts
--
2.5.0
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Re: [U-Boot] [PATCH 16/17] arm: ls1021atwr: Disable CONFIG_E1000 temporarily
On 01/11/2016 10:38 PM, Bin Meng wrote: > Before we switch to use driver model ethernet support, disable > CONFIG_E1000 temporarily as with driver model ethernet, E1000 > driver depends on driver model PCI which is not ready on this > board yet. > Any idea when PCI/E1000 can be enabled? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] pull request: u-boot-uniphier/master
Hi Tom,
U-Boot 2016.01 is out and it means the MW is open.
Excuse my haste, but here is the first pull-req for the 2016.04.
Please pull!
The following changes since commit fa85e826c16b9ce1ad302a57e9c4b24db0d8b930:
Prepare v2016.01 (2016-01-12 09:06:54 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-uniphier.git master
for you to fetch changes up to e69514cc7087255d0e9754a9bf04129309d81ed5:
ARM: uniphier: fix recommended board setting in document (2016-01-13
01:55:02 +0900)
Masahiro Yamada (7):
ARM: uniphier: kill bogus header includes
ARM: uniphier: move cmd_ddrphy.c to dram subdirectory
ARM: uniphier: move cmd_pinmon.c to boot-mode subdirectory
ARM: uniphier: move headers out of include/mach directory
ARM: uniphier: add DRAM init code for ProXstream2/PH1-LD6b
ARM: uniphier: add dump command for DDR Multi PHY registers
ARM: uniphier: fix recommended board setting in document
arch/arm/mach-uniphier/Kconfig | 9 +
arch/arm/mach-uniphier/Makefile | 2 -
arch/arm/mach-uniphier/{include/mach => }/arm-mpcore.h | 0
arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c | 5 +-
arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c| 5 +-
arch/arm/mach-uniphier/{include/mach => bcu}/bcu-regs.h | 0
arch/arm/mach-uniphier/board_common.c| 3 +-
arch/arm/mach-uniphier/board_early_init_f.c | 6 +-
arch/arm/mach-uniphier/board_early_init_r.c | 3 +-
arch/arm/mach-uniphier/boards.c | 3 +-
arch/arm/mach-uniphier/boot-mode/Makefile| 2 +
arch/arm/mach-uniphier/{include/mach => boot-mode}/boot-device.h | 0
arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c | 6 +-
arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c| 6 +-
arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c| 6 +-
arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c | 7 +-
arch/arm/mach-uniphier/boot-mode/boot-mode.c | 8 +-
arch/arm/mach-uniphier/{ => boot-mode}/cmd_pinmon.c | 7 +-
arch/arm/mach-uniphier/cache_uniphier.c | 3 +-
arch/arm/mach-uniphier/clk/clk-ph1-ld4.c | 5 +-
arch/arm/mach-uniphier/clk/clk-ph1-pro4.c| 5 +-
arch/arm/mach-uniphier/clk/clk-ph1-pro5.c| 5 +-
arch/arm/mach-uniphier/clk/clk-proxstream2.c | 5 +-
arch/arm/mach-uniphier/cmd_ddrmphy.c |
329 ++
arch/arm/mach-uniphier/cpu_info.c| 3 +-
arch/arm/mach-uniphier/debug_ll.S| 7 +-
arch/arm/mach-uniphier/dram/Makefile | 5 +
arch/arm/mach-uniphier/{ => dram}/cmd_ddrphy.c | 3 +-
arch/arm/mach-uniphier/dram/ddrmphy-regs.h | 146
arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 3 +-
arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c| 3 +-
arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c| 3 +-
arch/arm/mach-uniphier/{include/mach => dram}/ddrphy-regs.h | 0
arch/arm/mach-uniphier/dram/ddrphy-training.c| 3 +-
arch/arm/mach-uniphier/dram/umc-ph1-ld4.c| 7 +-
arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 7 +-
arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 7 +-
arch/arm/mach-uniphier/dram/umc-proxstream2.c|
669 +
arch/arm/mach-uniphier/{include/mach => dram}/umc-regs.h | 0
arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c | 5 +-
arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c| 5 +-
arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c | 5 +-
arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c| 4 +-
arch/arm/mach-uniphier/{include/mach => }/init.h | 1 +
arch/arm/mach-uniphier/init/init-ph1-ld4.c | 6 +-
arch/arm/mach-uniphier/init/init-ph1-pro4.c | 6 +-
arch/arm/mach-uniphier/init/init-ph1-pro5.c | 6 +-
arch/arm/mach-uniphier/init/init-ph1-sld3.c | 6 +-
arch/arm/mach-uniphier/init/init-ph1-sld8.c | 6 +-
arch/arm/mach-uniphier/init/init-proxstream2.c | 14 +-
arch/arm/mach-uniphier/init/init.c | 5 +-
arch/arm/mach-uniphier/late_lowlevel_init.S | 3 +-
arch/arm/mach-uniphier/low
Re: [U-Boot] [PATCH 0/7] ARM: uniphier: changes for v2016.04-rc1
2016-01-09 1:51 GMT+09:00 Masahiro Yamada : > This series includes a set of clean-ups, new features. > I want to merge them when the merge window opens. > > > > Masahiro Yamada (7): > ARM: uniphier: kill bogus header includes > ARM: uniphier: move cmd_ddrphy.c to dram subdirectory > ARM: uniphier: move cmd_pinmon.c to boot-mode subdirectory > ARM: uniphier: move headers out of include/mach directory > ARM: uniphier: add DRAM init code for ProXstream2/PH1-LD6b > ARM: uniphier: add dump command for DDR Multi PHY registers > ARM: uniphier: fix recommended board setting in document Series, applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt: __of_translate_address(): check parent's 'ranges' before translate
On 01/12/2016 03:25 AM, Przemyslaw Marczak wrote:
Hello Stephen,
On 01/11/2016 05:47 PM, Stephen Warren wrote:
On 01/11/2016 04:21 AM, Przemyslaw Marczak wrote:
Hello Stephen,
On 01/07/2016 07:25 PM, Stephen Warren wrote:
On 01/07/2016 04:40 AM, Przemyslaw Marczak wrote:
The present implementation of __of_translate_address() taken
from the Linux, is designed for translate bus/child address
mappings by using 'ranges' property - and it doesn't allow
for checking an address for a device's node with zero size-cells.
The 'size-cells > 0' is required for bus/child address mapping,
but is not required for non-memory mapped address, e.g.: I2C chip.
Then when we need only raw 'reg' property's value.
Since the I2C device address goes to a single-cell reg property,
support for that case is welcome, but currently calling dev_get_addr()
for I2C device will return 'FDT_ADDR_T_NONE', and print the warning:
warning:
__of_translate_address: Bad cell count for 'some-dev'
This patch takes the wrong approach.
It simply doesn't make sense to /attempt/ to translate an I2C address
into an MMIO address space. It's a nonsensical operation; no such
translation is possible under any circumstances because I2C and MMIO
addresses mean completely different things and simply can't be
translated to each-other.
Rather than making this nonsensical operation succeed in a way that
gives the desired no-op result, the nonsensical operation simply
shouldn't be performed in the first place.
Okay, the example with I2C may be little confusing - I could use some
general naming convention. However, this patch updates FDT-related code
only.
In one of your previous e-mails, you well argued that we shouldn't use
dev_get_reg() for some buses, since they have a different 'reg' meaning.
You are right, using dev_get_addr() as universal function may be
nonsensical.
Please note, that the present implementation of function:
'__of_translate_address()' - allows for 1:1 translation, but only if
'#size-cells' exists. So the below case is possible:
--
parent {
address-cells = <1>;
size-cells = <1>;
reg = <0x1000 0x1000>;
child {
reg = <0xa00 0x100>;
};
};
dev_get_reg(child) - will return '0xa00'
--
If we don't need the address length, we can define:
--
parent {
address-cells = <1>;
size-cells = <0>;
reg = <0x1000 0x1000>;
child {
reg = <0xa00>;
};
};
This case won't ever appear in a correctly written DT where reg
represents an MMIO address; MMIO addresses always have sizes, and hence
can't have size-cells=0. Hence, translating through a DT structures like
that is an error case, and shouldn't work.
As we found out, the 'reg' property can represent not only MMIO, but may
have other meaning,
Of course.
so the above case is possible.
Yes and no.
That DT snippet is certainly possible.
However, that's irrelevant to whether address translation should be
attempted across that boundary. *That* is not legal and should not be
attempted.
> The 'reg' for the
parent bus can represent MMIO (depends on what its parent defines) and
the child is non-MMIO.
Correct.
You won't allow to use dev_get_addr() for other than MMIO addresses.
Ok, I have no more arguments and no more time.
"You" is incorrect. This has absolutely nothing to do with me, but
rather the rule is imposed by the semantics of device tree.
Also, I never said that dev_get_addr() must not be used for non-MMIO
addresses. In fact, I offered a suggestion to make it work correctly.
What I actually stated is that address translation must not be attempted
across boundaries between address spaces, since it is semantically
non-sensical.
My issue can be also fixed by removing dev_get_addr() call from Exynos
GPIO driver - so I will do this and within this change, will also revert
the commit:
"fdt: fix address cell count checking in fdt_translate_address()"
That sounds fine. It'd be better to introduce some code into the I2C
subsystem to handle this, but the approach you mention should work in
practice.
___
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[U-Boot] [ANN] U-Boot v2016.01 released
Hey all, I've pushed v2016.01 out to the git servers and the tarballs are now available at both: ftp://ftp.denx.de/pub/u-boot/ https://www.amazon.com/clouddrive/share/iQRojZzxJnhZwGGUcyDdQDl6E5MAlTEeVwuCDdgUDo8?_encoding=UTF8&mgh=1&ref_=cd_ph_share_link_copy We've got the usual level of Kconfig and device model and general fixups going on, so thanks again everyone, and please feel free to follow up with what you would like to highlight. The big thing I want to talk about here is that I'm going to try an experiment. For the next 6 months, I want to try releasing every 2 months instead of 3. I'm still going to hold the release until I'm happy with it rather than release because it's the release date. But I think this will help me to be good about saying "too late, sorry" and also make that easier for others to hear too. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Newbie to u-boot needs help! Please help if you can
Hello Kevin Alexander, On 01/11/2016 03:13 PM, Kevin Alexander wrote: Hello I am making a bigeffort to try to acquire knowledge regarding embedded Linux. A big effort is a great idea. A long association is also beneficial as a lot of stuff happens that is not documented well (or at all) and being around provides for exposure to this type of change. Myprimary reference is the book entitled 'Embedded Linux Primer, SecondEdition A Practical, Real-World Approach' by Christopher Hallinan,published 2010 U-Boot has recently (at least when compared to the time taken to write and publish a book) gone through three major changes that I'm aware of. My work includes some U-Boot customization so I have some exposure to this, but I'm anything but an expert or core U-Boot developer. 1) The configuration system has changed from one based primarily on large number of #define in header files to something based closely on KConfig as used in the Linux kernel. 2) The build system has moved quite close to KBuild as used in the Linux kernel. 3) A unified device driver model has been introduced and conversion of existing drivers is currently under way. I have reachedchapter 7, 'Bootloaders', and I am having a few problems with thischapter. In section 7.3 it starts to make mention of u-boot. Aftergit cloning and examining the latest u boot source tree, it isapparent that the description in the book about how to configure andbuild u-boot is not congruent the latest u-boot source tree. Cansomeone reply to this message, or point me to a(nother) mailing list(s),wikis or urls that would allow me to acquire a good understanding onhow configure and build u-boot as represented by the latest u-bootsource tree. I'm not sure official U-Boot documentation has been modified yet to reflect these changes. Even if it had, it is likely to assume familiarity with the Linux kernel KConfig and KBuild systems. Referring to the Linux documentation for these subsystems might be helpful in understanding how the similar U-Boot facilities operate. The main documentation for U-Boot is the README file at the top directory level. Also, see files in the doc subdirectory. However, as I said, don't be too surprised if these sources are not up to date. Many thanks in advance Good luck, and welcome to U-Boot. If you end up developing understanding of these parts of the system by exploration, others in the community (like me) and other newbie's could really benifit from your knowledge. Please consider writing up what you find and submitting patches to README (or the wiki at http://www.denx.de/wiki/DULG/Manual) Best Regards, Jim -- Jim Chargin AJA Video Systems j...@aja.com (530) 271-3334 http://www.aja.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Don't wrap to negative after 2G sectors
Ping yet again!?
Stefan
> "Stefan" == Stefan Monnier writes:
> Signed-off-by: Stefan Monnier
> ---
> disk/part_dos.c | 29 +
> include/ide.h | 8
> 2 files changed, 21 insertions(+), 16 deletions(-)
> diff --git a/disk/part_dos.c b/disk/part_dos.c
> index 89263d3..6280660 100644
> --- a/disk/part_dos.c
> +++ b/disk/part_dos.c
> @@ -26,7 +26,7 @@
> /* Convert char[4] in little endian format to the host format integer
> */
> -static inline int le32_to_int(unsigned char *le32)
> +static inline unsigned int le32_to_int(unsigned char *le32)
> {
> return ((le32[3] << 24) +
> (le32[2] << 16) +
> @@ -47,13 +47,14 @@ static inline int is_bootable(dos_partition_t *p)
> return p->boot_ind == 0x80;
> }
> -static void print_one_part(dos_partition_t *p, int ext_part_sector,
> +static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector,
> int part_num, unsigned int disksig)
> {
> - int lba_start = ext_part_sector + le32_to_int (p->start4);
> - int lba_size = le32_to_int (p->size4);
> + lbaint_t lba_start = ext_part_sector + le32_to_int (p->start4);
> + lbaint_t lba_size = le32_to_int (p->size4);
> - printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n",
> + printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength
> + "u\t%08x-%02x\t%02x%s%s\n",
> part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
> (is_extended(p->sys_ind) ? " Extd" : ""),
> (is_bootable(p) ? " Boot" : ""));
> @@ -102,7 +103,8 @@ int test_part_dos (block_dev_desc_t *dev_desc)
> /* Print a partition that is relative to its Extended partition table
> */
> static void print_partition_extended(block_dev_desc_t *dev_desc,
> - int ext_part_sector, int relative,
> + lbaint_t ext_part_sector,
> + lbaint_t relative,
>int part_num, unsigned int disksig)
> {
> ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
> @@ -110,7 +112,7 @@ static void print_partition_extended(block_dev_desc_t
> *dev_desc,
> int i;
> if (dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (ulong *)
> buffer) != 1) {
> - printf ("** Can't read partition table on %d:%d **\n",
> + printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc-> dev, ext_part_sector);
> return;
> }
> @@ -149,7 +151,8 @@ static void print_partition_extended(block_dev_desc_t
> *dev_desc,
> pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
> for (i = 0; i < 4; i++, pt++) {
> if (is_extended (pt->sys_ind)) {
> - int lba_start = le32_to_int (pt->start4) + relative;
> + lbaint_t lba_start
> + = le32_to_int (pt->start4) + relative;
> print_partition_extended(dev_desc, lba_start,
> ext_part_sector == 0 ? lba_start : relative,
> @@ -163,8 +166,9 @@ static void print_partition_extended(block_dev_desc_t
> *dev_desc,
> /* Print a partition that is relative to its Extended partition table
> */
> -static int get_partition_info_extended (block_dev_desc_t *dev_desc, int
> ext_part_sector,
> - int relative, int part_num,
> +static int get_partition_info_extended (block_dev_desc_t *dev_desc,
> + lbaint_t ext_part_sector,
> + lbaint_t relative, int part_num,
>int which_part, disk_partition_t *info,
>unsigned int disksig)
> {
> @@ -174,7 +178,7 @@ static int get_partition_info_extended (block_dev_desc_t
> *dev_desc, int ext_part
> int dos_type;
> if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *)
> buffer) != 1) {
> - printf ("** Can't read partition table on %d:%d **\n",
> + printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc-> dev, ext_part_sector);
> return -1;
> }
> @@ -250,7 +254,8 @@ static int get_partition_info_extended (block_dev_desc_t
> *dev_desc, int ext_part
> pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
> for (i = 0; i < 4; i++, pt++) {
> if (is_extended (pt->sys_ind)) {
> - int lba_start = le32_to_int (pt->start4) + relative;
> + lbaint_t lba_start
> + = le32_to_int (pt->start4) + relative;
> return get_partition_info_extended (dev_desc, lba_start,
>ext_part_sector == 0 ? lba_start : relative,
> diff --git a/include/ide.h b/include/ide.h
> index d5e05e9..f9b43cb 100644
> --- a/include/ide.h
> +++ b/include/ide.
Re: [U-Boot] [PATCH] fdt: __of_translate_address(): check parent's 'ranges' before translate
Hi Przemyslaw,
On 12 January 2016 at 07:22, Przemyslaw Marczak wrote:
> Hello Simon,
>
>
> On 01/12/2016 02:57 PM, Simon Glass wrote:
>>
>> Hi Przemyslaw,
>>
>> On 12 January 2016 at 03:25, Przemyslaw Marczak
>> wrote:
>>>
>>>
>>> Hello Stephen,
>>>
>>>
>>> On 01/11/2016 05:47 PM, Stephen Warren wrote:
On 01/11/2016 04:21 AM, Przemyslaw Marczak wrote:
>
>
> Hello Stephen,
>
> On 01/07/2016 07:25 PM, Stephen Warren wrote:
>>
>>
>> On 01/07/2016 04:40 AM, Przemyslaw Marczak wrote:
>>>
>>>
>>> The present implementation of __of_translate_address() taken
>>> from the Linux, is designed for translate bus/child address
>>> mappings by using 'ranges' property - and it doesn't allow
>>> for checking an address for a device's node with zero size-cells.
>>>
>>> The 'size-cells > 0' is required for bus/child address mapping,
>>> but is not required for non-memory mapped address, e.g.: I2C chip.
>>> Then when we need only raw 'reg' property's value.
>>>
>>> Since the I2C device address goes to a single-cell reg property,
>>> support for that case is welcome, but currently calling
>>> dev_get_addr()
>>> for I2C device will return 'FDT_ADDR_T_NONE', and print the warning:
>>>
>>> warning:
>>> __of_translate_address: Bad cell count for 'some-dev'
>>
>>
>>
>> This patch takes the wrong approach.
>>
>> It simply doesn't make sense to /attempt/ to translate an I2C address
>> into an MMIO address space. It's a nonsensical operation; no such
>> translation is possible under any circumstances because I2C and MMIO
>> addresses mean completely different things and simply can't be
>> translated to each-other.
>>
>> Rather than making this nonsensical operation succeed in a way that
>> gives the desired no-op result, the nonsensical operation simply
>> shouldn't be performed in the first place.
>>
>>
>
> Okay, the example with I2C may be little confusing - I could use some
> general naming convention. However, this patch updates FDT-related code
> only.
>
> In one of your previous e-mails, you well argued that we shouldn't use
> dev_get_reg() for some buses, since they have a different 'reg'
> meaning.
>
> You are right, using dev_get_addr() as universal function may be
> nonsensical.
>
> Please note, that the present implementation of function:
> '__of_translate_address()' - allows for 1:1 translation, but only if
> '#size-cells' exists. So the below case is possible:
>
> --
> parent {
> address-cells = <1>;
> size-cells = <1>;
> reg = <0x1000 0x1000>;
>
> child {
> reg = <0xa00 0x100>;
> };
> };
>
> dev_get_reg(child) - will return '0xa00'
> --
>
> If we don't need the address length, we can define:
> --
> parent {
> address-cells = <1>;
> size-cells = <0>;
> reg = <0x1000 0x1000>;
>
> child {
> reg = <0xa00>;
> };
> };
This case won't ever appear in a correctly written DT where reg
represents an MMIO address; MMIO addresses always have sizes, and hence
can't have size-cells=0. Hence, translating through a DT structures like
that is an error case, and shouldn't work.
>>>
>>> As we found out, the 'reg' property can represent not only MMIO, but may
>>> have other meaning, so the above case is possible. The 'reg' for the parent
>>> bus can represent MMIO (depends on what its parent defines) and the child is
>>> non-MMIO.
>>>
>>> You won't allow to use dev_get_addr() for other than MMIO addresses.
>>> Ok, I have no more arguments and no more time.
>>>
>>> My issue can be also fixed by removing dev_get_addr() call from Exynos
>>> GPIO driver - so I will do this and within this change, will also revert the
>>> commit:
>>> "fdt: fix address cell count checking in fdt_translate_address()"
>>
>>
>> I'm sorry this has been so difficult. Thank you for digging into it.
>>
>> I'm going to take this patch as is unless there is an alternative
>> patch on the table. Stephen please let me know if you'd like to write
>> something. One idea seems to be a new function (like
>> dev_get_addr_local()) which avoids the address translation. But
>> Przemyslaw has put enough energy into this I think.
>>
>> Regards,
>> Simon
>>
>>
>
> I think, that we don't need such function.
>
> Stephen has right with the universal dev_get_addr() - it should be used only
> for MMIO addresses.
>
> And also any universal function for getting the reg value is useless, for
> some specific reasons, which Stephen mentioned.
>
> I'm going to send another patch soon, which I think (again) should close the
> issue at all. Changing GPIO driver
[U-Boot] [PATCH 1/2] dts:exynos:update pinctrl size-cells and fix child regs
This change is required to avoid warnings about invalid
size-cells defined in device-tree pinctrl nodes for Exynos.
Tested on:
- Odroid U3
- Odroid XU3
Signed-off-by: Przemyslaw Marczak
Cc: Stefan Roese
Cc: Tom Rini
Cc: Simon Glass
Cc: Stephen Warren
Cc: Stephen Warren
---
arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 8
arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 18 +-
arch/arm/dts/exynos5250-pinctrl-uboot.dtsi | 16
arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi | 12 ++--
arch/arm/dts/s5pc110-pinctrl.dtsi | 4 ++--
5 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
index 0ff41d0..b76c77d 100644
--- a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
@@ -9,21 +9,21 @@
/{
pinctrl_0: pinctrl@1140 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
compatible = "samsung,exynos4210-pinctrl";
};
pinctrl_1: pinctrl@1100 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
gpx0: gpx0 {
- reg = <0xc00>;
+ reg = <0xc00 0x20>;
};
};
pinctrl_2: pinctrl@0386 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
index 8e5a6c6..33ecc14 100644
--- a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
@@ -9,37 +9,37 @@
/{
pinctrl_0: pinctrl@1140 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
gpf0: gpf0 {
- reg = <0x180>;
+ reg = <0x180 0x20>;
};
gpj0: gpj0 {
- reg = <0x240>;
+ reg = <0x240 0x20>;
};
};
pinctrl_1: pinctrl@1100 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
gpk0: gpk0 {
- reg = <0x40>;
+ reg = <0x40 0x20>;
};
gpm0: gpm0 {
- reg = <0x260>;
+ reg = <0x260 0x20>;
};
gpx0: gpx0 {
- reg = <0xc00>;
+ reg = <0xc00 0x20>;
};
};
pinctrl_2: pinctrl@0386 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
};
pinctrl_3: pinctrl@106E {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
index 068c5f6..b8c0526 100644
--- a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
@@ -9,34 +9,34 @@
/{
pinctrl_0: pinctrl@1140 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
gpc4: gpc4 {
- reg = <0x2e0>;
+ reg = <0x2e0 0x20>;
};
gpx0: gpx0 {
- reg = <0xc00>;
+ reg = <0xc00 0x20>;
};
};
pinctrl_1: pinctrl@1340 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
};
pinctrl_2: pinctrl@10d1 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
gpv2: gpv2 {
- reg = <0x060>;
+ reg = <0x060 0x20>;
};
gpv4: gpv4 {
- reg = <0xc0>;
+ reg = <0xc0 0x20>;
};
};
pinctrl_3: pinctrl@0386 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
index 635a1b0..341194f 100644
--- a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
@@ -14,29 +14,29 @@
*/
pinctrl@1401 {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
};
pinctrl@1340 {
#address-cells = <1>;
-
[U-Boot] [PATCH 0/2] Revert changes to __of_translate_address()
Globally enabled CONFIG_OF_TRANSLATE causes, that function dev_get_addr() returns a different result for a node with: 'size-cells = <0>'. The above change, breaks the Exynos boards for a long time, because of GPIO driver, which uses the fdt in a non standard way. After sending few approaches with adding support for that case, the one was appllied for a temporary fix for the release: "fdt: fix address cell count checking in fdt_translate_address()" However, after discussion on the list, we found that this way can't be accepted because the function __of_translate_address() as a backend of dev_get_addr(), shouldn't be used for translating a non-MMIO addresses. Updating some device tree files with '#size-cells = 1' and by extending the 'reg' property by address length - fixes the problem. This applies on u-boot-dm/master: c5a7533 net: Fix delay in net_retry test Przemyslaw Marczak (2): dts:exynos:update pinctrl size-cells and fix child regs Revert "fdt: fix address cell count checking in fdt_translate_address()" arch/arm/dts/exynos4210-pinctrl-uboot.dtsi | 8 arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi | 18 +- arch/arm/dts/exynos5250-pinctrl-uboot.dtsi | 16 arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi | 12 ++-- arch/arm/dts/s5pc110-pinctrl.dtsi | 4 ++-- common/fdt_support.c | 7 --- 6 files changed, 33 insertions(+), 32 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] dm: core: Add option to configure an offset for the address translation
On 19.12.2015 23:23, Simon Glass wrote: On 14 December 2015 at 08:18, Stefan Roese wrote: Some platforms need to ability to configure an offset to the standard addresses extracted from the device-tree. This patch allows this by adding a function to DM to configure this offset (if needed). Signed-off-by: Stefan Roese Acked-by: Simon Glass Cc: Simon Glass --- v3: - Add comment to variable desclaration - Remove unnecessary checks for "!root" v2: - Change translation_offset type from u32 to fdt_addr_t - Add comments to function declarations drivers/core/device.c | 33 + drivers/core/root.c | 21 + include/dm/device.h | 21 + 3 files changed, 63 insertions(+), 12 deletions(-) Fixed whitespace nit and: Applied to u-boot-dm/next. Simon, just a quick question. Do you plan to send a pull request for this next branch soon after the merge window open? I'm asking, since I would like to prepare a Marvell / mvebu branch to pull also quickly after the release. And this depends on this small DM core patch. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] Revert "fdt: fix address cell count checking in fdt_translate_address()"
This reverts commit 71105f50fedddfa5b0535d102c3d5078671721ad.
The reverted commit was applied for a temporary to unbreak
few Exynos boards on the release.
After the discussion about the change, this commit should be avoided.
Fixed device-tree for Exynos, allows reverting it without any issues.
Signed-off-by: Przemyslaw Marczak
Cc: Stefan Roese
Cc: Tom Rini
Cc: Simon Glass
Cc: Stephen Warren
Cc: Stephen Warren
---
common/fdt_support.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index a539389..66464db 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -952,7 +952,8 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDRFDT_ADDR_T_NONE
-#define OF_CHECK_COUNTS(na)((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
+#define OF_CHECK_COUNTS(na, ns)((na) > 0 && (na) <= OF_MAX_ADDR_CELLS
&& \
+ (ns) > 0)
/* Debug utility */
#ifdef DEBUG
@@ -1120,7 +1121,7 @@ static u64 __of_translate_address(void *blob, int
node_offset, const fdt32_t *in
/* Cound address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
- if (!OF_CHECK_COUNTS(na)) {
+ if (!OF_CHECK_COUNTS(na, ns)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
goto bail;
@@ -1147,7 +1148,7 @@ static u64 __of_translate_address(void *blob, int
node_offset, const fdt32_t *in
/* Get new parent bus and counts */
pbus = &of_busses[0];
pbus->count_cells(blob, parent, &pna, &pns);
- if (!OF_CHECK_COUNTS(pna)) {
+ if (!OF_CHECK_COUNTS(pna, pns)) {
printf("%s: Bad cell count for %s\n", __FUNCTION__,
fdt_get_name(blob, node_offset, NULL));
break;
--
1.9.1
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Re: [U-Boot] [PATCH] fdt: fix address cell count checking in fdt_translate_address()
Hello Simon,
On 01/12/2016 02:59 PM, Simon Glass wrote:
Hi Przemyslaw,
On 12 January 2016 at 03:49, Przemyslaw Marczak wrote:
Hello Simon,
On 01/11/2016 05:59 PM, Simon Glass wrote:
Hi Przemyslaw,
On 8 January 2016 at 05:01, Przemyslaw Marczak
wrote:
Hello Simon,
On 01/07/2016 08:24 PM, Simon Glass wrote:
+Stephen
On 4 January 2016 at 17:59, Simon Glass wrote:
Hi Przemyslaw,
On 5 November 2015 at 23:47, Stefan Roese wrote:
On 06.11.2015 04:16, Simon Glass wrote:
Hi,
On 3 November 2015 at 02:57, Przemyslaw Marczak
wrote:
Hello All,
On 10/29/2015 06:15 PM, Simon Glass wrote:
Hi Stefan,
On 28 October 2015 at 08:37, Przemyslaw Marczak
wrote:
Commit: dm: core: Enable optional use of fdt_translate_address()
Enables use of this function as default, but after this it's not
possible to get dev address for the case in which: '#size-cells ==
0'
This causes errors when getting address for some GPIOs, for which
the '#size-cells' is set to 0.
Example error:
'__of_translate_address: Bad cell count for gpx0'
Allowing for that case by modifying the macro 'OF_CHECK_COUNTS',
(called from )__of_translate_address(), fixes the issue.
Now, this macro doesn't check, that '#size-cells' is greater than
0.
This is possible from the specification point of view, but I'm not
sure
that it doesn't introduce a regression for other configs.
Please test and share the results.
Tested-on: Odroid U3, Odroid X2, Odroid XU3, Sandbox.
Signed-off-by: Przemyslaw Marczak
Cc: Masahiro Yamada
Cc: Lukasz Majewski
Cc: Jaehoon Chung
Cc: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
Cc: Marek Vasut
---
common/fdt_support.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f86365e..5f808cc 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -946,8 +946,7 @@ void fdt_del_node_and_alias(void *blob, const
char
*alias)
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR((u64)-1)
-#define OF_CHECK_COUNTS(na, ns)((na) > 0 && (na) <=
OF_MAX_ADDR_CELLS && \
- (ns) > 0)
+#define OF_CHECK_COUNTS(na)((na) > 0 && (na) <=
OF_MAX_ADDR_CELLS)
/* Debug utility */
#ifdef DEBUG
@@ -1115,7 +1114,7 @@ static u64 __of_translate_address(void
*blob,
int
node_offset, const fdt32_t *in
/* Cound address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
- if (!OF_CHECK_COUNTS(na, ns)) {
+ if (!OF_CHECK_COUNTS(na)) {
This seems to conflict with the comment at the top of this
function:
* Note: We consider that crossing any level with #size-cells
== 0
to
mean
* that translation is impossible (that is we are not dealing
with
a
value
* that can be mapped to a cpu physical address). This is not
really
specified
* that way, but this is traditionally the way IBM at least do
things
What should we do here?
Is that commit acceptable? I would like send V2 with removing the
above
comment.
That's what I am worried about. Presumably the comment is accurate
today and this check has some value. I was hoping Stefan might know.
Unfortunately no. I just stumbled over this problem with the
translation of the "complex" ranges on the MVEBU platform. And
noticed that we already have this functionality to translate
the addresses the "right way".
I'm wondering how this problem with those GPIOs is handled in
the kernel? I assume that it is working correctly there, right?
Przemyslaw, could you perhaps check this and see, why its
working there? And change / fix it in U-Boot accordingly?
Let's pick up this patch for now as a bug-fix. We can deal with this
problem after the release.
Applied to u-boot-dm/master.
I'll post a revert after the release. It seems like you and Stephen
are making good progress.
- Simon
Why so fast with this one?
I think, that more proper for a temporary fix is my latest patch with
#size-cells count checking only if ranges found in the parent node.
I will continue the discussion with Stephen.
The release is scheduled for today, so we had to do something to fix
the breakage.
Once you have a full solution figured out we can revert this patch and
apply what you come up with.
Regards,
Simon
Ok. It's hard to convince Stephen to accept such change, so I will send a
patch with another solution - just bring back fdtdec_get_addr() for Exynos
GPIO driver. And will revert this one within the patchset.
Please hold off on that. I'll accept your other patch but let's see if
Stephen wants to write something first. Using fdtdec_get_addr()
doesn't make sense although I fully understand your frustration. Let's
give it a week.
Regards,
Simon
Ah, too late:)
I have prepared patch, it's simple and doesn't touch the code - only
device-tree. And this would be a proper approach, according to Stephen's
comme
Re: [U-Boot] axm SPL image too big
Hello Heiko, On Tue, 12 Jan 2016 11:48:17 +0100, Heiko Schocher wrote: > Hello Albert, > > Am 12.01.2016 um 11:26 schrieb Albert ARIBAUD: > > (cc:ing Heiko as the maintainer for axm/taurus) > > > > Hello, > > > > AXM is currently the only board failing 'buildman arm aarch64': > > > > +arm-unknown-linux-gnueabi-ld.bfd: SPL image too big > > +make[2]: *** [spl/u-boot-spl] Error 1 > > +make[1]: *** [spl/u-boot-spl] Error 2 > > +make: *** [sub-make] Error 2 > > > > Apparently SPL is already being built in Thumb instruction set, so no > > way to gain anything that way. > > I know, it was tricky to get SPL into 4k ... > > > What else can we do to get SPL size back under limit? > > Hmm.. what is your exact toolchain? I tested with the buildman-fetched gcc, -v gives 'gcc version 4.9.0 (GCC)'. I've deleted the toolchain and re-fetched it again through buildman in case there was an issue with the install, and am getting the same result. I've also tested with the latest ARM gcc package available with Ubuntu, that is, 'gcc version 5.2.1 20151010 (Ubuntu 5.2.1-22ubuntu1)', again with the same result. > I see for the axm board: > > With eldk-5.4 > pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot > textdata bss dec hex filename > 212583 23792 23552 259927 3f757 u-boot > pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl > textdata bss dec hex filename >1456812121140 169204218 spl/u-boot-spl > pollux:u-boot-smartweb hs [master] $ Confirmed right now that with eldk 5.4's gcc 4.7.2 axm builds fine. > With eldk-5.5 > pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot > textdata bss dec hex filename > 210690 23672 23556 257918 3ef7e u-boot > pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl > textdata bss dec hex filename >1447212121140 1682441b8 spl/u-boot-spl > pollux:u-boot-smartweb hs [master] $ Confirmed right now that with eldk 5.5's (or 5.5.3's) gcc 4.8.1 axm builds fine. The issue appears with gcc 4.9 and 5.2.1 (and I suspect any version between 4.9 and 5.2.1 and beyond 5.2.1) > bye, > Heiko > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt: __of_translate_address(): check parent's 'ranges' before translate
Hello Simon,
On 01/12/2016 02:57 PM, Simon Glass wrote:
Hi Przemyslaw,
On 12 January 2016 at 03:25, Przemyslaw Marczak wrote:
Hello Stephen,
On 01/11/2016 05:47 PM, Stephen Warren wrote:
On 01/11/2016 04:21 AM, Przemyslaw Marczak wrote:
Hello Stephen,
On 01/07/2016 07:25 PM, Stephen Warren wrote:
On 01/07/2016 04:40 AM, Przemyslaw Marczak wrote:
The present implementation of __of_translate_address() taken
from the Linux, is designed for translate bus/child address
mappings by using 'ranges' property - and it doesn't allow
for checking an address for a device's node with zero size-cells.
The 'size-cells > 0' is required for bus/child address mapping,
but is not required for non-memory mapped address, e.g.: I2C chip.
Then when we need only raw 'reg' property's value.
Since the I2C device address goes to a single-cell reg property,
support for that case is welcome, but currently calling dev_get_addr()
for I2C device will return 'FDT_ADDR_T_NONE', and print the warning:
warning:
__of_translate_address: Bad cell count for 'some-dev'
This patch takes the wrong approach.
It simply doesn't make sense to /attempt/ to translate an I2C address
into an MMIO address space. It's a nonsensical operation; no such
translation is possible under any circumstances because I2C and MMIO
addresses mean completely different things and simply can't be
translated to each-other.
Rather than making this nonsensical operation succeed in a way that
gives the desired no-op result, the nonsensical operation simply
shouldn't be performed in the first place.
Okay, the example with I2C may be little confusing - I could use some
general naming convention. However, this patch updates FDT-related code
only.
In one of your previous e-mails, you well argued that we shouldn't use
dev_get_reg() for some buses, since they have a different 'reg' meaning.
You are right, using dev_get_addr() as universal function may be
nonsensical.
Please note, that the present implementation of function:
'__of_translate_address()' - allows for 1:1 translation, but only if
'#size-cells' exists. So the below case is possible:
--
parent {
address-cells = <1>;
size-cells = <1>;
reg = <0x1000 0x1000>;
child {
reg = <0xa00 0x100>;
};
};
dev_get_reg(child) - will return '0xa00'
--
If we don't need the address length, we can define:
--
parent {
address-cells = <1>;
size-cells = <0>;
reg = <0x1000 0x1000>;
child {
reg = <0xa00>;
};
};
This case won't ever appear in a correctly written DT where reg
represents an MMIO address; MMIO addresses always have sizes, and hence
can't have size-cells=0. Hence, translating through a DT structures like
that is an error case, and shouldn't work.
As we found out, the 'reg' property can represent not only MMIO, but may have
other meaning, so the above case is possible. The 'reg' for the parent bus can
represent MMIO (depends on what its parent defines) and the child is non-MMIO.
You won't allow to use dev_get_addr() for other than MMIO addresses.
Ok, I have no more arguments and no more time.
My issue can be also fixed by removing dev_get_addr() call from Exynos GPIO
driver - so I will do this and within this change, will also revert the commit:
"fdt: fix address cell count checking in fdt_translate_address()"
I'm sorry this has been so difficult. Thank you for digging into it.
I'm going to take this patch as is unless there is an alternative
patch on the table. Stephen please let me know if you'd like to write
something. One idea seems to be a new function (like
dev_get_addr_local()) which avoids the address translation. But
Przemyslaw has put enough energy into this I think.
Regards,
Simon
I think, that we don't need such function.
Stephen has right with the universal dev_get_addr() - it should be used
only for MMIO addresses.
And also any universal function for getting the reg value is useless,
for some specific reasons, which Stephen mentioned.
I'm going to send another patch soon, which I think (again) should close
the issue at all. Changing GPIO driver is not required, it will be
enough when I fix the device-tree files (SoCxxx-pinctrl-uboot.dts).
We don't need to look at kernel, since we have two different drivers and
also the kernel doesn't use the GPIO's regs (addresses are hardcoded).
So fixing device-tree is a good choose. It's really only few lines per file.
Best regards,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] [PATCH v5] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Tuesday, January 12, 2016 at 03:20:43 AM, Dalon Westergreen wrote: > The hps_isw_handoff and bsp/generated folders are typically not in the same > path.This patch adds support for specifying the different input directories > for the bsp and quartus projects. > > Signed-off-by: Dalon Westergreen > Acked-by: Marek Vasut > Acked-by: Chin Liang See Applied to u-boot-socfpga/master , thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] common: usb: fix checking condition
On Tuesday, January 12, 2016 at 08:57:01 AM, Peng Fan wrote:
> From: Peng Fan
>
> We support max USB_MAXENDPOINTS, so need to use
> "epno >= USB_MAXENDPOINTS", but not "epno > USB_MAXENDPOINTS".
> If use ">", we may exceeds the array of if_desc->ep_desc.
>
> Signed-off-by: Peng Fan
> Cc: Simon Glass
> Cc: Hans de Goede
> Cc: Marek Vasut
> Cc: Paul Kocialkowski
> Cc: "Stefan Brüns"
> Cc: Vincent Palatin
Acked-by: Marek Vasut
> ---
> common/usb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/common/usb.c b/common/usb.c
> index 9f67cc1..c7b8b0e 100644
> --- a/common/usb.c
> +++ b/common/usb.c
> @@ -456,7 +456,7 @@ static int usb_parse_config(struct usb_device *dev,
> }
> epno = dev->config.if_desc[ifno].no_of_ep;
> if_desc = &dev->config.if_desc[ifno];
> - if (epno > USB_MAXENDPOINTS) {
> + if (epno >= USB_MAXENDPOINTS) {
> printf("Interface %d has too many endpoints!\n",
> if_desc->desc.bInterfaceNumber);
> return -EINVAL;
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] fdt: fix address cell count checking in fdt_translate_address()
Hi Przemyslaw,
On 12 January 2016 at 03:49, Przemyslaw Marczak wrote:
> Hello Simon,
>
>
> On 01/11/2016 05:59 PM, Simon Glass wrote:
>>
>> Hi Przemyslaw,
>>
>> On 8 January 2016 at 05:01, Przemyslaw Marczak
>> wrote:
>>>
>>> Hello Simon,
>>>
>>>
>>> On 01/07/2016 08:24 PM, Simon Glass wrote:
+Stephen
On 4 January 2016 at 17:59, Simon Glass wrote:
>
>
> Hi Przemyslaw,
>
> On 5 November 2015 at 23:47, Stefan Roese wrote:
>>
>>
>> On 06.11.2015 04:16, Simon Glass wrote:
>>>
>>>
>>>
>>> Hi,
>>>
>>> On 3 November 2015 at 02:57, Przemyslaw Marczak
>>>
>>> wrote:
Hello All,
On 10/29/2015 06:15 PM, Simon Glass wrote:
>
>
>
>
> Hi Stefan,
>
> On 28 October 2015 at 08:37, Przemyslaw Marczak
>
> wrote:
>>
>>
>>
>>
>> Commit: dm: core: Enable optional use of fdt_translate_address()
>>
>> Enables use of this function as default, but after this it's not
>> possible to get dev address for the case in which: '#size-cells ==
>> 0'
>>
>> This causes errors when getting address for some GPIOs, for which
>> the '#size-cells' is set to 0.
>>
>> Example error:
>> '__of_translate_address: Bad cell count for gpx0'
>>
>> Allowing for that case by modifying the macro 'OF_CHECK_COUNTS',
>> (called from )__of_translate_address(), fixes the issue.
>>
>> Now, this macro doesn't check, that '#size-cells' is greater than
>> 0.
>>
>> This is possible from the specification point of view, but I'm not
>> sure
>> that it doesn't introduce a regression for other configs.
>>
>> Please test and share the results.
>>
>> Tested-on: Odroid U3, Odroid X2, Odroid XU3, Sandbox.
>>
>> Signed-off-by: Przemyslaw Marczak
>> Cc: Masahiro Yamada
>> Cc: Lukasz Majewski
>> Cc: Jaehoon Chung
>> Cc: Stefan Roese
>> Cc: Simon Glass
>> Cc: Bin Meng
>> Cc: Marek Vasut
>> ---
>> common/fdt_support.c | 7 +++
>> 1 file changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/common/fdt_support.c b/common/fdt_support.c
>> index f86365e..5f808cc 100644
>> --- a/common/fdt_support.c
>> +++ b/common/fdt_support.c
>> @@ -946,8 +946,7 @@ void fdt_del_node_and_alias(void *blob, const
>> char
>> *alias)
>> /* Max address size we deal with */
>> #define OF_MAX_ADDR_CELLS 4
>> #define OF_BAD_ADDR((u64)-1)
>> -#define OF_CHECK_COUNTS(na, ns)((na) > 0 && (na) <=
>> OF_MAX_ADDR_CELLS && \
>> - (ns) > 0)
>> +#define OF_CHECK_COUNTS(na)((na) > 0 && (na) <=
>> OF_MAX_ADDR_CELLS)
>>
>> /* Debug utility */
>> #ifdef DEBUG
>> @@ -1115,7 +1114,7 @@ static u64 __of_translate_address(void
>> *blob,
>> int
>> node_offset, const fdt32_t *in
>>
>> /* Cound address cells & copy address locally */
>> bus->count_cells(blob, parent, &na, &ns);
>> - if (!OF_CHECK_COUNTS(na, ns)) {
>> + if (!OF_CHECK_COUNTS(na)) {
>
>
>
>
>
> This seems to conflict with the comment at the top of this
> function:
>
> * Note: We consider that crossing any level with #size-cells
> == 0
> to
> mean
> * that translation is impossible (that is we are not dealing
> with
> a
> value
> * that can be mapped to a cpu physical address). This is not
> really
> specified
> * that way, but this is traditionally the way IBM at least do
> things
>
> What should we do here?
>
Is that commit acceptable? I would like send V2 with removing the
above
comment.
>>>
>>>
>>>
>>>
>>> That's what I am worried about. Presumably the comment is accurate
>>> today and this check has some value. I was hoping Stefan might know.
>>
>>
>>
>>
>> Unfortunately no. I just stumbled over this problem with the
>> translation of the "complex" ranges on the MVEBU platform. And
>> noticed that we already have this functionality to translate
>> the addresses the "right way".
>>
>> I'm wondering how this problem with those GPIOs is handled in
>> the kernel? I assume that it is working correctly there, right?
>> Przemyslaw, could you perhaps check thi
Re: [U-Boot] [PATCH] fdt: __of_translate_address(): check parent's 'ranges' before translate
Hi Przemyslaw,
On 12 January 2016 at 03:25, Przemyslaw Marczak wrote:
>
> Hello Stephen,
>
>
> On 01/11/2016 05:47 PM, Stephen Warren wrote:
>>
>> On 01/11/2016 04:21 AM, Przemyslaw Marczak wrote:
>>>
>>> Hello Stephen,
>>>
>>> On 01/07/2016 07:25 PM, Stephen Warren wrote:
On 01/07/2016 04:40 AM, Przemyslaw Marczak wrote:
>
> The present implementation of __of_translate_address() taken
> from the Linux, is designed for translate bus/child address
> mappings by using 'ranges' property - and it doesn't allow
> for checking an address for a device's node with zero size-cells.
>
> The 'size-cells > 0' is required for bus/child address mapping,
> but is not required for non-memory mapped address, e.g.: I2C chip.
> Then when we need only raw 'reg' property's value.
>
> Since the I2C device address goes to a single-cell reg property,
> support for that case is welcome, but currently calling dev_get_addr()
> for I2C device will return 'FDT_ADDR_T_NONE', and print the warning:
>
> warning:
> __of_translate_address: Bad cell count for 'some-dev'
This patch takes the wrong approach.
It simply doesn't make sense to /attempt/ to translate an I2C address
into an MMIO address space. It's a nonsensical operation; no such
translation is possible under any circumstances because I2C and MMIO
addresses mean completely different things and simply can't be
translated to each-other.
Rather than making this nonsensical operation succeed in a way that
gives the desired no-op result, the nonsensical operation simply
shouldn't be performed in the first place.
>>>
>>> Okay, the example with I2C may be little confusing - I could use some
>>> general naming convention. However, this patch updates FDT-related code
>>> only.
>>>
>>> In one of your previous e-mails, you well argued that we shouldn't use
>>> dev_get_reg() for some buses, since they have a different 'reg' meaning.
>>>
>>> You are right, using dev_get_addr() as universal function may be
>>> nonsensical.
>>>
>>> Please note, that the present implementation of function:
>>> '__of_translate_address()' - allows for 1:1 translation, but only if
>>> '#size-cells' exists. So the below case is possible:
>>>
>>> --
>>> parent {
>>> address-cells = <1>;
>>> size-cells = <1>;
>>> reg = <0x1000 0x1000>;
>>>
>>> child {
>>> reg = <0xa00 0x100>;
>>> };
>>> };
>>>
>>> dev_get_reg(child) - will return '0xa00'
>>> --
>>>
>>> If we don't need the address length, we can define:
>>> --
>>> parent {
>>> address-cells = <1>;
>>> size-cells = <0>;
>>> reg = <0x1000 0x1000>;
>>>
>>> child {
>>> reg = <0xa00>;
>>> };
>>> };
>>
>>
>> This case won't ever appear in a correctly written DT where reg
>> represents an MMIO address; MMIO addresses always have sizes, and hence
>> can't have size-cells=0. Hence, translating through a DT structures like
>> that is an error case, and shouldn't work.
>>
>>
>>
>
> As we found out, the 'reg' property can represent not only MMIO, but may have
> other meaning, so the above case is possible. The 'reg' for the parent bus
> can represent MMIO (depends on what its parent defines) and the child is
> non-MMIO.
>
> You won't allow to use dev_get_addr() for other than MMIO addresses.
> Ok, I have no more arguments and no more time.
>
> My issue can be also fixed by removing dev_get_addr() call from Exynos GPIO
> driver - so I will do this and within this change, will also revert the
> commit:
> "fdt: fix address cell count checking in fdt_translate_address()"
I'm sorry this has been so difficult. Thank you for digging into it.
I'm going to take this patch as is unless there is an alternative
patch on the table. Stephen please let me know if you'd like to write
something. One idea seems to be a new function (like
dev_get_addr_local()) which avoids the address translation. But
Przemyslaw has put enough energy into this I think.
Regards,
Simon
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Re: [U-Boot] [PATCH v3] socfpga: Modify qts-filter args to allow input for bsp generated files and quartus project directories
On Tuesday, January 12, 2016 at 01:50:18 AM, Chin Liang See wrote: > On Tue, 2016-01-12 at 01:31 +0100, Marek Vasut wrote: > > On Tuesday, January 12, 2016 at 01:26:58 AM, Chin Liang See wrote: > > > On Mon, 2016-01-11 at 15:33 -0800, Dalon Westergreen wrote: > [...] > > > btw. Completely off-topic, but is there any chance altera will > > release the > > algorithm to compute these magic values which are in the header files > > from > > the base values inserted into the HPS component in QSys ? > > I would not suggesting that as Qsys and Quartus are doing heavylifting > tasks there. The value would depends on the options being choosed, > device type, device revision (if any). They also being patched from > time to time too. Is it all really _that_ complicated ? That's why I'd like to see the code that's doing all that computation. Even if it's done at compile-time, it'd still be better than the horrible headers which we have to use now. > > I think we might > > just put these values into OF and do the computation in U-Boot on-the > > -fly. > > This would also remove the need for this script. > > Slightly off topic, I am thinking to move all these generated files > into DTS too. This will have some out of box experience as Arria10 SoC. > But that might be challenging in term of resources. We might still > stick with this script for good. See above. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 02/14] MIPS: initial infrastructure for Microchip PIC32 architecture
2016-01-12 11:18 GMT+01:00 Purna Chandra Mandal :
> Create initial directory, Kconfigs needed for PIC32 architecture
> support. Also add PIC32 specific register definition required for drivers.
>
> Signed-off-by: Purna Chandra Mandal
maybe you could use ioremap() in pic32_get_syscfg_base(), apart from
that it looks good
Reviewed-by: Daniel Schwierzeck
>
> ---
>
> Changes in v3:
> - drop empty choices in mach-pic32/Kconfig
> - add pic32_get_syscfg_base() for device-config registers
>
> Changes in v2:
> - move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
> - define register-base as physical address
> - drop CONFIG_PIC32_SUPPORTS_FDT_BOOT
>
> arch/mips/Kconfig | 6 +++
> arch/mips/Makefile| 1 +
> arch/mips/mach-pic32/Kconfig | 7 +++
> arch/mips/mach-pic32/Makefile | 7 +++
> arch/mips/mach-pic32/cpu.c| 13 ++
> arch/mips/mach-pic32/include/mach/pic32.h | 76
> +++
> 6 files changed, 110 insertions(+)
> create mode 100644 arch/mips/mach-pic32/Kconfig
> create mode 100644 arch/mips/mach-pic32/Makefile
> create mode 100644 arch/mips/mach-pic32/cpu.c
> create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 1b39c4c..380ed81 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -54,6 +54,11 @@ config TARGET_PB1X00
> select SYS_MIPS_CACHE_INIT_RAM_LOAD
> select MIPS_TUNE_4KC
>
> +config MACH_PIC32
> + bool "Support Microchip PIC32"
> + select OF_CONTROL
> + select DM
> +
> endchoice
>
> source "board/dbau1x00/Kconfig"
> @@ -61,6 +66,7 @@ source "board/imgtec/malta/Kconfig"
> source "board/micronas/vct/Kconfig"
> source "board/pb1x00/Kconfig"
> source "board/qemu-mips/Kconfig"
> +source "arch/mips/mach-pic32/Kconfig"
>
> if MIPS
>
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 2133e7e..aec5a15 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
> libs-y += arch/mips/lib/
>
> machine-$(CONFIG_SOC_AU1X00) += au1x00
> +machine-$(CONFIG_MACH_PIC32) += pic32
>
> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
> libs-y += $(machdirs)
> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
> new file mode 100644
> index 000..c1cc5e3
> --- /dev/null
> +++ b/arch/mips/mach-pic32/Kconfig
> @@ -0,0 +1,7 @@
> +menu "Microchip PIC32 platforms"
> + depends on MACH_PIC32
> +
> +config SYS_SOC
> + default "none"
> +
> +endmenu
> diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
> new file mode 100644
> index 000..cb42607
> --- /dev/null
> +++ b/arch/mips/mach-pic32/Makefile
> @@ -0,0 +1,7 @@
> +# (C) Copyright 2015
> +# Purna Chandra Mandal, purna.man...@microchip.com.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y = cpu.o
> diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
> new file mode 100644
> index 000..58fd3ab
> --- /dev/null
> +++ b/arch/mips/mach-pic32/cpu.c
> @@ -0,0 +1,13 @@
> +/*
> + * Copyright (C) 2015
> + * Purna Chandra Mandal
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + */
> +#include
> +
> +phys_size_t initdram(int board_type)
> +{
> + return 0;
> +}
> diff --git a/arch/mips/mach-pic32/include/mach/pic32.h
> b/arch/mips/mach-pic32/include/mach/pic32.h
> new file mode 100644
> index 000..7e41810
> --- /dev/null
> +++ b/arch/mips/mach-pic32/include/mach/pic32.h
> @@ -0,0 +1,76 @@
> +/*
> + * (c) 2015 Paul Thacker
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + */
> +
> +#ifndef __PIC32_REGS_H__
> +#define __PIC32_REGS_H__
> +
> +#include
> +
> +/* System Configuration */
> +#define PIC32_CFG_BASE 0x1f80
> +
> +/* System config register offsets */
> +#define CFGCON 0x
> +#define DEVID 0x0020
> +#define SYSKEY 0x0030
> +#define PMD1 0x0040
> +#define PMD7 0x00a0
> +#define CFGEBIA0x00c0
> +#define CFGEBIC0x00d0
> +#define CFGPG 0x00e0
> +#define CFGMPLL0x0100
> +
> +/* Non Volatile Memory (NOR flash) */
> +#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
> +/* Oscillator Configuration */
> +#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
> +/* Peripheral Pin Select Input */
> +#define PPS_IN_BASE0x1f801400
> +/* Peripheral Pin Select Output */
> +#define PPS_OUT_BASE 0x1f801500
> +/* Pin Config */
> +#define PINCTRL_BASE 0x1f86
> +
> +/* USB Core */
> +#define PIC32_USB_CORE_BASE0x1f8e3000
> +#define PIC32_USB_CTRL_BASE0x1f884000
> +
> +/* SPI1-SPI6 */
> +#define PIC32_SPI1_BASE0x1f821000
> +
> +/* Prefetch Module */
> +#define PREFETCH_BASE 0x1f8e
> +
> +/* DDR2 Controller */
> +#define PIC32_DDR2C_BASE 0x1f8e8000
>
Re: [U-Boot] [PATCH v3 01/14] MIPS: initialize board_init_f() argument to zero.
2016-01-12 11:18 GMT+01:00 Purna Chandra Mandal : > Signed-off-by: Purna Chandra Mandal > --- > > Changes in v3: None > Changes in v2: None > > arch/mips/cpu/start.S | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S > index e95cdca..35d9650 100644 > --- a/arch/mips/cpu/start.S > +++ b/arch/mips/cpu/start.S > @@ -185,6 +185,8 @@ reset: > PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset > sw sp, 0(t0) > #endif > + /* Initialize args to zero */ > + movea0, zero the comment should be on the same line and more precise. That is useful in disassemblies or when debugging. E.g. movea0, zero# a0 <-- boot_flags = 0 Also add a commit message please explaining why the change is required. Something like that the boot_flags of board_init_f should be set to 0 because $a0 may be utilized in lowlevel_init or mips_cache_reset. > > PTR_LA t9, board_init_f > jr t9 > -- > 1.8.3.1 > -- - Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt: fix address cell count checking in fdt_translate_address()
Hello Simon,
On 01/11/2016 05:59 PM, Simon Glass wrote:
Hi Przemyslaw,
On 8 January 2016 at 05:01, Przemyslaw Marczak wrote:
Hello Simon,
On 01/07/2016 08:24 PM, Simon Glass wrote:
+Stephen
On 4 January 2016 at 17:59, Simon Glass wrote:
Hi Przemyslaw,
On 5 November 2015 at 23:47, Stefan Roese wrote:
On 06.11.2015 04:16, Simon Glass wrote:
Hi,
On 3 November 2015 at 02:57, Przemyslaw Marczak
wrote:
Hello All,
On 10/29/2015 06:15 PM, Simon Glass wrote:
Hi Stefan,
On 28 October 2015 at 08:37, Przemyslaw Marczak
wrote:
Commit: dm: core: Enable optional use of fdt_translate_address()
Enables use of this function as default, but after this it's not
possible to get dev address for the case in which: '#size-cells ==
0'
This causes errors when getting address for some GPIOs, for which
the '#size-cells' is set to 0.
Example error:
'__of_translate_address: Bad cell count for gpx0'
Allowing for that case by modifying the macro 'OF_CHECK_COUNTS',
(called from )__of_translate_address(), fixes the issue.
Now, this macro doesn't check, that '#size-cells' is greater than 0.
This is possible from the specification point of view, but I'm not
sure
that it doesn't introduce a regression for other configs.
Please test and share the results.
Tested-on: Odroid U3, Odroid X2, Odroid XU3, Sandbox.
Signed-off-by: Przemyslaw Marczak
Cc: Masahiro Yamada
Cc: Lukasz Majewski
Cc: Jaehoon Chung
Cc: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
Cc: Marek Vasut
---
common/fdt_support.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index f86365e..5f808cc 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -946,8 +946,7 @@ void fdt_del_node_and_alias(void *blob, const
char
*alias)
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR((u64)-1)
-#define OF_CHECK_COUNTS(na, ns)((na) > 0 && (na) <=
OF_MAX_ADDR_CELLS && \
- (ns) > 0)
+#define OF_CHECK_COUNTS(na)((na) > 0 && (na) <=
OF_MAX_ADDR_CELLS)
/* Debug utility */
#ifdef DEBUG
@@ -1115,7 +1114,7 @@ static u64 __of_translate_address(void *blob,
int
node_offset, const fdt32_t *in
/* Cound address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
- if (!OF_CHECK_COUNTS(na, ns)) {
+ if (!OF_CHECK_COUNTS(na)) {
This seems to conflict with the comment at the top of this function:
* Note: We consider that crossing any level with #size-cells == 0
to
mean
* that translation is impossible (that is we are not dealing with
a
value
* that can be mapped to a cpu physical address). This is not
really
specified
* that way, but this is traditionally the way IBM at least do
things
What should we do here?
Is that commit acceptable? I would like send V2 with removing the
above
comment.
That's what I am worried about. Presumably the comment is accurate
today and this check has some value. I was hoping Stefan might know.
Unfortunately no. I just stumbled over this problem with the
translation of the "complex" ranges on the MVEBU platform. And
noticed that we already have this functionality to translate
the addresses the "right way".
I'm wondering how this problem with those GPIOs is handled in
the kernel? I assume that it is working correctly there, right?
Przemyslaw, could you perhaps check this and see, why its
working there? And change / fix it in U-Boot accordingly?
Let's pick up this patch for now as a bug-fix. We can deal with this
problem after the release.
Applied to u-boot-dm/master.
I'll post a revert after the release. It seems like you and Stephen
are making good progress.
- Simon
Why so fast with this one?
I think, that more proper for a temporary fix is my latest patch with
#size-cells count checking only if ranges found in the parent node.
I will continue the discussion with Stephen.
The release is scheduled for today, so we had to do something to fix
the breakage.
Once you have a full solution figured out we can revert this patch and
apply what you come up with.
Regards,
Simon
Ok. It's hard to convince Stephen to accept such change, so I will send
a patch with another solution - just bring back fdtdec_get_addr() for
Exynos GPIO driver. And will revert this one within the patchset.
Best regards,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marc...@samsung.com
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Re: [U-Boot] axm SPL image too big
Hello Albert, Am 12.01.2016 um 11:26 schrieb Albert ARIBAUD: (cc:ing Heiko as the maintainer for axm/taurus) Hello, AXM is currently the only board failing 'buildman arm aarch64': +arm-unknown-linux-gnueabi-ld.bfd: SPL image too big +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +make: *** [sub-make] Error 2 Apparently SPL is already being built in Thumb instruction set, so no way to gain anything that way. I know, it was tricky to get SPL into 4k ... What else can we do to get SPL size back under limit? Hmm.. what is your exact toolchain? I see for the axm board: With eldk-5.4 pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot textdata bss dec hex filename 212583 23792 23552 259927 3f757 u-boot pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl textdata bss dec hex filename 1456812121140 169204218 spl/u-boot-spl pollux:u-boot-smartweb hs [master] $ With eldk-5.5 pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot textdata bss dec hex filename 210690 23672 23556 257918 3ef7e u-boot pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl textdata bss dec hex filename 1447212121140 1682441b8 spl/u-boot-spl pollux:u-boot-smartweb hs [master] $ for the taurus board: eldk-5.4 pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot textdata bss dec hex filename 284516 25500 1272228 1582244 1824a4 u-boot pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl textdata bss dec hex filename 1448812121140 1684041c8 spl/u-boot-spl pollux:u-boot-smartweb hs [master] $ eldk-5.5 pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size u-boot textdata bss dec hex filename 282155 25380 1274580 1582115 182423 u-boot pollux:u-boot-smartweb hs [master] $ arm-linux-gnueabi-size spl/u-boot-spl textdata bss dec hex filename 1439212121140 167444168 spl/u-boot-spl pollux:u-boot-smartweb hs [master] $ bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 00/14] Initial Microchip PIC32MZ[DA] Support
This patch series adds support for Microchip PIC32MZ[DA] MIPS microcontroller platform. All drivers required to boot from MMC uSD card and network are included in it; clock, pinctrl, gpio, DDR2, serial, SDHCI, ethernet. This series is tested on PIC32MZ[DA] Starter Kit. This series is generated on mips_io_v1 branch of u-boot-mips tree. A tree with these changes are available at [2]. [2] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v3 [1] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v2 [0] https://github.com/purna-mandal/u-boot/tree/pic32-upstream-v1 Changes in v3: - drop empty choices in mach-pic32/Kconfig - add pic32_get_syscfg_base() for device-config regs base - rename clk-pic32.c to clk_pic32.c - update clock binding documentation - replace pic32_ioremap() with ioremap() - read register base from device-tree - add/update comments to explain how pinctrl'r works. - remove ofdata_to_platdata, and replace platdata with priv - serial:remove special handling of '\r' as being handled by serial-uclass - serial:remove loop to wait for space in tx buffer before pumping char - pinctrl: annotating fixed table with const - ddr: fix camel-case in ddr2 timing parameters - ddr: fix cmd index parameter of host_load_cmd(). - drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig - indent assembly instructions in delay slot - made GPIO-nodes child of pinctrl-node in devicetree - drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header - move CMD_MEMTEST, CMD_MEMINFO to defconfig - increase SYS_MALLOC_F_LEN to 0x600 - use auto-generated defconfig - no hand edit - net: merge internal wrappers functions with eth operation callbacks - net: read ethernet-phy address from device-tree - net: rename ethernet callback functions Changes in v2: - move PIC32 specific headers to arch/mips/mach-pic32/include/mach/ - define register-base as physical address - drop CONFIG_PIC32_SUPPORTS_FDT_BOOT - add mpll get clock rate - add pinconf routine for configuring pin property - fix missing/corrupted chars during baud rate change - remove loop until any char is avaialbale in getc() - move ddr2 initialization from board/microchip/ to drivers/ddr/microchip - drop board_early_init_f - use macro LEAF(), END() for lowlevel_init - move initialization of board_init_f() argument to common start.S - move initdram() from board/microchip/ to mach-pic32/cpu.c - remove MIPS virtual address in favor physical one in dts file - move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to include/configs/.h - drop sdhci shared bus configuration (for shared interrupt, clock pins) - drop shared bus (shared pin selection) configuration. - replace unbounded loop with wait_for_bit() - replace register access as readl/writel(base + offset) - translate (dts provided) physical address to MIPS kseg1 address before use Andrei Pistirica (1): drivers: mmc: add driver for Microchip PIC32 SDHCI controller. Paul Thacker (1): drivers: serial: add driver for Microchip PIC32 UART controller. Purna Chandra Mandal (12): MIPS: initialize board_init_f() argument to zero. MIPS: initial infrastructure for Microchip PIC32 architecture drivers: clk: Add clock driver for Microchip PIC32 Microcontroller. drivers: pinctrl: Add pinctrl driver for Microchip PIC32. drivers: gpio: add driver for Microchip PIC32 GPIO controller. drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32. MIPS: Add support for Microchip PIC32MZ[DA] SoC family. board: Add Microchip PIC32MZ[DA]-Starter-Kit board. board: add SDHCI support for PIC32MZDASK board. drivers: net: phy: add SMSC LAN8740 Phy support. drivers: net: Add ethernet driver for Microchip PIC32. board: Enable ethernet, tftpboot support to pic32mzdask board. arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/cpu/start.S | 2 + arch/mips/dts/Makefile | 2 +- arch/mips/dts/pic32mzda.dtsi | 174 ++ arch/mips/dts/pic32mzda_sk.dts | 55 ++ arch/mips/mach-pic32/Kconfig | 38 ++ arch/mips/mach-pic32/Makefile | 7 + arch/mips/mach-pic32/cpu.c | 160 ++ arch/mips/mach-pic32/include/mach/ddr.h| 32 ++ arch/mips/mach-pic32/include/mach/pic32.h | 79 +++ arch/mips/mach-pic32/lowlevel_init.S | 27 + arch/mips/mach-pic32/reset.c | 36 ++ board/microchip/pic32mzda/Kconfig | 13 + board/microchip/pic32mzda/MAINTAINERS | 6 + board/microchip/pic32mzda/Makefile | 7 + board/microchip/pic32mzda/README | 22 + board/microchip/pic32mzda/pic32mzda.c | 31 ++ configs/pic32mzdask_defconfig | 426 +++ .../clock/microchip,pic32-clock.txt| 33 ++
[U-Boot] [PATCH 2/2] net: phy: implements probe for Cortina phy
From: Shaohui Xie
Cortine phy cannot support soft reset, this commit implements probe
for Cortina PHY to tell phylib to skip phy soft reset by setting
PHY_BROKEN_RESET in flags.
Signed-off-by: Shaohui Xie
---
drivers/net/phy/cortina.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index 3a2b3bb..2d04f62 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -256,6 +256,12 @@ int cs4340_config(struct phy_device *phydev)
return 0;
}
+int cs4340_probe(struct phy_device *phydev)
+{
+ phydev->flags = PHY_BROKEN_RESET;
+ return 0;
+}
+
int cs4340_startup(struct phy_device *phydev)
{
phydev->link = 1;
@@ -275,6 +281,7 @@ struct phy_driver cs4340_driver = {
MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
.config = &cs4340_config,
+ .probe = &cs4340_probe,
.startup = &cs4340_startup,
.shutdown = &gen10g_shutdown,
};
--
2.1.0.27.g96db324
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[U-Boot] [PATCH 1/2] net: phy: introduce a quirk PHY_BROKEN_RESET
From: Shaohui Xie
Current driver always performs a phy soft reset when connecting the phy
device, but soft reset is not always supported by a phy device, so
introduce a quirk PHY_BROKEN_RESET to let such a phy device to skip soft
reset. This commit uses 'flags' of phy device structure to store the
quirk.
Signed-off-by: Shaohui Xie
---
drivers/net/phy/phy.c | 3 +++
include/phy.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 51b5746..2a36ae7 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -707,6 +707,9 @@ int phy_reset(struct phy_device *phydev)
int timeout = 500;
int devad = MDIO_DEVAD_NONE;
+ if (phydev->flags == PHY_BROKEN_RESET)
+ return 0;
+
#ifdef CONFIG_PHYLIB_10G
/* If it's 10G, we need to issue reset through one of the MMDs */
if (is_10g_interface(phydev->interface)) {
diff --git a/include/phy.h b/include/phy.h
index 66cf61b..5f604a1 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -16,6 +16,7 @@
#include
#define PHY_MAX_ADDR 32
+#define PHY_BROKEN_RESET (1 << 0) /* soft reset not supported */
#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
SUPPORTED_10baseT_Full | \
--
2.1.0.27.g96db324
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[U-Boot] axm SPL image too big
(cc:ing Heiko as the maintainer for axm/taurus) Hello, AXM is currently the only board failing 'buildman arm aarch64': +arm-unknown-linux-gnueabi-ld.bfd: SPL image too big +make[2]: *** [spl/u-boot-spl] Error 1 +make[1]: *** [spl/u-boot-spl] Error 2 +make: *** [sub-make] Error 2 Apparently SPL is already being built in Thumb instruction set, so no way to gain anything that way. What else can we do to get SPL size back under limit? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fdt: __of_translate_address(): check parent's 'ranges' before translate
Hello Stephen,
On 01/11/2016 05:47 PM, Stephen Warren wrote:
On 01/11/2016 04:21 AM, Przemyslaw Marczak wrote:
Hello Stephen,
On 01/07/2016 07:25 PM, Stephen Warren wrote:
On 01/07/2016 04:40 AM, Przemyslaw Marczak wrote:
The present implementation of __of_translate_address() taken
from the Linux, is designed for translate bus/child address
mappings by using 'ranges' property - and it doesn't allow
for checking an address for a device's node with zero size-cells.
The 'size-cells > 0' is required for bus/child address mapping,
but is not required for non-memory mapped address, e.g.: I2C chip.
Then when we need only raw 'reg' property's value.
Since the I2C device address goes to a single-cell reg property,
support for that case is welcome, but currently calling dev_get_addr()
for I2C device will return 'FDT_ADDR_T_NONE', and print the warning:
warning:
__of_translate_address: Bad cell count for 'some-dev'
This patch takes the wrong approach.
It simply doesn't make sense to /attempt/ to translate an I2C address
into an MMIO address space. It's a nonsensical operation; no such
translation is possible under any circumstances because I2C and MMIO
addresses mean completely different things and simply can't be
translated to each-other.
Rather than making this nonsensical operation succeed in a way that
gives the desired no-op result, the nonsensical operation simply
shouldn't be performed in the first place.
Okay, the example with I2C may be little confusing - I could use some
general naming convention. However, this patch updates FDT-related code
only.
In one of your previous e-mails, you well argued that we shouldn't use
dev_get_reg() for some buses, since they have a different 'reg' meaning.
You are right, using dev_get_addr() as universal function may be
nonsensical.
Please note, that the present implementation of function:
'__of_translate_address()' - allows for 1:1 translation, but only if
'#size-cells' exists. So the below case is possible:
--
parent {
address-cells = <1>;
size-cells = <1>;
reg = <0x1000 0x1000>;
child {
reg = <0xa00 0x100>;
};
};
dev_get_reg(child) - will return '0xa00'
--
If we don't need the address length, we can define:
--
parent {
address-cells = <1>;
size-cells = <0>;
reg = <0x1000 0x1000>;
child {
reg = <0xa00>;
};
};
This case won't ever appear in a correctly written DT where reg
represents an MMIO address; MMIO addresses always have sizes, and hence
can't have size-cells=0. Hence, translating through a DT structures like
that is an error case, and shouldn't work.
As we found out, the 'reg' property can represent not only MMIO, but may
have other meaning, so the above case is possible. The 'reg' for the
parent bus can represent MMIO (depends on what its parent defines) and
the child is non-MMIO.
You won't allow to use dev_get_addr() for other than MMIO addresses.
Ok, I have no more arguments and no more time.
My issue can be also fixed by removing dev_get_addr() call from Exynos
GPIO driver - so I will do this and within this change, will also revert
the commit:
"fdt: fix address cell count checking in fdt_translate_address()"
Best regards,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marc...@samsung.com
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[U-Boot] [PATCH v3 14/14] board: Enable ethernet, tftpboot support to pic32mzdask board.
This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also
custom environment variables/scripts are added to help boot from network.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2:
- replace unbounded loop with wait_for_bit()
- replace register access as readl/writel(base + offset)
- translate (dts provided) physical address to MIPS kseg1 address before use
arch/mips/dts/pic32mzda.dtsi | 10 ++
arch/mips/dts/pic32mzda_sk.dts | 10 ++
configs/pic32mzdask_defconfig | 26 +-
include/configs/pic32mzdask.h | 27 +--
4 files changed, 62 insertions(+), 11 deletions(-)
diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 3d62a17..57612bc 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -161,4 +161,14 @@
bus-width = <4>;
status = "disabled";
};
+
+ ethernet: ethernet@1f882000 {
+ compatible = "microchip,pic32mzda-eth";
+ reg = <0x1f882000 0x1000>;
+ interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock PB5CLK>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index f886a0f..e5ce0bd 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -42,4 +42,14 @@
&sdhci {
status = "okay";
+};
+
+ðernet {
+ reset-gpios = <&gpioJ 15 0>;
+ status = "okay";
+ phy-mode = "rmii";
+ phy-handle = <ðernet_phy>;
+ ethernet_phy: lan8740_phy@0 {
+ reg = <0>;
+ };
};
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 6981cf7..5e78e14 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -165,13 +165,13 @@ CONFIG_CMD_SETEXPR=y
#
# Network commands
#
-# CONFIG_CMD_NET is not set
+CONFIG_CMD_NET=y
# CONFIG_CMD_TFTPPUT is not set
# CONFIG_CMD_TFTPSRV is not set
-# CONFIG_CMD_RARP is not set
-# CONFIG_CMD_DHCP is not set
-# CONFIG_CMD_NFS is not set
-# CONFIG_CMD_PING is not set
+CONFIG_CMD_RARP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_PING=y
# CONFIG_CMD_CDP is not set
# CONFIG_CMD_SNTP is not set
# CONFIG_CMD_DNS is not set
@@ -208,7 +208,10 @@ CONFIG_SUPPORT_OF_CONTROL=y
CONFIG_OF_CONTROL=y
# CONFIG_OF_SEPARATE is not set
CONFIG_OF_EMBED=y
-# CONFIG_NET is not set
+CONFIG_NET=y
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_NETCONSOLE is not set
+CONFIG_NET_TFTP_VARS=y
#
# Device Drivers
@@ -308,8 +311,13 @@ CONFIG_PIC32_SDHCI=y
# SPI Flash Support
#
# CONFIG_SPI_FLASH is not set
-# CONFIG_DM_ETH is not set
-# CONFIG_PHYLIB is not set
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_E1000 is not set
+# CONFIG_ETH_DESIGNWARE is not set
+CONFIG_PIC32_ETH=y
#
# PCI
@@ -398,7 +406,7 @@ CONFIG_SYS_HZ=1000
CONFIG_SYS_VSNPRINTF=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_REGEX=y
-# CONFIG_LIB_RAND is not set
+CONFIG_LIB_RAND=y
CONFIG_CMD_DHRYSTONE=y
# CONFIG_RSA is not set
# CONFIG_TPM is not set
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 224b21c..7339f0f 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -73,6 +73,25 @@
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_CMDLINE_EDITING 1
+/*---
+ * Networking Configuration
+ */
+#define CONFIG_MII
+#define CONFIG_PHY_SMSC
+#define CONFIG_SYS_RX_ETH_BUFFER 8
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_ARP_TIMEOUT 500 /* millisec */
+
+#define CONFIG_CMD_MII
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
/*
* Handover flattened device tree (dtb file) to Linux kernel
*/
@@ -127,12 +146,16 @@
"importbootenv= " \
"env import -t -r ${uenvaddr} ${filesize};\0" \
\
+ "tftploadenv=tftp ${uenvaddr} ${uenvfile} \0" \
+ "tftploadscr=tftp ${uenvaddr} ${scriptfile} \0" \
+ "tftploadub=tftp ${loadaddr} ${ubootfile} \0" \
+ \
"mmcloadenv=fatload mmc 0 ${uenvaddr} ${uenvfile}\0"\
"mmcloadscr=fatload mmc 0 ${uenvaddr} ${scriptfile}\0" \
"mmcloadub=fatload mmc 0 ${loadaddr} ${ubootfile}\0"\
\
- "loadbootenv=run mmcloadenv\0" \
- "loadbootscr=run mmcloadscr\0"
[U-Boot] [PATCH v3 13/14] drivers: net: Add ethernet driver for Microchip PIC32.
This driver implements MAC and MII layer of the ethernet controller.
Network data transfer is handled by controller internal DMA engine.
Ethernet controller is configurable through device-tree file.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- merge wrappers with eth operation callbacks
- read phy address from device-tree
- rename functions (e.g. _eth_xyz() with pic32_eth_xyz())
Changes in v2: None
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/pic32_eth.c | 606 +++
drivers/net/pic32_eth.h | 171 +
drivers/net/pic32_mdio.c | 121 ++
5 files changed, 906 insertions(+)
create mode 100644 drivers/net/pic32_eth.c
create mode 100644 drivers/net/pic32_eth.h
create mode 100644 drivers/net/pic32_mdio.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ae5e78d..dc49493 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -108,4 +108,11 @@ config ZYNQ_GEM
help
This MAC is present in Xilinx Zynq and ZynqMP SoCs.
+config PIC32_ETH
+ bool "Microchip PIC32 Ethernet Support"
+ depends on MACH_PIC32
+ help
+ This driver implements 10/100 Mbps Ethernet and MAC layer for
+ Microchip PIC32 microcontrollers.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 150470c..33a81ee 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o
+obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c
new file mode 100644
index 000..1cef62e
--- /dev/null
+++ b/drivers/net/pic32_eth.c
@@ -0,0 +1,606 @@
+/*
+ * (c) 2015 Purna Chandra Mandal
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pic32_eth.h"
+
+#define MAX_RX_BUF_SIZE1536
+#define MAX_RX_DESCR PKTBUFSRX
+#define MAX_TX_DESCR 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pic32eth_dev {
+ struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
+ struct eth_dma_desc txd_ring[MAX_TX_DESCR];
+ u32 rxd_idx; /* index of RX desc to read */
+ /* regs */
+ struct pic32_ectl_regs *ectl_regs;
+ struct pic32_emac_regs *emac_regs;
+ /* Phy */
+ struct phy_device *phydev;
+ phy_interface_t phyif;
+ u32 phy_addr;
+ struct gpio_desc rst_gpio;
+};
+
+void __weak board_netphy_reset(void *dev)
+{
+ struct pic32eth_dev *priv = (struct pic32eth_dev *)dev;
+
+ if (!dm_gpio_is_valid(&priv->rst_gpio))
+ return;
+
+ /* phy reset */
+ dm_gpio_set_value(&priv->rst_gpio, 0);
+ udelay(300);
+ dm_gpio_set_value(&priv->rst_gpio, 1);
+ udelay(300);
+}
+
+/* Initialize mii(MDIO) interface, discover which PHY is
+ * attached to the device, and configure it properly.
+ */
+static int pic32_mii_init(struct pic32eth_dev *priv)
+{
+ struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
+ struct pic32_emac_regs *emac_p = priv->emac_regs;
+
+ /* board phy reset */
+ board_netphy_reset(priv);
+
+ /* disable RX, TX & all transactions */
+ writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
+
+ /* wait till busy */
+ wait_for_bit(__func__, &ectl_p->stat.raw, ETHSTAT_BUSY, false,
+CONFIG_SYS_HZ, false);
+
+ /* turn controller ON to access PHY over MII */
+ writel(ETHCON_ON, &ectl_p->con1.set);
+
+ mdelay(10);
+
+ /* reset MAC */
+ writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
+ mdelay(10);
+ writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
+
+ /* initialize MDIO/MII */
+ if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
+ writel(EMAC_RMII_RESET, &emac_p->supp.set);
+ mdelay(10);
+ writel(EMAC_RMII_RESET, &emac_p->supp.clr);
+ }
+
+ return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
+}
+
+static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
+{
+ struct mii_dev *mii;
+
+ mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
+
+ /* find & connect PHY */
+ priv->phydev = phy_connect(mii, priv->phy_addr,
+ dev, priv->phyif);
+ if (!priv->phydev) {
+ printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
+ return 0;
+ }
+
+ /* Wait for phy to complete reset */
+ mdelay(10);
+
+ /* configure supported modes */
+ priv->phydev->supported = SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100ba
[U-Boot] [PATCH v3 12/14] drivers: net: phy: add SMSC LAN8740 Phy support.
Add SMSC LAN8740 Phy support required for PIC32MZDA devices.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2: None
drivers/net/phy/smsc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index bfd9815..34986a2 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -69,11 +69,21 @@ static struct phy_driver lan8710_driver = {
.shutdown = &genphy_shutdown,
};
+static struct phy_driver lan8740_driver = {
+ .name = "SMSC LAN8740",
+ .uid = 0x0007c110,
+ .mask = 0x0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &genphy_config_aneg,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
int phy_smsc_init(void)
{
phy_register(&lan8710_driver);
phy_register(&lan911x_driver);
phy_register(&lan8700_driver);
+ phy_register(&lan8740_driver);
return 0;
}
--
1.8.3.1
___
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[U-Boot] [PATCH v3 09/14] board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- drop SKIP_LOWLEVEL_INIT, GBL_DATA_OFFSET from config header
- move CMD_MEMTEST, CMD_MEMINFO to defconfig
- increase SYS_MALLOC_F_LEN to 0x600
- use auto-generated defconfig - no hand edit
Changes in v2:
- move CONFIG_SYS_TEXT_BASE (from board/*/config.mk) to
include/configs/.h
arch/mips/dts/Makefile| 2 +-
arch/mips/dts/pic32mzda_sk.dts| 38
arch/mips/mach-pic32/Kconfig | 13 ++
board/microchip/pic32mzda/Kconfig | 13 ++
board/microchip/pic32mzda/MAINTAINERS | 6 +
board/microchip/pic32mzda/Makefile| 7 +
board/microchip/pic32mzda/README | 22 ++
board/microchip/pic32mzda/pic32mzda.c | 31 +++
configs/pic32mzdask_defconfig | 416 ++
include/configs/pic32mzdask.h | 94
10 files changed, 641 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/pic32mzda_sk.dts
create mode 100644 board/microchip/pic32mzda/Kconfig
create mode 100644 board/microchip/pic32mzda/MAINTAINERS
create mode 100644 board/microchip/pic32mzda/Makefile
create mode 100644 board/microchip/pic32mzda/README
create mode 100644 board/microchip/pic32mzda/pic32mzda.c
create mode 100644 configs/pic32mzdask_defconfig
create mode 100644 include/configs/pic32mzdask.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 47b6eb5..b513918 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -2,7 +2,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-dtb-y +=
+dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
new file mode 100644
index 000..99e7f64
--- /dev/null
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal, purna.man...@microchip.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "pic32mzda.dtsi"
+
+/ {
+ model = "Microchip PIC32MZDASK";
+ compatible = "microchip,pic32mzdask", "microchip,pic32mzda";
+
+ aliases {
+ console = &uart2;
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&clock {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index 74be9fb..d665f63 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -22,4 +22,17 @@ config SOC_PIC32MZDA
endchoice
+choice
+ prompt "Board select"
+
+config TARGET_PIC32MZDASK
+ bool "Microchip PIC32MZ[DA] Starter Kit"
+ depends on SOC_PIC32MZDA
+ help
+ This supports Microchip PIC32MZ[DA] Starter Kit.
+
+endchoice
+
+source "board/microchip/pic32mzda/Kconfig"
+
endmenu
diff --git a/board/microchip/pic32mzda/Kconfig
b/board/microchip/pic32mzda/Kconfig
new file mode 100644
index 000..8acb393
--- /dev/null
+++ b/board/microchip/pic32mzda/Kconfig
@@ -0,0 +1,13 @@
+
+if TARGET_PIC32MZDASK
+
+config SYS_BOARD
+ default "pic32mzda"
+
+config SYS_VENDOR
+ default "microchip"
+
+config SYS_CONFIG_NAME
+ default "pic32mzdask"
+
+endif
diff --git a/board/microchip/pic32mzda/MAINTAINERS
b/board/microchip/pic32mzda/MAINTAINERS
new file mode 100644
index 000..c934f1a
--- /dev/null
+++ b/board/microchip/pic32mzda/MAINTAINERS
@@ -0,0 +1,6 @@
+PIC32MZDASK BOARD
+M: Purna Chandra Mandal
+S: Maintained
+F: board/microchip/pic32mzda/
+F: include/configs/pic32mzdask.h
+F: configs/pic32mzdask_defconfig
diff --git a/board/microchip/pic32mzda/Makefile
b/board/microchip/pic32mzda/Makefile
new file mode 100644
index 000..3629530
--- /dev/null
+++ b/board/microchip/pic32mzda/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.man...@microchip.com.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y := pic32mzda.o
diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README
new file mode 100644
index 000..91d16ab
--- /dev/null
+++ b/board/microchip/pic32mzda/README
@@ -0,0 +1,22 @@
+/*
+ * (c) 2015 Purna Chandra Mandal
+ */
+
+PIC32MZ[DA] Starter Kit
+
+PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller.
+This family is powered by MIPS M14KEC 32bit general purpose core and has
+advanced microcontroller features and peripherals.
+
+This processor boots with proprietary stage1 bootloader running from internal
+boot-flash. Stage1 bootloader inturns locates and jumps to U-Boot programmed
+on internal program-flash. Finally U-Boot loads OS image (alo
[U-Boot] [PATCH v3 10/14] drivers: mmc: add driver for Microchip PIC32 SDHCI controller.
From: Andrei Pistirica
This driver implements platform specific glue and fixups for
PIC32 internal SDHCI controller.
Signed-off-by: Andrei Pistirica
Signed-off-by: Sandeep Sheriker Mallikarjun
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- remove ofdata_to_platdata, and replace platdata with priv
- replace pic32_ioremap() with ioremap()
Changes in v2:
- drop sdhci shared bus configuration (for shared interrupt, clock pins)
drivers/mmc/Kconfig | 6 +
drivers/mmc/Makefile | 2 +-
drivers/mmc/pic32_sdhci.c | 61 +++
drivers/mmc/sdhci.c | 12 ++
4 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 drivers/mmc/pic32_sdhci.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index ceae7bc..0b6f54b 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -31,4 +31,10 @@ config SH_SDHI
help
Support for the on-chip SDHI host controller on SuperH/Renesas ARM
SoCs platform
+config PIC32_SDHCI
+ bool "Microchip PIC32 on-chip SDHCI support"
+ depends on DM_MMC && MACH_PIC32
+ help
+ Support for the on-chip SDHCI support on Microchip PIC32 platforms.
+
endmenu
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 5d35705..c9c3e3e 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
else
obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
endif
-
+obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
new file mode 100644
index 000..f8a5a23
--- /dev/null
+++ b/drivers/mmc/pic32_sdhci.c
@@ -0,0 +1,61 @@
+/*
+ * Support of SDHCI for Microchip PIC32 SoC.
+ *
+ * Copyright (C) 2015 Microchip Technology Inc.
+ * Andrei Pistirica
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int pic32_sdhci_probe(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+ const void *fdt = gd->fdt_blob;
+ u32 f_min_max[2];
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ host->ioaddr = ioremap(addr, size);
+ if (!host->ioaddr)
+ return -EINVAL;
+
+ host->name = (char *)dev->name;
+ host->quirks= SDHCI_QUIRK_NO_HISPD_BIT;
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "bus-width", 4);
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ "clock-freq-min-max", f_min_max, 2);
+ if (ret) {
+ printf("sdhci: clock-freq-min-max not found\n");
+ return ret;
+ }
+
+ return add_sdhci(host, f_min_max[1], f_min_max[0]);
+}
+
+static const struct udevice_id pic32_sdhci_ids[] = {
+ { .compatible = "microchip,pic32mzda-sdhci" },
+ { }
+};
+
+U_BOOT_DRIVER(pic32_sdhci_drv) = {
+ .name = "pic32_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = pic32_sdhci_ids,
+ .probe = pic32_sdhci_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+};
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 02d71b9..f32fe67 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -424,6 +424,18 @@ static void sdhci_set_ios(struct mmc *mmc)
if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
ctrl &= ~SDHCI_CTRL_HISPD;
+#if defined(CONFIG_PIC32_SDHCI)
+ /*
+ * In PIC32MZ[DA] due to h/w bug SDHCI fails detecting card when JTAG
+ * is not connected.
+ * To work-around this problem:
+ * - set Card_Detect_Signal_Selection bit in SDHCI_Host_Control register
+ * - clear Card_Detect_Test_Level bit in SDHCI_Host_Control register
+ */
+ ctrl |= SDHCI_CTRL_CD_TEST;
+ ctrl &= ~SDHCI_CTRL_CD_TEST_INS;
+#endif
+
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
--
1.8.3.1
___
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[U-Boot] [PATCH v3 11/14] board: add SDHCI support for PIC32MZDASK board.
Enable MMC, SDHCI, FAT FS, EXT4 FS support for PIC32MZ[DA] StarterKit.
Also add custom scripts, rules to boot Linux from microSD card.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3: None
Changes in v2:
- drop shared bus (shared pin selection) configuration.
arch/mips/dts/pic32mzda.dtsi | 11
arch/mips/dts/pic32mzda_sk.dts | 7 +
configs/pic32mzdask_defconfig | 6 +++--
include/configs/pic32mzdask.h | 61 ++
4 files changed, 83 insertions(+), 2 deletions(-)
diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index fe8b13a..3d62a17 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -150,4 +150,15 @@
#gpio-cells = <2>;
};
};
+
+ sdhci: sdhci@1f8ec000 {
+ compatible = "microchip,pic32mzda-sdhci";
+ reg = <0x1f8ec000 0x100>;
+ interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock REF4CLK>, <&clock PB5CLK>;
+ clock-names = "base_clk", "sys_clk";
+ clock-freq-min-max = <2500>,<2500>;
+ bus-width = <4>;
+ status = "disabled";
+ };
};
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index 99e7f64..f886a0f 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -23,6 +23,9 @@
};
&clock {
+ microchip,refo2-frequency = <5000>;
+ microchip,refo4-frequency = <2500>;
+ microchip,refo5-frequency = <4000>;
status = "okay";
u-boot,dm-pre-reloc;
};
@@ -36,3 +39,7 @@
status = "okay";
u-boot,dm-pre-reloc;
};
+
+&sdhci {
+ status = "okay";
+};
\ No newline at end of file
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 3483eb0..6981cf7 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -122,7 +122,7 @@ CONFIG_CMD_XIMG=y
#
# Environment commands
#
-# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_EXPORTENV=y
CONFIG_CMD_IMPORTENV=y
CONFIG_CMD_EDITENV=y
# CONFIG_CMD_SAVEENV is not set
@@ -284,7 +284,9 @@ CONFIG_PIC32_GPIO=y
#
# MMC Host controller Support
#
-# CONFIG_DM_MMC is not set
+CONFIG_DM_MMC=y
+# CONFIG_ROCKCHIP_DWMMC is not set
+CONFIG_PIC32_SDHCI=y
#
# MTD Support
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 6552fa2..224b21c 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -78,6 +78,33 @@
*/
#define CONFIG_OF_LIBFDT 1
+/*---
+ * SDHC Configuration
+ */
+#define CONFIG_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+
+/*---
+ * File System Configuration
+ */
+/* FAT FS */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_FAT
+
+/* EXT4 FS */
+#define CONFIG_FS_EXT4
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
/* -
* Environment
*/
@@ -91,4 +118,38 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after X seconds */
#undef CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"\
+ "uenvfile=uEnv.txt\0" \
+ "uenvaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0" \
+ "scriptfile=boot.scr\0" \
+ "ubootfile=u-boot.bin\0"\
+ "importbootenv= " \
+ "env import -t -r ${uenvaddr} ${filesize};\0" \
+ \
+ "mmcloadenv=fatload mmc 0 ${uenvaddr} ${uenvfile}\0"\
+ "mmcloadscr=fatload mmc 0 ${uenvaddr} ${scriptfile}\0" \
+ "mmcloadub=fatload mmc 0 ${loadaddr} ${ubootfile}\0"\
+ \
+ "loadbootenv=run mmcloadenv\0" \
+ "loadbootscr=run mmcloadscr\0" \
+ "bootcmd_root= "\
+ "if run loadbootenv; then " \
+ "echo Loaded environment ${uenvfile}; " \
+ "run importbootenv; " \
+ "fi; " \
+ "if test -n \"${bootcmd_uenv}\" ; then "\
+ "echo Running bootcmd_uenv ...; " \
+ "run bootcmd_uenv; "
[U-Boot] [PATCH v3 08/14] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.
Add Microchip PIC32MZ[DA] SoC family support.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
- indent assembly instructions in delay slot
- made GPIO-nodes child of pinctrl-node in devicetree
- replace pic32_ioremap() with ioremap()
Changes in v2:
- drop board_early_init_f
- use macro LEAF(), END() for lowlevel_init assembly
- move initialization of board_init_f() argument to common start.S
- move initdram() from board/microchip/ to mach-pic32/cpu.c
- remove MIPS virtual address in favor physical one in dts file
arch/mips/dts/pic32mzda.dtsi | 153 ++
arch/mips/mach-pic32/Kconfig | 20 +++-
arch/mips/mach-pic32/Makefile | 2 +-
arch/mips/mach-pic32/cpu.c| 147
arch/mips/mach-pic32/include/mach/pic32.h | 3 +
arch/mips/mach-pic32/lowlevel_init.S | 27 ++
arch/mips/mach-pic32/reset.c | 36 +++
7 files changed, 386 insertions(+), 2 deletions(-)
create mode 100644 arch/mips/dts/pic32mzda.dtsi
create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
create mode 100644 arch/mips/mach-pic32/reset.c
diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
new file mode 100644
index 000..fe8b13a
--- /dev/null
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2015 Microchip Technology, Inc.
+ * Purna Chandra Mandal,
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "microchip,pic32mzda", "microchip,pic32mz";
+
+ aliases {
+ gpio0 = &gpioA;
+ gpio1 = &gpioB;
+ gpio2 = &gpioC;
+ gpio3 = &gpioD;
+ gpio4 = &gpioE;
+ gpio5 = &gpioF;
+ gpio6 = &gpioG;
+ gpio7 = &gpioH;
+ gpio8 = &gpioJ;
+ gpio9 = &gpioK;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips14kc";
+ };
+ };
+
+ clock: clk@1f801200 {
+ compatible = "microchip,pic32mzda_clk";
+ reg = <0x1f801200 0x1000>;
+ clock-cells = <1>;
+ };
+
+ uart1: serial@1f822000 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <0x1f822000 0x50>;
+ interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&clock PB2CLK>;
+ };
+
+ uart2: serial@1f822200 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <0x1f822200 0x50>;
+ interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock PB2CLK>;
+ status = "disabled";
+ };
+
+ uart6: serial@1f822a00 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <0x1f822a00 0x50>;
+ interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock PB2CLK>;
+ status = "disabled";
+ };
+
+ evic: interrupt-controller@1f81 {
+ compatible = "microchip,pic32mzda-evic";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1f81 0x1000>;
+ };
+
+ pinctrl: pinctrl@1f801400 {
+ compatible = "microchip,pic32mzda-pinctrl";
+ reg = <0x1f801400 0x100>, /* in */
+ <0x1f801500 0x200>, /* out */
+ <0x1f86 0xa00>; /* port */
+ reg-names = "ppsin","ppsout","port";
+ status = "disabled";
+
+ ranges = <0 0x1f86 0xa00>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gpioA: gpio0@0 {
+ compatible = "microchip,pic32mzda-gpio";
+ reg = <0x000 0x48>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioB: gpio1@100 {
+ compatible = "microchip,pic32mzda-gpio";
+ reg = <0x100 0x48>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioC: gpio2@200 {
+ compatible = "microchip,pic32mzda-gpio";
+ reg = <0x200 0x48>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioD: gpio3@300 {
+ compatible = "microchip,pic32mzda-gpio";
+ reg = <0x300 0x48>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioE: gpio4@400 {
+ compatible = "microchip,pic32mzda-gpio";
+ reg = <0x
[U-Boot] [PATCH v3 06/14] drivers: serial: add driver for Microchip PIC32 UART controller.
From: Paul Thacker
This adds PIC32 UART controller support based on driver model.
Signed-off-by: Paul Thacker
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- remove ofdata_to_platdata, and replace platdata with priv
- remove special handling of '\r' as being handled by serial-uclass
- remove loop to wait for space in tx buffer before pumping char
Changes in v2:
- fix missing/corrupted chars during baud rate change
- remove loop until any char is avaialbale in getc()
.../serial/microchip,pic32-uart.txt| 5 +
drivers/serial/Kconfig | 13 ++
drivers/serial/Makefile| 1 +
drivers/serial/serial_pic32.c | 199 +
4 files changed, 218 insertions(+)
create mode 100644 doc/device-tree-bindings/serial/microchip,pic32-uart.txt
create mode 100644 drivers/serial/serial_pic32.c
diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
new file mode 100644
index 000..f00e215
--- /dev/null
+++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt
@@ -0,0 +1,5 @@
+* Microchip PIC32 serial UART
+
+Required properties:
+- compatible: must be "microchip,pic32mzda-uart".
+- reg: exactly one register range.
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1fc287e..9763ea1 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -107,6 +107,14 @@ config DEBUG_UART_APBUART
will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_PIC32
+ bool "Microchip PIC32"
+ help
+ Select this to enable a debug UART using the serial_pic32 driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver model serial is running.
+
+
endchoice
config DEBUG_UART_BASE
@@ -223,4 +231,9 @@ config UNIPHIER_SERIAL
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
+config PIC32_SERIAL
+ bool "Support for Microchip PIC32 on-chip UART"
+ help
+ Support for the UART found on Microchip PIC32 SoC's.
+
endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index dd87147..57cd38b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
+obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
new file mode 100644
index 000..ee9d056
--- /dev/null
+++ b/drivers/serial/serial_pic32.c
@@ -0,0 +1,199 @@
+/*
+ * (c) 2015 Paul Thacker
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* UART Control Registers */
+#define U_MOD 0x00
+#define U_MODCLR (U_MOD + _CLR_OFFSET)
+#define U_MODSET (U_MOD + _SET_OFFSET)
+#define U_STA 0x10
+#define U_STACLR (U_STA + _CLR_OFFSET)
+#define U_STASET (U_STA + _SET_OFFSET)
+#define U_TXR 0x20
+#define U_RXR 0x30
+#define U_BRG 0x40
+
+/* U_MOD bits */
+#define UART_ENABLEBIT(15)
+
+/* U_STA bits */
+#define UART_RX_ENABLE BIT(12)
+#define UART_TX_BRKBIT(11)
+#define UART_TX_ENABLE BIT(10)
+#define UART_TX_FULL BIT(9)
+#define UART_TX_EMPTY BIT(8)
+#define UART_RX_OERR BIT(1)
+#define UART_RX_DATA_AVAIL BIT(0)
+
+struct pic32_uart_priv {
+ void __iomem *base;
+ ulong uartclk;
+};
+
+/*
+ * Initialize the serial port with the given baudrate.
+ * The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate)
+{
+ u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
+
+ /* wait for TX FIFO to empty */
+ wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY,
+true, CONFIG_SYS_HZ, false);
+
+ /* send break */
+ writel(UART_TX_BRK, base + U_STASET);
+
+ /* disable and clear mode */
+ writel(0, base + U_MOD);
+ writel(0, base + U_STA);
+
+ /* set baud rate generator */
+ writel(div - 1, base + U_BRG);
+
+ /* enable the UART for TX and RX */
+ writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET);
+
+ /* enable the UART */
+ writel(UART_ENABLE, base + U_MODSET);
+ return 0;
+}
+
+/* Check number of characters ready in RX Fifo */
+static int pic32_uart_pending_input(void __iomem *base)
+
[U-Boot] [PATCH v3 07/14] drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy
module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).
Signed-off-by: Paul Thacker
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- annotating fixed table with const
- fix camel-case in ddr2 timing parameters
- fix cmd index parameter of host_load_cmd().
- fix compilation warning
Changes in v2:
- move ddr2 initialization from board/microchip/ to drivers/ddr/microchip
arch/mips/mach-pic32/include/mach/ddr.h | 32
drivers/Makefile| 1 +
drivers/ddr/microchip/Makefile | 6 +
drivers/ddr/microchip/ddr2.c| 278
drivers/ddr/microchip/ddr2_regs.h | 148 +
drivers/ddr/microchip/ddr2_timing.h | 65
6 files changed, 530 insertions(+)
create mode 100644 arch/mips/mach-pic32/include/mach/ddr.h
create mode 100644 drivers/ddr/microchip/Makefile
create mode 100644 drivers/ddr/microchip/ddr2.c
create mode 100644 drivers/ddr/microchip/ddr2_regs.h
create mode 100644 drivers/ddr/microchip/ddr2_timing.h
diff --git a/arch/mips/mach-pic32/include/mach/ddr.h
b/arch/mips/mach-pic32/include/mach/ddr.h
new file mode 100644
index 000..00abfa3
--- /dev/null
+++ b/arch/mips/mach-pic32/include/mach/ddr.h
@@ -0,0 +1,32 @@
+/*
+ * (c) 2015 Purna Chandra Mandal
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __MICROCHIP_PIC32_DDR_H
+#define __MICROCHIP_PIC32_DDR_H
+
+/* called by initdram() function */
+void ddr2_phy_init(void);
+void ddr2_ctrl_init(void);
+phys_size_t ddr2_calculate_size(void);
+
+/* Maximum number of agents */
+#define NUM_AGENTS 5
+
+/* Board can provide agent specific parameters for arbitration by
+ * filling struct ddr2_arbiter_params for all the agents and
+ * implementing board_get_ddr_arbiter_params() to return the filled
+ * structure.
+ */
+struct ddr2_arbiter_params {
+ u32 min_limit; /* min bursts to execute per arbitration */
+ u32 req_period; /* request period threshold for accepted cmds */
+ u32 min_cmd_acpt; /* min number of accepted cmds */
+};
+
+const struct ddr2_arbiter_params *board_get_ddr_arbiter_params(void);
+
+#endif /* __MICROCHIP_PIC32_DDR_H */
diff --git a/drivers/Makefile b/drivers/Makefile
index c9031f2..0ab54d9 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -68,4 +68,5 @@ obj-y += soc/
obj-$(CONFIG_REMOTEPROC) += remoteproc/
obj-y += thermal/
+obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
endif
diff --git a/drivers/ddr/microchip/Makefile b/drivers/ddr/microchip/Makefile
new file mode 100644
index 000..305c48b
--- /dev/null
+++ b/drivers/ddr/microchip/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2015 Microchip Technology Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-$(CONFIG_MACH_PIC32) += ddr2.o
diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c
new file mode 100644
index 000..6056418
--- /dev/null
+++ b/drivers/ddr/microchip/ddr2.c
@@ -0,0 +1,278 @@
+/*
+ * (c) 2015 Paul Thacker
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ddr2_regs.h"
+#include "ddr2_timing.h"
+
+/* init DDR2 Phy */
+void ddr2_phy_init(void)
+{
+ struct ddr2_phy_regs *ddr2_phy;
+ u32 pad_ctl;
+
+ ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
+
+ /* PHY_DLL_RECALIB */
+ writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) |
+ RECALIB_CNT(0x10), &ddr2_phy->dll_recalib);
+
+ /* PHY_PAD_CTRL */
+ pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) |
+ ODT_PULLDOWN(2) | ODT_PULLUP(3) |
+ EXTRA_OEN_CLK(0) | NOEXT_DLL |
+ DLR_DFT_WRCMD | HALF_RATE |
+ DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) |
+ RCVR_EN | PREAMBLE_DLY(2);
+ writel(pad_ctl, &ddr2_phy->pad_ctrl);
+
+ /* SCL_CONFIG_0 */
+ writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) |
+ SCL_ODTCSWW, &ddr2_phy->scl_config_1);
+
+ /* SCL_CONFIG_1 */
+ writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2);
+
+ /* SCL_LAT */
+ writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy->scl_latency);
+}
+
+/* start phy self calibration logic */
+static int ddr2_phy_calib_start(void)
+{
+ struct ddr2_phy_regs *ddr2_phy;
+
+ ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
+
+ /* DDR Phy SCL Start */
+ writel(SCL_START | SCL_EN, &ddr2_phy->scl_start);
+
+ /* Wait for SCL for data byte to pass */
+ return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS,
+ true, CONFIG_SYS_HZ, false);
+}
+
+/* DDR2 Controller initialization */
+
+/* Target Agent Arbiter */
+static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl,
+ const struct ddr2_arbiter_params *const param)
+{
+
[U-Boot] [PATCH v3 05/14] drivers: gpio: add driver for Microchip PIC32 GPIO controller.
In PIC32 GPIO controller is part of PIC32 pin controller.
PIC32 has ten independently programmable ports and each with multiple pins.
Each of these pins can be configured and used as GPIO, provided they
are not in use for other peripherals.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- add check on dev_get_addr()
Changes in v2: None
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile | 2 +-
drivers/gpio/pic32_gpio.c | 175 ++
3 files changed, 183 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpio/pic32_gpio.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e60e9fd..13e9a6a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -83,4 +83,11 @@ config VYBRID_GPIO
help
Say yes here to support Vybrid vf610 GPIOs.
+config PIC32_GPIO
+ bool "Microchip PIC32 GPIO driver"
+ depends on DM_GPIO
+ default y if MACH_PIC32
+ help
+ Say yes here to support Microchip PIC32 GPIOs.
+
endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb4fd25..845a6d4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
obj-$(CONFIG_ZYNQ_GPIO)+= zynq_gpio.o
obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o
obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o
-
+obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o
diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c
new file mode 100644
index 000..5b23af4
--- /dev/null
+++ b/drivers/gpio/pic32_gpio.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015 Microchip Technology Inc
+ * Purna Chandra Mandal
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Peripheral Pin Control */
+struct pic32_reg_port {
+ struct pic32_reg_atomic ansel;
+ struct pic32_reg_atomic tris;
+ struct pic32_reg_atomic port;
+ struct pic32_reg_atomic lat;
+ struct pic32_reg_atomic open_drain;
+ struct pic32_reg_atomic cnpu;
+ struct pic32_reg_atomic cnpd;
+ struct pic32_reg_atomic cncon;
+};
+
+enum {
+ MICROCHIP_GPIO_DIR_OUT,
+ MICROCHIP_GPIO_DIR_IN,
+ MICROCHIP_GPIOS_PER_BANK = 16,
+};
+
+struct pic32_gpio_priv {
+ struct pic32_reg_port *regs;
+ char name[2];
+};
+
+static int pic32_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+ return !!(readl(&priv->regs->port.raw) & BIT(offset));
+}
+
+static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct pic32_gpio_priv *priv = dev_get_priv(dev);
+ int mask = BIT(offset);
+
+ if (value)
+ writel(mask, &priv->regs->port.set);
+ else
+ writel(mask, &priv->regs->port.clr);
+
+ return 0;
+}
+
+static int pic32_gpio_direction(struct udevice *dev, unsigned offset)
+{
+ struct pic32_gpio_priv *priv = dev_get_priv(dev);
+
+ if (readl(&priv->regs->ansel.raw) & BIT(offset))
+ return -1;
+
+ if (readl(&priv->regs->tris.raw) & BIT(offset))
+ return MICROCHIP_GPIO_DIR_IN;
+ else
+ return MICROCHIP_GPIO_DIR_OUT;
+}
+
+static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct pic32_gpio_priv *priv = dev_get_priv(dev);
+ int mask = BIT(offset);
+
+ writel(mask, &priv->regs->ansel.clr);
+ writel(mask, &priv->regs->tris.set);
+
+ return 0;
+}
+
+static int pic32_gpio_direction_output(struct udevice *dev,
+ unsigned offset, int value)
+{
+ struct pic32_gpio_priv *priv = dev_get_priv(dev);
+ int mask = BIT(offset);
+
+ writel(mask, &priv->regs->ansel.clr);
+ writel(mask, &priv->regs->tris.clr);
+
+ pic32_gpio_set_value(dev, offset, value);
+ return 0;
+}
+
+static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args)
+{
+ desc->offset = args->args[0];
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ int ret = GPIOF_UNUSED;
+
+ switch (pic32_gpio_direction(dev, offset)) {
+ case MICROCHIP_GPIO_DIR_OUT:
+ ret = GPIOF_OUTPUT;
+ break;
+ case MICROCHIP_GPIO_DIR_IN:
+ ret = GPIOF_INPUT;
+ break;
+ default:
+ ret = GPIOF_UNUSED;
+ break;
+ }
+ return ret;
+}
+
+static const struct dm_gpio_ops gpio_pic32_ops = {
+ .direction_input= pic32_gpio_direction_input,
+ .direction_output
[U-Boot] [PATCH v3 04/14] drivers: pinctrl: Add pinctrl driver for Microchip PIC32.
In PIC32 pin-controller is a combined gpio-controller, pin-mux and
pin-config module. Remappable peripherals are assigned pins through
per-pin based muxing logic. And pin configuration are performed on
specific port registers which are shared along with gpio controller.
Note, non-remappable peripherals have default pins assigned thus require
no muxing.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- read register base from device-tree
- add/update comments to explain how pinctrl'r works.
- replace pic32_ioremap() with ioremap().
Changes in v2:
- add pinconf routine for configuring pin property
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/Makefile| 1 +
drivers/pinctrl/pinctrl_pic32.c | 363
3 files changed, 373 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl_pic32.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 57e6142..292c4e2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -131,6 +131,15 @@ config PINCTRL_SANDBOX
actually does nothing but print debug messages when pinctrl
operations are invoked.
+config PIC32_PINCTRL
+ bool "Microchip PIC32 pin-control and pin-mux driver"
+ depends on DM && MACH_PIC32
+ help
+ Supports individual pin selection and configuration for each
remappable
+ peripheral available on Microchip PIC32 SoCs. This driver is
controlled
+ by a device tree node which contains both GPIO defintion and pin
control
+ functions.
+
endif
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 70d25dc..b4f4650 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_ARCH_UNIPHIER)+= uniphier/
+obj-$(CONFIG_PIC32_PINCTRL)+= pinctrl_pic32.o
diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c
new file mode 100644
index 000..5cf97ec
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -0,0 +1,363 @@
+/*
+ * Pinctrl driver for Microchip PIC32 SoCs
+ * Copyright (c) 2015 Microchip Technology Inc.
+ * Written by Purna Chandra Mandal
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 has 10 peripheral ports with 16 pins each.
+ * Ports are marked PORTA-PORTK or PORT0-PORT9.
+ */
+enum {
+ PIC32_PORT_A = 0,
+ PIC32_PORT_B = 1,
+ PIC32_PORT_C = 2,
+ PIC32_PORT_D = 3,
+ PIC32_PORT_E = 4,
+ PIC32_PORT_F = 5,
+ PIC32_PORT_G = 6,
+ PIC32_PORT_H = 7,
+ PIC32_PORT_J = 8, /* no PORT_I */
+ PIC32_PORT_K = 9,
+ PIC32_PINS_PER_PORT = 16,
+};
+
+#define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_PIC32_ANALOG(PIN_CONFIG_END + 2)
+
+/* pin configuration descriptor */
+struct pic32_pin_config {
+ u16 port; /* port number */
+ u16 pin;/* pin number in the port */
+ u32 config; /* one of PIN_CONFIG_* */
+};
+#define PIN_CONFIG(_prt, _pin, _cfg) \
+ {.port = (_prt), .pin = (_pin), .config = (_cfg), }
+
+/* In PIC32 muxing is performed at pin-level through two
+ * different set of registers - one set for input functions,
+ * and other for output functions.
+ * Pin configuration is handled through port register.
+ */
+/* Port control registers */
+struct pic32_reg_port {
+ struct pic32_reg_atomic ansel;
+ struct pic32_reg_atomic tris;
+ struct pic32_reg_atomic port;
+ struct pic32_reg_atomic lat;
+ struct pic32_reg_atomic odc;
+ struct pic32_reg_atomic cnpu;
+ struct pic32_reg_atomic cnpd;
+ struct pic32_reg_atomic cncon;
+ struct pic32_reg_atomic unused[8];
+};
+
+/* Input function mux registers */
+struct pic32_reg_in_mux {
+ u32 unused0;
+ u32 int1[4];
+ u32 unused1;
+ u32 t2ck[8];
+ u32 ic1[9];
+ u32 unused2;
+ u32 ocfar;
+ u32 unused3;
+ u32 u1rx;
+ u32 u1cts;
+ u32 u2rx;
+ u32 u2cts;
+ u32 u3rx;
+ u32 u3cts;
+ u32 u4rx;
+ u32 u4cts;
+ u32 u5rx;
+ u32 u5cts;
+ u32 u6rx;
+ u32 u6cts;
+ u32 unused4;
+ u32 sdi1;
+ u32 ss1;
+ u32 unused5;
+ u32 sdi2;
+ u32 ss2;
+ u32 unused6;
+ u32 sdi3;
+ u32 ss3;
+ u32 unused7;
+ u32 sdi4;
+ u32 ss4;
+ u32 unused8;
+ u32 sdi5;
+ u32 ss5;
+ u32 unused9;
+ u32 sdi6;
+ u32 ss6;
+ u32 c1rx;
+ u32 c2rx;
+ u32 refclki1;
+ u32 refclki2;
+ u32 refclki3;
+ u32 refclki4;
+};
+
+/* output mux register offset */
+#define PPS_OUT(__port, __pin) \
+ (((__port) * PIC32_PINS_PER
[U-Boot] [PATCH v3 03/14] drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.
Signed-off-by: Purna Chandra Mandal
Reviewed-by: Simon Glass
---
Changes in v3:
- rename clk-pic32.c to clk_pic32.c
- update clock binding documentation
- replace pic32_ioremap() with ioremap()
- separate MPLL initialization constants
Changes in v2:
- add mpll get clock rate
.../clock/microchip,pic32-clock.txt| 33 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk_pic32.c| 433 +
include/dt-bindings/clock/microchip,clock.h| 29 ++
4 files changed, 496 insertions(+)
create mode 100644 doc/device-tree-bindings/clock/microchip,pic32-clock.txt
create mode 100644 drivers/clk/clk_pic32.c
create mode 100644 include/dt-bindings/clock/microchip,clock.h
diff --git a/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
new file mode 100644
index 000..02e5ce4
--- /dev/null
+++ b/doc/device-tree-bindings/clock/microchip,pic32-clock.txt
@@ -0,0 +1,33 @@
+* Microchip PIC32 Clock and Oscillator
+
+Microchip PIC32 clock tree consists of few oscillators, PLLs,
+multiplexers and few divider modules capable of supplying clocks
+to various controllers within SoC and also to off-chip.
+
+PIC32 clock controller output is defined by indices as defined
+in [0]
+
+[0] include/dt-bindings/clock/microchip,clock.h
+
+Required Properties:
+- compatible: should be "microchip,pic32mzda_clk"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+
+Example: Clock controller node:
+
+ clock: clk@1f801200 {
+ compatible = "microchip,pic32mzda_clk";
+ reg = <0x1f801200 0x1000>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+controller:
+
+ uart1: serial@1f822000 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <0xbf822000 0x50>;
+ interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock PB2CLK>;
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4a6a4a8..adda769 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
new file mode 100644
index 000..bb0a1cf
--- /dev/null
+++ b/drivers/clk/clk_pic32.c
@@ -0,0 +1,433 @@
+/*
+ * Copyright (C) 2015 Purna Chandra Mandal
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Primary oscillator */
+#define SYS_POSC_CLK_HZ2400
+
+/* FRC clk rate */
+#define SYS_FRC_CLK_HZ 800
+
+/* Clock Registers */
+#define OSCCON 0x
+#define OSCTUNE0x0010
+#define SPLLCON0x0020
+#define REFO1CON 0x0080
+#define REFO1TRIM 0x0090
+#define PB1DIV 0x0140
+
+/* SPLL */
+#define ICLK_MASK 0x0080
+#define PLLIDIV_MASK 0x0007
+#define PLLODIV_MASK 0x0007
+#define CUROSC_MASK0x0007
+#define PLLMUL_MASK0x007F
+#define FRCDIV_MASK0x0007
+
+/* PBCLK */
+#define PBDIV_MASK 0x0007
+
+/* SYSCLK MUX */
+#define SCLK_SRC_FRC1 0
+#define SCLK_SRC_SPLL 1
+#define SCLK_SRC_POSC 2
+#define SCLK_SRC_FRC2 7
+
+/* Reference Oscillator Control Reg fields */
+#define REFO_SEL_MASK 0x0f
+#define REFO_SEL_SHIFT 0
+#define REFO_ACTIVEBIT(8)
+#define REFO_DIVSW_EN BIT(9)
+#define REFO_OEBIT(12)
+#define REFO_ONBIT(15)
+#define REFO_DIV_SHIFT 16
+#define REFO_DIV_MASK 0x7fff
+
+/* Reference Oscillator Trim Register Fields */
+#define REFO_TRIM_REG 0x10
+#define REFO_TRIM_MASK 0x1ff
+#define REFO_TRIM_SHIFT23
+#define REFO_TRIM_MAX 511
+
+#define ROCLK_SRC_SCLK 0x0
+#define ROCLK_SRC_SPLL 0x7
+#define ROCLK_SRC_ROCLKI 0x8
+
+/* Memory PLL */
+#define MPLL_IDIV 0x3f
+#define MPLL_MULT 0xff
+#define MPLL_ODIV1 0x7
+#define MPLL_ODIV2 0x7
+#define MPLL_VREG_RDY BIT(23)
+#define MPLL_RDY BIT(31)
+#define MPLL_IDIV_SHIFT0
+#define MPLL_MULT_SHIFT8
+#define MPLL_ODIV1_SHIFT 24
+#define MPLL_ODIV2_SHIFT 27
+#define MPLL_IDIV_INIT 0x03
+#define MPLL_MULT_INIT 0x32
+#define MPLL_ODIV1_INIT0x02
+#define MPLL_ODIV2_INIT0x01
+
+struct pic32_clk_priv {
+ void __iomem *iobase;
+ void __iomem *syscfg_
[U-Boot] [PATCH v3 01/14] MIPS: initialize board_init_f() argument to zero.
Signed-off-by: Purna Chandra Mandal --- Changes in v3: None Changes in v2: None arch/mips/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index e95cdca..35d9650 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -185,6 +185,8 @@ reset: PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset sw sp, 0(t0) #endif + /* Initialize args to zero */ + movea0, zero PTR_LA t9, board_init_f jr t9 -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 02/14] MIPS: initial infrastructure for Microchip PIC32 architecture
Create initial directory, Kconfigs needed for PIC32 architecture
support. Also add PIC32 specific register definition required for drivers.
Signed-off-by: Purna Chandra Mandal
---
Changes in v3:
- drop empty choices in mach-pic32/Kconfig
- add pic32_get_syscfg_base() for device-config registers
Changes in v2:
- move PIC32 specific headers to arch/mips/mach-pic32/include/mach/
- define register-base as physical address
- drop CONFIG_PIC32_SUPPORTS_FDT_BOOT
arch/mips/Kconfig | 6 +++
arch/mips/Makefile| 1 +
arch/mips/mach-pic32/Kconfig | 7 +++
arch/mips/mach-pic32/Makefile | 7 +++
arch/mips/mach-pic32/cpu.c| 13 ++
arch/mips/mach-pic32/include/mach/pic32.h | 76 +++
6 files changed, 110 insertions(+)
create mode 100644 arch/mips/mach-pic32/Kconfig
create mode 100644 arch/mips/mach-pic32/Makefile
create mode 100644 arch/mips/mach-pic32/cpu.c
create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1b39c4c..380ed81 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -54,6 +54,11 @@ config TARGET_PB1X00
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select MIPS_TUNE_4KC
+config MACH_PIC32
+ bool "Support Microchip PIC32"
+ select OF_CONTROL
+ select DM
+
endchoice
source "board/dbau1x00/Kconfig"
@@ -61,6 +66,7 @@ source "board/imgtec/malta/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+source "arch/mips/mach-pic32/Kconfig"
if MIPS
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 2133e7e..aec5a15 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
+machine-$(CONFIG_MACH_PIC32) += pic32
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
libs-y += $(machdirs)
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
new file mode 100644
index 000..c1cc5e3
--- /dev/null
+++ b/arch/mips/mach-pic32/Kconfig
@@ -0,0 +1,7 @@
+menu "Microchip PIC32 platforms"
+ depends on MACH_PIC32
+
+config SYS_SOC
+ default "none"
+
+endmenu
diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
new file mode 100644
index 000..cb42607
--- /dev/null
+++ b/arch/mips/mach-pic32/Makefile
@@ -0,0 +1,7 @@
+# (C) Copyright 2015
+# Purna Chandra Mandal, purna.man...@microchip.com.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpu.o
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
new file mode 100644
index 000..58fd3ab
--- /dev/null
+++ b/arch/mips/mach-pic32/cpu.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2015
+ * Purna Chandra Mandal
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+#include
+
+phys_size_t initdram(int board_type)
+{
+ return 0;
+}
diff --git a/arch/mips/mach-pic32/include/mach/pic32.h
b/arch/mips/mach-pic32/include/mach/pic32.h
new file mode 100644
index 000..7e41810
--- /dev/null
+++ b/arch/mips/mach-pic32/include/mach/pic32.h
@@ -0,0 +1,76 @@
+/*
+ * (c) 2015 Paul Thacker
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ */
+
+#ifndef __PIC32_REGS_H__
+#define __PIC32_REGS_H__
+
+#include
+
+/* System Configuration */
+#define PIC32_CFG_BASE 0x1f80
+
+/* System config register offsets */
+#define CFGCON 0x
+#define DEVID 0x0020
+#define SYSKEY 0x0030
+#define PMD1 0x0040
+#define PMD7 0x00a0
+#define CFGEBIA0x00c0
+#define CFGEBIC0x00d0
+#define CFGPG 0x00e0
+#define CFGMPLL0x0100
+
+/* Non Volatile Memory (NOR flash) */
+#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600)
+/* Oscillator Configuration */
+#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200)
+/* Peripheral Pin Select Input */
+#define PPS_IN_BASE0x1f801400
+/* Peripheral Pin Select Output */
+#define PPS_OUT_BASE 0x1f801500
+/* Pin Config */
+#define PINCTRL_BASE 0x1f86
+
+/* USB Core */
+#define PIC32_USB_CORE_BASE0x1f8e3000
+#define PIC32_USB_CTRL_BASE0x1f884000
+
+/* SPI1-SPI6 */
+#define PIC32_SPI1_BASE0x1f821000
+
+/* Prefetch Module */
+#define PREFETCH_BASE 0x1f8e
+
+/* DDR2 Controller */
+#define PIC32_DDR2C_BASE 0x1f8e8000
+
+/* DDR2 PHY */
+#define PIC32_DDR2P_BASE 0x1f8e9100
+
+/* EBI */
+#define PIC32_EBI_BASE 0x1f8e1000
+
+/* SQI */
+#define PIC32_SQI_BASE 0x1f8e2000
+
+struct pic32_reg_atomic {
+ u32 raw;
+ u32 clr;
+ u32 set;
+ u32 inv;
+};
+
+#define _CLR_OFFSET0x04
+#define _SET_OFFSET0x08
+#define _INV_OFFSET0x0c
+
+static inline void __iomem *pic32_get_syscfg_base(void)
+{
+ return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE);
+}
+
+#
[U-Boot] [PATCH] imx: mx6/7 define CONFIG_SYS_VSNPRINTF
From: Peng Fan Define CONFIG_SYS_VSNPRINTF to use snprintf. If not define CONFIG_SYS_VSNPRINTF, snprintf is sprintf. Report by Coverity: pass string init_val of unknown size to sprintf Signed-off-by: Peng Fan Cc: Peter Robinson Cc: Fabio Estevam Cc: Adrian Alonso Cc: Stefano Babic --- include/configs/mx6_common.h | 4 include/configs/mx7_common.h | 4 2 files changed, 8 insertions(+) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 1fd7ce3..1a470a4 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -17,6 +17,10 @@ #ifndef __MX6_COMMON_H #define __MX6_COMMON_H +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_VSNPRINTF +#endif + #ifndef CONFIG_MX6UL #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index d507fb4..505f6cc 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -13,6 +13,10 @@ #include #include +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_VSNPRINTF +#endif + #ifndef CONFIG_MX7 #define CONFIG_MX7 #endif -- 2.6.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] common: env_flags: fix loop condition when using env_flags_varaccess_mask
From: Peng Fan
We should use ARRAY_SIZE, but not sizeof. The size of
env_flags_varaccess_mask is 16bytes, but we only need 4 loops.
If using 16 as the end condition, we may access memory that
not belong to array env_flags_varaccess_mask.
Signed-off-by: Peng Fan
Cc: Joe Hershberger
Cc: York Sun
Cc: Simon Glass
Cc: Tom Rini
---
common/env_flags.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/env_flags.c b/common/env_flags.c
index 7719355..9c3aed1 100644
--- a/common/env_flags.c
+++ b/common/env_flags.c
@@ -152,7 +152,7 @@ enum env_flags_varaccess
env_flags_parse_varaccess_from_binflags(int binflags)
{
int i;
- for (i = 0; i < sizeof(env_flags_varaccess_mask); i++)
+ for (i = 0; i < ARRAY_SIZE(env_flags_varaccess_mask); i++)
if (env_flags_varaccess_mask[i] ==
(binflags & ENV_FLAGS_VARACCESS_BIN_MASK))
return (enum env_flags_varaccess)i;
--
2.6.2
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/8] Convert lpuart serial driver to driver model
Hi Bin, On 01/12/2016 12:21 PM, Bin Meng wrote: Hi Bhuvanchandra, On Tue, Jan 12, 2016 at 2:43 PM, Bhuvanchandra DV wrote: Hi Bin, On 01/12/2016 11:05 AM, Bin Meng wrote: Hi Bhuvanchandra, On Tue, Jan 12, 2016 at 12:28 PM, Bhuvanchandra DV wrote: - Convert lpuart driver to driver model and remove the legacy code. - Update Toradex Colibri VF50/VF61 serial support with driver model. - Update Freescale vf610twr serial support with driver model. - Update Freescale ls1021atwr serial support with driver model. - Update Phytec pcm052 serial support with driver model. - Tested the driver on Toradex Colibri VF50/VF61 hardware. - Compile checked board files for vf610twr, ls1021atwr and pcm052 since I don't have access to such hardware at my end. Reviewers and testers welcome! Bhuvanchandra DV (8): dm: lpuart: Add driver model support for the serial driver colibri_vf: Update enabling lpuart support with driver model arm: vf610twr: Add driver model support vf610twr: Update enabling lpuart with driver model arm: ls102xa: Add driver model support ls1021x: Update enabling lpuart with driver model arm: pcm052: Enable driver model support pcm052: Update enabling lpuart support with driver model arch/arm/include/asm/arch-ls102xa/serial.h | 16 arch/arm/include/asm/arch-vf610/serial.h | 16 board/freescale/ls1021atwr/ls1021atwr.c| 15 ++- board/freescale/vf610twr/vf610twr.c| 13 +++ board/phytec/pcm052/pcm052.c | 13 +++ board/toradex/colibri_vf/colibri_vf.c | 13 +++ configs/ls1021atwr_nor_lpuart_defconfig| 1 + configs/pcm052_defconfig | 1 + configs/vf610twr_defconfig | 1 + configs/vf610twr_nand_defconfig| 1 + drivers/serial/Kconfig | 6 ++ drivers/serial/serial_lpuart.c | 148 +++-- include/configs/colibri_vf.h | 6 +- include/configs/ls1021atwr.h | 1 + include/configs/pcm052.h | 6 +- include/configs/vf610twr.h | 6 +- 16 files changed, 180 insertions(+), 83 deletions(-) create mode 100644 arch/arm/include/asm/arch-ls102xa/serial.h create mode 100644 arch/arm/include/asm/arch-vf610/serial.h -- Please see existing patch series @ http://patchwork.ozlabs.org/patch/561855/. You can drop the ls102xa changes and rebase your patch series on top of that. Thanks! We are not aware of this patch set, sorry! about that. You want me to drop only the ls102xa changes? How about the changes/updates to the lpuart driver? should i update them with your device tree support stuff and rebase the remaining patch set along with your Signed-off-by tag ? Any suggestions ? I believe you can: - Drop the LPUART DM conversion patch in your series, which was already done I believe that the patch set[1] is now _only_ supporting device tree enabled boards, there are boards using lpuart which are not yet having device trees, boards like vf610twr and Phytec pcm052. Even with driver model enabled i guess these boards canont use lpuart via platform data with this patch set. I think it would be nice to have the support for both platform data and device tree so that we can use it with platform data via board files and device tree too. Since only few boards are using lpuart driver we can update the driver completly to driver model, drop the legacy code and update the boards. Seems the legacy code in lpuart driver is broken: drivers/serial/serial_lpuart.c:148:9: error: too few arguments to function '_lpuart_serial_tstc' I will test the patch set[1] atleast on Toradex Colibri VF50/VF61 h/w and will provide a detailed report of my observations. [1] http://patchwork.ozlabs.org/patch/561855/ - Drop the ls1021atwr changes, which was already done - Do the similar changes to all other boards in your series, by following ls1021atwr changes in my series - There is no need to add my SOB tag in your series as I was actually not doing anything :) Regards, Bin -- Best regards, Bhuvan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv3 4/4] igep00x0: UBIize
Hello Ladislav,
Am 11.01.2016 um 13:58 schrieb Ladislav Michl:
Hi Heiko,
On Mon, Jan 11, 2016 at 07:20:06AM +0100, Heiko Schocher wrote:
[...]
Could you seperate common changes in "common/*" and your special
board changes?
It is done bellow, just common/* part to start discussion...
;-)
Beside of that, this patch does not apply ...
Ah, igep00x0 part is based on top of this:
http://lists.denx.de/pipermail/u-boot/2016-January/240013.html
I silently hoped to be applied for 2016.01 release, but never mind :)
;-)
Ah, I added them to my automated build, and now it works again :-D
BTW: patch "[U-Boot,PATCHv2,2/5] igep00x0: Cleanup ethernet support"
has a checkpatch warning, search in
http://xeidos.ddns.net/buildbot/builders/smartweb_dfu/builds/43/steps/shell/logs/tbotlog
for "2016-01-12 07:47:08,369"
Now assumption is that once board switches to UBI, loading u-boot or kernel
from bare flash does not make a sense anymore, so with CONFIG_SPL_UBI
all that code in spl_nor.c (reevaluate?!), spl_nand.c and spl_onenand.c
is not used in favour of spl_ubi.c. As ubispl can load volumes by volume id
I thought about this change too, and I think your assumption is OK
here. Let us bring in this change, and if someone has other needs,
we have to look again at this place .. but I think, if switching to
use UBI, than it makes no sense to read in raw mode ...
Other opinions?
and not by name, it is bringing some inconsistencies with for example ubi
environment code, which is using volume names. Is it worth fixing?
It would be nice to have ... yes, if it is easy to do? Also we must
have a look at the codesize.
All that ubispl_info structure is board specific and there is not much left
besides initializing it. Also volumes can differ per board basis, so
providing common function is somewhat questionable. However here it is,
just to show how does it look like. Suggestions are very welcome as silence
around this part of patch is a bit suspicious ;-)
Questions are coming if there are users ;-)
I vote for bringing this in, and we will see, where we have to make
things more configurable ... some nitpicks below ...
commit f68d017a4d35bfac3cccd7c7f19ab1c2fe76d908
Author: Ladislav Michl
Date: Mon Jan 11 13:08:10 2016 +0100
spl: support loading from UBI volumes
Add simple support for loading from UBI volumes.
This is just a test and needs to be made configurable
Signed-off-by: Ladislav Michl
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 10a4589..e4535c4 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,10 +10,13 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
-obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+ifndef CONFIG_SPL_UBI
+obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
+endif
+obj-$(CONFIG_SPL_UBI) += spl_ubi.o
obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 6e6dee7..048a325 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -286,6 +286,18 @@ static int spl_load_image(u32 boot_device)
case BOOT_DEVICE_MMC2_2:
return spl_mmc_load_image(boot_device);
#endif
+#ifdef CONFIG_SPL_UBI
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_NAND:
+#endif
+#ifdef CONFIG_SPL_ONENAND_SUPPORT
+ case BOOT_DEVICE_ONENAND:
+#endif
+#ifdef CONFIG_SPL_NOR_SUPPORT
+ case BOOT_DEVICE_NOR:
+#endif
+ return spl_ubi_load_image(boot_device);
+#else
#ifdef CONFIG_SPL_NAND_SUPPORT
case BOOT_DEVICE_NAND:
return spl_nand_load_image();
@@ -298,6 +310,7 @@ static int spl_load_image(u32 boot_device)
case BOOT_DEVICE_NOR:
return spl_nor_load_image();
#endif
+#endif /* CONFIG_SPL_UBI */
#ifdef CONFIG_SPL_YMODEM_SUPPORT
case BOOT_DEVICE_UART:
return spl_ymodem_load_image();
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
new file mode 100644
index 000..38ddb57
--- /dev/null
+++ b/common/spl/spl_ubi.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016
+ * Ladislav Michl
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+int spl_ubi_load_image(u32 boot_device)
+{
+ int ret;
+ struct image_header *header;
+ struct ubispl_info info;
+ struct ubispl_load volumes[2];
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ if (boot_device == BOOT_DEVICE_NAND)
+ nand_init();
+#endif
+
+ /* TODO: Make it decently configurable */
+ info.ubi = (struct ubi_scan_info *)
+ (CONFIG_SYS_SPL_MALLOC_START + CONFIG_SYS_SPL_MALLOC_SIZE);
+ info.fastmap = 1;
+ info.read = nand_spl_read_block;
+
+ info.peb_offset = 4;
+ info.pe
[U-Boot] [PATCH] common: usb: fix checking condition
From: Peng Fan
We support max USB_MAXENDPOINTS, so need to use
"epno >= USB_MAXENDPOINTS", but not "epno > USB_MAXENDPOINTS".
If use ">", we may exceeds the array of if_desc->ep_desc.
Signed-off-by: Peng Fan
Cc: Simon Glass
Cc: Hans de Goede
Cc: Marek Vasut
Cc: Paul Kocialkowski
Cc: "Stefan Brüns"
Cc: Vincent Palatin
---
common/usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/usb.c b/common/usb.c
index 9f67cc1..c7b8b0e 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -456,7 +456,7 @@ static int usb_parse_config(struct usb_device *dev,
}
epno = dev->config.if_desc[ifno].no_of_ep;
if_desc = &dev->config.if_desc[ifno];
- if (epno > USB_MAXENDPOINTS) {
+ if (epno >= USB_MAXENDPOINTS) {
printf("Interface %d has too many endpoints!\n",
if_desc->desc.bInterfaceNumber);
return -EINVAL;
--
2.6.2
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