Re: [U-Boot] [PATCH] iocon / bamboo: Drop CONFIG_SYS_LONGHELP
2016-01-19 19:01 GMT+01:00 Tom Rini : > The iocon and bamboo boards are often on the verge of, or going over, > their allowed size limits depending on toolchain used. If we turn off > CONFIG_SYS_LONGHELP we can gain approximately 14KiB back. > > Cc: Dirk Eibach > Cc: Stefan Roese > Signed-off-by: Tom Rini Acked-by: Dirk Eibach Cheers Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/14] dm: video: Introduce initial driver-model video support
Hi Simon, On Mon, 18 Jan 2016 19:57:53 -0700 Simon Glass wrote: ... > >> Changes in v2: > >> - Fix Ebabling typo in comment > >> - Remove duplicated @fb_size line in common > >> - Fix comment for video_get_ysize() > >> - Fix reference to \n which should be \b > >> - Fix 'withthe' typo in comment > >> - Fix 'resolutino' typo in comment > > If this looks OK, please let me know if you plan to pick this up, > otherwise I'll bring it via DM. There are some dependent patches in > dm/master, but I can send a pull request for those. I can apply this series when the dependent patches in dm/master are merged to u-boot/master. You can merge this series via DM if you like, no objection from my side. Thanks, Anatolij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board
This patch adds support for the Armada XP (MV78260) based theadorable board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR, LCD and SATA (SSD) interfaces / devices. Two defconfigs are added: theadorable_defconfig: The production U-Boot version with a stripped down drivers and feature list. This removes networking, USB and PCI support. theadorable_debug_defconfig: The debugging / testing U-Boot version with full support for all drivers. Signed-off-by: Stefan Roese Cc: Luka Perkov --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/armada-xp-theadorable.dts | 143 +++ arch/arm/mach-mvebu/Kconfig| 6 ++ board/theadorable/MAINTAINERS | 7 ++ board/theadorable/Makefile | 7 ++ board/theadorable/kwbimage.cfg | 12 +++ board/theadorable/theadorable.c| 171 + configs/theadorable_debug_defconfig| 28 ++ configs/theadorable_defconfig | 26 + include/configs/theadorable.h | 170 10 files changed, 572 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/armada-xp-theadorable.dts create mode 100644 board/theadorable/MAINTAINERS create mode 100644 board/theadorable/Makefile create mode 100644 board/theadorable/kwbimage.cfg create mode 100644 board/theadorable/theadorable.c create mode 100644 configs/theadorable_debug_defconfig create mode 100644 configs/theadorable_defconfig create mode 100644 include/configs/theadorable.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e4f8aae..9b933ac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-gp.dtb \ armada-xp-gp.dtb\ armada-xp-maxbcm.dtb\ - armada-xp-synology-ds414.dtb + armada-xp-synology-ds414.dtb\ + armada-xp-theadorable.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-ph1-ld4-ref.dtb \ diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts new file mode 100644 index 000..cf1be2a --- /dev/null +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -0,0 +1,143 @@ +/* + * Device Tree file for Marvell Armada XP theadorable board + * + * Copyright (C) 2013-2014 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf100 (instead of the default + * 0xd000). The 0xf100 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ +
[U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller
This patch adds basic support for the LCD controller of the Marvell
Armada XP SoC.
An AXP based custom board port will be added later, to use this
driver to display a splash screen via the bmp command later.
Signed-off-by: Stefan Roese
Cc: Anatolij Gustschin
Cc: Luka Perkov
---
arch/arm/mach-mvebu/include/mach/cpu.h | 13 +
arch/arm/mach-mvebu/include/mach/soc.h | 1 +
drivers/video/Kconfig | 7 +
drivers/video/Makefile | 1 +
drivers/video/mvebu_lcd.c | 532 +
5 files changed, 554 insertions(+)
create mode 100644 drivers/video/mvebu_lcd.c
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
b/arch/arm/mach-mvebu/include/mach/cpu.h
index 47f45c1..017d55f 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -145,5 +145,18 @@ int serdes_phy_config(void);
* drivers/ddr/marvell
*/
int ddr3_init(void);
+
+struct mvebu_lcd_info {
+ u32 fb_base;
+ int x_res;
+ int y_res;
+ int x_fp; /* frontporch */
+ int y_fp;
+ int x_bp; /* backporch */
+ int y_bp;
+};
+
+int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
+
#endif /* __ASSEMBLY__ */
#endif /* _MVEBU_CPU_H */
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index cb216bc..b317940 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -67,6 +67,7 @@
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE(MVEBU_REGISTER(0xd))
#define MVEBU_SDIO_BASE(MVEBU_REGISTER(0xd8000))
+#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe))
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index caf1efc..64dbf1f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -247,6 +247,13 @@ config DISPLAY_PORT
to drive LCD panels. This framework provides support for enabling
these displays where supported by the video hardware.
+config VIDEO_MVEBU
+ bool "Armada XP LCD controller"
+ default n
+ ---help---
+ Support for the LCD controller integrated in the Marvell
+ Armada XP SoC.
+
config VIDEO_TEGRA124
bool "Enable video support on Tegra124"
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index e85fd8a..64cb61c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
diff --git a/drivers/video/mvebu_lcd.c b/drivers/video/mvebu_lcd.c
new file mode 100644
index 000..86dae52
--- /dev/null
+++ b/drivers/video/mvebu_lcd.c
@@ -0,0 +1,532 @@
+/*
+ * Video driver for Marvell Armada XP SoC
+ *
+ * Initialization of LCD interface and setup of SPLASH screen image
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MVEBU_LCD_WIN_CONTROL(w)(MVEBU_LCD_BASE + 0xf000 + ((w) << 4))
+#define MVEBU_LCD_WIN_BASE(w) (MVEBU_LCD_BASE + 0xf004 + ((w) << 4))
+#define MVEBU_LCD_WIN_REMAP(w) (MVEBU_LCD_BASE + 0xf00c + ((w) << 4))
+
+#define MVEBU_LCD_CFG_DMA_START_ADDR_0 (MVEBU_LCD_BASE + 0x00cc)
+#define MVEBU_LCD_CFG_DMA_START_ADDR_1 (MVEBU_LCD_BASE + 0x00dc)
+
+#define MVEBU_LCD_CFG_GRA_START_ADDR0 (MVEBU_LCD_BASE + 0x00f4)
+#define MVEBU_LCD_CFG_GRA_START_ADDR1 (MVEBU_LCD_BASE + 0x00f8)
+#define MVEBU_LCD_CFG_GRA_PITCH(MVEBU_LCD_BASE + 0x00fc)
+#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN(MVEBU_LCD_BASE + 0x0100)
+#define MVEBU_LCD_SPU_GRA_HPXL_VLN (MVEBU_LCD_BASE + 0x0104)
+#define MVEBU_LCD_SPU_GZM_HPXL_VLN (MVEBU_LCD_BASE + 0x0108)
+#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN(MVEBU_LCD_BASE + 0x010c)
+#define MVEBU_LCD_SPU_HWC_HPXL_VLN (MVEBU_LCD_BASE + 0x0110)
+#define MVEBU_LCD_SPUT_V_H_TOTAL (MVEBU_LCD_BASE + 0x0114)
+#define MVEBU_LCD_SPU_V_H_ACTIVE (MVEBU_LCD_BASE + 0x0118)
+#define MVEBU_LCD_SPU_H_PORCH (MVEBU_LCD_BASE + 0x011c)
+#define MVEBU_LCD_SPU_V_PORCH (MVEBU_LCD_BASE + 0x0120)
+#define MVEBU_LCD_SPU_BLANKCOLOR (MVEBU_LCD_BASE + 0x0124)
+#define MVEBU_LCD_SPU_ALPHA_COLOR1 (MVEBU_LCD_BASE + 0x0128)
+#define MVEBU_LCD_SPU_ALPHA_COLOR2 (MVEBU_LCD_BASE + 0x012c)
+#define MVEBU_LCD_SPU_COLORKEY_Y (MVEBU_LCD_BASE + 0x0130)
+#define MVEBU_LCD_SPU_COLORKEY_U (MVEBU_LCD_BASE + 0x0134)
+#defi
[U-Boot] [PATCH 1/2] driver: net: ldpaa_eth: Add support of PHY framework
This patch integrate DPAA2 ethernet driver existing PHY framework.
Call phy_connect and phy_config as per available DPMAC id defined
in SerDes Protcol.
Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
---
drivers/net/ldpaa_eth/ldpaa_eth.c | 116 --
1 file changed, 85 insertions(+), 31 deletions(-)
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c
b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 3857122..0a82bc6 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -14,15 +14,34 @@
#include
#include
+#include
#include "ldpaa_eth.h"
-#undef CONFIG_PHYLIB
+#ifdef CONFIG_PHYLIB
static int init_phy(struct eth_device *dev)
{
- /*TODO for external PHY */
+ struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
+ struct phy_device *phydev = NULL;
+ struct mii_dev *bus;
+
+ bus = wriop_get_mdio(priv->dpmac_id);
+ if (bus == NULL)
+ return 0;
+
+ phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id),
+dev, wriop_get_enet_if(priv->dpmac_id));
+ if (!phydev) {
+ printf("Failed to connect\n");
+ return -1;
+ }
+
+ priv->phydev = phydev;
+
+ phy_config(phydev);
return 0;
}
+#endif
#ifdef DEBUG
static void ldpaa_eth_get_dpni_counter(void)
@@ -303,7 +322,9 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t
*bd)
#ifdef DEBUG
struct dpni_link_state link_state;
#endif
- int err;
+ int err = 0;
+ struct mii_dev *bus;
+ phy_interface_t enet_if;
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
@@ -317,11 +338,48 @@ static int ldpaa_eth_open(struct eth_device *net_dev,
bd_t *bd)
printf("ERROR (DPL is deployed. No device available)\n");
return -ENODEV;
}
+
/* DPMAC initialization */
err = ldpaa_dpmac_setup(priv);
if (err < 0)
goto err_dpmac_setup;
+#ifdef CONFIG_PHYLIB
+ if (priv->phydev)
+ err = phy_startup(priv->phydev);
+ if (err) {
+ printf("%s: Could not initialize\n",
+ priv->phydev->dev->name);
+ goto err_dpamc_bind;
+ }
+#else
+ priv->phydev = (struct phy_device *)malloc(sizeof(struct phy_device));
+ memset(priv->phydev, 0, sizeof(struct phy_device));
+
+ priv->phydev->speed = SPEED_1000;
+ priv->phydev->link = 1;
+ priv->phydev->duplex = DUPLEX_FULL;
+#endif
+
+ bus = wriop_get_mdio(priv->dpmac_id);
+ enet_if = wriop_get_enet_if(priv->dpmac_id);
+ if ((bus == NULL) &&
+ (enet_if == PHY_INTERFACE_MODE_XGMII)) {
+ priv->phydev = (struct phy_device *)
+ malloc(sizeof(struct phy_device));
+ memset(priv->phydev, 0, sizeof(struct phy_device));
+
+ priv->phydev->speed = SPEED_1;
+ priv->phydev->link = 1;
+ priv->phydev->duplex = DUPLEX_FULL;
+ }
+
+ if (!priv->phydev->link) {
+ printf("%s: No link.\n", priv->phydev->dev->name);
+ err = -1;
+ goto err_dpamc_bind;
+ }
+
/* DPMAC binding DPNI */
err = ldpaa_dpmac_bind(priv);
if (err)
@@ -348,28 +406,24 @@ static int ldpaa_eth_open(struct eth_device *net_dev,
bd_t *bd)
return err;
}
-#ifdef CONFIG_PHYLIB
- /* TODO Check this path */
- err = phy_startup(priv->phydev);
- if (err) {
- printf("%s: Could not initialize\n", priv->phydev->dev->name);
- return err;
- }
-#else
- priv->phydev->speed = SPEED_1000;
- priv->phydev->link = 1;
- priv->phydev->duplex = DUPLEX_FULL;
-#endif
-
err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
printf("dpni_enable() failed\n");
return err;
}
- dpmac_link_state.rate = SPEED_1000;
- dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG;
- dpmac_link_state.up = 1;
+ dpmac_link_state.rate = priv->phydev->speed;
+
+ if (priv->phydev->autoneg == AUTONEG_DISABLE)
+ dpmac_link_state.options &= ~DPMAC_LINK_OPT_AUTONEG;
+ else
+ dpmac_link_state.options |= DPMAC_LINK_OPT_AUTONEG;
+
+ if (priv->phydev->duplex == DUPLEX_HALF)
+ dpmac_link_state.options |= DPMAC_LINK_OPT_HALF_DUPLEX;
+
+ dpmac_link_state.up = priv->phydev->link;
+
err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
priv->dpmac_handle, &dpmac_link_state);
if (err < 0) {
@@ -407,10 +461,7 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t
*bd)
goto err_qdid;
[U-Boot] [PATCH ] board: ls2080a: Add "mcinitcmd" env for MC & DPL deployment
From: Pratiyush Mohan Srivastava
Environment variable mcinitcmd is defined to initiate MC and DPL deployment
from the location where it is stored(NOR, NAND, SD, SATA, USB)during u-boot
booting.If this variable is not defined then macro MC_BOOT_ENV_VAR will be null
and
MC will not be booted and DPL will not be applied during U-boot booting.
Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
---
arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 | 29 ++
board/freescale/ls2080aqds/eth.c | 5 +
board/freescale/ls2080ardb/eth_ls2080rdb.c | 5 +
3 files changed, 39 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
index f9323c1..da5e052 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@@ -121,6 +121,35 @@ mcboottimeout: MC boot timeout in milliseconds. If
this variable is not defined
mcmemsize: MC DRAM block size. If this variable is not defined, the value
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+mcinitcmd: This environment variable is defined to initiate MC and DPL
deployment
+ from the location where it is stored(NOR, NAND, SD, SATA,
USB)during
+ u-boot booting.If this variable is not defined then
MC_BOOT_ENV_VAR
+ will be null and MC will not be booted and DPL will not be
applied
+ during U-boot booting.However the MC, DPC and DPL can be
applied from
+ console independently.
+ The variable needs to be set from the console once and then on
+ rebooting the parameters set in the varible will automatically
be
+ executed. The commmand is demostrated taking an example of mc
boot
+ using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR
flash:
+
+ cp.b 0xa000 0x58030 $filesize
+ cp.b 0x8000 0x58080 $filesize
+ cp.b 0x9000 0x58070 $filesize
+
+ setenv mcinitcmd 'fsl_mc start mc 0x58030 0x58080'
+
+ If only linux is to be booted then the mcinitcmd environment
should be set as
+
+ setenv mcinitcmd 'fsl_mc start mc 0x58030
0x58080;fsl_mc apply DPL 0x58070'
+
+ Here the addresses 0xa000, 0x8000, 0x8000 are of
DDR to where
+ MC binary, DPC binary and DPL binary are stored and
0x58030, 0x58080
+ and 0x58070 are addresses in NOR where these are copied. It
is to be
+ noted that these addresses in 'fsl_mc start mc 0x58030
0x58080;fsl_mc apply DPL 0x58070'
+ can be replaced with the addresses of DDR to
+ which these will be copied in case of these binaries being
stored in other
+ devices like SATA, USB, NAND, SD etc.
+
Booting from NAND
---
Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 5b9c2d1..db9de77 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -20,6 +20,7 @@
#include "ls2080aqds_qixis.h"
+#define MC_BOOT_ENV_VAR "mcinitcmd"
#ifdef CONFIG_FSL_MC_ENET
/* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
@@ -714,6 +715,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
int board_eth_init(bd_t *bis)
{
int error;
+ char *mc_boot_env_var;
#ifdef CONFIG_FSL_MC_ENET
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@@ -781,6 +783,9 @@ int board_eth_init(bd_t *bis)
}
}
+ mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c
b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 58ea746..758bb3d 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -20,9 +20,11 @@
DECLARE_GLOBAL_DATA_PTR;
+#define MC_BOOT_ENV_VAR "mcinitcmd"
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
+ char *mc_boot_env_var;
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
@@ -89,6 +91,9 @@ int board_eth_init(bd_t *bis)
}
}
+ mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
--
1.9.1
___
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U-Boot@lis
[U-Boot] [PATCH] armv8/ls1043a: Implement workaround for erratum A009660
From: Mingkai Hu
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..485f5cd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -210,6 +210,18 @@ static void erratum_a009929(void)
#endif
}
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+ u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -232,6 +244,7 @@ void fsl_lsch2_early_init_f(void)
/* Erratum */
erratum_a009929();
+ erratum_a009660();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113d..66399b2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -167,6 +167,7 @@
#define GICC_BASE 0x01402000
#define CONFIG_SYS_FSL_ERRATUM_A009929
+#define CONFIG_SYS_FSL_ERRATUM_A009660
#else
#error SoC not defined
#endif
--
2.1.0.27.g96db324
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Re: [U-Boot] [PATCH 2/4] armv8/ls1043aqds: Add lpuart defconfig
Hi: Bin, Could you tell me which tree your patches have been merged into ? Regards Wenbin Song -Original Message- From: Bin Meng [mailto:bmeng...@gmail.com] Sent: Tuesday, January 19, 2016 4:03 PM To: Wenbin Song Cc: York Sun ; Mingkai Hu ; Qianyu Gong ; Shaohui Xie ; U-Boot Mailing List Subject: Re: [U-Boot] [PATCH 2/4] armv8/ls1043aqds: Add lpuart defconfig Hi Wenbin, On Tue, Jan 19, 2016 at 2:48 PM, Wenbin Song wrote: > --- Please include a commit message and SoB here. > configs/ls1043aqds_lpuart_defconfig | 8 > 1 file changed, 8 insertions(+) > create mode 100644 configs/ls1043aqds_lpuart_defconfig > > diff --git a/configs/ls1043aqds_lpuart_defconfig > b/configs/ls1043aqds_lpuart_defconfig > new file mode 100644 > index 000..ca06abe > --- /dev/null > +++ b/configs/ls1043aqds_lpuart_defconfig > @@ -0,0 +1,8 @@ > +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" > +CONFIG_ARM=y > +CONFIG_TARGET_LS1043AQDS=y > +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds" > +CONFIG_OF_CONTROL=y > +CONFIG_DM=y > +CONFIG_SPI_FLASH=y > +CONFIG_DM_SPI=y > -- Please use the driver model LPUART driver in this series (http://patchwork.ozlabs.org/patch/567250/). Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 2/2] usb: eth: add Realtek RTL8152B/RTL8153 DRIVER
This patch adds driver support for the Realtek RTL8152B/RTL8153 USB
network adapters.
Signed-off-by: Ted Chen
[swarren, fixed a few compiler warnings]
[swarren, with permission, converted license header to SPDX]
[swarren, removed printf() spew during probe()]
Signed-off-by: Stephen Warren
---
drivers/usb/eth/Makefile|1 +
drivers/usb/eth/r8152.c | 1456 +++
drivers/usb/eth/r8152.h | 631 +++
drivers/usb/eth/r8152_fw.c | 980 +
drivers/usb/eth/usb_ether.c |7 +
include/usb_ether.h |6 +
6 files changed, 3081 insertions(+)
create mode 100644 drivers/usb/eth/r8152.c
create mode 100644 drivers/usb/eth/r8152.h
create mode 100644 drivers/usb/eth/r8152_fw.c
Changes for v2: Modified by Marek's comments.
- Remove pattern informations.
- Don't allocate & free when read/write register.
- relpace udelay to mdelay.
- pull firmware into global variable.
- code review.
Changes for v3: Modified by Marek's and Joe's comments.
- Remove driver version informations.
- separate firmware code to individual file.
- split extensive defines to r8152.h.
- code review.
Changes for v4: Modified by Marek's comments.
- remove the redundant code in generic_ocp_read and generic_ocp_write.
- remove redundant typecasting.
- collect the codes of busy waiting to rtl8152_reinit_ll and rtl8152_nic_reset.
- use ARRAY_SIZE() to avoid having 0x00 as a terminating entry of r8152_dongles.
- using if (!ep_in_found && (ep_addr & USB_DIR_IN)) ... to replace old version.
- code review.
Changes for v5: Modified by Marek's comments.
- add r8152_wait_for_bit to replace busy wait.
- change the name of patch4 to r8152b_set_dq_desc.
- add r8152_versions to store the hw's version.
diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
index c92d2b0..4c44efc 100644
--- a/drivers/usb/eth/Makefile
+++ b/drivers/usb/eth/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o
obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
+obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o r8152_fw.o
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
new file mode 100644
index 000..325b70c
--- /dev/null
+++ b/drivers/usb/eth/r8152.c
@@ -0,0 +1,1456 @@
+/*
+ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "usb_ether.h"
+#include "r8152.h"
+
+/* local vars */
+static int curr_eth_dev; /* index for name of next device detected */
+
+struct r8152_dongle {
+ unsigned short vendor;
+ unsigned short product;
+};
+
+struct r8152_version {
+ unsigned short tcr;
+ unsigned short version;
+ bool gmii;
+};
+
+static const struct r8152_dongle const r8152_dongles[] = {
+ /* Realtek */
+ { 0x0bda, 0x8050 },
+ { 0x0bda, 0x8152 },
+ { 0x0bda, 0x8153 },
+
+ /* Samsung */
+ { 0x04e8, 0xa101 },
+
+ /* Lenovo */
+ { 0x17ef, 0x304f },
+ { 0x17ef, 0x3052 },
+ { 0x17ef, 0x3054 },
+ { 0x17ef, 0x3057 },
+ { 0x17ef, 0x7205 },
+ { 0x17ef, 0x720a },
+ { 0x17ef, 0x720b },
+ { 0x17ef, 0x720c },
+
+ /* TP-LINK */
+ { 0x2357, 0x0601 },
+
+ /* Nvidia */
+ { 0x0955, 0x09ff },
+};
+
+static const struct r8152_version const r8152_versions[] = {
+ { 0x4c00, RTL_VER_01, 0 },
+ { 0x4c10, RTL_VER_02, 0 },
+ { 0x5c00, RTL_VER_03, 1 },
+ { 0x5c10, RTL_VER_04, 1 },
+ { 0x5c20, RTL_VER_05, 1 },
+ { 0x5c30, RTL_VER_06, 1 },
+ { 0x4800, RTL_VER_07, 0 },
+};
+
+static
+int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
+{
+ return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
+ RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
+ value, index, data, size, 500);
+}
+
+static
+int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
+{
+ return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
+ RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
+ value, index, data, size, 500);
+}
+
+int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
+void *data, u16 type)
+{
+ u16 burst_size = 64;
+ int ret;
+ int txsize;
+
+ /* both size and index must be 4 bytes align */
+ if ((size & 3) || !size || (index & 3) || !data)
+ return -EINVAL;
+
+ if (index + size > 0x)
+ return -EINVAL;
+
+ while (size) {
+ txsize = min(size, burst_size);
+ ret = get_registers(tp, index, type, txsize, data);
+ if (ret < 0)
+
[U-Boot] [PATCH] driver: net: fsl-mc: Update print to reflect correct string
From: Prabhakar Kushwaha
Update printf with dpbp_exit to match with previous function call.
Signed-off-by: Itai Katz
Signed-off-by: Prabhakar Kushwaha
---
drivers/net/fsl-mc/mc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 6269dab..b5eafd2 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -1099,7 +1099,7 @@ int fsl_mc_ldpaa_exit(bd_t *bd)
err = dpbp_exit();
if (err < 0) {
- printf("dpni_exit() failed: %d\n", err);
+ printf("dpbp_exit() failed: %d\n", err);
goto err;
}
--
1.9.1
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[U-Boot] [PATCH 2/2] armv8: ls2085a: Remove phy configuration from QDS and RDB
From: Prabhakar Kushwaha
As phy_connect and phy_config are being called from DPAA2 driver.
Remove calling of mentioned function from board file.
Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
---
board/freescale/ls2080aqds/eth.c | 25 ---
board/freescale/ls2080ardb/eth_ls2080rdb.c | 39 --
2 files changed, 64 deletions(-)
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index ebc9d47..5499af6 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -548,12 +548,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 2:
/* Slot housing a SGMII riser card? */
@@ -562,12 +556,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
bus = mii_dev_for_muxval(EMI1_SLOT2);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;
@@ -606,12 +594,6 @@ serdes2:
dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
bus = mii_dev_for_muxval(EMI1_SLOT4);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 5:
break;
@@ -679,13 +661,6 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
-
- phy_config(dpmac_info[dpmac_id].phydev);
break;
case 3:
break;
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c
b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index db50e4e..58ea746 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -20,42 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int load_firmware_cortina(struct phy_device *phy_dev)
-{
- if (phy_dev->drv->config)
- return phy_dev->drv->config(phy_dev);
-
- return 0;
-}
-
-void load_phy_firmware(void)
-{
- int i;
- u8 phy_addr;
- struct phy_device *phy_dev;
- struct mii_dev *dev;
- phy_interface_t interface;
-
- /*Initialize and upload firmware for all the PHYs*/
- for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
- interface = wriop_get_enet_if(i);
- if (interface == PHY_INTERFACE_MODE_XGMII) {
- dev = wriop_get_mdio(i);
- phy_addr = wriop_get_phy_address(i);
- phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
- interface);
- if (!phy_dev) {
- printf("No phydev for phyaddr %d\n", phy_addr);
- continue;
- }
-
- /*Flash firmware for All CS4340 PHYS */
-
[U-Boot] [PATCH] driver: net: fsl-mc: Memset dprc_cfg before configuring
From: Prabhakar Kushwaha All fields of struct dprc_cfg are not being configured while creating child container. "Not" configured fields are assumed to be 0. So memset dprc_cfg before configuring the fields. Signed-off-by: Itai Katz Signed-off-by: Prabhakar Kushwaha --- drivers/net/fsl-mc/mc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index bac4610..6269dab 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -784,6 +784,7 @@ static int dprc_init(void) goto err_root_open; } + memset(&cfg, 0, sizeof(struct dprc_cfg)); cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED | DPRC_CFG_OPT_OBJ_CREATE_ALLOWED | DPRC_CFG_OPT_ALLOC_ALLOWED; -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/3] axm/taurus: Enable tiny printf in SPL
Hello Tom, Am 19.01.2016 um 19:08 schrieb Tom Rini: On Thu, Jan 14, 2016 at 01:02:04PM -0500, Tom Rini wrote: Both of these boards are very close to their limit and with some toolchains such as gcc 5.x are too large. Switch to tiny printf to reclaim some size. Signed-off-by: Tom Rini Applied to u-boot/master, thanks! Missed this patch, tested it on the taurus board, works! Thanks! bye, Heiko -- -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] iocon / bamboo: Drop CONFIG_SYS_LONGHELP
On 19.01.2016 19:01, Tom Rini wrote: The iocon and bamboo boards are often on the verge of, or going over, their allowed size limits depending on toolchain used. If we turn off CONFIG_SYS_LONGHELP we can gain approximately 14KiB back. Cc: Dirk Eibach Cc: Stefan Roese Signed-off-by: Tom Rini Acked-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/50] dm: clk: Add support for decoding clocks from the device tree
Hi Simon, >>> >>> +/** >>> + * clk_get_by_index() - look up a clock referenced by a device >>> + * >>> + * Parse a device's 'clocks' list, returning information on the indexed >>> clock, >>> + * ensuring that it is activated. >>> + * >>> + * @dev: Device containing the clock reference >>> + * @index: Clock index to return (0 = first) >>> + * @clk_devp: Returns clock device >>> + * @return:Peripheral ID for the device to control. This is the first >>> + * argument after the clock node phandle. If there is no >>> arguemnt, >>> + * returns 0. Return -ve error code on any error >>> + */ >>> +int clk_get_by_index(struct udevice *dev, int index, struct udevice >>> **clk_devp); >>> #endif /* _CLK_H_ */ >> >> >> I want #ifdef in the header too, like mine >> http://patchwork.ozlabs.org/patch/566812/ > > I am not keen on that idea since it clutters up header files and we'll > get a link error anyway if something is missing. Anyway, I've added > it. I am afraid there is misunderstanding here. Please see my patch carefully. What I mean is like this: #if ... declaration of function prototype #else static inline empty function #endif This is a common technique to avoid a link error. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] armv8/ls1043aqds: Add lpuart defconfig
Hi Wenbin, On Wed, Jan 20, 2016 at 12:29 PM, Wenbin Song wrote: > Hi: Bin, > > Could you tell me which tree your patches have been merged into ? > I believe it will be merged via u-boot-dm, cc Simon to confirm. > Regards > > Wenbin Song > [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, PATCHv2, 2/5] igep00x0: Cleanup ethernet support
Hello Tom, Am 04.01.2016 um 23:07 schrieb Enric Balletbò i Serra: From: Ladislav Michl - move chip reset to separate function - use CONFIG_SMC911X_BASE instead of hardcoded value - remove unneeded local variable from board_eth_init. Signed-off-by: Ladislav Michl Reviewed-by: Tom Rini Acked-by: Enric Balletbo Serra --- board/isee/igep00x0/igep00x0.c | 33 +++-- 1 file changed, 19 insertions(+), 14 deletions(-) Reviewed-by: Heiko Schocher Tom? Is it OK if I apply this patch to u-boot-ubi.git, as the SPL ubi patches depend on this series? bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 5/5] igep00x0: Remove no-op macros from config header
Hello Tom, Am 04.01.2016 um 23:24 schrieb Tom Rini: On Mon, Jan 04, 2016 at 11:08:02PM +0100, Enric Balletbo i Serra wrote: From: Ladislav Michl The patch removes some macros that are not used. Signed-off-by: Ladislav Michl Acked-by: Enric Balletbo Serra Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher Tom? Is it OK if I apply this patch to u-boot-ubi.git, as the SPL ubi patches depend on this series? bye, Heiko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 4/5] igep00x0: Fix config header indentation
Hello Tom, Am 04.01.2016 um 23:24 schrieb Tom Rini: On Mon, Jan 04, 2016 at 11:08:01PM +0100, Enric Balletbo i Serra wrote: From: Ladislav Michl The patch fixes some indentation style problems in omap3_igep00x0.h file. Signed-off-by: Ladislav Michl Acked-by: Enric Balletbo Serra Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher Tom? Is it OK if I apply this patch to u-boot-ubi.git, as the SPL ubi patches depend on this series? bye, Heiko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 3/5] igep00x0: Do not include config_distro_defaults.h
Hello Tom, Am 04.01.2016 um 23:23 schrieb Tom Rini: On Mon, Jan 04, 2016 at 11:08:00PM +0100, Enric Balletbo i Serra wrote: From: Ladislav Michl File is already included: omap3_igep00x0.h -> ti_omap3_common.h -> ti_armv7_omap.h -> ti_armv7_common.h -> config_distro_defaults.h Signed-off-by: Ladislav Michl Acked-by: Enric Balletbo Serra Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher Tom? Is it OK if I apply this patch to u-boot-ubi.git, as the SPL ubi patches depend on this series? bye, Heiko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCHv2 1/5] igep00x0: enable CONFIG_NET_RANDOM_ETHADDR
Hello Tom, Am 04.01.2016 um 23:23 schrieb Tom Rini: On Mon, Jan 04, 2016 at 11:07:58PM +0100, Enric Balletbo i Serra wrote: Enable CONFIG_NET_RANDOM_ETHADDR to generate a random MAC address when ETHADDR is not set. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher Tom? Is it OK if I apply this patch to u-boot-ubi.git, as the SPL ubi patches depend on this series? bye, Heiko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] i2c: omap24xx: Convert fully to DM_I2C
Hello Christophe, Am 18.01.2016 um 22:22 schrieb Christophe Ricard: Hi Heiko, I was expecting such kind of feedback on this one :). I had myself to hack around between the MLO and the u-boot.img to get it working. For omap, i think twl drivers are kind of the main item to convert. Would you accept to take the first 4 patches until the board are fully ready for the 5th one ? Yes. If they have no checkpatch errors and apply clean ;-) I try to look at it, today. bye, Heiko Best Regards Christophe 2016-01-18 7:04 GMT+01:00 Heiko Schocher mailto:h...@denx.de>>: Hello Christophe, Am 17.01.2016 um 12:09 schrieb Christophe Ricard: For several reasons: - code clarity - DM trends in u-boot ... It is better to make omap24xx_i2c driver 100% DM_I2C based. Signed-off-by: Christophe Ricard mailto:christophe-h.ric...@st.com>> --- drivers/i2c/omap24xx_i2c.c | 447 + drivers/i2c/omap24xx_i2c.h | 154 2 files changed, 163 insertions(+), 438 deletions(-) delete mode 100644 drivers/i2c/omap24xx_i2c.h Full Ack .. but does this patch does not breeak boards, which use this driver, and are not converted to DM ? I think, we could remove the old style only, if all boards are converted ... bye, Heiko diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 774edaf..baccb89 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -49,31 +49,164 @@ #include #include -#include "omap24xx_i2c.h" - ? Why do you remove the header file, and move all definitions into the c file? DECLARE_GLOBAL_DATA_PTR; +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB(1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC(1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL(1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN(1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN(1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB(1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST(1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX(1 << 9) /* Transmitter/receiver mode */ + /* (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP(1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT(1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ +#def
Re: [U-Boot] [PATCH v2 01/50] dm: clk: Add support for decoding clocks from the device tree
Hi Masahiro,
On 18 January 2016 at 21:29, Masahiro Yamada
wrote:
> Hi Simon,
>
>
> 2016-01-19 11:27 GMT+09:00 Simon Glass :
>> Add a method which can locate a clock for a device, given its index. This
>> uses the normal device tree bindings to return the clock device and the
>> first argument which is normally used as a peripheral ID in U-Boot.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Make the peripheral ID a return value
>> - Add an assert for clk_devp
>> - Make the function dependent on OF_CONTROL
>>
>> drivers/clk/clk-uclass.c | 28
>> include/clk.h| 14 ++
>> 2 files changed, 42 insertions(+)
>>
>> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
>> index 8078b0f..f80beaf 100644
>> --- a/drivers/clk/clk-uclass.c
>> +++ b/drivers/clk/clk-uclass.c
>> @@ -12,6 +12,8 @@
>> #include
>> #include
>>
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> ulong clk_get_rate(struct udevice *dev)
>> {
>> struct clk_ops *ops = clk_get_ops(dev);
>> @@ -62,6 +64,32 @@ int clk_get_id(struct udevice *dev, int args_count,
>> uint32_t *args)
>> return ops->get_id(dev, args_count, args);
>> }
>>
>> +#ifdef CONFIG_OF_CONTROL
>
> Isn't this #if CONFIG_IS_ENABLED(OF_CONTROL)?
>
> SPL is controlled by CONFIG_SPL_OF_CONTROL.
>
OK
>
>
>> +int clk_get_by_index(struct udevice *dev, int index, struct udevice
>> **clk_devp)
>> +{
>> + struct fdtdec_phandle_args args;
>> + int ret;
>> +
>> + assert(*clk_devp);
>> + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
>> +"clocks", "#clock-cells", 0,
>> index,
>> +&args);
>> + if (ret) {
>> + debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
>> + __func__, ret);
>> + return ret;
>> + }
>> +
>> + ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node,
>> clk_devp);
>> + if (ret) {
>> + debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
>> + __func__, ret);
>> + return ret;
>> + }
>> + return args.args_count > 0 ? args.args[0] : 0;
>> +}
>> +#endif
>> +
>> UCLASS_DRIVER(clk) = {
>> .id = UCLASS_CLK,
>> .name = "clk",
>> diff --git a/include/clk.h b/include/clk.h
>> index ce2db41..0af2824 100644
>> --- a/include/clk.h
>> +++ b/include/clk.h
>> @@ -150,4 +150,18 @@ static inline int fdt_clk_get(const void *fdt, int
>> nodeoffset, int index,
>> }
>> #endif
>>
>> +/**
>> + * clk_get_by_index() - look up a clock referenced by a device
>> + *
>> + * Parse a device's 'clocks' list, returning information on the indexed
>> clock,
>> + * ensuring that it is activated.
>> + *
>> + * @dev: Device containing the clock reference
>> + * @index: Clock index to return (0 = first)
>> + * @clk_devp: Returns clock device
>> + * @return:Peripheral ID for the device to control. This is the first
>> + * argument after the clock node phandle. If there is no
>> arguemnt,
>> + * returns 0. Return -ve error code on any error
>> + */
>> +int clk_get_by_index(struct udevice *dev, int index, struct udevice
>> **clk_devp);
>> #endif /* _CLK_H_ */
>
>
> I want #ifdef in the header too, like mine
> http://patchwork.ozlabs.org/patch/566812/
I am not keen on that idea since it clutters up header files and we'll
get a link error anyway if something is missing. Anyway, I've added
it.
Regards,
Simon
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[U-Boot] [PATCH v3 01/50] dm: clk: Add support for decoding clocks from the device tree
Add a method which can locate a clock for a device, given its index. This
uses the normal device tree bindings to return the clock device and the
first argument which is normally used as a peripheral ID in U-Boot.
Signed-off-by: Simon Glass
---
Changes in v3:
- Use CONFIG_IS_ENABLED(OF_CONTROL) in C and header file
Changes in v2:
- Make the peripheral ID a return value
- Add an assert for clk_devp
- Make the function dependent on OF_CONTROL
drivers/clk/clk-uclass.c | 28
include/clk.h| 17 +
2 files changed, 45 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index f2eb73c..18ded9c 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -12,6 +12,8 @@
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
ulong clk_get_rate(struct udevice *dev)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -72,6 +74,32 @@ int clk_get_id(struct udevice *dev, int args_count, uint32_t
*args)
return ops->get_id(dev, args_count, args);
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
+{
+ struct fdtdec_phandle_args args;
+ int ret;
+
+ assert(*clk_devp);
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+"clocks", "#clock-cells", 0, index,
+&args);
+ if (ret) {
+ debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, clk_devp);
+ if (ret) {
+ debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+ return args.args_count > 0 ? args.args[0] : 0;
+}
+#endif
+
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",
diff --git a/include/clk.h b/include/clk.h
index 1e334ed..aea1c41 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -159,4 +159,21 @@ static inline int fdt_clk_get(const void *fdt, int
nodeoffset, int index,
}
#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/**
+ * clk_get_by_index() - look up a clock referenced by a device
+ *
+ * Parse a device's 'clocks' list, returning information on the indexed clock,
+ * ensuring that it is activated.
+ *
+ * @dev: Device containing the clock reference
+ * @index: Clock index to return (0 = first)
+ * @clk_devp: Returns clock device
+ * @return:Peripheral ID for the device to control. This is the first
+ * argument after the clock node phandle. If there is no arguemnt,
+ * returns 0. Return -ve error code on any error
+ */
+int clk_get_by_index(struct udevice *dev, int index, struct udevice
**clk_devp);
+#endif
+
#endif /* _CLK_H_ */
--
2.7.0.rc3.207.g0ac5344
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Re: [U-Boot] [PATCH v2 0/6] dm: x86: Remove pirq_init() and cpu_irq_init()
Hi Bin. On 19 January 2016 at 02:15, Bin Meng wrote: > Hi Simon, > > On Tue, Jan 19, 2016 at 11:39 AM, Simon Glass wrote: >> This series adds an interrupt driver for x86. Since different platforms >> can implement this in their own way, we no-longer need the platform-specific >> weak function. We can also dispense with the arch_misc_init() call in some >> cases. >> >> Changes in v2: >> - Rebase on top of updated SPI flash series >> >> Simon Glass (6): >> dm: x86: Create a driver for x86 interrupts >> dm: x86: Set up interrupt routing from interrupt_init() >> dm: x86: Add a common PIRQ init function >> dm: x86: quark: Add an interrupt driver >> dm: x86: queensbay: Add an interrupt driver >> dm: x86: Drop the weak cpu_irq_init() function >> > > I've tested this series, but oops, it broke queensbay and quark. Sorry > I did not catch this during previous review :( > > The issue is with: > > Both queensbay and quark irq driver's probe will call > create_pirq_routing_table() in the end, where it calls: > > node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER); > > but COMPAT_INTEL_IRQ_ROUTER is not the string for queensbay and quark. > Maybe we need pass the compatible string as the parameter to > create_pirq_routing_table()? I think we can drop this with a few more patches. I sent a v3 for you to try/review. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] Move all command code into its own directory
Hi, On 19 January 2016 at 08:53, Tom Rini wrote: > On Tue, Jan 19, 2016 at 12:59:10PM +0900, Masahiro Yamada wrote: >> Hi Simon, >> >> 2016-01-18 12:53 GMT+09:00 Simon Glass : >> > There are a lot of unrelated files in common, including all of the >> > commands. >> > Moving them into their own directory makes them easier to find and is more >> > logical. >> > >> > Some commands include non-command code, such as cmd_scsi.c. This should be >> > sorted out at some point so that the function can be enabled with or >> > without >> > the associated command. >> > >> > Unfortunately, with m68k I get this error: >> > >> > m68k: + M5329AFEE >> > +arch/m68k/cpu/mcf532x/start.o: In function `_start': >> > +arch/m68k/cpu/mcf532x/start.S:159:(.text+0x452): relocation truncated to >> > fit: R_68K_PC16 against symbol `board_init_f' defined in >> > .text.board_init_f section in common/built-in.o >> > >> > I hope someone can shed some light on what this means. I hope it isn't >> > depending on the position of code in the image. >> > >> > Signed-off-by: Simon Glass >> >> >> Thanks for working on this! >> >> This is a nice improvement, >> but we might want to think about the best place for device access commands >> in the future. >> >> >> I mean, >> >> cmd_nand.c in drivers/mtd/nand/ rather than cmd/ >> cmd_mmc.c in drivers/mmc/ rather than cmd/ >> cmd_usb.c in drivers/usb/ rather thant cmd/ >> >> etc. > > But we're not going to have anywhere near a 1:1 mapping of commands to > some subdirectories. So I would make the inverse point, we would have > commands in drivers/mtd/nand, drivers/mmc, drivers/usb/host, > drivers/usb/gadget, drivers/dm, board/foo instead of being able to say > "If you add a new command, it goes into cmd/" and similarly, "Did you > see cmd/foo.c? That sound a whole lot like what you're doing in > cmd/fauxoo.c" and possibly even short-circuting that problem at the > design phase when people see that someone else already had a similar > problem and solved it. Yes I think it helps to have commands in one directory. There may be some board-specific commands elsewhere in the tree, but I think it is useful. > >> This patch moves cmd_usb.c, but leaves common/usb*.c. >> >> With this patch, USB files are located in three places: >> - cmd/cmd_usb.c >> - common/usb*.c >> - drivers/usb/ >> >> >> Is collecting all them into drivers/usb/ more logical? > > Skimming common/usb*.c, I think a lot of that needs to move into > drivers/usb/. Yes, and in cases where there is non-command logic in cmd/ we should try to fix it. > >> I think this needs closer look and more discussion, though. > > I like this approach as it does expose some of the problems with the > current lack-of-structure, ie all of the non-command stuff in the cmd > files, and other things we've shoved into common/ that don't quite > belong there now really. It will also make it easier to split up the > current command files where we have a lot of 'hidden' commands. > > -- > Tom That's my feeling too. In principle I think the commands should be a veneer on top of the implementation. Ideally there should not be a lot of processing logic in the cmd/ files. We are close to this in most cases, but things like USB and SCSI need work. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/23] dm: video: Flush the cache after a puts()
Hi Tom, On 19 January 2016 at 09:53, Tom Warren wrote: > Simon, > >> -Original Message- >> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass >> Sent: Monday, January 18, 2016 7:03 PM >> To: Tom Warren >> Cc: U-Boot Mailing List ; Stephen Warren >> ; Stephen Warren ; Marek >> Vasut ; Anatolij Gustschin ; Pavel >> Herrmann >> Subject: Re: [PATCH 02/23] dm: video: Flush the cache after a puts() >> >> Hi Tom, >> >> On 18 January 2016 at 15:29, Tom Warren wrote: >> > Simon, >> > >> >> -Original Message- >> >> From: Simon Glass [mailto:s...@google.com] On Behalf Of Simon Glass >> >> Sent: Thursday, January 14, 2016 11:28 AM >> >> To: U-Boot Mailing List >> >> Cc: Tom Warren ; Stephen Warren >> >> ; Stephen Warren ; >> Simon >> >> Glass ; Marek Vasut ; >> >> Anatolij Gustschin ; Pavel Herrmann >> >> >> >> Subject: [PATCH 02/23] dm: video: Flush the cache after a puts() >> >> >> >> This helps keep the display consistent. puts() is used when printing >> >> the prompt, so is a useful way to make sure the current display contents >> >> is >> visible. >> >> >> >> Signed-off-by: Simon Glass >> >> --- >> > This doesn't apply to TOT u-boot-tegra/master (just rebased against TOT u- >> boot/master). Vidconsole-uclass.c is missing: >> > >> > Applying: dm: video: Flush the cache after a puts() >> > error: drivers/video/vidconsole-uclass.c: does not exist in index >> > Patch failed at 0002 dm: video: Flush the cache after a puts() The >> > copy of the patch that failed is found in: >> >/home/tom/denx/uboot-tegra/.git/rebase-apply/patch >> > >> >> Yes this depends on the driver model series - see u-boot-dm/rkf-working for >> the >> source tree. I've got a few comments on the uclass now so I'll send v2 at >> some >> point and hopefully apply it soon after that. > > OK. But you've assigned these to me in Patchwork (or I've been automatically > designated as the Delegate), which makes me think I need to at least try and > apply them to u-boot-tegra. > Same with the 23-part display driver-model changes, which don't apply either. > > If these are going to go in thru the DM repo, please reassign to yourself. If > they're eventually going to apply cleanly to u-boot-tegra, leave them > delegated to me and let me know when V2 is ready. I have some concerns with applying these as they are. Once the prerequisites are applied I'll come back to it. Thanks for looking at it. If you are able to test the series, please try the u-boot-dm/rkf-working tree. > > Thanks, > > Tom >> >> > Tom >> > > -- > nvpublic >> > >> >> >> >> drivers/video/vidconsole-uclass.c | 1 + >> >> 1 file changed, 1 insertion(+) >> >> >> >> diff --git a/drivers/video/vidconsole-uclass.c >> >> b/drivers/video/vidconsole-uclass.c >> >> index 706a189..a4c919e 100644 >> >> --- a/drivers/video/vidconsole-uclass.c >> >> +++ b/drivers/video/vidconsole-uclass.c >> >> @@ -139,6 +139,7 @@ static void vidconsole_puts(struct stdio_dev >> >> *sdev, const char *s) >> >> >> >> while (*s) >> >> vidconsole_put_char(dev, *s++); >> >> + video_sync(dev->parent); >> >> } >> >> >> >> /* Set up the number of rows and colours (rotated drivers override >> >> this) */ >> >> -- >> >> 2.6.0.rc2.230.g3dd15c0 >> > >> >> Regards, >> Simon Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] At start of autoboot check, flush any pending RX bytes
Hi, On 18 January 2016 at 23:46, Craig McQueen wrote: >> Tom Rini wrote: >> >> On Mon, Jan 11, 2016 at 09:59:18AM -0700, Simon Glass wrote: >> > Hi Craig, >> > >> > On 20 December 2015 at 19:07, Craig McQueen >> > wrote: >> > > This is to avoid the boot sequence halting due to initial "junk" >> > > received on serial input. >> > > >> > > Signed-off-by: Craig McQueen >> > > --- >> > > I have found that on the BeagleBone Black, U-Boot occasionally halts >> > > at the U-Boot prompt at boot-up, whether power-up, warm external >> > > reset or software reset. I have seen other people report the same issue. >> > > >> > > This seems to be due to U-Boot receiving "junk" data on the serial >> > > console. The BeagleBone Black has a pull-down resistor which was >> > > apparently added to try to mitigate this issue, but it doesn't >> > > entirely fix it. >> > >> > I wonder if this can be fixed for that board only? >> >> No, and it's not -exactly- a that board only problem. It's a HW design issue >> that can show up elsewhere too. I _think_ however in this case the answer >> would be to migrate to perhaps CONFIG_AUTOBOOT_KEYED_CTRLC as that's >> one of the reason various other boards use that set of options. >> >> I would suggest bringing this up on the beaglebone list to see what the >> various people that ship and support these boards think, thanks! > > Other options such as CONFIG_AUTOBOOT_KEYED_CTRLC sound like a work-around of > the problem, rather than a fix of the root-cause. But maybe that's just my > opinion. Simon Glass' suggestion (clear out the UART input buffer when the > driver is probed) sounded reasonable, but I haven't tried it. Since it seems like a hardware bug, we can only have a workaround. A real fix would involve fixing the root cause, i.e. fixing the hardware. > > I think BeagleBone Black definitely needs _some_ sort of fix -- currently BBB > can randomly fail to boot, which isn't good. If my patch isn't wanted, then > please implement a suitable alternative. How about what Tom suggested? Ctrl-C is not likely to happen by accident. > > It could be worth checking the UART's error flags (break, framing error, > parity error, etc), and ignoring a byte with any error. But it looks as > though the U-Boot code would need more extensive changes to support that. I'm not sure. You could add a Kconfig option to flush the UART on probe(). > > On what BeagleBone list do you suggest this should be brought up? > > -- > Craig McQueen > Regads, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] clk: add fixed rate clock driver
On 18 January 2016 at 21:55, Masahiro Yamada wrote: > This commit intends to implement "fixed-clock" as in Linux. > (drivers/clk/clk-fixed-rate.c in Linux) > > If you need a very simple clock to just provide fixed clock rate > like a crystal oscillator, you do not have to write a new driver. > This driver can support it. > > Signed-off-by: Masahiro Yamada > --- > > Changes in v2: > - Change file name from clk-fixed-rate.c to clk_fixed-rate.c > - Use .ofdata_to_platdata method instead of .probe > - Change driver name "Fixed Rate Clock" to "fixed_rate_clock" > > drivers/clk/Makefile | 2 +- > drivers/clk/clk_fixed_rate.c | 57 > > 2 files changed, 58 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/clk_fixed_rate.c Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 43/50] rockchip: pinctrl: Reduce the size for SPL
Hi, On 18 January 2016 at 02:39, Sjoerd Simons wrote: > On Thu, 2016-01-14 at 08:51 -0700, Simon Glass wrote: >> Hi Eddie, >> >> On 14 January 2016 at 05:47, Eddie Cai >> wrote: >> > Hi Simon >> > >> > I think the best way to reduce SPL size is to jump back to boot >> > rom. >> > Which don't require eMMC, SD card driver in SPL any more. Even >> > clock >> > and pinctrl driver is not required. All we need is DDR >> > initialization. >> > We should do as little thing as possible in SPL and let U-boot take >> > care others. >> > >> >> Is it possible to use the ROM to load U-Boot and then get control >> back >> before jumping to it? If so, then I agree this would be best. >> >> Ideally we just need a routine we can call which can load from >> eMMC/SD. > > Incidentally I've been playing with this a bit over the last week. > Mostly because I wanted to load u-boot over USB OTG to make it simpler > to quickly test things (e.g. to test my networking series more easily). > > I've got some work in progress code to jump back to the bootrom after > the SPL which allows me to load u-boot via USB OTG as well, which is > great start. > > Unfortunately it seems that loading a kernel after that will cause the > kernel to wedge during early boot. Initial analysis shows it doesn't > get interrupts from the architecture timer, but it might well be > interrupts don't work at all... > > Eddie, any ideas what the maskrom code might do different with the > interrupt setup if loading things over OTG vs. from MMC? > > It would certainly be great if we can use the boot ROM code. This is what we do on exynos and it makes a big difference to the SPL size. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 6/6] clk: add fixed rate clock driver
Hi Masahiro,
On 18 January 2016 at 22:15, Masahiro Yamada
wrote:
> 2015-12-28 23:20 GMT+09:00 Simon Glass :
>> Hi Masahiro,
>>
>> On 18 December 2015 at 04:15, Masahiro Yamada
>> wrote:
>>> This commit intends to implement "fixed-clock" as in Linux.
>>> (drivers/clk/clk-fixed-rate.c in Linux)
>>>
>>> If you need a very simple clock to just provide fixed clock rate
>>> like a crystal oscillator, you do not have to write a new driver.
>>> This driver can support it.
>>>
>>> Note:
>>> As you see in dts/ directories, fixed clocks are often collected in
>>> one container node like this:
>>>
>>> clocks {
>>> refclk_a: refclk_a {
>>> #clock-cells = <0>;
>>> compatible = "fixed-clock";
>>> clock-frequency = <1000>;
>>> };
>>>
>>> refclk_b: refclk_b {
>>> #clock-cells = <0>;
>>> compatible = "fixed-clock";
>>> clock-frequency = <2000>;
>>> };
>>> };
>>>
>>> This does not work in the current DM of U-Boot, unfortunately.
>>> The "clocks" node must have 'compatible = "simple-bus";' or something
>>> to bind children.
>>
>> I suppose we could explicitly probe the children of the 'clocks' node
>> somewhere. What do you suggest?
>>
>>>
>>> Most of developers would be unhappy about adding such a compatible
>>> string only in U-Boot because we generally want to use the same set
>>> of device trees beyond projects.
>>
>> I'm not sure we need to change it, but if we did, we could try to
>> upstream the change.
>>
>>>
>>> Signed-off-by: Masahiro Yamada
>>> ---
>>>
>>> I do not understand why we need both .get_rate and .get_periph_rate.
>>>
>>> I set both in this driver, but I am not sure if I am doing right.
>>
>> This is to avoid needing a new clock device for every single clock
>> divider in the SoC. For example, it is common to have a PLL be used by
>> 20-30 devices. In U-Boot we can encode the device number as a
>> peripheral ID, Then we can adjust those dividers by settings the
>> clock's rate on a per-peripheral basis. Thus we need only one clock
>> device instead of 20-30.
>>
>> In the case of your clock I think you could return -ENOSYS for
>> get_periph_rate().
>
> I've just posted v2.
>
> I am still keeping both .get_rate() and .get_periph_rate().
>
> If I follow your suggestion, each clock consumer must know the
> detail of its clock providers to choose the correct one,
> either .get_rate() or .get_periph_rate().
>
> Or do you want drivers to do like this?
>
>
>
> clock_cells = clk_get_nr_cells(...);
>
> if (clock_cells == 0)
> rate = clk_get_rate(...);
> else
> rate = clk_get_periph_rate(...);
>
>
>
> For the proper use of these two, the details of clocks must be
> hard-coded in drivers.
> They, of course should be describe in device tree and clock providers.
In general drivers don't use PLLs directly. So I doubt this case will
arise. Do you have an example?
Regards,
Simon
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Re: [U-Boot] [PATCH 2/6] dm: implement a SATA uclass
Hi,
On 18 January 2016 at 22:09, Mugunthan V N wrote:
>
> On Monday 18 January 2016 02:53 PM, Bin Meng wrote:
> > +Simon
> >
> > On Mon, Jan 18, 2016 at 4:47 PM, Mugunthan V N wrote:
> >> Implement a SATA uclass that can represent a SATA controller.
> >>
> >> Signed-off-by: Mugunthan V N
> >> ---
> >> drivers/block/Kconfig | 10 +++
> >> drivers/block/Makefile | 2 ++
> >> drivers/block/sata-uclass.c | 69
> >> +
> >> include/dm/uclass-id.h | 1 +
> >> 4 files changed, 82 insertions(+)
> >> create mode 100644 drivers/block/sata-uclass.c
> >>
> >> diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
> >> index e69de29..44d8a6b 100644
> >> --- a/drivers/block/Kconfig
> >> +++ b/drivers/block/Kconfig
> >> @@ -0,0 +1,10 @@
> >> +menu "SATA Device Support"
> >> +
> >> +config SATA
> >> + bool "Enable driver model for SATA drivers"
> >> + depends on DM
> >> + help
> >> + Enable driver model for block devices like SCSI. It uses the
> >> + same API as block, but now implemented by the uclass.
> >> +
> >> +endmenu
> >> diff --git a/drivers/block/Makefile b/drivers/block/Makefile
> >> index eb8bda9..c2dae17 100644
> >> --- a/drivers/block/Makefile
> >> +++ b/drivers/block/Makefile
> >> @@ -5,6 +5,8 @@
> >> # SPDX-License-Identifier: GPL-2.0+
> >> #
> >>
> >> +obj-$(CONFIG_SATA) += sata-uclass.o
> >> +
> >> obj-$(CONFIG_SCSI_AHCI) += ahci.o
> >> obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
> >> obj-$(CONFIG_FSL_SATA) += fsl_sata.o
> >> diff --git a/drivers/block/sata-uclass.c b/drivers/block/sata-uclass.c
> >> new file mode 100644
> >> index 000..62773b6
> >> --- /dev/null
> >> +++ b/drivers/block/sata-uclass.c
> >> @@ -0,0 +1,69 @@
> >> +/*
> >> + * SATA device U-Class driver
> >> + *
> >> + * (C) Copyright 2016
> >> + * Texas Instruments Incorporated,
> >> + *
> >> + * Author: Mugunthan V N
> >> + *
> >> + * SPDX-License-Identifier: GPL-2.0+
> >> + */
> >> +
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> +/*
> >> + * struct mmc_uclass_priv - Holds information about a device used by the
> >> uclass
> >> + */
> >
> > Please use single-line comment when it fits just one line. Also it's not
> > mmc.
>
> Will fix it in next version.
>
> >
> >> +struct sata_uclass_priv {
> >> + struct block_dev_desc_t *block_dev;
> >> +};
> >> +
> >> +int scsi_get_device(int index, struct udevice **devp)
> >> +{
> >> + struct udevice *dev;
> >> + int ret;
> >> +
> >> + ret = uclass_find_device(UCLASS_SATA, index, &dev);
> >> + if (ret || !dev) {
> >> + printf("%d device not found\n", index);
> >> + return ret;
> >> + }
> >> +
> >> + ret = device_probe(dev);
> >> + if (ret) {
> >> + error("device probe error\n");
> >> + return ret;
> >> + }
> >> +
> >> + *devp = dev;
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +void scsi_init(void)
> >> +{
> >> + struct udevice *dev;
> >> + int ret;
> >> +
> >> + ret = scsi_get_device(0, &dev);
> >> + if (ret || !dev) {
> >> + error("scsi device not found\n");
> >> + return;
> >> + }
> >> +
> >> + scsi_scan(1);
> >> +}
> >> +
> >> +UCLASS_DRIVER(sata) = {
> >> + .id = UCLASS_SATA,
> >> + .name = "sata",
> >> + .flags = DM_UC_FLAG_SEQ_ALIAS,
> >> + .per_device_auto_alloc_size = sizeof(struct sata_uclass_priv),
> >> +};
> >> diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
> >> index 27fa0b6..80977ca 100644
> >> --- a/include/dm/uclass-id.h
> >> +++ b/include/dm/uclass-id.h
> >> @@ -55,6 +55,7 @@ enum uclass_id {
> >> UCLASS_RESET, /* Reset device */
> >> UCLASS_REMOTEPROC, /* Remote Processor device */
> >> UCLASS_RTC, /* Real time clock device */
> >> + UCLASS_SATA,/* SATA devices */
> >> UCLASS_SERIAL, /* Serial UART */
> >> UCLASS_SPI, /* SPI bus */
> >> UCLASS_SPI_FLASH, /* SPI flash */
> >> --
> >
> > I would like to see a full DM conversion of the SCSI codes. But this
> > patch looks to me it's just a place holder?
>
> Ultimately that will be the final goal, now this is just a place holder
> to move towards DM conversion.
I have a series which adds a disk uclass. It was using AHCI (=SATA)
but Bin pointed out that this might be too specific.
So perhaps you should use that?
http://patchwork.ozlabs.org/patch/569381/
Regards,
Simon
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Re: [U-Boot] [PATCH v3 1/5] lib: Add wait_for_bit
Hi,
On 27 December 2015 at 10:28, Mateusz Kulikowski
wrote:
> Add function to poll register waiting for specific bit(s).
> Similar functions are implemented in few drivers - they are almost
> identical and can be generalized.
> Signed-off-by: Mateusz Kulikowski
> ---
>
> include/wait_bit.h | 71
> ++
> 1 file changed, 71 insertions(+)
> create mode 100644 include/wait_bit.h
>
Sorry I only just saw this, but thought I'd make a few comments.
> diff --git a/include/wait_bit.h b/include/wait_bit.h
> new file mode 100644
> index 000..4867ced
> --- /dev/null
> +++ b/include/wait_bit.h
> @@ -0,0 +1,71 @@
> +/*
> + * Wait for bit with timeout and ctrlc
> + *
> + * (C) Copyright 2015 Mateusz Kulikowski
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef __WAIT_BIT_H
> +#define __WAIT_BIT_H
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/**
> + * wait_for_bit() waits for bit set/cleared in register
> + *
> + * Function polls register waiting for specific bit(s) change
> + * (either 0->1 or 1->0). It can fail under two conditions:
> + * - Timeout
> + * - User interaction (CTRL-C)
> + * Function succeeds only if all bits of masked register are set/cleared
> + * (depending on set option).
> + *
> + * @param prefix Prefix added to timeout messagge (message visible only
> + * with debug enabled)
> + * @param reg Register that will be read (using readl())
> + * @param mask Bit(s) of register that must be active
> + * @param set Selects wait condition (bit set or clear)
> + * @param timeout Timeout (in miliseconds)
> + * @param breakableEnables CTRL-C interruption
> + * @return 0 on success, -ETIMEDOUT or -EINTR on failure
> + */
> +static inline int wait_for_bit(const char *prefix, const u32 *reg,
> + const u32 mask, const bool set,
> + const unsigned int timeout,
timeout_ms would be more obvious
> + const bool breakable)
Wow this is a pretty big inline function.
Do you need the 'prefix' parameter? It seems that the callers print
messages anyway. How about adding a flags word for @set and
@breakable? Those params could then be combined, and you end up with 4
parameters instead of 6.
> +{
> + u32 val;
> + unsigned long start = get_timer(0);
> +
> + while (1) {
> + val = readl(reg);
> +
> + if (!set)
> + val = ~val;
> +
> + if ((val & mask) == mask)
> + return 0;
> +
> + if (get_timer(start) > timeout)
> + break;
> +
> + if (breakable && ctrlc()) {
> + puts("Abort\n");
This is bad if used from drivers. We try not to output things. It it necessary?
> + return -EINTR;
> + }
> +
> + udelay(1);
> + }
> +
> + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", prefix, reg,
> mask,
> + set);
> +
> + return -ETIMEDOUT;
> +}
> +
> +
> +#endif
> --
> 2.5.0
>
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Re: [U-Boot] [PATCH v1 16/16] board: Add Qualcomm Dragonboard 410C support
Hi Mateusz,
On 6 January 2016 at 11:21, Mateusz Kulikowski
wrote:
> This commit add support for 96Boards Dragonboard410C.
>
> It is board based on APQ8016 Qualcomm SoC, complying with
> 96boards specification.
>
> Features (present out of the box):
> - 4x Cortex A53 (ARMv8)
> - 2x USB Host port
> - 1x USB Device port
> - 4x LEDs
> - 1x HDMI connector
> - 1x uSD connector
> - 3x buttons (Power, Vol+, Vol-/Reset)
> - WIFI, Bluetooth with integrated antenna
> - 8GiB eMMC
>
> U-Boot boots chained with fastboot in 64-bit mode.
> For detailed build instructions see readme.txt in board directory.
>
> Signed-off-by: Mateusz Kulikowski
> ---
>
> Changes in v1:
> - Add better help for dragonboard
> - Move static structures to board_prepare_usb
> - Add DM_SPMI to defconfig
>
> arch/arm/dts/Makefile| 2 +
> arch/arm/dts/dragonboard410c.dts | 154 +++
> arch/arm/mach-snapdragon/Kconfig | 20 +++
> board/qualcomm/dragonboard410c/Kconfig | 15 ++
> board/qualcomm/dragonboard410c/Makefile | 8 +
> board/qualcomm/dragonboard410c/dragonboard410c.c | 111 ++
> board/qualcomm/dragonboard410c/head.S| 20 +++
> board/qualcomm/dragonboard410c/readme.txt| 40 +
> board/qualcomm/dragonboard410c/u-boot.lds| 90 +++
> configs/dragonboard410c_defconfig| 30
> include/configs/dragonboard410c.h| 182
> +++
> 11 files changed, 672 insertions(+)
> create mode 100644 arch/arm/dts/dragonboard410c.dts
> create mode 100644 board/qualcomm/dragonboard410c/Kconfig
> create mode 100644 board/qualcomm/dragonboard410c/Makefile
> create mode 100644 board/qualcomm/dragonboard410c/dragonboard410c.c
> create mode 100644 board/qualcomm/dragonboard410c/head.S
> create mode 100644 board/qualcomm/dragonboard410c/readme.txt
> create mode 100644 board/qualcomm/dragonboard410c/u-boot.lds
> create mode 100644 configs/dragonboard410c_defconfig
> create mode 100644 include/configs/dragonboard410c.h
Can you please add a MAINTAINERS file also?
Tested-by: Simon Glass
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0bcd316..47aecf5 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -95,6 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
> dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
> fsl-ls1043a-rdb.dtb
>
> +dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
> +
> dtb-$(CONFIG_MACH_SUN4I) += \
> sun4i-a10-a1000.dtb \
> sun4i-a10-ba10-tvbox.dtb \
> diff --git a/arch/arm/dts/dragonboard410c.dts
> b/arch/arm/dts/dragonboard410c.dts
> new file mode 100644
> index 000..1de5d23
> --- /dev/null
> +++ b/arch/arm/dts/dragonboard410c.dts
> @@ -0,0 +1,154 @@
> +/dts-v1/;
> +
> +#include "skeleton64.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. Dragonboard 410c";
> + compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
> + qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
> + qcom,board-id = <0x10018 0x0>;
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x8000 0 0x3da0>;
> + };
> +
> + chosen {
> + stdout-path = "/soc/serial@78b";
> + };
> +
> +
> + soc {
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + ranges = <0x0 0x0 0x0 0x>;
> + compatible = "simple-bus";
> +
> + clkc: qcom,gcc@180 {
> + compatible = "qcom,gcc-apq8016";
> + reg = <0x180 0x8>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + };
> +
> + serial@78b {
> + compatible = "qcom,msm-uartdm-v1.4";
> + reg = <0x78b 0x200>;
> + u-boot,dm-pre-reloc;
> + clock = <&clkc 4>;
> + };
> +
> + restart@4ab000 {
> + compatible = "qcom,pshold";
> + reg = <0x4ab000 0x4>;
> + };
> +
> + soc_gpios: pinctrl@100 {
> + compatible = "qcom,apq8016-pinctrl";
> + reg = <0x100 0x30>;
> + gpio-controller;
> + gpio-count = <122>;
> + gpio-bank-name="soc";
> + #gpio-cells = <1>;
> + };
> +
> + ehci@78d9000 {
> + compatible = "qcom,ehci-host";
> + reg = <0x78d9000 0x400>;
> + };
> +
> + sdhci@07824000 {
> + compatible = "qcom,sdhci-msm-v4";
> +
[U-Boot] [PATCH v3 7/8] dm: x86: queensbay: Add an interrupt driver
Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/cpu/queensbay/irq.c| 65 +
arch/x86/cpu/queensbay/tnc.c| 37 ---
arch/x86/dts/crownbay.dts | 2 +-
4 files changed, 67 insertions(+), 39 deletions(-)
create mode 100644 arch/x86/cpu/queensbay/irq.c
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index 660f967..af3ffad 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += fsp_configs.o
+obj-y += fsp_configs.o irq.o
obj-y += tnc.o topcliff.o
diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
new file mode 100644
index 000..44369f7
--- /dev/null
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2014, Bin Meng
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int queensbay_irq_router_probe(struct udevice *dev)
+{
+ struct tnc_rcba *rcba;
+ u32 base;
+
+ base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct tnc_rcba *)base;
+
+ /* Make sure all internal PCI devices are using INTA */
+ writel(INTA, &rcba->d02ip);
+ writel(INTA, &rcba->d03ip);
+ writel(INTA, &rcba->d27ip);
+ writel(INTA, &rcba->d31ip);
+ writel(INTA, &rcba->d23ip);
+ writel(INTA, &rcba->d24ip);
+ writel(INTA, &rcba->d25ip);
+ writel(INTA, &rcba->d26ip);
+
+ /*
+* Route TunnelCreek PCI device interrupt pin to PIRQ
+*
+* Since PCIe downstream ports received INTx are routed to PIRQ
+* A/B/C/D directly and not configurable, we have to route PCIe
+* root ports' INTx to PIRQ A/B/C/D as well. For other devices
+* on TunneCreek, route them to PIRQ E/F/G/H.
+*/
+ writew(PIRQE, &rcba->d02ir);
+ writew(PIRQF, &rcba->d03ir);
+ writew(PIRQG, &rcba->d27ir);
+ writew(PIRQH, &rcba->d31ir);
+ writew(PIRQA, &rcba->d23ir);
+ writew(PIRQB, &rcba->d24ir);
+ writew(PIRQC, &rcba->d25ir);
+ writew(PIRQD, &rcba->d26ir);
+
+ return irq_router_common_init(dev);
+}
+
+static const struct udevice_id queensbay_irq_router_ids[] = {
+ { .compatible = "intel,queensbay-irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(queensbay_irq_router_drv) = {
+ .name = "queensbay_intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = queensbay_irq_router_ids,
+ .probe = queensbay_irq_router_probe,
+};
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index b65906b..75f7adb 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -69,43 +69,6 @@ int arch_early_init_r(void)
return 0;
}
-void cpu_irq_init(void)
-{
- struct tnc_rcba *rcba;
- u32 base;
-
- base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
- base &= ~MEM_BAR_EN;
- rcba = (struct tnc_rcba *)base;
-
- /* Make sure all internal PCI devices are using INTA */
- writel(INTA, &rcba->d02ip);
- writel(INTA, &rcba->d03ip);
- writel(INTA, &rcba->d27ip);
- writel(INTA, &rcba->d31ip);
- writel(INTA, &rcba->d23ip);
- writel(INTA, &rcba->d24ip);
- writel(INTA, &rcba->d25ip);
- writel(INTA, &rcba->d26ip);
-
- /*
-* Route TunnelCreek PCI device interrupt pin to PIRQ
-*
-* Since PCIe downstream ports received INTx are routed to PIRQ
-* A/B/C/D directly and not configurable, we have to route PCIe
-* root ports' INTx to PIRQ A/B/C/D as well. For other devices
-* on TunneCreek, route them to PIRQ E/F/G/H.
-*/
- writew(PIRQE, &rcba->d02ir);
- writew(PIRQF, &rcba->d03ir);
- writew(PIRQG, &rcba->d27ir);
- writew(PIRQH, &rcba->d31ir);
- writew(PIRQA, &rcba->d23ir);
- writew(PIRQB, &rcba->d24ir);
- writew(PIRQC, &rcba->d25ir);
- writew(PIRQD, &rcba->d26ir);
-}
-
int arch_misc_init(void)
{
unprotect_spi_flash();
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 2a18be0..d6dd0b4 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -164,7 +164,7 @@
compatible = "intel,pch7";
irq-router {
- compatible = "intel,irq-router";
+ compatible = "intel,queensbay-irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
[U-Boot] [PATCH v3 8/8] dm: x86: Drop the weak cpu_irq_init() function
There are no callers now. Platforms which need to set up interrupts their
own way can implement an interrupt driver. Drop this function.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Rebase on top of updated SPI flash series
arch/x86/cpu/irq.c | 7 ---
arch/x86/include/asm/irq.h | 10 --
2 files changed, 17 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index d6151e0..0b36ace 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -83,11 +83,6 @@ static inline void fill_irq_info(struct irq_info *slot, int
bus, int device,
slot->irq[pin - 1].bitmap = irq_router.irq_mask;
}
-__weak void cpu_irq_init(void)
-{
- return;
-}
-
static int create_pirq_routing_table(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
@@ -227,8 +222,6 @@ int irq_router_common_init(struct udevice *dev)
{
int ret;
- cpu_irq_init();
-
ret = create_pirq_routing_table(dev);
if (ret) {
debug("Failed to create pirq routing table\n");
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 46e1c31..5b9e673 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -56,16 +56,6 @@ struct pirq_routing {
#define PIRQ_BITMAP0xdef8
/**
- * cpu_irq_init() - Initialize CPU IRQ routing
- *
- * This initializes some platform-specific registers related to IRQ routing,
- * like configuring internal PCI devices to use which PCI interrupt pin,
- * and which PCI interrupt pin is mapped to which PIRQ line. Note on some
- * platforms, such IRQ routing might be hard-coded thus cannot configure.
- */
-void cpu_irq_init(void);
-
-/**
* irq_router_common_init() - Perform common x86 interrupt init
*
* This creates the PIRQ routing table and routes the IRQs
--
2.7.0.rc3.207.g0ac5344
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Re: [U-Boot] [PATCH 2/4] video: tegra: Move to using simple-panel and pwm-backlight
Hi Stephen,
On 19 January 2016 at 09:49, Stephen Warren wrote:
>
> On 01/18/2016 07:08 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 18 January 2016 at 12:43, Stephen Warren wrote:
>>>
>>> On 01/14/2016 01:26 PM, Simon Glass wrote:
We have standard drivers for panels and backlights which can do most of
the
work for us. Move the tegra20 LCD driver over to use those instead of
custom
code.
This patch includes device tree changes for the nvidia boards. I have only
been able to test seaboard. If this patch is applied, these boards will
also need to be synced with the kernel, and updated to use
display-timings:
- colibri
- medcom-wide
- paz00
- tec
>>>
>>>
>>>
diff --git a/arch/arm/dts/tegra20-harmony.dts
b/arch/arm/dts/tegra20-harmony.dts
>>>
>>>
>>>
>>> This file has huge changes unrelated to panel, video, and backlight. Perhaps
>>> patch 1/4 was meant to sync the DTs for Harmony and Ventana too rather than
>>> just Seaboard, leaving this commit to make roughly identical DT changes for
>>> all 3 boards?
>>
>>
>> Yes I think that would be better. I started on seaboard since that's
>> the only one I have. But then I thought I could do the other two since
>> you or Tom should be able to test it.
>>
>>>
diff --git a/arch/arm/dts/tegra20-seaboard.dts
b/arch/arm/dts/tegra20-seaboard.dts
>>>
>>>
>>>
+
+ display-timings {
+ timing@0 {
+ /* Seaboard has 1366x768
*/
+ clock-frequency =
<7060>;
+ hactive = <1366>;
+ vactive = <768>;
+ hback-porch = <58>;
+ hfront-porch = <58>;
+ hsync-len = <58>;
+ vback-porch = <4>;
+ vfront-porch = <4>;
+ vsync-len = <4>;
+ hsync-active = <1>;
+ };
+ };
>>>
>>>
>>>
>>> It seems very strange to go to the effort of creating patch 1 to sync the
>>> U-Boot and Linux DT files (such that I assume they're 100% identical?) yet
>>> immediately have patch 2 diverge the two DTs again.
>>>
>>> This lends more weight to my argument that the U-Boot DTs should contain
>>> only nodes that U-Boot actively uses. I can see the argument for copying
>>> over the entire DT from Linux into U-Boot in order to keep them 100%
>>> identical, and in turn that means importing a bunch of DT content that
>>> U-Boot doesn't use. However, that argument completely breaks down if the DTs
>>> are just going to diverge still.
>>>
>>> At least the display-timings node is a standard binding, even if it isn't
>>> one that the Linux Tegra DTs make use of.
>>
>>
>> How about adding this to the Linux Tegra DT? It's a hardware
>> description so shouldn't ruffle too many feathres.
>>
>>>
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 14125b4..0de56a9 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -12,9 +12,11 @@ CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
@@ -22,3 +24,4 @@ CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_ERRNO_STR=y
>>>
>>>
>>>
>>> I assume those are all needed by the modified Tegra video/LCD driver. If so,
>>> wouldn't it make sense for that driver to select those Kconfig options
>>> rather than requiring every board defconfig to be modified to enable the
>>> features?
>>
>>
>> Do you mean 'depends on' in the Kconfig? This is a discussion that
>> goes back and forth...I don't really mind. It would mean that you
>> would have to play detective in menuconfig to turn the display on for
>> a board: find all the options it depends on, turn them on one by one
>> and then the display option appears.
>
>
> I was thinking of "select" in Kconfig, so that if someone enables Tegra
> LCD/display support then regulators etc. get automatically enabled too.
>
> But "depends" would work too.
'select' sounds better. I'll take a look.
Regards,
Simon
[U-Boot] [PATCH v3 6/8] dm: x86: quark: Add an interrupt driver
Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/quark/Makefile | 2 +-
arch/x86/cpu/quark/irq.c| 49 +
arch/x86/cpu/quark/quark.c | 25 ---
arch/x86/dts/galileo.dts| 2 +-
4 files changed, 51 insertions(+), 27 deletions(-)
create mode 100644 arch/x86/cpu/quark/irq.c
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 8f1d018..6d670d7 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += car.o dram.o msg_port.o quark.o
+obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c
new file mode 100644
index 000..1f8f909
--- /dev/null
+++ b/arch/x86/cpu/quark/irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015, Bin Meng
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+int quark_irq_router_probe(struct udevice *dev)
+{
+ struct quark_rcba *rcba;
+ u32 base;
+
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct quark_rcba *)base;
+
+ /*
+* Route Quark PCI device interrupt pin to PIRQ
+*
+* Route device#23's INTA/B/C/D to PIRQA/B/C/D
+* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
+*/
+ writew(PIRQC, &rcba->rmu_ir);
+ writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
+ &rcba->d23_ir);
+ writew(PIRQD, &rcba->core_ir);
+ writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
+ &rcba->d20d21_ir);
+
+ return irq_router_common_init(dev);
+}
+
+static const struct udevice_id quark_irq_router_ids[] = {
+ { .compatible = "intel,quark-irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(quark_irq_router_drv) = {
+ .name = "quark_intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = quark_irq_router_ids,
+ .probe = quark_irq_router_probe,
+};
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index f652d99..3097565 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,12 +7,10 @@
#include
#include
#include
-#include
#include
#include
#include
#include
-#include
#include
#include
#include
@@ -341,29 +339,6 @@ int cpu_mmc_init(bd_t *bis)
return pci_mmc_init("Quark SDHCI", mmc_supported);
}
-void cpu_irq_init(void)
-{
- struct quark_rcba *rcba;
- u32 base;
-
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
- base &= ~MEM_BAR_EN;
- rcba = (struct quark_rcba *)base;
-
- /*
-* Route Quark PCI device interrupt pin to PIRQ
-*
-* Route device#23's INTA/B/C/D to PIRQA/B/C/D
-* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
-*/
- writew(PIRQC, &rcba->rmu_ir);
- writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
- &rcba->d23_ir);
- writew(PIRQD, &rcba->core_ir);
- writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
- &rcba->d20d21_ir);
-}
-
int arch_misc_init(void)
{
#ifdef CONFIG_ENABLE_MRC_CACHE
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 9d82bb3..a2f5a1f 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -84,7 +84,7 @@
compatible = "intel,pch7";
irq-router {
- compatible = "intel,irq-router";
+ compatible = "intel,quark-irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xdef8>;
--
2.7.0.rc3.207.g0ac5344
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[U-Boot] [PATCH v3 2/8] dm: x86: Set up interrupt routing from interrupt_init()
At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().
This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.
Drop pirq_init() since it is no-longer used.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/baytrail/valleyview.c | 2 +-
arch/x86/cpu/interrupts.c | 9 +
arch/x86/cpu/irq.c | 7 ---
arch/x86/cpu/qemu/qemu.c | 5 -
arch/x86/cpu/quark/quark.c | 2 +-
arch/x86/cpu/queensbay/tnc.c | 2 +-
arch/x86/include/asm/irq.h | 10 --
include/configs/qemu-x86.h | 1 -
8 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/arch/x86/cpu/baytrail/valleyview.c
b/arch/x86/cpu/baytrail/valleyview.c
index 7299f2c..25382f9 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -50,7 +50,7 @@ int arch_misc_init(void)
mrccache_save();
#endif
- return pirq_init();
+ return 0;
}
int reserve_arch(void)
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index b00ddc0..c40200b 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -12,6 +12,7 @@
*/
#include
+#include
#include
#include
#include
@@ -244,6 +245,14 @@ int disable_interrupts(void)
int interrupt_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ /* Try to set up the interrupt router, but don't require one */
+ ret = uclass_first_device(UCLASS_IRQ, &dev);
+ if (ret && ret != -ENODEV)
+ return ret;
+
/*
* When running as an EFI application we are not in control of
* interrupts and should leave them alone.
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 9b699cf..8f59b23 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -231,13 +231,6 @@ static int create_pirq_routing_table(void)
return 0;
}
-int pirq_init(void)
-{
- struct udevice *dev;
-
- return uclass_first_device(UCLASS_IRQ, &dev);
-}
-
int irq_router_probe(struct udevice *dev)
{
int ret;
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 46111c9..5a7b929 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -96,11 +96,6 @@ int arch_early_init_r(void)
return 0;
}
-int arch_misc_init(void)
-{
- return pirq_init();
-}
-
#ifdef CONFIG_GENERATE_MP_TABLE
int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
{
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 37ce394..f652d99 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -375,7 +375,7 @@ int arch_misc_init(void)
mrccache_save();
#endif
- return pirq_init();
+ return 0;
}
void board_final_cleanup(void)
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index fb81919..b65906b 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -110,5 +110,5 @@ int arch_misc_init(void)
{
unprotect_spi_flash();
- return pirq_init();
+ return 0;
}
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 6697da3..74da66e 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -65,14 +65,4 @@ struct pirq_routing {
*/
void cpu_irq_init(void);
-/**
- * pirq_init() - Initialize platform PIRQ routing
- *
- * This initializes the PIRQ routing on the platform and configures all PCI
- * devices' interrupt line register to a working IRQ number on the 8259 PIC.
- *
- * @return 0 if OK, -ve on error
- */
-int pirq_init(void);
-
#endif /* _ARCH_IRQ_H_ */
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 4258dcb..b0d2ffe 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -14,7 +14,6 @@
#include
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_PCI_PNP
--
2.7.0.rc3.207.g0ac5344
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[U-Boot] [PATCH v3 3/8] dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/irq.c | 7 ++-
arch/x86/include/asm/irq.h | 7 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 8f59b23..e2feba7 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -231,7 +231,7 @@ static int create_pirq_routing_table(void)
return 0;
}
-int irq_router_probe(struct udevice *dev)
+int irq_router_common_init(struct udevice *dev)
{
int ret;
@@ -249,6 +249,11 @@ int irq_router_probe(struct udevice *dev)
return 0;
}
+int irq_router_probe(struct udevice *dev)
+{
+ return irq_router_common_init(dev);
+}
+
u32 write_pirq_routing_table(u32 addr)
{
if (!pirq_routing_table)
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 74da66e..46e1c31 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -65,4 +65,11 @@ struct pirq_routing {
*/
void cpu_irq_init(void);
+/**
+ * irq_router_common_init() - Perform common x86 interrupt init
+ *
+ * This creates the PIRQ routing table and routes the IRQs
+ */
+int irq_router_common_init(struct udevice *dev);
+
#endif /* _ARCH_IRQ_H_ */
--
2.7.0.rc3.207.g0ac5344
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[U-Boot] [PATCH v3 5/8] x86: Drop the irq router compatible string
We use driver model for this now, so we don't need this string.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to drop the irq router compatible string
Changes in v2: None
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 27b350e..285da95 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -164,7 +164,6 @@ enum fdt_compat_id {
COMPAT_INTEL_X86_PINCTRL, /* Intel ICH7/9 pin control */
COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
COMPAT_INTEL_PCH, /* Intel PCH */
- COMPAT_INTEL_IRQ_ROUTER,/* Intel Interrupt Router */
COMPAT_ALTERA_SOCFPGA_DWMAC,/* SoCFPGA Ethernet controller */
COMPAT_ALTERA_SOCFPGA_DWMMC,/* SoCFPGA DWMMC controller */
COMPAT_ALTERA_SOCFPGA_DWC2USB, /* SoCFPGA DWC2 USB controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b50d105..4b8fc0c 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -69,7 +69,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_X86_PINCTRL, "intel,x86-pinctrl"),
COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
- COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
--
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[U-Boot] [PATCH v3 1/8] dm: x86: Create a driver for x86 interrupts
It seems likely that at some point we will want a generic interrupt uclass.
But this is a big undertaking as it involves unifying code across multiple
architectures.
As a first step, create a simple IRQ uclass and a driver for x86. This can
be generalised later as required.
Adjust pirq_init() to probe this driver, which has the effect of creating
routing tables and setting up the interrupt routing. This is a start
towards making interrupts fit better with driver model.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/irq.c | 25 +
include/dm/uclass-id.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 205405b..9b699cf 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -232,6 +233,13 @@ static int create_pirq_routing_table(void)
int pirq_init(void)
{
+ struct udevice *dev;
+
+ return uclass_first_device(UCLASS_IRQ, &dev);
+}
+
+int irq_router_probe(struct udevice *dev)
+{
int ret;
cpu_irq_init();
@@ -255,3 +263,20 @@ u32 write_pirq_routing_table(u32 addr)
return copy_pirq_routing_table(addr, pirq_routing_table);
}
+
+static const struct udevice_id irq_router_ids[] = {
+ { .compatible = "intel,irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(irq_router_drv) = {
+ .name = "intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = irq_router_ids,
+ .probe = irq_router_probe,
+};
+
+UCLASS_DRIVER(irq) = {
+ .id = UCLASS_IRQ,
+ .name = "irq",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 27fa0b6..ef145af 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -37,6 +37,7 @@ enum uclass_id {
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_MUX, /* I2C multiplexer */
+ UCLASS_IRQ, /* Interrupt controller */
UCLASS_KEYBOARD,/* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
--
2.7.0.rc3.207.g0ac5344
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[U-Boot] [PATCH v3 4/8] x86: Use the IRQ device when setting up the mptable
Instead of searching for the device tree node, use the IRQ device which has
a record of it.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to use the IRQ device when setting up the mptable
Changes in v2: None
arch/x86/cpu/irq.c| 16
arch/x86/lib/mpspec.c | 14 +++---
2 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index e2feba7..d6151e0 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -88,7 +88,7 @@ __weak void cpu_irq_init(void)
return;
}
-static int create_pirq_routing_table(void)
+static int create_pirq_routing_table(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct fdt_pci_addr addr;
@@ -102,16 +102,8 @@ static int create_pirq_routing_table(void)
int i;
int ret;
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
- if (node < 0) {
- debug("%s: Cannot find irq router node\n", __func__);
- return -EINVAL;
- }
-
- /* TODO(s...@chromium.org): Drop this when PIRQ is a driver */
- parent = fdt_parent_offset(blob, node);
- if (parent < 0)
- return -EINVAL;
+ node = dev->of_offset;
+ parent = dev->parent->of_offset;
ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
"reg", &addr);
if (ret)
@@ -237,7 +229,7 @@ int irq_router_common_init(struct udevice *dev)
cpu_irq_init();
- ret = create_pirq_routing_table();
+ ret = create_pirq_routing_table(dev);
if (ret) {
debug("Failed to create pirq routing table\n");
return ret;
diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c
index f3ad116..0faa582 100644
--- a/arch/x86/lib/mpspec.c
+++ b/arch/x86/lib/mpspec.c
@@ -292,19 +292,19 @@ static int mptable_add_intsrc(struct mp_config_table *mc,
struct mpc_config_intsrc *intsrc_base;
int intsrc_entries = 0;
const void *blob = gd->fdt_blob;
- int node;
+ struct udevice *dev;
int len, count;
const u32 *cell;
- int i;
+ int i, ret;
- /* Get I/O interrupt information from device tree */
- node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
- if (node < 0) {
+ ret = uclass_first_device(UCLASS_IRQ, &dev);
+ if (ret && ret != -ENODEV) {
debug("%s: Cannot find irq router node\n", __func__);
- return -ENOENT;
+ return ret;
}
- cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
+ /* Get I/O interrupt information from device tree */
+ cell = fdt_getprop(blob, dev->of_offset, "intel,pirq-routing", &len);
if (!cell)
return -ENOENT;
--
2.7.0.rc3.207.g0ac5344
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[U-Boot] [PATCH v3 0/8] dm: x86: Remove pirq_init() and cpu_irq_init()
This series adds an interrupt driver for x86. Since different platforms can implement this in their own way, we no-longer need the platform-specific weak function. We can also dispense with the arch_misc_init() call in some cases. Changes in v3: - Add new patch to use the IRQ device when setting up the mptable - Add new patch to drop the irq router compatible string Changes in v2: - Rebase on top of updated SPI flash series Simon Glass (8): dm: x86: Create a driver for x86 interrupts dm: x86: Set up interrupt routing from interrupt_init() dm: x86: Add a common PIRQ init function x86: Use the IRQ device when setting up the mptable x86: Drop the irq router compatible string dm: x86: quark: Add an interrupt driver dm: x86: queensbay: Add an interrupt driver dm: x86: Drop the weak cpu_irq_init() function arch/x86/cpu/baytrail/valleyview.c | 2 +- arch/x86/cpu/interrupts.c | 9 ++ arch/x86/cpu/irq.c | 48 arch/x86/cpu/qemu/qemu.c | 5 --- arch/x86/cpu/quark/Makefile| 2 +- arch/x86/cpu/quark/irq.c | 49 arch/x86/cpu/quark/quark.c | 27 +--- arch/x86/cpu/queensbay/Makefile| 2 +- arch/x86/cpu/queensbay/irq.c | 65 ++ arch/x86/cpu/queensbay/tnc.c | 39 +-- arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/galileo.dts | 2 +- arch/x86/include/asm/irq.h | 19 ++- arch/x86/lib/mpspec.c | 14 include/configs/qemu-x86.h | 1 - include/dm/uclass-id.h | 1 + include/fdtdec.h | 1 - lib/fdtdec.c | 1 - 18 files changed, 169 insertions(+), 120 deletions(-) create mode 100644 arch/x86/cpu/quark/irq.c create mode 100644 arch/x86/cpu/queensbay/irq.c -- 2.7.0.rc3.207.g0ac5344 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] x86: qemu: re-structure qemu_fwcfg_list_firmware()
Re-write the logic in qemu_fwcfg_list_firmware(), add a function
qemu_fwcfg_read_firmware_list() to handle reading firmware list.
Signed-off-by: Miao Yan
---
Changes in v2:
- coding style fix
- add comments in header file
arch/x86/cpu/qemu/fw_cfg.c| 63 +--
arch/x86/include/asm/fw_cfg.h | 9 ---
2 files changed, 55 insertions(+), 17 deletions(-)
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
index 0599214..bcd34af 100644
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ b/arch/x86/cpu/qemu/fw_cfg.c
@@ -10,10 +10,13 @@
#include
#include
#include
+#include
static bool fwcfg_present;
static bool fwcfg_dma_present;
+static LIST_HEAD(fw_list);
+
/* Read configuration item using fw_cfg PIO interface */
static void qemu_fwcfg_read_entry_pio(uint16_t entry,
uint32_t size, void *address)
@@ -162,29 +165,61 @@ static int qemu_fwcfg_setup_kernel(void *load_addr, void
*initrd_addr)
return 0;
}
-static int qemu_fwcfg_list_firmware(void)
+static int qemu_fwcfg_read_firmware_list(void)
{
int i;
uint32_t count;
- struct fw_cfg_files *files;
+ struct fw_file *file;
+ struct list_head *entry;
+
+ /* don't read it twice */
+ if (!list_empty(&fw_list))
+ return 0;
qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
if (!count)
return 0;
count = be32_to_cpu(count);
- files = malloc(count * sizeof(struct fw_cfg_file));
- if (!files)
- return -ENOMEM;
-
- files->count = count;
- qemu_fwcfg_read_entry(FW_CFG_INVALID,
- count * sizeof(struct fw_cfg_file),
- files->files);
-
- for (i = 0; i < files->count; i++)
- printf("%-56s\n", files->files[i].name);
- free(files);
+ for (i = 0; i < count; i++) {
+ file = malloc(sizeof(*file));
+ if (!file) {
+ printf("error: allocating resource\n");
+ goto err;
+ }
+ qemu_fwcfg_read_entry(FW_CFG_INVALID,
+ sizeof(struct fw_cfg_file), &file->cfg);
+ file->addr = 0;
+ list_add_tail(&file->list, &fw_list);
+ }
+
+ return 0;
+
+err:
+ list_for_each(entry, &fw_list) {
+ file = list_entry(entry, struct fw_file, list);
+ free(file);
+ }
+
+ return -ENOMEM;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+ int ret;
+ struct list_head *entry;
+ struct fw_file *file;
+
+ /* make sure fw_list is loaded */
+ ret = qemu_fwcfg_read_firmware_list();
+ if (ret)
+ return ret;
+
+ list_for_each(entry, &fw_list) {
+ file = list_entry(entry, struct fw_file, list);
+ printf("%-56s\n", file->cfg.name);
+ }
+
return 0;
}
diff --git a/arch/x86/include/asm/fw_cfg.h b/arch/x86/include/asm/fw_cfg.h
index fb110fa..2acf43e 100644
--- a/arch/x86/include/asm/fw_cfg.h
+++ b/arch/x86/include/asm/fw_cfg.h
@@ -12,6 +12,8 @@
#define FW_DMA_PORT_LOW0x514
#define FW_DMA_PORT_HIGH 0x518
+#include
+
enum qemu_fwcfg_items {
FW_CFG_SIGNATURE= 0x00,
FW_CFG_ID = 0x01,
@@ -67,9 +69,10 @@ struct fw_cfg_file {
char name[FW_CFG_MAX_FILE_PATH];
};
-struct fw_cfg_files {
- __be32 count;
- struct fw_cfg_file files[];
+struct fw_file {
+ struct fw_cfg_file cfg; /* firmware file information */
+ unsigned long addr; /* firmware file in-memory address */
+ struct list_head list; /* list node to link to fw_list */
};
struct fw_cfg_dma_access {
--
1.9.1
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[U-Boot] [PATCH v2 3/4] x86: config option for loading ACPI table from QEMU
This patch adds a config option for loading ACPI table from QEMU. When enabled, U-Boot won't generate ACPI tables, but use those provided by QEMU. Signed-off-by: Miao Yan --- arch/x86/Kconfig | 9 + arch/x86/cpu/qemu/Makefile | 2 ++ arch/x86/lib/Makefile | 2 ++ 3 files changed, 13 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f07567c..26c8d83 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -358,6 +358,15 @@ config GENERATE_ACPI_TABLE by the operating system. It defines platform-independent interfaces for configuration and power management monitoring. +config QEMU_ACPI_TABLE + bool "load ACPI table from QEMU fw_cfg interface" + depends on GENERATE_ACPI_TABLE && QEMU + default y + help + By default, U-Boot generates its own ACPI tables. This option, if + enabled, disables U-Boot's version and loads ACPI tables generated + by QEMU. + config GENERATE_SMBIOS_TABLE bool "Generate an SMBIOS (System Management BIOS) table" default y diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 176ea54..801413a 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -8,4 +8,6 @@ ifndef CONFIG_EFI_STUB obj-y += car.o dram.o endif obj-y += cpu.o fw_cfg.o qemu.o +ifndef CONFIG_QEMU_ACPI_TABLE obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o +endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index cd5ecb6..75719e3 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -32,7 +32,9 @@ obj-$(CONFIG_X86_RAMTEST) += ramtest.o obj-y += sfi.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-y += string.o +ifndef CONFIG_QEMU_ACPI_TABLE obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o +endif obj-y += tables.o obj-$(CONFIG_CMD_ZBOOT)+= zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/4] add support for loading ACPI tables from QEMU
Currently, if CONFIG_GENERATE_ACPI_TABLE is defined, U-Boot will generate ACPI tables itlself, this patchset adds the ability to load the ACPI tables generated by QEMU. Changes in v2: - Drop [PATCH 4/4] x86: qemu: loading ACPI table from QEMU, add a config option CONFIG_QEMU_ACPI_TABLE - various cleanups Miao Yan (4): x86: qemu: re-structure qemu_fwcfg_list_firmware() x86: qemu: setup PM IO base for ACPI in southbridge x86: config option for loading ACPI table from QEMU x86: qemu: add the ability to load and link ACPI tables from QEMU arch/x86/Kconfig| 9 + arch/x86/cpu/qemu/Kconfig | 7 + arch/x86/cpu/qemu/Makefile | 2 + arch/x86/cpu/qemu/fw_cfg.c | 316 ++-- arch/x86/cpu/qemu/qemu.c| 29 +++ arch/x86/include/asm/arch-qemu/device.h | 2 + arch/x86/include/asm/arch-qemu/qemu.h | 5 + arch/x86/include/asm/fw_cfg.h | 70 ++- arch/x86/lib/Makefile | 2 + arch/x86/lib/acpi_table.c | 4 + 10 files changed, 429 insertions(+), 17 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] x86: qemu: add the ability to load and link ACPI tables from QEMU
This patch adds the ability to load and link ACPI tables provided by QEMU.
QEMU tells guests how to load and patch ACPI tables through its fw_cfg
interface, by adding a firmware file 'etc/table-loader'. Guests are
supposed to parse this file and execute corresponding QEMU commands.
Signed-off-by: Miao Yan
---
Changes in v2:
- add function comment
- improve error handling
arch/x86/cpu/qemu/fw_cfg.c| 253 ++
arch/x86/include/asm/fw_cfg.h | 61 ++
arch/x86/lib/acpi_table.c | 4 +
3 files changed, 318 insertions(+)
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/cpu/qemu/fw_cfg.c
index bcd34af..5ea7a6e 100644
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ b/arch/x86/cpu/qemu/fw_cfg.c
@@ -10,7 +10,10 @@
#include
#include
#include
+#include
+#include
#include
+#include
static bool fwcfg_present;
static bool fwcfg_dma_present;
@@ -204,6 +207,256 @@ err:
return -ENOMEM;
}
+#ifdef CONFIG_QEMU_ACPI_TABLE
+static struct fw_file *qemu_fwcfg_find_file(const char *name)
+{
+ struct list_head *entry;
+ struct fw_file *file;
+
+ list_for_each(entry, &fw_list) {
+ file = list_entry(entry, struct fw_file, list);
+ if (!strcmp(file->cfg.name, name))
+ return file;
+ }
+
+ return NULL;
+}
+
+/*
+ * This function allocates memory for ACPI tables
+ *
+ * @entry : BIOS linker command entry which tells where to allocate memory
+ * (either high memory or low memory)
+ * @addr : The address that should be used for low memory allcation. If the
+ * memory allocation request is 'ZONE_HIGH' then this parameter will
+ * be ignored.
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_allocate(struct bios_linker_entry *entry,
+ unsigned long *addr)
+{
+ uint32_t size, align;
+ struct fw_file *file;
+ unsigned long aligned_addr;
+
+ align = le32_to_cpu(entry->alloc.align);
+ /* align must be power of 2 */
+ if (align & (align - 1)) {
+ printf("error: wrong alignment %u\n", align);
+ return -EINVAL;
+ }
+
+ file = qemu_fwcfg_find_file(entry->alloc.file);
+ if (!file) {
+ printf("error: can't find file %s\n", entry->alloc.file);
+ return -ENOENT;
+ }
+
+ size = be32_to_cpu(file->cfg.size);
+
+ /*
+* ZONE_HIGH means we need to allocate from high memory, since
+* malloc space is already at the end of RAM, so we directly use it.
+* If allocation zone is ZONE_FSEG, then we use the 'addr' passed
+* in which is low memory
+*/
+ if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+ aligned_addr = (unsigned long)memalign(align, size);
+ if (!aligned_addr) {
+ printf("error: allocating resource\n");
+ return -ENOMEM;
+ }
+ } else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG) {
+ aligned_addr = ALIGN(*addr, align);
+ } else {
+ printf("error: invalid allocation zone\n");
+ return -EINVAL;
+ }
+
+ debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align
%u, addr 0x%lx\n",
+ file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
+
+ qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
+ size, (void *)aligned_addr);
+ file->addr = aligned_addr;
+
+ /* adjust address for low memory allocation */
+ if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+ *addr = (aligned_addr + size);
+
+ return 0;
+}
+
+/*
+ * This function patches ACPI tables previously loaded
+ * by bios_linker_allocate()
+ *
+ * @entry : BIOS linker command entry which tells how to patch
+ * ACPI tables
+ * @return: 0 on success, or negative value on failure
+ */
+static int bios_linker_add_pointer(struct bios_linker_entry *entry)
+{
+ struct fw_file *dest, *src;
+ uint32_t offset = le32_to_cpu(entry->pointer.offset);
+ uint64_t pointer = 0;
+
+ dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
+ if (!dest || !dest->addr)
+ return -ENOENT;
+ src = qemu_fwcfg_find_file(entry->pointer.src_file);
+ if (!src || !src->addr)
+ return -ENOENT;
+
+ debug("bios_linker_add_pointer: dest->addr 0x%lx, src->addr 0x%lx,
offset 0x%x size %u, 0x%llx\n",
+ dest->addr, src->addr, offset, entry->pointer.size, pointer);
+
+ memcpy(&pointer, (char *)dest->addr + offset, entry->pointer.size);
+ pointer = le64_to_cpu(pointer);
+ pointer += (unsigned long)src->addr;
+ pointer = cpu_to_le64(pointer);
+ memcpy((char *)dest->addr + offset, &pointer, entry->pointer.size);
+
+
[U-Boot] [PATCH v2 2/4] x86: qemu: setup PM IO base for ACPI in southbridge
Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)
Signed-off-by: Miao Yan
---
Changes in v2:
- add ACPI_PM1_BASE in Kconfig
- drop PCI device ID checks
arch/x86/cpu/qemu/Kconfig | 7 +++
arch/x86/cpu/qemu/qemu.c| 29 +
arch/x86/include/asm/arch-qemu/device.h | 2 ++
arch/x86/include/asm/arch-qemu/qemu.h | 5 +
4 files changed, 43 insertions(+)
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 4f98621..6808c9a 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -17,4 +17,11 @@ config SYS_CAR_SIZE
hex
default 0x1
+config ACPI_PM1_BASE
+ hex
+ default 0xe400
+ help
+ ACPI Power Managment 1 (PM1) i/o-mapped base address.
+ This device is defined in ACPI specification, with 16 bytes in size.
+
endif
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 46111c9..b794cfe 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,6 +15,31 @@
static bool i440fx;
+static void enable_pm_piix(void)
+{
+ u8 en;
+ u16 cmd;
+
+ /* Set the PM I/O base */
+ x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+
+ /* Enable access to the PM I/O space */
+ cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
+ cmd |= PCI_COMMAND_IO;
+ x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
+
+ /* PM I/O Space Enable (PMIOSE) */
+ en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
+ en |= PMIOSE;
+ x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
+}
+
+static void enable_pm_ich9(void)
+{
+ /* Set the PM I/O base */
+ x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+}
+
static void qemu_chipset_init(void)
{
u16 device, xbcs;
@@ -53,10 +78,14 @@ static void qemu_chipset_init(void)
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+
+ enable_pm_piix();
} else {
/* Configure PCIe ECAM base address */
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
+
+ enable_pm_ich9();
}
qemu_fwcfg_init();
diff --git a/arch/x86/include/asm/arch-qemu/device.h
b/arch/x86/include/asm/arch-qemu/device.h
index 75a435e..38ab798 100644
--- a/arch/x86/include/asm/arch-qemu/device.h
+++ b/arch/x86/include/asm/arch-qemu/device.h
@@ -13,6 +13,8 @@
#define PIIX_ISA PCI_BDF(0, 1, 0)
#define PIIX_IDE PCI_BDF(0, 1, 1)
#define PIIX_USB PCI_BDF(0, 1, 2)
+#define PIIX_PMPCI_BDF(0, 1, 3)
+#define ICH9_PMPCI_BDF(0, 0x1f, 0)
#define I440FX_VGA PCI_BDF(0, 2, 0)
#define QEMU_Q35 PCI_BDF(0, 0, 0)
diff --git a/arch/x86/include/asm/arch-qemu/qemu.h
b/arch/x86/include/asm/arch-qemu/qemu.h
index b67d342..a85eee8 100644
--- a/arch/x86/include/asm/arch-qemu/qemu.h
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -33,4 +33,9 @@
#define LOW_RAM_ADDR 0x34
#define HIGH_RAM_ADDR 0x35
+/* PM registers */
+#define PMBA 0x40
+#define PMREGMISC 0x80
+#define PMIOSE (1 << 0)
+
#endif /* _ARCH_QEMU_H_ */
--
1.9.1
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Re: [U-Boot] [Patch V4 1/4] spi: fsl_qspi: fix compile warning for 64-bit platform
> -Original Message- > From: york sun > Sent: Wednesday, January 20, 2016 2:42 AM > To: Qianyu Gong ; u-boot@lists.denx.de > Cc: Mingkai Hu ; jt...@openedev.com; Yao Yuan > ; r58...@freescale.com; Gong Qianyu > > Subject: Re: [Patch V4 1/4] spi: fsl_qspi: fix compile warning for 64-bit > platform > > On 01/10/2016 06:14 PM, Gong Qianyu wrote: > > From: Gong Qianyu > > > > This patch fixes the following compile warning: > > drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': > > drivers/spi/fsl_qspi.c:937:15: > > warning: cast to pointer from integer of different size > > [-Wint-to-pointer-cast] > > priv->regs = (struct fsl_qspi_regs *)plat->reg_base; > >^ > > Just make the cast explict. > > > > Signed-off-by: Gong Qianyu > > --- > > V4: > > - Revise the commit message. > > V2-V3: > > - No change. > > > > drivers/spi/fsl_qspi.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index > > feec3e8..9f23c10 100644 > > --- a/drivers/spi/fsl_qspi.c > > +++ b/drivers/spi/fsl_qspi.c > > @@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus) > > > > dm_spi_bus->max_hz = plat->speed_hz; > > > > - priv->regs = (struct fsl_qspi_regs *)plat->reg_base; > > The reg_base is u32. Is it always correct on 64-bit SoC? > So far it's always a u32 type of CCSR address. > > + priv->regs = (struct fsl_qspi_regs *)(unsigned long)plat->reg_base; > > How about (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base? > > York > The size of ''unsigned long'' depends on compilers. It works well with GCC. Looks the same. But not sure what is defining CONFIG_USE_STDIN for. #ifdef CONFIG_USE_STDIN /* Provided by gcc. */ #include #else /* Type for `void *' pointers. */ typedef unsigned long int uintptr_t; #endif Regards, Qianyu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V4 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue
> -Original Message-
> From: york sun
> Sent: Wednesday, January 20, 2016 2:47 AM
> To: Qianyu Gong ; u-boot@lists.denx.de
> Cc: Mingkai Hu ; jt...@openedev.com; Yao Yuan
> ; r58...@freescale.com; Gong Qianyu
>
> Subject: Re: [Patch V4 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue
>
> On 01/10/2016 06:15 PM, Gong Qianyu wrote:
> > From: Gong Qianyu
> >
> > In current driver everytime we memcpy 4 bytes to the dest memory
> > regardless of the remaining length.
> > This patch adds checking the remaining length before memcpy.
> > If the length is shorter than 4 bytes, memcpy the actual length of
> > data to the dest memory.
> >
> > Signed-off-by: Gong Qianyu
> > ---
> > V2-V4:
> > - No change.
> >
> > drivers/spi/fsl_qspi.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 9f23c10..4d58211 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -500,7 +500,10 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv,
> > u32
> *rxbuf, u32 len)
> > if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
> > data = qspi_read32(priv->flags, ®s->rbdr[i]);
> > data = qspi_endian_xchg(data);
> > - memcpy(rxbuf, &data, 4);
> > + if (size < 4)
> > + memcpy(rxbuf, &data, size);
> > + else
> > + memcpy(rxbuf, &data, 4);
> > rxbuf++;
> > size -= 4;
> > i++;
> >
>
> Doesn't the line "size -= 4" need a fix as well? I guess it runs OK for
> checking (size >
> 0), but it looks odd.
>
> York
I paste the related code. It checks (size > 0) in the while loop:
i = 0;
size = len;
while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
rbsr_reg = qspi_read32(priv->flags, ®s->rbsr);
if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
data = qspi_read32(priv->flags, ®s->rbdr[i]);
data = qspi_endian_xchg(data);
if (size < 4)
memcpy(rxbuf, &data, size);
else
memcpy(rxbuf, &data, 4);
rxbuf++;
size -= 4;
i++;
}
}
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Re: [U-Boot] [PATCH 2/4] x86: qemu: setup PM IO base for ACPI in southbridge
Hi Miao,
On Wed, Jan 20, 2016 at 9:58 AM, Miao Yan wrote:
> Hi Bin,
>
> 2016-01-19 17:25 GMT+08:00 Bin Meng :
>> Hi Miao,
>>
>> On Tue, Jan 19, 2016 at 10:46 AM, Miao Yan wrote:
>>> Hi Bin,
>>>
>>> 2016-01-16 21:23 GMT+08:00 Bin Meng :
Hi Miao,
On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan wrote:
> Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)
>
> Signed-off-by: Miao Yan
> ---
> arch/x86/cpu/qemu/qemu.c| 39
> +
> arch/x86/include/asm/arch-qemu/device.h | 8 +++
> 2 files changed, 47 insertions(+)
>
> diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
> index 46111c9..e7d8a6c 100644
> --- a/arch/x86/cpu/qemu/qemu.c
> +++ b/arch/x86/cpu/qemu/qemu.c
> @@ -15,6 +15,41 @@
>
> static bool i440fx;
>
> +static void enable_pm_piix(void)
> +{
> + u8 en;
> + u16 device, cmd;
> +
> + device = x86_pci_read_config16(PIIX_PM, PCI_DEVICE_ID);
> + if (device != PCI_DEVICE_ID_INTEL_82371AB_3)
> + return;
Guess the check is already covered in qemu_chipset_init().
>>>
>>>
>>> Do you mean this check ?
>>>
>>> device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
>>> i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
>>>
>>> So is it guaranteed that PIIX_PM is always on that BDF ?
>>
>> I believe so. If you look at the codes in qemu.c, the variable "static
>> bool i440fx" is used to distinguish QEMU machine pc and q35. It does
>> not check whether the chipset is i440fx, or PIIX which is the chipset
>> connected to i440fx.
>>
>>>
>>> IMO, we are operating on another chipset, and we better make
>>> sure it's the one we expect, besides, an extra check won't do any harm.
>>>
>>
>> Yes, that makes sense. So if we go with your way, maybe we need expand
>> "static bool i440fx" to multiple variables and use correct variable to
>> check? But this looks a bit complex than a single variable.
>>
>
> Yes, that's a little bit complex and not necessary if their PCI
> addresses are fixed . And I don't think we should do it in this
> patchset.
>
> So how do you suggest we do this ? Either I remove the two checks to
> make it aligned with the rest or create a separate patch to do the
> checks ?
>
I suggest we do it in existing way (single variable).
[snip]
Regards,
Bin
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[U-Boot] Block/Disable U-Boot Console Access
Hi, I am an application software guy learning low-level embedded programming. I am trying to block/disable u-boot console access all together. Is there any helpful documentation for this topic. The things I gathered until now: 1. Disable Serial Port pins. Question - If an attacker gains root access, can he reconfigure serial port pins to re-enable this ? How can we disable serial port access at the hardware level ? 2. Enable "silent" & bootdelay=0 environment variables. 3. Enable password protection of U-Boot console. 4. Encrypt "Environment Memory Block" in case of *any* hardware interruptions, the u-boot opens the console. Can we disable this behavior to stop the device unless a power recycle happens or start the boot process again. I appreciate any general comments on this topic. -- View this message in context: http://u-boot.10912.n7.nabble.com/Block-Disable-U-Boot-Console-Access-tp242504.html Sent from the U-Boot mailing list archive at Nabble.com. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Block/Disable U-Boot Console Access
Hi, I am an application software guy learning low-level embedded programming. I am trying to block/disable u-boot console access all together. Is there any helpful documentation for this topic. The things I gathered until now: 1. Disable Serial Port pins. Question - If an attacker gains root access, can he reconfigure serial port pins to re-enable this ? How can we disable serial port access at the hardware level ? 2. Enable "silent" & bootdelay=0 environment variables. 3. Enable password protection of U-Boot console. 4. Encrypt "Environment Memory Block" in case of *any* hardware interruptions, the u-boot opens the console. Can we disable this behavior to stop the device unless a power recycle happens or start the boot process again. I appreciate any general comments on this topic. Thanks, Alan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] x86: qemu: setup PM IO base for ACPI in southbridge
Hi Bin,
2016-01-19 17:25 GMT+08:00 Bin Meng :
> Hi Miao,
>
> On Tue, Jan 19, 2016 at 10:46 AM, Miao Yan wrote:
>> Hi Bin,
>>
>> 2016-01-16 21:23 GMT+08:00 Bin Meng :
>>> Hi Miao,
>>>
>>> On Fri, Jan 15, 2016 at 11:12 AM, Miao Yan wrote:
Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board)
Signed-off-by: Miao Yan
---
arch/x86/cpu/qemu/qemu.c| 39
+
arch/x86/include/asm/arch-qemu/device.h | 8 +++
2 files changed, 47 insertions(+)
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 46111c9..e7d8a6c 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,6 +15,41 @@
static bool i440fx;
+static void enable_pm_piix(void)
+{
+ u8 en;
+ u16 device, cmd;
+
+ device = x86_pci_read_config16(PIIX_PM, PCI_DEVICE_ID);
+ if (device != PCI_DEVICE_ID_INTEL_82371AB_3)
+ return;
>>>
>>> Guess the check is already covered in qemu_chipset_init().
>>
>>
>> Do you mean this check ?
>>
>> device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
>> i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
>>
>> So is it guaranteed that PIIX_PM is always on that BDF ?
>
> I believe so. If you look at the codes in qemu.c, the variable "static
> bool i440fx" is used to distinguish QEMU machine pc and q35. It does
> not check whether the chipset is i440fx, or PIIX which is the chipset
> connected to i440fx.
>
>>
>> IMO, we are operating on another chipset, and we better make
>> sure it's the one we expect, besides, an extra check won't do any harm.
>>
>
> Yes, that makes sense. So if we go with your way, maybe we need expand
> "static bool i440fx" to multiple variables and use correct variable to
> check? But this looks a bit complex than a single variable.
>
Yes, that's a little bit complex and not necessary if their PCI
addresses are fixed . And I don't think we should do it in this
patchset.
So how do you suggest we do this ? Either I remove the two checks to
make it aligned with the rest or create a separate patch to do the
checks ?
>>
>>>
+
+ /* Set the PM I/O base. */
>>>
>>> nits: please remove the ending period. Please fix this globally in this
>>> file.
>>>
+ x86_pci_write_config32(PIIX_PM, PMBA, DEFAULT_PMBASE | 1);
+
+ /* Enable access to the PM I/O space. */
+ cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
+ cmd |= PCI_COMMAND_IO;
+ x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
+
+ /* PM I/O Space Enable (PMIOSE). */
+ en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
+ en |= PMIOSE;
+ x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
+}
+
+static void enable_pm_ich9(void)
+{
+ u16 device;
+
+ device = x86_pci_read_config16(ICH9_PM, PCI_DEVICE_ID);
+ if (device != PCI_DEVICE_ID_INTEL_ICH9_8)
+ return;
>>>
>>> Guess the check is already covered in qemu_chipset_init().
>>>
+
+ /* Set the PM I/O base. */
+ x86_pci_write_config32(ICH9_PM, PMBA, DEFAULT_PMBASE | 1);
+}
+
static void qemu_chipset_init(void)
{
u16 device, xbcs;
@@ -53,10 +88,14 @@ static void qemu_chipset_init(void)
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+
+ enable_pm_piix();
} else {
/* Configure PCIe ECAM base address */
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
+
+ enable_pm_ich9();
}
qemu_fwcfg_init();
diff --git a/arch/x86/include/asm/arch-qemu/device.h
b/arch/x86/include/asm/arch-qemu/device.h
index 75a435e..2e11100 100644
--- a/arch/x86/include/asm/arch-qemu/device.h
+++ b/arch/x86/include/asm/arch-qemu/device.h
@@ -13,9 +13,17 @@
#define PIIX_ISA PCI_BDF(0, 1, 0)
#define PIIX_IDE PCI_BDF(0, 1, 1)
#define PIIX_USB PCI_BDF(0, 1, 2)
+#define PIIX_PMPCI_BDF(0, 1, 3)
+#define ICH9_PMPCI_BDF(0, 0x1f, 0)
#define I440FX_VGA PCI_BDF(0, 2, 0)
#define QEMU_Q35 PCI_BDF(0, 0, 0)
#define Q35_VGAPCI_BDF(0, 1, 0)
+#define PMBA 0x40
+#define DEFAULT_PMBASE 0xe400
>>>
>>> See arch/x86/cpu/quark/Kconfig we have ACPI_PM1_BASE already. Maybe we
>>> need consolidate this to introduce a similar one for QEMU.
>>
>> OK, will fix this.
>>
>>>
+#define PM_IO_BASE DEFAULT_PMBASE
>>>
>>> PM_IO_BASE is not refe
Re: [U-Boot] pull request: u-boot-uniphier/master
On Wed, Jan 20, 2016 at 08:54:21AM +0900, Masahiro Yamada wrote: > Hi Tom, > > Sorry for the short interval from the previous one, > but please pull one more series. No worries :) > > > The following changes since commit 3ed2ece5e162b104cd3ea3788cae841ecd24408f: > > armv8: cavium: Get DRAM size from ATF (2016-01-19 22:26:13 +) > > are available in the git repository at: > > git://git.denx.de/u-boot-uniphier.git master > > for you to fetch changes up to 048c61d674c4e5c793f5391fb7a57c8c79c99ebd: > > ARM: uniphier: remove unneeded if conditionals (2016-01-20 08:40:33 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ls2-2085ardb: Correct the model name of ls2085ardb
> -Original Message-
> From: york sun
> Sent: Wednesday, January 20, 2016 12:02 AM
> To: Prabhakar Kushwaha ; Ashish Kumar
> ; u-boot@lists.denx.de
> Subject: Re: [PATCH] ls2-2085ardb: Correct the model name of ls2085ardb
>
> On 01/14/2016 08:49 PM, Prabhakar Kushwaha wrote:
> >
> >> -Original Message-
> >> From: york sun [mailto:york@nxp.com]
> >> Sent: Thursday, January 14, 2016 10:36 PM
> >> To: Ashish Kumar ; u-boot@lists.denx.de
> >> Cc: Prabhakar Kushwaha
> >> Subject: Re: [PATCH] ls2-2085ardb: Correct the model name of
> >> ls2085ardb
> >>
> >> On 01/14/2016 04:42 AM, Ashish Kumar wrote:
> >>> Signed-off-by: Ashish Kumar
> >>> ---
> >>> arch/arm/dts/fsl-ls2080a-rdb.dts |2 +-
> >>> 1 files changed, 1 insertions(+), 1 deletions(-)
> >>>
> >>> diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts
> >>> b/arch/arm/dts/fsl-ls2080a-
> >> rdb.dts
> >>> index 1a1813b..71d1969 100644
> >>> --- a/arch/arm/dts/fsl-ls2080a-rdb.dts
> >>> +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts
> >>> @@ -11,7 +11,7 @@
> >>> #include "fsl-ls2080a.dtsi"
> >>>
> >>> / {
> >>> - model = "Freescale Layerscape 2080a RDB Board";
> >>> + model = "Freescale Layerscape 2085a RDB Board";
> >>> compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
> >>>
> >>> aliases {
> >>>
> >>
> >> Ashish,
> >>
> >> Why change this? This product has been renamed to LS2080A.
> >>
> >
> > LS2085ARDB is a platform/board hosting LS2080A, LS2085A and LS2088A.
> >
> > This is the reason board name is being updated.
> >
>
> Prabhakar,
>
> You changed the name from LS2085A to LS2080A not long ago, including the
> board LS2085ARDB, stating LS2080A is the prime personality. Now you want
> to change it back? You have to give a good reason.
>
LS2080A and LS2085A name is correct.
Things nail down to platform/board which will host the SoC. LS2085ARDB "board"
will host both LS2080A, LS2085A and in future LS2088A. Same name is printed on
the board. So to avoid confusion board name has been updated.
looks like v2 of this patch is required, as in board/Freescale/ls2080rdb.c
board name is printed as per SoC name with suffix of QDS or RDB.
--prabhakar
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[U-Boot] [PATCH 2/2] arm, powerpc: Update cc-version tests to check for cc-name as well
For compatibility clang will report some gcc version. However since we are checking gcc versions in order to then fail to build, we should limit these tests only to when we are using gcc and not clang. Signed-off-by: Tom Rini --- arch/arm/config.mk |3 ++- arch/powerpc/config.mk |3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 0550225..a3e14a8 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -40,7 +40,8 @@ ifeq ($(CONFIG_SYS_THUMB_BUILD),y) archprepare: checkthumb checkthumb: - @if test "$(call cc-version)" -lt "0404"; then \ + @if test "$(call cc-name)" = "gcc" -a \ + "$(call cc-version)" -lt "0404"; then \ echo -n '*** Your GCC does not produce working '; \ echo 'binaries in THUMB mode.'; \ echo '*** Your board is configured for THUMB mode.'; \ diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 6b44a37..b0ed374 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -41,7 +41,8 @@ archprepare: checkgcc4 # that U-Boot wants. # See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html checkgcc4: - @if test $(call cc-version) -lt 0400; then \ + @if test "$(call cc-name)" = "gcc" -a \ + $(call cc-version) -lt 0400; then \ echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \ false; \ fi -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] kbuild: Add clang detection
Adapted from: >From 5631d9c429857194bd55d7bcd8fa5bdd1a9899a3 Mon Sep 17 00:00:00 2001 From: Michal Marek Date: Wed, 19 Aug 2015 17:36:41 +0200 Subject: [PATCH 1/1] kbuild: Fix clang detection We cannot detect clang before including the arch Makefile, because that can set the default cross compiler. We also cannot detect clang after including the arch Makefile, because powerpc wants to know about clang. Solve this by using an deferred variable. This costs us a few shell invocations, but this is only a constant number. Reported-by: Behan Webster Reported-by: Anton Blanchard Signed-off-by: Michal Marek in the Linux kernel. This will allow us to make better decisions about when to run tests later on for gcc features. Signed-off-by: Tom Rini --- scripts/Kbuild.include |4 1 file changed, 4 insertions(+) diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 98e09ce..30e6e31 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -130,6 +130,10 @@ cc-option-align = $(subst -functions=0,,\ cc-disable-warning = $(call try-run,\ $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1))) +# cc-name +# Expands to either gcc or clang +cc-name = $(shell $(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc) + # cc-version cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC)) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO board
On Tue, Jan 19, 2016 at 09:16:36PM +0800, Ye Li wrote: >Initial version for mx6sx SABREAUTO board support with features: >PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander. > >Signed-off-by: Ye Li Tested-by: Peng Fan >--- > arch/arm/cpu/armv7/mx6/Kconfig |6 + > board/freescale/mx6sxsabreauto/Kconfig | 12 + > board/freescale/mx6sxsabreauto/MAINTAINERS |6 + > board/freescale/mx6sxsabreauto/Makefile |6 + > board/freescale/mx6sxsabreauto/imximage.cfg | 136 ++ > board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 508 +++ > configs/mx6sxsabreauto_defconfig| 11 + > include/configs/mx6sxsabreauto.h| 212 ++ > 8 files changed, 897 insertions(+), 0 deletions(-) > create mode 100644 board/freescale/mx6sxsabreauto/Kconfig > create mode 100644 board/freescale/mx6sxsabreauto/MAINTAINERS > create mode 100644 board/freescale/mx6sxsabreauto/Makefile > create mode 100644 board/freescale/mx6sxsabreauto/imximage.cfg > create mode 100644 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c > create mode 100644 configs/mx6sxsabreauto_defconfig > create mode 100644 include/configs/mx6sxsabreauto.h > >diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig >index 8489182..c72a150 100644 >--- a/arch/arm/cpu/armv7/mx6/Kconfig >+++ b/arch/arm/cpu/armv7/mx6/Kconfig >@@ -96,6 +96,11 @@ config TARGET_MX6SXSABRESD > select DM > select DM_THERMAL > >+config TARGET_MX6SXSABREAUTO >+bool "mx6sxsabreauto" >+select DM >+select DM_THERMAL >+ > config TARGET_MX6UL_9X9_EVK > bool "mx6ul_9x9_evk" > select MX6UL >@@ -166,6 +171,7 @@ source "board/freescale/mx6qsabreauto/Kconfig" > source "board/freescale/mx6sabresd/Kconfig" > source "board/freescale/mx6slevk/Kconfig" > source "board/freescale/mx6sxsabresd/Kconfig" >+source "board/freescale/mx6sxsabreauto/Kconfig" > source "board/freescale/mx6ul_14x14_evk/Kconfig" > source "board/gateworks/gw_ventana/Kconfig" > source "board/kosagi/novena/Kconfig" >diff --git a/board/freescale/mx6sxsabreauto/Kconfig >b/board/freescale/mx6sxsabreauto/Kconfig >new file mode 100644 >index 000..ae2ea02 >--- /dev/null >+++ b/board/freescale/mx6sxsabreauto/Kconfig >@@ -0,0 +1,12 @@ >+if TARGET_MX6SXSABREAUTO >+ >+config SYS_BOARD >+ default "mx6sxsabreauto" >+ >+config SYS_VENDOR >+ default "freescale" >+ >+config SYS_CONFIG_NAME >+ default "mx6sxsabreauto" >+ >+endif >diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS >b/board/freescale/mx6sxsabreauto/MAINTAINERS >new file mode 100644 >index 000..6f2ff44 >--- /dev/null >+++ b/board/freescale/mx6sxsabreauto/MAINTAINERS >@@ -0,0 +1,6 @@ >+MX6SXSABREAUTO BOARD >+M:Fabio Estevam >+S:Maintained >+F:board/freescale/mx6sxsabreauto/ >+F:include/configs/mx6sxsabreauto.h >+F:configs/mx6sxsabreauto_defconfig >diff --git a/board/freescale/mx6sxsabreauto/Makefile >b/board/freescale/mx6sxsabreauto/Makefile >new file mode 100644 >index 000..f0cd1ce >--- /dev/null >+++ b/board/freescale/mx6sxsabreauto/Makefile >@@ -0,0 +1,6 @@ >+# (C) Copyright 2014 Freescale Semiconductor, Inc. >+# >+# SPDX-License-Identifier:GPL-2.0+ >+# >+ >+obj-y := mx6sxsabreauto.o >diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg >b/board/freescale/mx6sxsabreauto/imximage.cfg >new file mode 100644 >index 000..529e555 >--- /dev/null >+++ b/board/freescale/mx6sxsabreauto/imximage.cfg >@@ -0,0 +1,136 @@ >+/* >+ * Copyright (C) 2014 Freescale Semiconductor, Inc. >+ * >+ * SPDX-License-Identifier: GPL-2.0+ >+ */ >+ >+#define __ASSEMBLY__ >+#include >+ >+/* image version */ >+ >+IMAGE_VERSION 2 >+ >+/* >+ * Boot Device : one of >+ * spi/sd/nand/onenand, qspi/nor >+ */ >+ >+BOOT_FROM sd >+ >+/* >+ * Device Configuration Data (DCD) >+ * >+ * Each entry must have the format: >+ * Addr-type AddressValue >+ * >+ * where: >+ *Addr-type register length (1,2 or 4 bytes) >+ *Address absolute address of the register >+ *value value to be stored in the register >+ */ >+ >+/* Enable all clocks */ >+DATA 4 0x020c4068 0x >+DATA 4 0x020c406c 0x >+DATA 4 0x020c4070 0x >+DATA 4 0x020c4074 0x >+DATA 4 0x020c4078 0x >+DATA 4 0x020c407c 0x >+DATA 4 0x020c4080 0x >+DATA 4 0x020c4084 0x >+ >+/* IOMUX - DDR IO Type */ >+DATA 4 0x020e0618 0x000c >+DATA 4 0x020e05fc 0x >+ >+/* Clock */ >+DATA 4 0x020e032c 0x0030 >+ >+/* Address */ >+DATA 4 0x020e0300 0x0030 >+DATA 4 0x020e02fc 0x0030 >+DATA 4 0x020e05f4 0x0030 >+ >+/* Control */ >+DATA 4 0x020e0340 0x0030 >+ >+DATA 4 0x020e0320 0x >+DATA 4 0x020e0310 0x0030 >+DATA 4 0x020e0314 0x0030 >+DATA 4 0x020e0614 0x0030 >+ >+/* Data Strobe */ >+DATA 4 0x020e05f8 0x0002 >+DATA 4 0x020e0330 0x0030 >+DATA 4 0x020e0334 0x0030 >+DATA 4 0x020e0338 0x0030 >+DATA
Re: [U-Boot] [PATCH 1/2] mx6: soc: Add ENET2 mac address support
On Tue, Jan 19, 2016 at 09:16:35PM +0800, Ye Li wrote:
>The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
>MAC address from fuse for ENET2.
>
>Signed-off-by: Ye Li
Reviewed-by: Peng Fan
>---
> arch/arm/cpu/armv7/mx6/soc.c | 32 +
> arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +
> 2 files changed, 24 insertions(+), 27 deletions(-)
>
>diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
>index bf5ae8c..e521bf2 100644
>--- a/arch/arm/cpu/armv7/mx6/soc.c
>+++ b/arch/arm/cpu/armv7/mx6/soc.c
>@@ -364,15 +364,29 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char
>*mac)
> struct fuse_bank4_regs *fuse =
> (struct fuse_bank4_regs *)bank->fuse_regs;
>
>- u32 value = readl(&fuse->mac_addr_high);
>- mac[0] = (value >> 8);
>- mac[1] = value ;
>-
>- value = readl(&fuse->mac_addr_low);
>- mac[2] = value >> 24 ;
>- mac[3] = value >> 16 ;
>- mac[4] = value >> 8 ;
>- mac[5] = value ;
>+ if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
>+ 1 == dev_id) {
>+ u32 value = readl(&fuse->mac_addr2);
>+ mac[0] = value >> 24 ;
>+ mac[1] = value >> 16 ;
>+ mac[2] = value >> 8 ;
>+ mac[3] = value ;
>+
>+ value = readl(&fuse->mac_addr_high);
>+ mac[4] = value >> 24 ;
>+ mac[5] = value >> 16 ;
>+
>+ } else {
>+ u32 value = readl(&fuse->mac_addr_high);
>+ mac[0] = (value >> 8);
>+ mac[1] = value ;
>+
>+ value = readl(&fuse->mac_addr_low);
>+ mac[2] = value >> 24 ;
>+ mac[3] = value >> 16 ;
>+ mac[4] = value >> 8 ;
>+ mac[5] = value ;
>+ }
>
> }
> #endif
>diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
>b/arch/arm/include/asm/arch-mx6/imx-regs.h
>index f24525e..d0324a0 100644
>--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
>+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
>@@ -715,7 +715,6 @@ struct fuse_bank1_regs {
> u32 rsvd7[3];
> };
>
>-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> struct fuse_bank4_regs {
> u32 sjc_resp_low;
> u32 rsvd0[3];
>@@ -725,29 +724,13 @@ struct fuse_bank4_regs {
> u32 rsvd2[3];
> u32 mac_addr_high;
> u32 rsvd3[3];
>- u32 mac_addr2;
>+ u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
> u32 rsvd4[7];
> u32 gp1;
> u32 rsvd5[3];
> u32 gp2;
> u32 rsvd6[3];
> };
>-#else
>-struct fuse_bank4_regs {
>- u32 sjc_resp_low;
>- u32 rsvd0[3];
>- u32 sjc_resp_high;
>- u32 rsvd1[3];
>- u32 mac_addr_low;
>- u32 rsvd2[3];
>- u32 mac_addr_high;
>- u32 rsvd3[0xb];
>- u32 gp1;
>- u32 rsvd4[3];
>- u32 gp2;
>- u32 rsvd5[3];
>-};
>-#endif
>
> struct aipstz_regs {
> u32 mprot0;
>--
>1.7.4.1
>
>___
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Re: [U-Boot] [PATCH] fsl_qspi: fix address mask issue
On Tue, Jan 19, 2016 at 09:07:18PM +0800, Ye Li wrote: >The OFFSET_BITS_MASK should mask bit from 0-23. >By using GENMASK(24, 0), when using the fast read common (0xb), a >invalid sf_addr 0x100 is produced by swab32(txbuf) & OFFSET_BITS_MASK. > >Signed-off-by: Ye Li >--- > drivers/spi/fsl_qspi.c |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > >diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c >index feec3e8..542b6cf 100644 >--- a/drivers/spi/fsl_qspi.c >+++ b/drivers/spi/fsl_qspi.c >@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; > #define TX_BUFFER_SIZE0x40 > #endif > >-#define OFFSET_BITS_MASK GENMASK(24, 0) >+#define OFFSET_BITS_MASK GENMASK(23, 0) > > #define FLASH_STATUS_WEL 0x02 Reviewed-by: Peng Fan > >-- >1.7.4.1 > >___ >U-Boot mailing list >U-Boot@lists.denx.de >http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 04/14] efi_loader: Add boot time services
On Fri, Jan 15, 2016 at 06:06:10AM +0100, Alexander Graf wrote:
> When an EFI application runs, it has access to a few descriptor and callback
> tables to instruct the EFI compliant firmware to do things for it. The bulk
> of those interfaces are "boot time services". They handle all object
> management,
> and memory allocation.
>
> This patch adds support for the boot time services and also exposes a system
> table, which is the point of entry descriptor table for EFI payloads.
>
> Signed-off-by: Alexander Graf
>
> ---
>
> v1 -> v2:
>
> - Fix typo s/does now/does not/
> - Add #ifdefs around header to allow inclusion when efi_loader is disabled
> - Add stub efi_restore_gd() function when efi_loader is disabled
> - Disable debug
> - Mark runtime region as such
> - Fix up memory map
> - Allow efi_restore_gd to be called before first efi entry
> - Add 32bit arm cache workaround
> - Move memory map to separate patch
> - Change BTS version to 2.5
> - Fix return values for a few callbacks to more EFI compliant ones
> - Change vendor to "Das U-Boot"
> - Add warning when truncating timer trigger
> - Move to GPLv2+
> ---
> include/efi_loader.h | 51 +++
> lib/efi_loader/efi_boottime.c | 761
> ++
> 2 files changed, 812 insertions(+)
> create mode 100644 lib/efi_loader/efi_boottime.c
>
> diff --git a/include/efi_loader.h b/include/efi_loader.h
> index bf77573..391459e 100644
> --- a/include/efi_loader.h
> +++ b/include/efi_loader.h
> @@ -6,18 +6,69 @@
> * SPDX-License-Identifier: GPL-2.0+
> */
>
> +#include
> #include
> #include
> +
> +#ifdef CONFIG_EFI_LOADER
> +
> #include
>
> +/* #define DEBUG_EFI */
> +
> +#ifdef DEBUG_EFI
> +#define EFI_ENTRY(format, ...) do { \
> + efi_restore_gd(); \
> + printf("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
> + } while(0)
> +#else
> +#define EFI_ENTRY(format, ...) do { \
> + efi_restore_gd(); \
> + } while(0)
> +#endif
> +
> +#define EFI_EXIT(ret) efi_exit_func(ret);
> +
> +extern struct efi_system_table systab;
> +
> extern const efi_guid_t efi_guid_device_path;
> extern const efi_guid_t efi_guid_loaded_image;
>
> +struct efi_class_map {
> + const efi_guid_t *guid;
> + const void *interface;
> +};
> +
> +struct efi_handler {
> + const efi_guid_t *guid;
> + efi_status_t (EFIAPI *open)(void *handle,
> + efi_guid_t *protocol, void **protocol_interface,
> + void *agent_handle, void *controller_handle,
> + uint32_t attributes);
> +};
> +
> +struct efi_object {
> + struct list_head link;
> + struct efi_handler protocols[4];
> + void *handle;
> +};
> +extern struct list_head efi_obj_list;
> +
> efi_status_t efi_return_handle(void *handle,
> efi_guid_t *protocol, void **protocol_interface,
> void *agent_handle, void *controller_handle,
> uint32_t attributes);
> +void efi_timer_check(void);
> void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info);
> +void efi_save_gd(void);
> +void efi_restore_gd(void);
> +efi_status_t efi_exit_func(efi_status_t ret);
>
> #define EFI_LOADER_POOL_SIZE (128 * 1024 * 1024)
> void *efi_loader_alloc(uint64_t len);
> +
> +#else /* defined(EFI_LOADER) */
> +
> +static inline void efi_restore_gd(void) { }
> +
> +#endif
> diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
> new file mode 100644
> index 000..5756c9c
> --- /dev/null
> +++ b/lib/efi_loader/efi_boottime.c
> @@ -0,0 +1,761 @@
> +/*
> + * EFI application boot time services
> + *
> + * Copyright (c) 2016 Alexander Graf
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/* #define DEBUG_EFI */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * If we're running on nasty systems (32bit ARM booting into non-EFI Linux)
> + * we need to do trickery with caches. Since we don't want to break the EFI
> + * aware boot path, only apply hacks when loading exiting directly (breaking
> + * direct Linux EFI booting along the way - oh well).
> + */
> +static bool efi_is_direct_boot = true;
> +
> +/*
> + * EFI can pass arbitrary additional "tables" containing vendor specific
> + * information to the payload. One such table is the FDT table which contains
> + * a pointer to a flattened device tree blob.
> + *
> + * In most cases we want to pass an FDT to the payload, so reserve one slot
> of
> + * config table space for it. The pointer gets populated by
> do_bootefi_exec().
> + */
> +static struct efi_configuration_table efi_conf_table[] = {
> + {
> + .guid = EFI_FDT_GUID,
> + },
> +};
> +
> +/*
> + * The "gd" pointer lives in a register on ARM and AArch64 that we declare
> + * fixed when compiling U-Boot. However, the payload does not know ab
[U-Boot] pull request: u-boot-uniphier/master
Hi Tom, Sorry for the short interval from the previous one, but please pull one more series. The following changes since commit 3ed2ece5e162b104cd3ea3788cae841ecd24408f: armv8: cavium: Get DRAM size from ATF (2016-01-19 22:26:13 +) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 048c61d674c4e5c793f5391fb7a57c8c79c99ebd: ARM: uniphier: remove unneeded if conditionals (2016-01-20 08:40:33 +0900) Masahiro Yamada (8): ARM: uniphier: define CONFIG_SYS_BOOTMAPSZ ARM: uniphier: add bootm_low environment ARM: uniphier: refactor outer cache operation slightly ARM: uniphier: factor out outer cache sync as a helper function ARM: uniphier: fix range invalidate for outer cache ARM: uniphier: set active ways to really enable outer cache ARM: uniphier: move UMC register macros to umc-regs.h ARM: uniphier: remove unneeded if conditionals arch/arm/mach-uniphier/cache_uniphier.c | 43 +-- arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 10 ++ arch/arm/mach-uniphier/dram/umc-proxstream2.c | 49 + arch/arm/mach-uniphier/dram/umc-regs.h| 26 ++ include/configs/uniphier.h| 11 --- 5 files changed, 74 insertions(+), 65 deletions(-) -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/4] ARM: uniphier: refactor and fix UniPhier outer cache
2016-01-17 10:13 GMT+09:00 Masahiro Yamada : > Masahiro Yamada (4): > ARM: uniphier: refactor outer cache operation slightly > ARM: uniphier: factor out outer cache sync as a helper function > ARM: uniphier: fix range invalidate for outer cache > ARM: uniphier: set active ways to really enable outer cache > > arch/arm/mach-uniphier/cache_uniphier.c | 43 > - > 1 file changed, 37 insertions(+), 6 deletions(-) Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: uniphier: remove unneeded if conditionals
2016-01-20 2:05 GMT+09:00 Masahiro Yamada : > The if block does the same as the else block does. The conditional > is not necessary at all. > > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] ARM: uniphier: add bootm_low environment
2016-01-09 2:12 GMT+09:00 Masahiro Yamada : > The load address of the kernel can be changed via "kernel_addr_r" > environment. The device tree and the initramdisk should be relocated > according to the kernel location. > > The "bootm_low" should be calculated by masking the lower bits > (TEXT_OFFSET part) of the "kernel_addr_r" environment value. > > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] ARM: uniphier: define CONFIG_SYS_BOOTMAPSZ
2016-01-09 2:12 GMT+09:00 Masahiro Yamada : > U-Boot relocates the device tree and the initramdisk to the tail > of the memory region before booting the kernel. > > Some UniPhier boards are equipped with a large amount of memory. > For those boards, the device tree and the initramdisk are placed out > of the the kernel causing a kernel panic. > > Add CONFIG_SYS_BOOTMAPSZ to prevent them from going too high. > > Signed-off-by: Masahiro Yamada Applied to u-boot-uniphier/master. -- Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: socfpga: revert "set the fpga global bit to disable HPS to FPGA signals"
On Tuesday, January 19, 2016 at 04:50:06 PM, Dinh Nguyen wrote: > Hi Marek, Hi Dinh, > On 01/19/2016 09:16 AM, Dinh Nguyen wrote: > > Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA > > signals" > > I apologize for the original patch "arm: socfpga: set the fpga global > bit to disable HPS to FPGA signals". I did not test the patch when it > was sent out. I did go back to testing it after I was able to > consolidate a bit the FPGA driver for Gen5 and Gen10 devices, and found > out that behavior for the global FPGA bit is different. Good thing it went in after 2016.01 was out, so nothing that bad really happened. Thanks for finding this. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: socfpga: revert "set the fpga global bit to disable HPS to FPGA signals"
On Tuesday, January 19, 2016 at 04:16:21 PM, Dinh Nguyen wrote: > Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA > signals" > > Apparently, the logic for the FPGA global bit is not universal between Gen5 > and Gen10 devices is not the same. Disabling this bit, while applicable to > Gen10 devices, will break FPGA programming on Gen5 devices. > > Signed-off-by: Dinh Nguyen Applied, thanks. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 5/9] arm: serial: Add ability to use pre-initialized UARTs
On Wed, Oct 14, 2015 at 09:55:48AM -0700, Sergey Temerkhanov wrote: > On some systems, UART initialization is performed before running U-Boot. > This commit allows to skip UART re-initializaion on those systems > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla > Reviewed-by: Simon Glass In the end, this appears to have become mired in a lack of getting a device tree binding for this functionality in particular to be accepted upstream from us. I'm deferring on this particular version until someone with the time and desire to resolve the binding does so. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 8/9] armv8: cavium: Add an implementation of ATF calling functions
On Wed, Oct 14, 2015 at 09:55:51AM -0700, Sergey Temerkhanov wrote: > This commit adds functions issuing calls to the product-specific ATF > services > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v7,9/9] armv8: cavium: Get DRAM size from ATF
On Wed, Oct 14, 2015 at 09:55:52AM -0700, Sergey Temerkhanov wrote: > Change the dram_init() function on ThunderX to query ATF services for > the real installed DRAM size > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 4/9] armv8: Add psci.h from the Linux kernel
On Wed, Oct 14, 2015 at 09:55:47AM -0700, Sergey Temerkhanov wrote: > This commit adds the psci.h header file from Linux kernel > which contains definitions related to the PSCI interface provided > by firmware > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 7/9] armv8: cavium: Add ThunderX 88xx board definition
On Wed, Oct 14, 2015 at 09:55:50AM -0700, Sergey Temerkhanov wrote: > This commit adds basic Cavium ThunderX 88xx board definitions and support. > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla With a minor change for current API, applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 3/9] armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure
On Wed, Oct 14, 2015 at 09:55:46AM -0700, Sergey Temerkhanov wrote: > This commit adds functions issuing calls to secure monitor or > hypervisore. This allows using services such as Power State > Coordination Interface (PSCI) provided by firmware, e.g. ARM > Trusted Firmware (ATF) > > The SMC call can destroy all registers declared temporary by the > calling conventions. The clobber list is "x0..x17" because of > this > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Corey Minyard > Signed-off-by: Radha Mohan Chintakuntla > Reviewed-by: Simon Glass > Tested-by: Mateusz Kulikowski Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 6/9] armv8: cavium: Add the device tree for ThunderX
On Wed, Oct 14, 2015 at 09:55:49AM -0700, Sergey Temerkhanov wrote: > This commit adds the FDT for the ThunderX family of SoCs > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla > > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v7, 2/9] armv8: New MMU setup code allowing to use 48+ bits PA/VA
On Wed, Oct 14, 2015 at 09:55:45AM -0700, Sergey Temerkhanov wrote: > This patch adds code which sets up 2-level page tables on ARM64 thus > extending available VA space. CPUs implementing 64k translation > granule are able to use direct PA-VA mapping of the whole 48 bit > address space. > It also adds the ability to reset the SCTRL register at the very beginning > of execution to avoid interference from stale mappings set up by early > firmware/loaders/etc. > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v7,1/9] armv8: Add read_mpidr() function
On Wed, Oct 14, 2015 at 09:55:44AM -0700, Sergey Temerkhanov wrote: > This patch adds the read_mpidr() function which returns the > MPIDR_EL1 register value > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla > > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, RESEND, v2, 2/2] arm: serial: Add Kconfig entries to facilitate usage of the pl01x driver for early debug output
On Wed, Oct 14, 2015 at 09:54:24AM -0700, Sergey Temerkhanov wrote: > This patch adds Kconfig entries to facilitate usage of pl01x as > a debug UART. > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla > > Acked-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, RESEND, v2, 1/2] arm: serial: Add debug UART capability to the pl01x driver
On Wed, Oct 14, 2015 at 09:54:23AM -0700, Sergey Temerkhanov wrote: > This patch adds an ability to use pl01x as a debug UART. It must > be configured like other types of debug UARTs > > Signed-off-by: Sergey Temerkhanov > Signed-off-by: Radha Mohan Chintakuntla > > Acked-by: Simon Glass With a minor rework for current API, applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V4 1/4] spi: fsl_qspi: fix compile warning for 64-bit platform
On 01/10/2016 06:14 PM, Gong Qianyu wrote: > From: Gong Qianyu > > This patch fixes the following compile warning: > drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': > drivers/spi/fsl_qspi.c:937:15: > warning: cast to pointer from integer of different size >[-Wint-to-pointer-cast] > priv->regs = (struct fsl_qspi_regs *)plat->reg_base; >^ > Just make the cast explict. > > Signed-off-by: Gong Qianyu > --- > V4: > - Revise the commit message. > V2-V3: > - No change. > > drivers/spi/fsl_qspi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c > index feec3e8..9f23c10 100644 > --- a/drivers/spi/fsl_qspi.c > +++ b/drivers/spi/fsl_qspi.c > @@ -936,7 +936,7 @@ static int fsl_qspi_probe(struct udevice *bus) > > dm_spi_bus->max_hz = plat->speed_hz; > > - priv->regs = (struct fsl_qspi_regs *)plat->reg_base; The reg_base is u32. Is it always correct on 64-bit SoC? > + priv->regs = (struct fsl_qspi_regs *)(unsigned long)plat->reg_base; How about (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base? York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V4 2/4] spi: fsl_qspi: Fix qspi_op_rdid memcpy issue
On 01/10/2016 06:15 PM, Gong Qianyu wrote:
> From: Gong Qianyu
>
> In current driver everytime we memcpy 4 bytes to the dest memory
> regardless of the remaining length.
> This patch adds checking the remaining length before memcpy.
> If the length is shorter than 4 bytes, memcpy the actual length of data
> to the dest memory.
>
> Signed-off-by: Gong Qianyu
> ---
> V2-V4:
> - No change.
>
> drivers/spi/fsl_qspi.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
> index 9f23c10..4d58211 100644
> --- a/drivers/spi/fsl_qspi.c
> +++ b/drivers/spi/fsl_qspi.c
> @@ -500,7 +500,10 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32
> *rxbuf, u32 len)
> if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
> data = qspi_read32(priv->flags, ®s->rbdr[i]);
> data = qspi_endian_xchg(data);
> - memcpy(rxbuf, &data, 4);
> + if (size < 4)
> + memcpy(rxbuf, &data, size);
> + else
> + memcpy(rxbuf, &data, 4);
> rxbuf++;
> size -= 4;
> i++;
>
Doesn't the line "size -= 4" need a fix as well? I guess it runs OK for checking
(size > 0), but it looks odd.
York
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Re: [U-Boot] [PATCH] ls2-2085ardb: Correct the model name of ls2085ardb
On 01/14/2016 08:49 PM, Prabhakar Kushwaha wrote:
>
>> -Original Message-
>> From: york sun [mailto:york@nxp.com]
>> Sent: Thursday, January 14, 2016 10:36 PM
>> To: Ashish Kumar ; u-boot@lists.denx.de
>> Cc: Prabhakar Kushwaha
>> Subject: Re: [PATCH] ls2-2085ardb: Correct the model name of ls2085ardb
>>
>> On 01/14/2016 04:42 AM, Ashish Kumar wrote:
>>> Signed-off-by: Ashish Kumar
>>> ---
>>> arch/arm/dts/fsl-ls2080a-rdb.dts |2 +-
>>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts b/arch/arm/dts/fsl-ls2080a-
>> rdb.dts
>>> index 1a1813b..71d1969 100644
>>> --- a/arch/arm/dts/fsl-ls2080a-rdb.dts
>>> +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts
>>> @@ -11,7 +11,7 @@
>>> #include "fsl-ls2080a.dtsi"
>>>
>>> / {
>>> - model = "Freescale Layerscape 2080a RDB Board";
>>> + model = "Freescale Layerscape 2085a RDB Board";
>>> compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
>>>
>>> aliases {
>>>
>>
>> Ashish,
>>
>> Why change this? This product has been renamed to LS2080A.
>>
>
> LS2085ARDB is a platform/board hosting LS2080A, LS2085A and LS2088A.
>
> This is the reason board name is being updated.
>
Prabhakar,
You changed the name from LS2085A to LS2080A not long ago, including the board
LS2085ARDB, stating LS2080A is the prime personality. Now you want to change it
back? You have to give a good reason.
York
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Re: [U-Boot] [PATCH 6/6] defconfig: dra72_evm: enable sata driver model
On Mon, Jan 18, 2016 at 02:17:43PM +0530, Mugunthan V N wrote: > Enable sata driver model for dra72_evm as dwc_ahci supports > driver model > > Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] defconfig: dra74_evm: enable sata driver model
On Mon, Jan 18, 2016 at 02:17:42PM +0530, Mugunthan V N wrote: > Enable sata driver model for dra74_evm as dwc_ahci supports > driver model > > Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] arm: omap-common: sata: prepare driver for DM conversion
On Mon, Jan 18, 2016 at 02:17:40PM +0530, Mugunthan V N wrote: > Prepare sata driver for DM conversion by abstracting sata phy > init to seperate function. > > Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] drivers: block: dwc_ahci: Implement a driver for Synopsys DWC sata device
On Mon, Jan 18, 2016 at 02:17:41PM +0530, Mugunthan V N wrote: > Implement a sata driver for Synopsys DWC sata device based on > U-boot driver model. > > Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] x86: quark: Fix boot breakage
On Mon, Jan 18, 2016 at 07:29:32AM -0800, Bin Meng wrote: > With driver model timer conversion, quark based board does not boot > any more as mdelay() is called during quark_pcie_early_init() which > is before driver model gets initialized. Fix this breakage. > > Signed-off-by: Bin Meng > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] arm: omap: sata: move enable sata clocks to enable_basic_clocks()
On Mon, Jan 18, 2016 at 02:17:38PM +0530, Mugunthan V N wrote: > All the clocks which has to be enabled has to be done in > enable_basic_clocks(), so moving enable sata clock to common > clocks enable function. > > Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] pci_rom.c: Fix may be used uninitialized warning
On Sat, Jan 16, 2016 at 02:50:26PM +, Tom Rini wrote: > With gcc-5.x we get: > drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios': > drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in > this function [-Wmaybe-uninitialized] > > While unconvinced that this can happen in practice (if we malloc we set > alloced to true, it will be false otherwise), silence the compiler. > > Signed-off-by: Tom Rini > Reviewed-by: Bin Meng > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] drivers/spi/rk_spi.c: Fix debug format warning
On Sun, Jan 17, 2016 at 02:42:41AM +, Tom Rini wrote: > We need to use %lx not %x to describe a fdt_addr_t > > Cc: Simon Glass > Signed-off-by: Tom Rini Reworded the subject and applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] drivers/power/regulator/max77686.c: Don't use switch() on bools
On Sun, Jan 17, 2016 at 02:44:37AM +, Tom Rini wrote: > With gcc-5.3 we get a warning for using switch() on a bool type. > Rewrite these sections as if/else and update the one section that was > using 1/0 instead of true/false. > > Cc: Simon Glass > Cc: Przemyslaw Marczak > Signed-off-by: Tom Rini > Reviewed-by: Bin Meng > Acked-by: Przemyslaw Marczak Reworded the subject and applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Add more SPDX-License-Identifier tags
On Thu, Jan 14, 2016 at 10:05:13PM -0500, Tom Rini wrote: > In a number of places we had wordings of the GPL (or LGPL in a few > cases) license text that were split in such a way that it wasn't caught > previously. Convert all of these to the correct SPDX-License-Identifier > tag. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/3] gunzip.c: Only include gzwrite on CONFIG_CMD_UNZIP
On Thu, Jan 14, 2016 at 01:02:05PM -0500, Tom Rini wrote: > Only when we have CONFIG_CMD_UNZIP enabled do we have the 'gzwrite' > command. While this command should be separated from CONFIG_CMD_UNZIP > we should also only include the write portion of the gz code in that > case as well. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] scripts/Makefile* Add SPDX-License-Identifier tag
On Thu, Jan 14, 2016 at 06:24:44PM -0500, Tom Rini wrote: > A general best practice for SPDX is that Makefiles should have an > identifier, add these as everything else is currently covered. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/3] axm/taurus: Enable tiny printf in SPL
On Thu, Jan 14, 2016 at 01:02:04PM -0500, Tom Rini wrote: > Both of these boards are very close to their limit and with some toolchains > such as gcc 5.x are too large. Switch to tiny printf to reclaim some size. > > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-video/master
On Tue, Jan 19, 2016 at 08:58:45AM +0100, Anatolij Gustschin wrote: > Hi Tom, > > The following changes since commit 52bc7c7e2b31d6ba8d394f3d22b551abfa365363: > > eeprom: fix eeprom write procedure (2015-12-16 10:31:31 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-video.git master > > for you to fetch changes up to 535cce0f90b06f4555ba2e3090ca8118ae724751: > > video: Typo cleanup in drivers/video/da8xx-fb.c (2015-12-16 21:02:03 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/3] vsprintf.c: Always enable CONFIG_SYS_VSNPRINTF
On Thu, Jan 14, 2016 at 01:02:03PM -0500, Tom Rini wrote: > Enabling this function always removes some class of string saftey issues. > The size change here in general is about 400 bytes and this seems a reasonable > trade-off. > > Cc: Peng Fan > Cc: Peter Robinson > Cc: Fabio Estevam > Cc: Adrian Alonso > Cc: Stefano Babic > Cc: Hans de Goede > Signed-off-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] image: fix getenv_bootm_size() function
On Fri, Dec 18, 2015 at 02:17:10PM +0900, Masahiro Yamada wrote: > Currently, this function returns wrong size if "bootm_low" is defined, > but "bootm_size" is not. > > Signed-off-by: Masahiro Yamada > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
