From: Mingkai Hu <mingkai...@nxp.com>
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13 +++++++++++++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..485f5cd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -210,6 +210,18 @@ static void erratum_a009929(void)
#endif
}
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+ u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -232,6 +244,7 @@ void fsl_lsch2_early_init_f(void)
/* Erratum */
erratum_a009929();
+ erratum_a009660();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113d..66399b2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -167,6 +167,7 @@
#define GICC_BASE 0x01402000
#define CONFIG_SYS_FSL_ERRATUM_A009929
+#define CONFIG_SYS_FSL_ERRATUM_A009660
#else
#error SoC not defined
#endif
--
2.1.0.27.g96db324
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